2 * drivers/video/rockchip/lcdc/rk3036_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 * Author:zhengyang<zhengyang@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <asm/div64.h>
30 #include <linux/uaccess.h>
31 #include <linux/rockchip/cpu.h>
32 #include <linux/rockchip/iomap.h>
33 #include <linux/rockchip/grf.h>
34 #include <linux/rockchip/common.h>
35 #include <dt-bindings/clock/rk_system_status.h>
36 #if defined(CONFIG_ION_ROCKCHIP)
37 #include <linux/rockchip-iovmm.h>
39 #include "rk3036_lcdc.h"
41 static int dbg_thresd;
42 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
44 #define DBG(level, x...) do { \
45 if (unlikely(dbg_thresd >= level)) \
46 dev_info(dev_drv->dev, x); \
49 #define grf_writel(offset, v) do { \
50 writel_relaxed(v, RK_GRF_VIRT + offset); \
54 static struct rk_lcdc_win lcdc_win[] = {
72 static irqreturn_t rk3036_lcdc_isr(int irq, void *dev_id)
74 struct lcdc_device *lcdc_dev =
75 (struct lcdc_device *)dev_id;
76 ktime_t timestamp = ktime_get();
77 u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
79 if (int_reg & m_FS_INT_STA) {
80 timestamp = ktime_get();
81 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
83 /*if (lcdc_dev->driver.wait_fs) {*/
85 spin_lock(&(lcdc_dev->driver.cpl_lock));
86 complete(&(lcdc_dev->driver.frame_done));
87 spin_unlock(&(lcdc_dev->driver.cpl_lock));
89 lcdc_dev->driver.vsync_info.timestamp = timestamp;
90 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
92 } else if (int_reg & m_LF_INT_STA) {
93 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
99 static int rk3036_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
101 #ifdef CONFIG_RK_FPGA
102 lcdc_dev->clk_on = 1;
105 if (!lcdc_dev->clk_on) {
106 clk_prepare_enable(lcdc_dev->hclk);
107 clk_prepare_enable(lcdc_dev->dclk);
108 clk_prepare_enable(lcdc_dev->aclk);
109 /* clk_prepare_enable(lcdc_dev->pd);*/
110 spin_lock(&lcdc_dev->reg_lock);
111 lcdc_dev->clk_on = 1;
112 spin_unlock(&lcdc_dev->reg_lock);
118 static int rk3036_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
120 #ifdef CONFIG_RK_FPGA
121 lcdc_dev->clk_on = 0;
124 if (lcdc_dev->clk_on) {
125 spin_lock(&lcdc_dev->reg_lock);
126 lcdc_dev->clk_on = 0;
127 spin_unlock(&lcdc_dev->reg_lock);
129 clk_disable_unprepare(lcdc_dev->dclk);
130 clk_disable_unprepare(lcdc_dev->hclk);
131 clk_disable_unprepare(lcdc_dev->aclk);
132 /* clk_disable_unprepare(lcdc_dev->pd);*/
138 static int rk3036_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
141 struct lcdc_device *lcdc_dev = container_of(dev_drv,
142 struct lcdc_device, driver);
143 mask = m_FS_INT_CLEAR | m_FS_INT_EN;
144 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1);
145 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
149 static int rk3036_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
153 spin_lock(&lcdc_dev->reg_lock);
154 if (likely(lcdc_dev->clk_on)) {
155 mask = m_FS_INT_CLEAR | m_FS_INT_EN;
156 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0);
157 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
158 spin_unlock(&lcdc_dev->reg_lock);
160 spin_unlock(&lcdc_dev->reg_lock);
166 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device
172 spin_lock(&lcdc_dev->reg_lock);
173 for (reg = 0; reg < 0xe0; reg += 4)
174 value = lcdc_readl(lcdc_dev, reg);
176 spin_unlock(&lcdc_dev->reg_lock);
179 static int rk3036_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
183 enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format;
184 enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format;
186 int win0_alpha_en = ((win0_format == ARGB888) ||
187 (win0_format == ABGR888)) ? 1 : 0;
188 int win1_alpha_en = ((win1_format == ARGB888) ||
189 (win1_format == ABGR888)) ? 1 : 0;
190 int atv_layer_cnt = lcdc_dev->driver.win[0]->state +
191 lcdc_dev->driver.win[1]->state;
192 u32 *_pv = (u32 *)lcdc_dev->regsbak;
194 _pv += (DSP_CTRL0 >> 2);
195 win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
197 if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) {
198 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
200 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0) |
201 v_WIN1_PREMUL_SCALE(0);
202 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
204 mask = m_WIN0_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
206 val = v_WIN0_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
207 v_ALPHA_MODE_SEL1(0);
208 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
209 } else if ((!win0_top) && (atv_layer_cnt >= 2) &&
211 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
213 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1) |
214 v_WIN1_PREMUL_SCALE(0);
215 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
217 mask = m_WIN1_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
219 val = v_WIN1_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
220 v_ALPHA_MODE_SEL1(0);
221 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
223 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
224 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
225 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
228 if (lcdc_dev->driver.win[2]->state == 1) {
229 mask = m_HWC_ALPAH_EN;
230 val = v_HWC_ALPAH_EN(1);
231 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
233 mask = m_HWC_ALPHA_MODE;
234 val = v_HWC_ALPHA_MODE(1);
235 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
237 mask = m_HWC_ALPAH_EN;
238 val = v_HWC_ALPAH_EN(0);
239 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
245 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
246 struct rk_lcdc_win *win)
251 if (win->state == 1) {
253 mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
254 val = v_WIN0_EN(win->state) |
255 v_WIN0_FORMAT(win->area[0].fmt_cfg) |
256 v_WIN0_RB_SWAP(win->area[0].swap_rb);
257 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
258 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
259 v_X_SCL_FACTOR(win->scale_yrgb_x) |
260 v_Y_SCL_FACTOR(win->scale_yrgb_y));
261 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
262 v_X_SCL_FACTOR(win->scale_cbcr_x) |
263 v_Y_SCL_FACTOR(win->scale_cbcr_y));
264 lcdc_msk_reg(lcdc_dev, WIN0_VIR,
265 m_YRGB_VIR | m_CBBR_VIR,
266 v_YRGB_VIR(win->area[0].y_vir_stride) |
267 v_CBBR_VIR(win->area[0].uv_vir_stride));
268 lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
269 v_ACT_WIDTH(win->area[0].xact) |
270 v_ACT_HEIGHT(win->area[0].yact));
271 lcdc_writel(lcdc_dev, WIN0_DSP_ST,
272 v_DSP_STX(win->area[0].dsp_stx) |
273 v_DSP_STY(win->area[0].dsp_sty));
274 lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
275 v_DSP_WIDTH(win->post_cfg.xsize) |
276 v_DSP_HEIGHT(win->post_cfg.ysize));
278 lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
279 win->area[0].y_addr);
280 lcdc_writel(lcdc_dev, WIN0_CBR_MST,
281 win->area[0].uv_addr);
282 } else if (win->id == 1) {
283 mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
284 val = v_WIN1_EN(win->state) |
285 v_WIN1_FORMAT(win->area[0].fmt_cfg) |
286 v_WIN1_RB_SWAP(win->area[0].swap_rb);
287 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
288 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
289 v_X_SCL_FACTOR(win->scale_yrgb_x) |
290 v_Y_SCL_FACTOR(win->scale_yrgb_y));
292 lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
293 v_YRGB_VIR(win->area[0].y_vir_stride));
294 lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
295 v_ACT_WIDTH(win->area[0].xact) |
296 v_ACT_HEIGHT(win->area[0].yact));
297 lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
298 v_DSP_WIDTH(win->post_cfg.xsize) |
299 v_DSP_HEIGHT(win->post_cfg.ysize));
300 lcdc_writel(lcdc_dev, WIN1_DSP_ST,
301 v_DSP_STX(win->area[0].dsp_stx) |
302 v_DSP_STY(win->area[0].dsp_sty));
303 lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
304 } else if (win->id == 2) {
305 mask = m_HWC_EN | m_HWC_LODAD_EN;
306 val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1);
307 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
308 if ((win->area[0].xsize == 32) &&
309 (win->area[0].ysize == 32))
311 else if ((win->area[0].xsize == 64) &&
312 (win->area[0].ysize == 64))
315 dev_err(lcdc_dev->dev,
316 "unsupport hwc size:x=%d,y=%d\n",
319 lcdc_writel(lcdc_dev, HWC_DSP_ST,
320 v_DSP_STX(win->area[0].dsp_stx) |
321 v_DSP_STY(win->area[0].dsp_sty));
322 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
325 win->area[0].y_addr = 0;
326 win->area[0].uv_addr = 0;
328 lcdc_msk_reg(lcdc_dev,
329 SYS_CTRL, m_WIN0_EN, v_WIN0_EN(0));
330 else if (win->id == 1)
331 lcdc_msk_reg(lcdc_dev,
332 SYS_CTRL, m_WIN1_EN, v_WIN1_EN(0));
333 else if (win->id == 2)
334 lcdc_msk_reg(lcdc_dev,
335 SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
337 rk3036_lcdc_alpha_cfg(lcdc_dev);
340 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev,
341 unsigned int win_id, bool open)
343 spin_lock(&lcdc_dev->reg_lock);
344 if (likely(lcdc_dev->clk_on) &&
345 lcdc_dev->driver.win[win_id]->state != open) {
347 if (!lcdc_dev->atv_layer_cnt) {
348 dev_info(lcdc_dev->dev,
349 "wakeup from standby!\n");
350 lcdc_dev->standby = 0;
352 lcdc_dev->atv_layer_cnt |= (1 << win_id);
353 } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) {
354 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
356 lcdc_dev->driver.win[win_id]->state = open;
358 lcdc_layer_update_regs(lcdc_dev,
359 lcdc_dev->driver.win[win_id]);
360 lcdc_cfg_done(lcdc_dev);
362 /*if no layer used,disable lcdc*/
363 if (!lcdc_dev->atv_layer_cnt) {
364 dev_info(lcdc_dev->dev,
365 "no layer is used, go to standby!\n");
366 lcdc_dev->standby = 1;
369 spin_unlock(&lcdc_dev->reg_lock);
372 static int rk3036_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
374 struct lcdc_device *lcdc_dev =
375 container_of(dev_drv, struct lcdc_device, driver);
376 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
377 struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
381 spin_lock(&lcdc_dev->reg_lock);
382 if (likely(lcdc_dev->clk_on)) {
383 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
384 v_LCDC_STANDBY(lcdc_dev->standby));
385 lcdc_layer_update_regs(lcdc_dev, win0);
386 lcdc_layer_update_regs(lcdc_dev, win1);
387 rk3036_lcdc_alpha_cfg(lcdc_dev);
388 lcdc_cfg_done(lcdc_dev);
390 spin_unlock(&lcdc_dev->reg_lock);
392 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
393 init_completion(&dev_drv->frame_done);
394 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
395 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
397 (dev_drv->cur_screen->ft
399 if (!timeout && (!dev_drv->frame_done.done)) {
400 dev_warn(lcdc_dev->dev,
401 "wait for new frame start time out!\n");
405 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
409 static void rk3036_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
411 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0);
414 static void rk3036_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
417 struct lcdc_device *lcdc_dev =
418 container_of(dev_drv, struct lcdc_device, driver);
420 /*spin_lock(&lcdc_dev->reg_lock);*/
421 if (likely(lcdc_dev->clk_on)) {
422 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
423 m_AXI_OUTSTANDING_MAX_NUM;
424 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
425 v_AXI_MAX_OUTSTANDING_EN(1);
426 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
428 /*spin_unlock(&lcdc_dev->reg_lock);*/
431 static int rk3036_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv,
432 int *hwc_lut, int mode)
439 struct lcdc_device *lcdc_dev =
440 container_of(dev_drv, struct lcdc_device, driver);
441 if (dev_drv->hwc_lut == NULL)
442 dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL);
444 spin_lock(&lcdc_dev->reg_lock);
445 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0));
446 lcdc_cfg_done(lcdc_dev);
448 for (i = 0; i < 256; i++) {
450 dev_drv->hwc_lut[i] = hwc_lut[i];
451 v = dev_drv->hwc_lut[i];
452 c = lcdc_dev->hwc_lut_addr_base + i;
453 writel_relaxed(v, c);
455 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
456 lcdc_cfg_done(lcdc_dev);
457 spin_unlock(&lcdc_dev->reg_lock);
462 static int rk3036_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
464 #ifdef CONFIG_RK_FPGA
468 struct lcdc_device *lcdc_dev =
469 container_of(dev_drv, struct lcdc_device, driver);
470 struct rk_screen *screen = dev_drv->cur_screen;
472 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
474 dev_err(dev_drv->dev,
475 "set lcdc%d dclk failed\n", lcdc_dev->id);
477 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
478 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
480 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
481 screen->ft = 1000 / fps;
482 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
483 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
487 /********do basic init*********/
488 static int rk3036_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
490 struct lcdc_device *lcdc_dev = container_of(dev_drv,
491 struct lcdc_device, driver);
493 if (lcdc_dev->pre_init)
495 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
496 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
497 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
498 /* lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); */
500 if (/*IS_ERR(lcdc_dev->pd) ||*/ (IS_ERR(lcdc_dev->aclk)) ||
501 (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
502 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
506 rk_disp_pwr_enable(dev_drv);
507 rk3036_lcdc_clk_enable(lcdc_dev);
509 /*backup reg config at uboot*/
510 rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
511 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN,
512 v_AUTO_GATING_EN(0));
513 lcdc_cfg_done(lcdc_dev);
514 if (dev_drv->iommu_enabled)
515 /*disable win0 to workaround iommu pagefault*/
516 lcdc_layer_enable(lcdc_dev, 0, 0);
517 lcdc_dev->pre_init = true;
522 static int rk3036_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
527 struct lcdc_device *lcdc_dev = container_of(dev_drv,
528 struct lcdc_device, driver);
529 struct rk_screen *screen = dev_drv->cur_screen;
530 u16 right_margin = screen->mode.right_margin;
531 u16 left_margin = screen->mode.left_margin;
532 u16 lower_margin = screen->mode.lower_margin;
533 u16 upper_margin = screen->mode.upper_margin;
534 u16 x_res = screen->mode.xres;
535 u16 y_res = screen->mode.yres;
538 spin_lock(&lcdc_dev->reg_lock);
539 if (likely(lcdc_dev->clk_on)) {
540 switch (screen->type) {
542 mask = m_HDMI_DCLK_EN;
543 val = v_HDMI_DCLK_EN(1);
544 if (screen->pixelrepeat) {
545 mask |= m_CORE_CLK_DIV_EN;
546 val |= v_CORE_CLK_DIV_EN(1);
548 mask |= m_CORE_CLK_DIV_EN;
549 val |= v_CORE_CLK_DIV_EN(0);
551 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
552 mask = (1 << 4) | (1 << 5) | (1 << 6);
553 val = (screen->pin_hsync << 4) |
554 (screen->pin_vsync << 5) |
555 (screen->pin_den << 6);
556 grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
559 mask = m_TVE_DAC_DCLK_EN;
560 val = v_TVE_DAC_DCLK_EN(1);
561 if (screen->pixelrepeat) {
562 mask |= m_CORE_CLK_DIV_EN;
563 val |= v_CORE_CLK_DIV_EN(1);
565 mask |= m_CORE_CLK_DIV_EN;
566 val |= v_CORE_CLK_DIV_EN(0);
568 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
569 if ((x_res == 720) && (y_res == 576)) {
570 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
571 m_TVE_MODE, v_TVE_MODE(TV_PAL));
572 } else if ((x_res == 720) && (y_res == 480)) {
573 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
574 m_TVE_MODE, v_TVE_MODE(TV_NTSC));
576 dev_err(lcdc_dev->dev,
577 "unsupported video timing!\n");
582 dev_err(lcdc_dev->dev, "un supported interface!\n");
586 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
587 m_DEN_POL | m_DCLK_POL;
588 val = v_DSP_OUT_FORMAT(face) |
589 v_HSYNC_POL(screen->pin_hsync) |
590 v_VSYNC_POL(screen->pin_vsync) |
591 v_DEN_POL(screen->pin_den) |
592 v_DCLK_POL(screen->pin_dclk);
593 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
595 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
596 m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
597 m_DSP_DUMMY_SWAP | m_BLANK_EN;
599 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
600 v_DSP_RB_SWAP(screen->swap_rb) |
601 v_DSP_RG_SWAP(screen->swap_rg) |
602 v_DSP_DELTA_SWAP(screen->swap_delta) |
603 v_DSP_DUMMY_SWAP(screen->swap_dumy) |
606 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
608 v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode.
613 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
614 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
615 v_HASP(screen->mode.hsync_len + left_margin);
616 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
618 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
619 /*First Field Timing*/
620 lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
621 v_VSYNC(screen->mode.vsync_len) |
622 v_VERPRD(2 * (screen->mode.vsync_len +
623 upper_margin + lower_margin)
625 lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
626 v_VAEP(screen->mode.vsync_len +
627 upper_margin + y_res/2) |
628 v_VASP(screen->mode.vsync_len +
630 /*Second Field Timing*/
631 lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
632 v_VSYNC_ST_F1(screen->mode.vsync_len +
633 upper_margin + y_res/2 +
635 v_VSYNC_END_F1(2 * screen->mode.vsync_len
636 + upper_margin + y_res/2 +
638 lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
639 v_VAEP(2 * (screen->mode.vsync_len +
640 upper_margin) + y_res +
642 v_VASP(2 * (screen->mode.vsync_len +
643 upper_margin) + y_res/2 +
646 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
648 m_INTERLACE_DSP_POL |
649 m_WIN1_DIFF_DCLK_EN |
650 m_WIN0_YRGB_DEFLICK_EN |
651 m_WIN0_CBR_DEFLICK_EN |
652 m_WIN0_INTERLACE_EN |
654 v_INTERLACE_DSP_EN(1) |
655 v_INTERLACE_DSP_POL(0) |
656 v_WIN1_DIFF_DCLK_EN(1) |
657 v_WIN0_YRGB_DEFLICK_EN(1) |
658 v_WIN0_CBR_DEFLICK_EN(1) |
659 v_WIN0_INTERLACE_EN(1) |
660 v_WIN1_INTERLACE_EN(1));
662 val = v_VSYNC(screen->mode.vsync_len) |
663 v_VERPRD(screen->mode.vsync_len + upper_margin +
664 y_res + lower_margin);
665 lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
667 val = v_VAEP(screen->mode.vsync_len +
668 upper_margin + y_res) |
669 v_VASP(screen->mode.vsync_len +
670 screen->mode.upper_margin);
671 lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
673 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
675 m_WIN1_DIFF_DCLK_EN |
676 m_WIN0_YRGB_DEFLICK_EN |
677 m_WIN0_CBR_DEFLICK_EN |
678 m_WIN0_INTERLACE_EN |
680 v_INTERLACE_DSP_EN(0) |
681 v_WIN1_DIFF_DCLK_EN(0) |
682 v_WIN0_YRGB_DEFLICK_EN(0) |
683 v_WIN0_CBR_DEFLICK_EN(0) |
684 v_WIN0_INTERLACE_EN(1) |
685 v_WIN1_INTERLACE_EN(1));
688 spin_unlock(&lcdc_dev->reg_lock);
690 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
692 dev_err(dev_drv->dev,
693 "set lcdc%d dclk failed\n", lcdc_dev->id);
695 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
696 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
698 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
699 screen->ft = 1000 / fps;
700 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
701 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
702 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
703 dev_drv->trsm_ops->enable();
710 static int rk3036_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
713 struct lcdc_device *lcdc_dev = container_of(dev_drv,
714 struct lcdc_device, driver);
716 /*enable clk,when first layer open */
717 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
718 rk3036_lcdc_pre_init(dev_drv);
719 rk3036_lcdc_clk_enable(lcdc_dev);
720 #if defined(CONFIG_ROCKCHIP_IOMMU)
721 if (dev_drv->iommu_enabled) {
722 if (!dev_drv->mmu_dev) {
724 rk_fb_get_sysmmu_device_by_compatible(
725 dev_drv->mmu_dts_name);
726 if (dev_drv->mmu_dev) {
727 rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
730 dev_err(dev_drv->dev,
731 "failed to get iommu device\n"
738 rk3036_lcdc_reg_restore(lcdc_dev);
739 /*if (dev_drv->iommu_enabled)
740 rk3036_lcdc_mmu_en(dev_drv);*/
741 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
742 /*rk3036_lcdc_set_dclk(dev_drv);*/
743 rk3036_lcdc_enable_irq(dev_drv);
745 rk3036_load_screen(dev_drv, 1);
749 if (win_id < ARRAY_SIZE(lcdc_win))
750 lcdc_layer_enable(lcdc_dev, win_id, open);
752 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
754 /*when all layer closed,disable clk */
756 if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
757 rk3036_lcdc_disable_irq(lcdc_dev);
758 rk3036_lcdc_reg_update(dev_drv);
759 #if defined(CONFIG_ROCKCHIP_IOMMU)
760 if (dev_drv->iommu_enabled) {
761 if (dev_drv->mmu_dev)
762 rockchip_iovmm_deactivate(dev_drv->dev);
765 rk3036_lcdc_clk_disable(lcdc_dev);
771 static int rk3036_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
773 struct lcdc_device *lcdc_dev =
774 container_of(dev_drv, struct lcdc_device, driver);
775 struct rk_screen *screen = dev_drv->cur_screen;
776 struct rk_lcdc_win *win = NULL;
777 char fmt[9] = "NULL";
780 dev_err(dev_drv->dev, "screen is null!\n");
785 win = dev_drv->win[0];
786 } else if (win_id == 1) {
787 win = dev_drv->win[1];
788 } else if (win_id == 2) {
789 win = dev_drv->win[2];
791 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
795 spin_lock(&lcdc_dev->reg_lock);
796 win->post_cfg.xpos = win->area[0].xpos * (dev_drv->overscan.left +
797 dev_drv->overscan.right)/200 + screen->mode.xres *
798 (100 - dev_drv->overscan.left) / 200;
800 win->post_cfg.ypos = win->area[0].ypos * (dev_drv->overscan.top +
801 dev_drv->overscan.bottom)/200 +
803 (100 - dev_drv->overscan.top) / 200;
804 win->post_cfg.xsize = win->area[0].xsize *
805 (dev_drv->overscan.left +
806 dev_drv->overscan.right)/200;
807 win->post_cfg.ysize = win->area[0].ysize *
808 (dev_drv->overscan.top +
809 dev_drv->overscan.bottom)/200;
811 win->area[0].dsp_stx = win->post_cfg.xpos + screen->mode.left_margin +
812 screen->mode.hsync_len;
813 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
814 win->post_cfg.ysize /= 2;
815 win->area[0].dsp_sty = win->post_cfg.ypos/2 +
816 screen->mode.upper_margin +
817 screen->mode.vsync_len;
819 win->area[0].dsp_sty = win->post_cfg.ypos +
820 screen->mode.upper_margin +
821 screen->mode.vsync_len;
823 win->scale_yrgb_x = calscale(win->area[0].xact, win->post_cfg.xsize);
824 win->scale_yrgb_y = calscale(win->area[0].yact, win->post_cfg.ysize);
826 switch (win->area[0].format) {
828 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
829 win->area[0].swap_rb = 0;
832 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
833 win->area[0].swap_rb = 1;
836 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
837 win->area[0].swap_rb = 1;
840 win->area[0].fmt_cfg = VOP_FORMAT_RGB888;
841 win->area[0].swap_rb = 0;
844 win->area[0].fmt_cfg = VOP_FORMAT_RGB565;
845 win->area[0].swap_rb = 0;
849 win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444;
850 win->scale_cbcr_x = calscale(win->area[0].xact,
851 win->post_cfg.xsize);
852 win->scale_cbcr_y = calscale(win->area[0].yact,
853 win->post_cfg.ysize);
854 win->area[0].swap_rb = 0;
856 dev_err(lcdc_dev->driver.dev,
857 "%s:un supported format!\n",
863 win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422;
864 win->scale_cbcr_x = calscale((win->area[0].xact / 2),
865 win->post_cfg.xsize);
866 win->scale_cbcr_y = calscale(win->area[0].yact,
867 win->post_cfg.ysize);
868 win->area[0].swap_rb = 0;
870 dev_err(lcdc_dev->driver.dev,
871 "%s:un supported format!\n",
877 win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420;
878 win->scale_cbcr_x = calscale(win->area[0].xact / 2,
879 win->post_cfg.xsize);
880 win->scale_cbcr_y = calscale(win->area[0].yact / 2,
881 win->post_cfg.ysize);
882 win->area[0].swap_rb = 0;
884 dev_err(lcdc_dev->driver.dev,
885 "%s:un supported format!\n",
890 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
894 spin_unlock(&lcdc_dev->reg_lock);
896 DBG(2, "lcdc%d>>%s\n"
897 ">>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
898 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
899 __func__, get_format_string(win->area[0].format, fmt),
900 win->area[0].xact, win->area[0].yact, win->post_cfg.xsize,
901 win->post_cfg.ysize, win->area[0].xvir, win->area[0].yvir,
902 win->post_cfg.xpos, win->post_cfg.ypos);
906 static int rk3036_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
908 struct lcdc_device *lcdc_dev = container_of(dev_drv,
909 struct lcdc_device, driver);
910 struct rk_lcdc_win *win = NULL;
911 struct rk_screen *screen = dev_drv->cur_screen;
914 dev_err(dev_drv->dev, "screen is null!\n");
919 win = dev_drv->win[0];
920 } else if (win_id == 1) {
921 win = dev_drv->win[1];
922 } else if (win_id == 2) {
923 win = dev_drv->win[2];
925 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
929 spin_lock(&lcdc_dev->reg_lock);
930 if (likely(lcdc_dev->clk_on)) {
931 win->area[0].y_addr = win->area[0].smem_start +
932 win->area[0].y_offset;
933 win->area[0].uv_addr = win->area[0].cbr_start +
934 win->area[0].c_offset;
935 if (win->area[0].y_addr)
936 lcdc_layer_update_regs(lcdc_dev, win);
937 /*lcdc_cfg_done(lcdc_dev);*/
939 spin_unlock(&lcdc_dev->reg_lock);
941 DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
942 lcdc_dev->id, __func__, win->area[0].y_addr,
943 win->area[0].uv_addr, win->area[0].y_offset);
944 /* this is the first frame of the system,
945 enable frame start interrupt*/
946 if ((dev_drv->first_frame)) {
947 dev_drv->first_frame = 0;
948 rk3036_lcdc_enable_irq(dev_drv);
953 static int rk3036_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
954 unsigned long arg, int win_id)
956 struct lcdc_device *lcdc_dev = container_of(dev_drv,
957 struct lcdc_device, driver);
959 void __user *argp = (void __user *)arg;
960 struct color_key_cfg clr_key_cfg;
963 case RK_FBIOGET_PANEL_SIZE:
964 panel_size[0] = lcdc_dev->screen->mode.xres;
965 panel_size[1] = lcdc_dev->screen->mode.yres;
966 if (copy_to_user(argp, panel_size, 8))
969 case RK_FBIOPUT_COLOR_KEY_CFG:
970 if (copy_from_user(&clr_key_cfg, argp,
971 sizeof(struct color_key_cfg)))
973 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
974 clr_key_cfg.win0_color_key_cfg);
975 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
976 clr_key_cfg.win1_color_key_cfg);
985 static int rk3036_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
990 mutex_lock(&dev_drv->fb_win_id_mutex);
991 if (!strcmp(id, "fb0"))
992 win_id = dev_drv->fb0_win_id;
993 else if (!strcmp(id, "fb1"))
994 win_id = dev_drv->fb1_win_id;
995 else if (!strcmp(id, "fb2"))
996 win_id = dev_drv->fb2_win_id;
997 mutex_unlock(&dev_drv->fb_win_id_mutex);
1002 static int rk3036_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
1005 return dev_drv->win[win_id]->state;
1008 static int rk3036_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1011 struct lcdc_device *lcdc_dev =
1012 container_of(dev_drv, struct lcdc_device, driver);
1013 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
1014 struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
1015 int ovl, needswap = 0;
1018 if (win0->z_order > win1->z_order)
1025 spin_lock(&lcdc_dev->reg_lock);
1026 if (lcdc_dev->clk_on) {
1028 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1029 v_WIN0_TOP(needswap));
1032 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1037 spin_unlock(&lcdc_dev->reg_lock);
1042 static int rk3036_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1044 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1045 struct lcdc_device, driver);
1046 if (dev_drv->suspend_flag)
1048 dev_drv->suspend_flag = 1;
1049 flush_kthread_worker(&dev_drv->update_regs_worker);
1051 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1052 dev_drv->trsm_ops->disable();
1053 spin_lock(&lcdc_dev->reg_lock);
1054 if (likely(lcdc_dev->clk_on)) {
1055 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1057 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
1059 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1061 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1063 lcdc_cfg_done(lcdc_dev);
1064 if (dev_drv->iommu_enabled) {
1065 if (dev_drv->mmu_dev)
1066 rockchip_iovmm_deactivate(dev_drv->dev);
1068 spin_unlock(&lcdc_dev->reg_lock);
1070 spin_unlock(&lcdc_dev->reg_lock);
1073 rk3036_lcdc_clk_disable(lcdc_dev);
1074 rk_disp_pwr_disable(dev_drv);
1078 static int rk3036_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1080 struct lcdc_device *lcdc_dev =
1081 container_of(dev_drv, struct lcdc_device, driver);
1083 if (!dev_drv->suspend_flag)
1085 rk_disp_pwr_enable(dev_drv);
1086 dev_drv->suspend_flag = 0;
1088 if (lcdc_dev->atv_layer_cnt) {
1089 rk3036_lcdc_clk_enable(lcdc_dev);
1090 rk3036_lcdc_reg_restore(lcdc_dev);
1092 rk3036_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
1094 spin_lock(&lcdc_dev->reg_lock);
1096 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1098 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1100 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1102 lcdc_cfg_done(lcdc_dev);
1103 if (dev_drv->iommu_enabled) {
1104 if (dev_drv->mmu_dev)
1105 rockchip_iovmm_activate(dev_drv->dev);
1107 spin_unlock(&lcdc_dev->reg_lock);
1110 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1111 dev_drv->trsm_ops->enable();
1116 static int rk3036_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1117 int win_id, int blank_mode)
1119 switch (blank_mode) {
1120 case FB_BLANK_UNBLANK:
1121 rk3036_lcdc_early_resume(dev_drv);
1123 case FB_BLANK_NORMAL:
1124 rk3036_lcdc_early_suspend(dev_drv);
1127 rk3036_lcdc_early_suspend(dev_drv);
1131 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1136 static int rk3036_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1138 struct lcdc_device *lcdc_dev =
1139 container_of(dev_drv, struct lcdc_device, driver);
1141 unsigned int mask, val;
1142 struct rk_lcdc_win *win = NULL;
1144 spin_lock(&lcdc_dev->reg_lock);
1145 if (lcdc_dev->clk_on) {
1146 #if defined(CONFIG_ROCKCHIP_IOMMU)
1147 if (dev_drv->iommu_enabled) {
1148 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1149 lcdc_dev->iommu_status = 1;
1150 if (support_uboot_display() &&
1151 lcdc_dev->prop == PRMRY) {
1152 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1156 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1158 lcdc_cfg_done(lcdc_dev);
1160 rockchip_iovmm_activate(dev_drv->dev);
1161 rk3036_lcdc_mmu_en(dev_drv);
1165 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1166 v_LCDC_STANDBY(lcdc_dev->standby));
1167 for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) {
1168 win = dev_drv->win[i];
1169 if ((win->state == 0) && (win->last_state == 1)) {
1174 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1180 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1186 lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1193 win->last_state = win->state;
1195 lcdc_cfg_done(lcdc_dev);
1197 spin_unlock(&lcdc_dev->reg_lock);
1203 sin_hue = sin(a)*256 +0x100;
1204 cos_hue = cos(a)*256;
1206 sin_hue = sin(a)*256;
1207 cos_hue = cos(a)*256;
1209 static int rk3036_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1212 struct lcdc_device *lcdc_dev =
1213 container_of(dev_drv, struct lcdc_device, driver);
1216 spin_lock(&lcdc_dev->reg_lock);
1217 if (lcdc_dev->clk_on) {
1218 val = lcdc_readl(lcdc_dev, BCSH_H);
1221 val &= m_BCSH_SIN_HUE;
1224 val &= m_BCSH_COS_HUE;
1231 spin_unlock(&lcdc_dev->reg_lock);
1237 static int rk3036_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1238 int sin_hue, int cos_hue)
1240 struct lcdc_device *lcdc_dev =
1241 container_of(dev_drv, struct lcdc_device, driver);
1244 spin_lock(&lcdc_dev->reg_lock);
1245 if (lcdc_dev->clk_on) {
1246 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1247 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1248 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1249 lcdc_cfg_done(lcdc_dev);
1251 spin_unlock(&lcdc_dev->reg_lock);
1256 static int rk3036_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1257 bcsh_bcs_mode mode, int value)
1259 struct lcdc_device *lcdc_dev =
1260 container_of(dev_drv, struct lcdc_device, driver);
1263 spin_lock(&lcdc_dev->reg_lock);
1264 if (lcdc_dev->clk_on) {
1267 /*from 0 to 255,typical is 128*/
1270 else if (value >= 0x20)
1271 value = value - 0x20;
1272 mask = m_BCSH_BRIGHTNESS;
1273 val = v_BCSH_BRIGHTNESS(value);
1276 /*from 0 to 510,typical is 256*/
1277 mask = m_BCSH_CONTRAST;
1278 val = v_BCSH_CONTRAST(value);
1281 /*from 0 to 1015,typical is 256*/
1282 mask = m_BCSH_SAT_CON;
1283 val = v_BCSH_SAT_CON(value);
1288 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1289 lcdc_cfg_done(lcdc_dev);
1291 spin_unlock(&lcdc_dev->reg_lock);
1295 static int rk3036_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1298 struct lcdc_device *lcdc_dev =
1299 container_of(dev_drv, struct lcdc_device, driver);
1302 spin_lock(&lcdc_dev->reg_lock);
1303 if (lcdc_dev->clk_on) {
1304 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1307 val &= m_BCSH_BRIGHTNESS;
1310 else if (val == 0x20)
1314 val &= m_BCSH_CONTRAST;
1318 val &= m_BCSH_SAT_CON;
1325 spin_unlock(&lcdc_dev->reg_lock);
1330 static int rk3036_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1332 struct lcdc_device *lcdc_dev =
1333 container_of(dev_drv, struct lcdc_device, driver);
1336 spin_lock(&lcdc_dev->reg_lock);
1337 if (lcdc_dev->clk_on) {
1339 lcdc_writel(lcdc_dev, BCSH_CTRL,
1340 v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1341 lcdc_writel(lcdc_dev, BCSH_BCS,
1342 v_BCSH_BRIGHTNESS(0x00) |
1343 v_BCSH_CONTRAST(0x80) |
1344 v_BCSH_SAT_CON(0x80));
1345 lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1349 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1351 lcdc_cfg_done(lcdc_dev);
1353 spin_unlock(&lcdc_dev->reg_lock);
1357 static int rk3036_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
1358 struct overscan *overscan)
1362 dev_drv->overscan = *overscan;
1363 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1364 if (dev_drv->win[i] && dev_drv->win[i]->state) {
1365 rk3036_lcdc_set_par(dev_drv, i);
1366 rk3036_lcdc_pan_display(dev_drv, i);
1369 rk3036_lcdc_cfg_done(dev_drv);
1373 static int rk3036_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
1375 struct rk_lcdc_win_area area;
1376 int fb2_win_id, fb1_win_id, fb0_win_id;
1378 mutex_lock(&dev_drv->fb_win_id_mutex);
1379 if (order == FB_DEFAULT_ORDER)
1380 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
1382 fb2_win_id = order / 100;
1383 fb1_win_id = (order / 10) % 10;
1384 fb0_win_id = order % 10;
1386 if (fb0_win_id != dev_drv->fb0_win_id) {
1387 area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0];
1388 dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] =
1389 dev_drv->win[fb0_win_id]->area[0];
1390 dev_drv->win[fb0_win_id]->area[0] = area;
1391 dev_drv->fb0_win_id = fb0_win_id;
1393 dev_drv->fb1_win_id = fb1_win_id;
1394 dev_drv->fb2_win_id = fb2_win_id;
1396 mutex_unlock(&dev_drv->fb_win_id_mutex);
1401 static int rk3036_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1404 struct lcdc_device *lcdc_dev =
1405 container_of(dev_drv, struct lcdc_device, driver);
1406 struct rk_screen *screen = dev_drv->cur_screen;
1411 u32 x_total, y_total;
1414 ft = div_u64(1000000000000llu, fps);
1416 screen->mode.upper_margin + screen->mode.lower_margin +
1417 screen->mode.yres + screen->mode.vsync_len;
1419 screen->mode.left_margin + screen->mode.right_margin +
1420 screen->mode.xres + screen->mode.hsync_len;
1421 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1422 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1423 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1426 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1427 lcdc_dev->pixclock = pixclock;
1428 dev_drv->pixclock = pixclock;
1429 fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1430 screen->ft = 1000 / fps; /*one frame time in ms */
1433 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1434 clk_get_rate(lcdc_dev->dclk), fps);
1439 static int rk3036_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1441 struct lcdc_device *lcdc_dev =
1442 container_of(dev_drv, struct lcdc_device, driver);
1446 if (lcdc_dev->clk_on) {
1447 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1448 if (int_reg & m_LF_INT_STA) {
1449 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1451 ret = RK_LF_STATUS_FC;
1453 ret = RK_LF_STATUS_FR;
1456 ret = RK_LF_STATUS_NC;
1462 static int rk3036_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1463 unsigned int *dsp_addr)
1465 struct lcdc_device *lcdc_dev =
1466 container_of(dev_drv, struct lcdc_device, driver);
1468 if (lcdc_dev->clk_on) {
1469 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1470 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1475 static ssize_t rk3036_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1476 char *buf, int win_id)
1478 struct rk_lcdc_win *win = NULL;
1479 char fmt[9] = "NULL";
1482 if (win_id < ARRAY_SIZE(lcdc_win)) {
1483 win = dev_drv->win[win_id];
1485 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1489 size = snprintf(buf, PAGE_SIZE, "win%d: %s\n", win_id,
1490 get_format_string(win->area[0].format, fmt));
1491 size += snprintf(buf + size, PAGE_SIZE - size,
1492 " xact %d yact %d xvir %d yvir %d\n",
1493 win->area[0].xact, win->area[0].yact,
1494 win->area[0].xvir, win->area[0].yvir);
1495 size += snprintf(buf + size, PAGE_SIZE - size,
1496 " xpos %d ypos %d xsize %d ysize %d\n",
1497 win->area[0].xpos, win->area[0].ypos,
1498 win->area[0].xsize, win->area[0].ysize);
1499 size += snprintf(buf + size, PAGE_SIZE - size,
1500 " yaddr 0x%x uvaddr 0x%x\n",
1501 win->area[0].y_addr, win->area[0].uv_addr);
1505 static int rk3036_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1507 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1510 int *cbase = (int *)lcdc_dev->regs;
1511 int *regsbak = (int *)lcdc_dev->regsbak;
1514 dev_info(dev_drv->dev, "back up reg:\n");
1515 for (i = 0; i <= (0xDC >> 4); i++) {
1516 for (j = 0; j < 4; j++)
1517 dev_info(dev_drv->dev, "%08x ",
1518 *(regsbak + i * 4 + j));
1519 dev_info(dev_drv->dev, "\n");
1522 dev_info(dev_drv->dev, "lcdc reg:\n");
1523 for (i = 0; i <= (0xDC >> 4); i++) {
1524 for (j = 0; j < 4; j++)
1525 dev_info(dev_drv->dev, "%08x ",
1526 readl_relaxed(cbase + i * 4 + j));
1527 dev_info(dev_drv->dev, "\n");
1532 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1533 .open = rk3036_lcdc_open,
1534 .load_screen = rk3036_load_screen,
1535 .set_par = rk3036_lcdc_set_par,
1536 .pan_display = rk3036_lcdc_pan_display,
1537 .blank = rk3036_lcdc_blank,
1538 .ioctl = rk3036_lcdc_ioctl,
1539 .get_win_state = rk3036_lcdc_get_win_state,
1540 .ovl_mgr = rk3036_lcdc_ovl_mgr,
1541 .get_disp_info = rk3036_lcdc_get_disp_info,
1542 .fps_mgr = rk3036_lcdc_fps_mgr,
1543 .fb_get_win_id = rk3036_lcdc_get_win_id,
1544 .fb_win_remap = rk3036_fb_win_remap,
1545 .poll_vblank = rk3036_lcdc_poll_vblank,
1546 .get_dsp_addr = rk3036_lcdc_get_dsp_addr,
1547 .cfg_done = rk3036_lcdc_cfg_done,
1548 .dump_reg = rk3036_lcdc_reg_dump,
1549 .set_dsp_bcsh_hue = rk3036_lcdc_set_bcsh_hue,
1550 .set_dsp_bcsh_bcs = rk3036_lcdc_set_bcsh_bcs,
1551 .get_dsp_bcsh_hue = rk3036_lcdc_get_bcsh_hue,
1552 .get_dsp_bcsh_bcs = rk3036_lcdc_get_bcsh_bcs,
1553 .open_bcsh = rk3036_lcdc_open_bcsh,
1554 .set_overscan = rk3036_lcdc_set_overscan,
1555 .set_hwc_lut = rk3036_lcdc_set_hwc_lut,
1558 static int rk3036_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1560 struct device_node *np = lcdc_dev->dev->of_node;
1563 #if defined(CONFIG_ROCKCHIP_IOMMU)
1564 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1565 lcdc_dev->driver.iommu_enabled = 0;
1567 lcdc_dev->driver.iommu_enabled = val;
1569 lcdc_dev->driver.iommu_enabled = 0;
1571 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
1572 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
1574 lcdc_dev->driver.fb_win_map = val;
1579 static int rk3036_lcdc_probe(struct platform_device *pdev)
1581 struct lcdc_device *lcdc_dev = NULL;
1582 struct rk_lcdc_driver *dev_drv;
1583 struct device *dev = &pdev->dev;
1584 struct resource *res;
1587 lcdc_dev = devm_kzalloc(dev,
1588 sizeof(struct lcdc_device), GFP_KERNEL);
1590 dev_err(&pdev->dev, "rk3036 lcdc device kmalloc fail!");
1593 platform_set_drvdata(pdev, lcdc_dev);
1594 lcdc_dev->dev = dev;
1595 rk3036_lcdc_parse_dt(lcdc_dev);
1597 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1598 lcdc_dev->reg_phy_base = res->start;
1599 lcdc_dev->len = resource_size(res);
1600 lcdc_dev->regs = devm_ioremap_resource(dev, res);
1601 if (IS_ERR(lcdc_dev->regs))
1602 return PTR_ERR(lcdc_dev->regs);
1604 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1605 if (IS_ERR(lcdc_dev->regsbak))
1606 return PTR_ERR(lcdc_dev->regsbak);
1608 lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR);
1609 lcdc_dev->prop = PRMRY;
1610 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1611 dev_drv = &lcdc_dev->driver;
1613 dev_drv->prop = PRMRY;
1614 dev_drv->id = lcdc_dev->id;
1615 dev_drv->ops = &lcdc_drv_ops;
1616 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1617 spin_lock_init(&lcdc_dev->reg_lock);
1619 lcdc_dev->irq = platform_get_irq(pdev, 0);
1620 if (lcdc_dev->irq < 0) {
1621 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
1626 ret = devm_request_irq(dev, lcdc_dev->irq, rk3036_lcdc_isr,
1627 IRQF_DISABLED | IRQF_SHARED,
1628 dev_name(dev), lcdc_dev);
1630 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
1631 lcdc_dev->irq, ret);
1635 if (dev_drv->iommu_enabled)
1636 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
1638 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
1640 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
1643 lcdc_dev->screen = dev_drv->screen0;
1645 dev_info(dev, "lcdc probe ok, iommu %s\n",
1646 dev_drv->iommu_enabled ? "enabled" : "disabled");
1651 #if defined(CONFIG_PM)
1652 static int rk3036_lcdc_suspend(struct platform_device *pdev,
1658 static int rk3036_lcdc_resume(struct platform_device *pdev)
1663 #define rk3036_lcdc_suspend NULL
1664 #define rk3036_lcdc_resume NULL
1667 static int rk3036_lcdc_remove(struct platform_device *pdev)
1672 static void rk3036_lcdc_shutdown(struct platform_device *pdev)
1676 #if defined(CONFIG_OF)
1677 static const struct of_device_id rk3036_lcdc_dt_ids[] = {
1678 {.compatible = "rockchip,rk3036-lcdc",},
1683 static struct platform_driver rk3036_lcdc_driver = {
1684 .probe = rk3036_lcdc_probe,
1685 .remove = rk3036_lcdc_remove,
1687 .name = "rk3036-lcdc",
1688 .owner = THIS_MODULE,
1689 .of_match_table = of_match_ptr(rk3036_lcdc_dt_ids),
1691 .suspend = rk3036_lcdc_suspend,
1692 .resume = rk3036_lcdc_resume,
1693 .shutdown = rk3036_lcdc_shutdown,
1696 static int __init rk3036_lcdc_module_init(void)
1698 return platform_driver_register(&rk3036_lcdc_driver);
1701 static void __exit rk3036_lcdc_module_exit(void)
1703 platform_driver_unregister(&rk3036_lcdc_driver);
1706 fs_initcall(rk3036_lcdc_module_init);
1707 module_exit(rk3036_lcdc_module_exit);