drivers/video/rockchip/lcdc/rk3036_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3036_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:zhengyang<zhengyang@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <asm/div64.h>
  30 #include <linux/uaccess.h>
  31 #include <linux/rockchip/cpu.h>
  32 #include <linux/rockchip/iomap.h>
  33 #include <linux/rockchip/grf.h>
  34 #include <linux/rockchip/common.h>
  35 #include <dt-bindings/clock/rk_system_status.h>
  36 #if defined(CONFIG_ION_ROCKCHIP)
  37 #include <linux/rockchip-iovmm.h>
  38 #endif
  39 #include "rk3036_lcdc.h"
  40
  41 static int dbg_thresd;
  42 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  43
  44 #define DBG(level, x...) do {                   \
  45         if (unlikely(dbg_thresd >= level))      \
  46                 dev_info(dev_drv->dev, x);              \
  47         } while (0)
  48
  49 #define grf_writel(offset, v)   do { \
  50         writel_relaxed(v, RK_GRF_VIRT + offset); \
  51         dsb(); \
  52         } while (0)
  53
  54 static struct rk_lcdc_win lcdc_win[] = {
  55         [0] = {
  56                .name = "win0",
  57                .id = 0,
  58                .support_3d = false,
  59                },
  60         [1] = {
  61                .name = "win1",
  62                .id = 1,
  63                .support_3d = false,
  64                },
  65         [2] = {
  66                .name = "hwc",
  67                .id = 2,
  68                .support_3d = false,
  69                },
  70 };
  71
  72 static irqreturn_t rk3036_lcdc_isr(int irq, void *dev_id)
  73 {
  74         struct lcdc_device *lcdc_dev =
  75             (struct lcdc_device *)dev_id;
  76         ktime_t timestamp = ktime_get();
  77         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  78
  79         if (int_reg & m_FS_INT_STA) {
  80                 timestamp = ktime_get();
  81                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  82                              v_FS_INT_CLEAR(1));
  83                 /*if (lcdc_dev->driver.wait_fs) {*/
  84                 if (0) {
  85                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  86                         complete(&(lcdc_dev->driver.frame_done));
  87                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  88                 }
  89                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  90                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  91
  92         } else if (int_reg & m_LF_INT_STA) {
  93                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  94                              v_LF_INT_CLEAR(1));
  95         }
  96         return IRQ_HANDLED;
  97 }
  98
  99 static int rk3036_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 100 {
 101 #ifdef CONFIG_RK_FPGA
 102         lcdc_dev->clk_on = 1;
 103         return 0;
 104 #endif
 105         if (!lcdc_dev->clk_on) {
 106                 clk_prepare_enable(lcdc_dev->hclk);
 107                 clk_prepare_enable(lcdc_dev->dclk);
 108                 clk_prepare_enable(lcdc_dev->aclk);
 109 /*              clk_prepare_enable(lcdc_dev->pd);*/
 110                 spin_lock(&lcdc_dev->reg_lock);
 111                 lcdc_dev->clk_on = 1;
 112                 spin_unlock(&lcdc_dev->reg_lock);
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int rk3036_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 0;
 122         return 0;
 123 #endif
 124         if (lcdc_dev->clk_on) {
 125                 spin_lock(&lcdc_dev->reg_lock);
 126                 lcdc_dev->clk_on = 0;
 127                 spin_unlock(&lcdc_dev->reg_lock);
 128                 mdelay(25);
 129                 clk_disable_unprepare(lcdc_dev->dclk);
 130                 clk_disable_unprepare(lcdc_dev->hclk);
 131                 clk_disable_unprepare(lcdc_dev->aclk);
 132 /*              clk_disable_unprepare(lcdc_dev->pd);*/
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk3036_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 139 {
 140         u32 mask, val;
 141         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 142                                         struct lcdc_device, driver);
 143         mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 144         val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1);
 145         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 146         return 0;
 147 }
 148
 149 static int rk3036_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 150 {
 151         u32 mask, val;
 152
 153         spin_lock(&lcdc_dev->reg_lock);
 154         if (likely(lcdc_dev->clk_on)) {
 155                 mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 156                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0);
 157                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         } else {
 160                 spin_unlock(&lcdc_dev->reg_lock);
 161         }
 162         mdelay(1);
 163         return 0;
 164 }
 165
 166 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device
 167                                              *lcdc_dev)
 168 {
 169         int reg = 0;
 170         u32 value = 0;
 171
 172         spin_lock(&lcdc_dev->reg_lock);
 173         for (reg = 0; reg < 0xdc; reg += 4)
 174                 value = lcdc_readl(lcdc_dev, reg);
 175
 176         spin_unlock(&lcdc_dev->reg_lock);
 177 }
 178
 179 static int rk3036_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 180 {
 181         int win0_top = 0;
 182         u32 mask, val;
 183         enum data_format win0_format = lcdc_dev->driver.win[0]->format;
 184         enum data_format win1_format = lcdc_dev->driver.win[1]->format;
 185
 186         int win0_alpha_en = ((win0_format == ARGB888) ||
 187                                 (win0_format == ABGR888)) ? 1 : 0;
 188         int win1_alpha_en = ((win1_format == ARGB888) ||
 189                                 (win1_format == ABGR888)) ? 1 : 0;
 190         u32 *_pv = (u32 *)lcdc_dev->regsbak;
 191
 192         _pv += (DSP_CTRL0 >> 2);
 193         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 194         if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) {
 195                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 196                         m_WIN1_PREMUL_SCALE;
 197                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0) |
 198                         v_WIN1_PREMUL_SCALE(0);
 199                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 200
 201                 mask = m_WIN0_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 202                         m_ALPHA_MODE_SEL1;
 203                 val = v_WIN0_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 204                         v_ALPHA_MODE_SEL1(0);
 205                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 206         } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2) &&
 207                    (win1_alpha_en)) {
 208                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 209                         m_WIN1_PREMUL_SCALE;
 210                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1) |
 211                         v_WIN1_PREMUL_SCALE(0);
 212                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 213
 214                 mask = m_WIN1_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 215                         m_ALPHA_MODE_SEL1;
 216                 val = v_WIN1_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 217                         v_ALPHA_MODE_SEL1(0);
 218                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 219         } else {
 220                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 221                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 222                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 223         }
 224         return 0;
 225 }
 226
 227 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 228                                    struct rk_lcdc_win *win)
 229 {
 230         u32 mask, val;
 231
 232         if (win->state == 1) {
 233                 if (win->id == 0) {
 234                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 235                         val = v_WIN0_EN(win->state) |
 236                               v_WIN0_FORMAT(win->fmt_cfg) |
 237                               v_WIN0_RB_SWAP(win->swap_rb);
 238                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 239                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_INTERLACE_EN,
 240                                      v_WIN0_INTERLACE_EN(win->interlace_read));
 241                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 242                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 243                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 244                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 245                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 246                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 247                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 248                                      m_YRGB_VIR | m_CBBR_VIR,
 249                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 250                                      v_CBBR_VIR(win->area[0].uv_vir_stride));
 251                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 252                                     v_ACT_WIDTH(win->area[0].xact) |
 253                                     v_ACT_HEIGHT(win->area[0].yact));
 254                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 255                                     v_DSP_STX(win->area[0].dsp_stx) |
 256                                     v_DSP_STY(win->area[0].dsp_sty));
 257                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 258                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 259                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 260
 261                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 262                                     win->area[0].y_addr);
 263                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 264                                     win->area[0].uv_addr);
 265                 } else if (win->id == 1) {
 266                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 267                         val = v_WIN1_EN(win->state) |
 268                               v_WIN1_FORMAT(win->fmt_cfg) |
 269                               v_WIN1_RB_SWAP(win->swap_rb);
 270                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 271                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_INTERLACE_EN,
 272                                      v_WIN1_INTERLACE_EN(win->interlace_read));
 273                         lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 274                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 275                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 276
 277                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 278                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 279                         lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 280                                     v_ACT_WIDTH(win->area[0].xact) |
 281                                     v_ACT_HEIGHT(win->area[0].yact));
 282                         lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 283                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 284                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 285                         lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 286                                     v_DSP_STX(win->area[0].dsp_stx) |
 287                                     v_DSP_STY(win->area[0].dsp_sty));
 288                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 289                 } /* else if (win->id == 2) {
 290                 }*/
 291         } else {
 292                 win->area[0].y_addr = 0;
 293                 win->area[0].uv_addr = 0;
 294                 if (win->id == 0)
 295                         lcdc_msk_reg(lcdc_dev,
 296                                      SYS_CTRL, m_WIN0_EN, v_WIN0_EN(0));
 297                 else if (win->id == 1)
 298                         lcdc_msk_reg(lcdc_dev,
 299                                      SYS_CTRL, m_WIN1_EN, v_WIN1_EN(0));
 300                 else if (win->id == 2)
 301                         lcdc_msk_reg(lcdc_dev,
 302                                      SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
 303         }
 304         rk3036_lcdc_alpha_cfg(lcdc_dev);
 305 }
 306
 307 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev,
 308                               unsigned int win_id, bool open)
 309 {
 310         spin_lock(&lcdc_dev->reg_lock);
 311         if (likely(lcdc_dev->clk_on) &&
 312             lcdc_dev->driver.win[win_id]->state != open) {
 313                 if (open) {
 314                         if (!lcdc_dev->atv_layer_cnt) {
 315                                 dev_info(lcdc_dev->dev,
 316                                          "wakeup from standby!\n");
 317                                 lcdc_dev->standby = 0;
 318                         }
 319                         lcdc_dev->atv_layer_cnt++;
 320                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
 321                         lcdc_dev->atv_layer_cnt--;
 322                 }
 323                 lcdc_dev->driver.win[win_id]->state = open;
 324                 if (!open) {
 325                         lcdc_layer_update_regs(lcdc_dev,
 326                                                lcdc_dev->driver.win[win_id]);
 327                         lcdc_cfg_done(lcdc_dev);
 328                 }
 329                 /*if no layer used,disable lcdc*/
 330                 if (!lcdc_dev->atv_layer_cnt) {
 331                         dev_info(lcdc_dev->dev,
 332                                  "no layer is used, go to standby!\n");
 333                         lcdc_dev->standby = 1;
 334                 }
 335         }
 336         spin_unlock(&lcdc_dev->reg_lock);
 337 }
 338
 339 static int rk3036_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 340 {
 341         struct lcdc_device *lcdc_dev =
 342             container_of(dev_drv, struct lcdc_device, driver);
 343         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 344         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 345         int timeout;
 346         unsigned long flags;
 347
 348         spin_lock(&lcdc_dev->reg_lock);
 349         if (likely(lcdc_dev->clk_on)) {
 350                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 351                              v_LCDC_STANDBY(lcdc_dev->standby));
 352                 lcdc_layer_update_regs(lcdc_dev, win0);
 353                 lcdc_layer_update_regs(lcdc_dev, win1);
 354                 rk3036_lcdc_alpha_cfg(lcdc_dev);
 355                 lcdc_cfg_done(lcdc_dev);
 356         }
 357         spin_unlock(&lcdc_dev->reg_lock);
 358         /* if (dev_drv->wait_fs) { */
 359         if (0) {
 360                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 361                 init_completion(&dev_drv->frame_done);
 362                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 363                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 364                                                       msecs_to_jiffies
 365                                                       (dev_drv->cur_screen->ft
 366                                                        + 5));
 367                 if (!timeout && (!dev_drv->frame_done.done)) {
 368                         dev_warn(lcdc_dev->dev,
 369                                  "wait for new frame start time out!\n");
 370                         return -ETIMEDOUT;
 371                 }
 372         }
 373         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 374         return 0;
 375 }
 376
 377 static void rk3036_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 378 {
 379         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xdc);
 380 }
 381
 382 static void rk3036_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 383 {
 384         u32 mask, val;
 385         struct lcdc_device *lcdc_dev =
 386             container_of(dev_drv, struct lcdc_device, driver);
 387
 388         spin_lock(&lcdc_dev->reg_lock);
 389         if (likely(lcdc_dev->clk_on)) {
 390                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 391                         m_AXI_OUTSTANDING_MAX_NUM;
 392                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 393                         v_AXI_MAX_OUTSTANDING_EN(1);
 394                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 395         }
 396         spin_unlock(&lcdc_dev->reg_lock);
 397 }
 398
 399 static int rk3036_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 400 {
 401 #ifdef CONFIG_RK_FPGA
 402         return 0;
 403 #endif
 404         int ret, fps;
 405         struct lcdc_device *lcdc_dev =
 406             container_of(dev_drv, struct lcdc_device, driver);
 407         struct rk_screen *screen = dev_drv->cur_screen;
 408
 409         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 410         if (ret)
 411                 dev_err(dev_drv->dev,
 412                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 413         lcdc_dev->pixclock =
 414                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 415         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 416
 417         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 418         screen->ft = 1000 / fps;
 419         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 420                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 421         return 0;
 422 }
 423
 424 /********do basic init*********/
 425 static int rk3036_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 426 {
 427         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 428                                 struct lcdc_device, driver);
 429
 430         if (lcdc_dev->pre_init)
 431                 return 0;
 432         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 433         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 434         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 435 /*      lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); */
 436
 437         if (/*IS_ERR(lcdc_dev->pd) ||*/ (IS_ERR(lcdc_dev->aclk)) ||
 438             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 439                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 440                         lcdc_dev->id);
 441         }
 442
 443         rk_disp_pwr_enable(dev_drv);
 444         rk3036_lcdc_clk_enable(lcdc_dev);
 445
 446         /*backup reg config at uboot*/
 447         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 448         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN,
 449                      v_AUTO_GATING_EN(0));
 450         lcdc_cfg_done(lcdc_dev);
 451         if (dev_drv->iommu_enabled)
 452                 /*disable win0 to workaround iommu pagefault*/
 453                 lcdc_layer_enable(lcdc_dev, 0, 0);
 454         lcdc_dev->pre_init = true;
 455
 456         return 0;
 457 }
 458
 459 static int rk3036_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 460 {
 461         int ret = -EINVAL;
 462         int fps;
 463         u16 face = 0;
 464         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 465                                                 struct lcdc_device, driver);
 466         struct rk_screen *screen = dev_drv->cur_screen;
 467         u16 right_margin = screen->mode.right_margin;
 468         u16 left_margin = screen->mode.left_margin;
 469         u16 lower_margin = screen->mode.lower_margin;
 470         u16 upper_margin = screen->mode.upper_margin;
 471         u16 x_res = screen->mode.xres;
 472         u16 y_res = screen->mode.yres;
 473         u32 mask, val;
 474
 475         spin_lock(&lcdc_dev->reg_lock);
 476         if (likely(lcdc_dev->clk_on)) {
 477                 switch (screen->type) {
 478                 case SCREEN_HDMI:
 479                         mask = m_HDMI_DCLK_EN;
 480                         val = v_HDMI_DCLK_EN(1);
 481                         if (screen->pixelrepeat) {
 482                                 mask |= m_CORE_CLK_DIV_EN;
 483                                 val |= v_CORE_CLK_DIV_EN(1);
 484                         } else {
 485                                 mask |= m_CORE_CLK_DIV_EN;
 486                                 val |= v_CORE_CLK_DIV_EN(0);
 487                         }
 488                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 489                         mask = (1 << 4) | (1 << 5) | (1 << 6);
 490                         val = (screen->pin_hsync << 4) |
 491                                 (screen->pin_vsync << 5) |
 492                                 (screen->pin_den << 6);
 493                         grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
 494                         break;
 495                 case SCREEN_TVOUT:
 496                         mask = m_TVE_DAC_DCLK_EN;
 497                         val = v_TVE_DAC_DCLK_EN(1);
 498                         if (screen->pixelrepeat) {
 499                                 mask |= m_CORE_CLK_DIV_EN;
 500                                 val |= v_CORE_CLK_DIV_EN(1);
 501                         } else {
 502                                 mask |= m_CORE_CLK_DIV_EN;
 503                                 val |= v_CORE_CLK_DIV_EN(0);
 504                         }
 505                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 506                         if ((x_res == 720) && (y_res == 576)) {
 507                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 508                                              m_TVE_MODE, v_TVE_MODE(TV_PAL));
 509                         } else if ((x_res == 720) && (y_res == 480)) {
 510                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 511                                              m_TVE_MODE, v_TVE_MODE(TV_NTSC));
 512                         } else {
 513                                 dev_err(lcdc_dev->dev,
 514                                         "unsupported video timing!\n");
 515                                 return -1;
 516                         }
 517                         break;
 518                 default:
 519                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 520                         break;
 521                 }
 522
 523                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 524                     m_DEN_POL | m_DCLK_POL;
 525                 val = v_DSP_OUT_FORMAT(face) |
 526                         v_HSYNC_POL(screen->pin_hsync) |
 527                         v_VSYNC_POL(screen->pin_vsync) |
 528                         v_DEN_POL(screen->pin_den) |
 529                         v_DCLK_POL(screen->pin_dclk);
 530                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 531
 532                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 533                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
 534                     m_DSP_DUMMY_SWAP | m_BLANK_EN;
 535
 536                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
 537                     v_DSP_RB_SWAP(screen->swap_rb) |
 538                     v_DSP_RG_SWAP(screen->swap_rg) |
 539                     v_DSP_DELTA_SWAP(screen->swap_delta) |
 540                                      v_DSP_DUMMY_SWAP(screen->swap_dumy) |
 541                                                       v_BLANK_EN(0) |
 542                                      v_BLACK_EN(0);
 543                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 544                 val =
 545                     v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode.
 546                                                                hsync_len +
 547                                                                left_margin +
 548                                                                x_res +
 549                                                                right_margin);
 550                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
 551                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
 552                     v_HASP(screen->mode.hsync_len + left_margin);
 553                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
 554
 555                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 556                         /*First Field Timing*/
 557                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
 558                                     v_VSYNC(screen->mode.vsync_len) |
 559                                     v_VERPRD(2 * (screen->mode.vsync_len +
 560                                                   upper_margin + lower_margin)
 561                                              + y_res + 1));
 562                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
 563                                     v_VAEP(screen->mode.vsync_len +
 564                                         upper_margin + y_res/2) |
 565                                     v_VASP(screen->mode.vsync_len +
 566                                         upper_margin));
 567                         /*Second Field Timing*/
 568                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
 569                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
 570                                                   upper_margin + y_res/2 +
 571                                                   lower_margin) |
 572                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len
 573                                                    + upper_margin + y_res/2 +
 574                                                    lower_margin));
 575                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
 576                                     v_VAEP(2 * (screen->mode.vsync_len +
 577                                                 upper_margin) + y_res +
 578                                                 lower_margin + 1) |
 579                                     v_VASP(2 * (screen->mode.vsync_len +
 580                                                 upper_margin) + y_res/2 +
 581                                                 lower_margin + 1));
 582
 583                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 584                                      m_INTERLACE_DSP_EN |
 585                                      m_INTERLACE_DSP_POL |
 586                                      m_WIN1_DIFF_DCLK_EN |
 587                                      m_WIN0_YRGB_DEFLICK_EN |
 588                                      m_WIN0_CBR_DEFLICK_EN,
 589                                      v_INTERLACE_DSP_EN(1) |
 590                                      v_INTERLACE_DSP_POL(0) |
 591                                      v_WIN1_DIFF_DCLK_EN(1) |
 592                                      v_WIN0_YRGB_DEFLICK_EN(1) |
 593                                      v_WIN0_CBR_DEFLICK_EN(1));
 594                 } else {
 595                         val = v_VSYNC(screen->mode.vsync_len) |
 596                               v_VERPRD(screen->mode.vsync_len + upper_margin +
 597                                         y_res + lower_margin);
 598                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
 599
 600                         val = v_VAEP(screen->mode.vsync_len +
 601                                      upper_margin + y_res) |
 602                             v_VASP(screen->mode.vsync_len +
 603                                    screen->mode.upper_margin);
 604                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
 605
 606                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 607                                      m_INTERLACE_DSP_EN |
 608                                      m_WIN1_DIFF_DCLK_EN |
 609                                      m_WIN0_YRGB_DEFLICK_EN |
 610                                      m_WIN0_CBR_DEFLICK_EN,
 611                                      v_INTERLACE_DSP_EN(0) |
 612                                      v_WIN1_DIFF_DCLK_EN(0) |
 613                                      v_WIN0_YRGB_DEFLICK_EN(0) |
 614                                      v_WIN0_CBR_DEFLICK_EN(0));
 615                 }
 616         }
 617         spin_unlock(&lcdc_dev->reg_lock);
 618
 619         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 620         if (ret)
 621                 dev_err(dev_drv->dev,
 622                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 623         lcdc_dev->pixclock =
 624             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 625         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 626
 627         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 628         screen->ft = 1000 / fps;
 629         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 630                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 631         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
 632                 dev_drv->trsm_ops->enable();
 633         if (screen->init)
 634                 screen->init();
 635
 636         return 0;
 637 }
 638
 639 static int rk3036_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
 640                             bool open)
 641 {
 642         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 643                                         struct lcdc_device, driver);
 644
 645         /*enable clk,when first layer open */
 646         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
 647                 rk3036_lcdc_pre_init(dev_drv);
 648                 rk3036_lcdc_clk_enable(lcdc_dev);
 649         #if defined(CONFIG_ROCKCHIP_IOMMU)
 650                 if (dev_drv->iommu_enabled) {
 651                         if (!dev_drv->mmu_dev) {
 652                                 dev_drv->mmu_dev =
 653                                 rk_fb_get_sysmmu_device_by_compatible(
 654                                         dev_drv->mmu_dts_name);
 655                                 if (dev_drv->mmu_dev) {
 656                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
 657                                                             dev_drv->dev);
 658                                         rockchip_iovmm_activate(dev_drv->dev);
 659                                 } else {
 660                                         dev_err(dev_drv->dev,
 661                                                 "failed to get iommu device\n"
 662                                                 );
 663                                         return -1;
 664                                 }
 665                         }
 666                 }
 667         #endif
 668                 rk3036_lcdc_reg_restore(lcdc_dev);
 669                 if (dev_drv->iommu_enabled)
 670                         rk3036_lcdc_mmu_en(dev_drv);
 671                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
 672                         rk3036_lcdc_set_dclk(dev_drv);
 673                         rk3036_lcdc_enable_irq(dev_drv);
 674                 } else {
 675                         rk3036_load_screen(dev_drv, 1);
 676                 }
 677         }
 678
 679         if (win_id < ARRAY_SIZE(lcdc_win))
 680                 lcdc_layer_enable(lcdc_dev, win_id, open);
 681         else
 682                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
 683
 684         /*when all layer closed,disable clk */
 685         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
 686                 rk3036_lcdc_disable_irq(lcdc_dev);
 687                 rk3036_lcdc_reg_update(dev_drv);
 688                 #if defined(CONFIG_ROCKCHIP_IOMMU)
 689                 if (dev_drv->iommu_enabled) {
 690                         if (dev_drv->mmu_dev)
 691                                 rockchip_iovmm_deactivate(dev_drv->dev);
 692                 }
 693                 #endif
 694                 rk3036_lcdc_clk_disable(lcdc_dev);
 695         }
 696
 697         return 0;
 698 }
 699
 700 static int rk3036_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
 701 {
 702         struct lcdc_device *lcdc_dev =
 703                         container_of(dev_drv, struct lcdc_device, driver);
 704         struct rk_screen *screen = dev_drv->cur_screen;
 705         struct rk_lcdc_win *win = NULL;
 706         char fmt[9] = "NULL";
 707
 708         if (!screen) {
 709                 dev_err(dev_drv->dev, "screen is null!\n");
 710                 return -ENOENT;
 711         }
 712
 713         if (win_id == 0) {
 714                 win = dev_drv->win[0];
 715         } else if (win_id == 1) {
 716                 win = dev_drv->win[1];
 717         } else {
 718                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
 719                 return -EINVAL;
 720         }
 721
 722         spin_lock(&lcdc_dev->reg_lock);
 723         win->post_cfg.xpos = win->area[0].xpos * (dev_drv->overscan.left +
 724                 dev_drv->overscan.right)/200 + screen->mode.xres *
 725                         (100 - dev_drv->overscan.left) / 200;
 726
 727         win->post_cfg.ypos = win->area[0].ypos * (dev_drv->overscan.top +
 728                 dev_drv->overscan.bottom)/200 +
 729                 screen->mode.yres *
 730                         (100 - dev_drv->overscan.top) / 200;
 731         win->post_cfg.xsize = win->area[0].xsize *
 732                                 (dev_drv->overscan.left +
 733                                 dev_drv->overscan.right)/200;
 734         win->post_cfg.ysize = win->area[0].ysize *
 735                                 (dev_drv->overscan.top +
 736                                 dev_drv->overscan.bottom)/200;
 737
 738         win->area[0].dsp_stx = win->post_cfg.xpos + screen->mode.left_margin +
 739                                 screen->mode.hsync_len;
 740         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 741                 win->post_cfg.ysize /= 2;
 742                 win->area[0].dsp_sty = win->post_cfg.ypos/2 +
 743                                         screen->mode.upper_margin +
 744                                         screen->mode.vsync_len;
 745         } else {
 746                 win->area[0].dsp_sty = win->post_cfg.ypos +
 747                                         screen->mode.upper_margin +
 748                                         screen->mode.vsync_len;
 749         }
 750         win->scale_yrgb_x = calscale(win->area[0].xact, win->post_cfg.xsize);
 751         win->scale_yrgb_y = calscale(win->area[0].yact, win->post_cfg.ysize);
 752         win->interlace_read = 0;
 753         if((screen->mode.xres == 720) &&
 754           ((screen->mode.yres == 576) || (screen->mode.yres == 480))) {
 755                 if(win->scale_yrgb_y > 2*0x1000)
 756                         win->interlace_read = 1;
 757         }
 758         switch (win->format) {
 759         case ARGB888:
 760                 win->fmt_cfg = VOP_FORMAT_ARGB888;
 761                 win->swap_rb = 0;
 762                 break;
 763         case XBGR888:
 764                 win->fmt_cfg = VOP_FORMAT_ARGB888;
 765                 win->swap_rb = 1;
 766                 break;
 767         case ABGR888:
 768                 win->fmt_cfg = VOP_FORMAT_ARGB888;
 769                 win->swap_rb = 1;
 770                 break;
 771         case RGB888:
 772                 win->fmt_cfg = VOP_FORMAT_RGB888;
 773                 win->swap_rb = 0;
 774                 break;
 775         case RGB565:
 776                 win->fmt_cfg = VOP_FORMAT_RGB565;
 777                 win->swap_rb = 0;
 778                 break;
 779         case YUV444:
 780                 if (win_id == 0) {
 781                         win->fmt_cfg = VOP_FORMAT_YCBCR444;
 782                         win->scale_cbcr_x = calscale(win->area[0].xact,
 783                                                      win->post_cfg.xsize);
 784                         win->scale_cbcr_y = calscale(win->area[0].yact,
 785                                                      win->post_cfg.ysize);
 786                         win->swap_rb = 0;
 787                 } else {
 788                         dev_err(lcdc_dev->driver.dev,
 789                                 "%s:un supported format!\n",
 790                                 __func__);
 791                 }
 792                 break;
 793         case YUV422:
 794                 if (win_id == 0) {
 795                         win->fmt_cfg = VOP_FORMAT_YCBCR422;
 796                         win->scale_cbcr_x = calscale((win->area[0].xact / 2),
 797                                                      win->post_cfg.xsize);
 798                         win->scale_cbcr_y = calscale(win->area[0].yact,
 799                                                      win->post_cfg.ysize);
 800                         win->swap_rb = 0;
 801                 } else {
 802                         dev_err(lcdc_dev->driver.dev,
 803                                 "%s:un supported format!\n",
 804                                 __func__);
 805                 }
 806                 break;
 807         case YUV420:
 808                 if (win_id == 0) {
 809                         win->fmt_cfg = VOP_FORMAT_YCBCR420;
 810                         win->scale_cbcr_x = calscale(win->area[0].xact / 2,
 811                                                      win->post_cfg.xsize);
 812                         win->scale_cbcr_y = calscale(win->area[0].yact / 2,
 813                                                      win->post_cfg.ysize);
 814                         win->swap_rb = 0;
 815                 } else {
 816                         dev_err(lcdc_dev->driver.dev,
 817                                 "%s:un supported format!\n",
 818                                 __func__);
 819                 }
 820                 break;
 821         default:
 822                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
 823                         __func__);
 824                 break;
 825         }
 826         spin_unlock(&lcdc_dev->reg_lock);
 827
 828         DBG(2, "lcdc%d>>%s\n"
 829                 ">>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
 830                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
 831                 __func__, get_format_string(win->format, fmt),
 832                 win->area[0].xact, win->area[0].yact, win->post_cfg.xsize,
 833                 win->post_cfg.ysize, win->area[0].xvir, win->area[0].yvir,
 834                 win->post_cfg.xpos, win->post_cfg.ypos);
 835         return 0;
 836 }
 837
 838 static int rk3036_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
 839 {
 840         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 841                                                 struct lcdc_device, driver);
 842         struct rk_lcdc_win *win = NULL;
 843         struct rk_screen *screen = dev_drv->cur_screen;
 844
 845         if (!screen) {
 846                 dev_err(dev_drv->dev, "screen is null!\n");
 847                 return -ENOENT;
 848         }
 849
 850         if (win_id == 0) {
 851                 win = dev_drv->win[0];
 852         } else if (win_id == 1) {
 853                 win = dev_drv->win[1];
 854         } else {
 855                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
 856                 return -EINVAL;
 857         }
 858
 859         spin_lock(&lcdc_dev->reg_lock);
 860         if (likely(lcdc_dev->clk_on)) {
 861                 win->area[0].y_addr = win->area[0].smem_start +
 862                                         win->area[0].y_offset;
 863                 win->area[0].uv_addr = win->area[0].cbr_start +
 864                                         win->area[0].c_offset;
 865                 if (win->area[0].y_addr)
 866                         lcdc_layer_update_regs(lcdc_dev, win);
 867                 /*lcdc_cfg_done(lcdc_dev);*/
 868         }
 869         spin_unlock(&lcdc_dev->reg_lock);
 870
 871         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
 872             lcdc_dev->id, __func__, win->area[0].y_addr,
 873             win->area[0].uv_addr, win->area[0].y_offset);
 874          /* this is the first frame of the system,
 875                 enable frame start interrupt*/
 876         if ((dev_drv->first_frame))  {
 877                 dev_drv->first_frame = 0;
 878                 rk3036_lcdc_enable_irq(dev_drv);
 879         }
 880         return 0;
 881 }
 882
 883 static int rk3036_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
 884                              unsigned long arg, int win_id)
 885 {
 886         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 887                                         struct lcdc_device, driver);
 888         u32 panel_size[2];
 889         void __user *argp = (void __user *)arg;
 890         struct color_key_cfg clr_key_cfg;
 891
 892         switch (cmd) {
 893         case RK_FBIOGET_PANEL_SIZE:
 894                 panel_size[0] = lcdc_dev->screen->mode.xres;
 895                 panel_size[1] = lcdc_dev->screen->mode.yres;
 896                 if (copy_to_user(argp, panel_size, 8))
 897                         return -EFAULT;
 898                 break;
 899         case RK_FBIOPUT_COLOR_KEY_CFG:
 900                 if (copy_from_user(&clr_key_cfg, argp,
 901                                    sizeof(struct color_key_cfg)))
 902                         return -EFAULT;
 903                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
 904                             clr_key_cfg.win0_color_key_cfg);
 905                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
 906                             clr_key_cfg.win1_color_key_cfg);
 907                 break;
 908
 909         default:
 910                 break;
 911         }
 912         return 0;
 913 }
 914
 915 static int rk3036_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
 916                                   const char *id)
 917 {
 918         int win_id = 0;
 919
 920         mutex_lock(&dev_drv->fb_win_id_mutex);
 921         if (!strcmp(id, "fb0"))
 922                 win_id = dev_drv->fb0_win_id;
 923         else if (!strcmp(id, "fb1"))
 924                 win_id = dev_drv->fb1_win_id;
 925         else if (!strcmp(id, "fb2"))
 926                 win_id = dev_drv->fb2_win_id;
 927         mutex_unlock(&dev_drv->fb_win_id_mutex);
 928
 929         return win_id;
 930 }
 931
 932 static int rk3036_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
 933                                      int win_id)
 934 {
 935         return dev_drv->win[win_id]->state;
 936 }
 937
 938 static int rk3036_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
 939                                bool set)
 940 {
 941         struct lcdc_device *lcdc_dev =
 942             container_of(dev_drv, struct lcdc_device, driver);
 943         int ovl;
 944
 945         spin_lock(&lcdc_dev->reg_lock);
 946         if (lcdc_dev->clk_on) {
 947                 if (set) {
 948                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
 949                                      v_WIN0_TOP(swap));
 950                         ovl = swap;
 951                 } else {
 952                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
 953                 }
 954         } else {
 955                 ovl = -EPERM;
 956         }
 957         spin_unlock(&lcdc_dev->reg_lock);
 958
 959         return ovl;
 960 }
 961
 962 static int rk3036_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
 963 {
 964         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 965                                         struct lcdc_device, driver);
 966         if (dev_drv->suspend_flag)
 967                 return 0;
 968         dev_drv->suspend_flag = 1;
 969         flush_kthread_worker(&dev_drv->update_regs_worker);
 970
 971         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
 972                 dev_drv->trsm_ops->disable();
 973         spin_lock(&lcdc_dev->reg_lock);
 974         if (likely(lcdc_dev->clk_on)) {
 975                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
 976                              v_BLANK_EN(1));
 977                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
 978                              v_FS_INT_CLEAR(1));
 979                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
 980                              v_DSP_OUT_ZERO(1));
 981                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 982                              v_LCDC_STANDBY(1));
 983                 lcdc_cfg_done(lcdc_dev);
 984                 if (dev_drv->iommu_enabled) {
 985                         if (dev_drv->mmu_dev)
 986                                 rockchip_iovmm_deactivate(dev_drv->dev);
 987                 }
 988                 spin_unlock(&lcdc_dev->reg_lock);
 989         } else {
 990                 spin_unlock(&lcdc_dev->reg_lock);
 991                 return 0;
 992         }
 993         rk3036_lcdc_clk_disable(lcdc_dev);
 994         rk_disp_pwr_disable(dev_drv);
 995         return 0;
 996 }
 997
 998 static int rk3036_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
 999 {
1000         struct lcdc_device *lcdc_dev =
1001             container_of(dev_drv, struct lcdc_device, driver);
1002
1003         if (!dev_drv->suspend_flag)
1004                 return 0;
1005         rk_disp_pwr_enable(dev_drv);
1006         dev_drv->suspend_flag = 0;
1007
1008         if (lcdc_dev->atv_layer_cnt) {
1009                 rk3036_lcdc_clk_enable(lcdc_dev);
1010                 rk3036_lcdc_reg_restore(lcdc_dev);
1011
1012                 spin_lock(&lcdc_dev->reg_lock);
1013
1014                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1015                              v_DSP_OUT_ZERO(0));
1016                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1017                              v_LCDC_STANDBY(0));
1018                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1019                              v_BLANK_EN(0));
1020                 lcdc_cfg_done(lcdc_dev);
1021                 if (dev_drv->iommu_enabled) {
1022                         if (dev_drv->mmu_dev)
1023                                 rockchip_iovmm_activate(dev_drv->dev);
1024                 }
1025                 spin_unlock(&lcdc_dev->reg_lock);
1026         }
1027
1028         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1029                 dev_drv->trsm_ops->enable();
1030         return 0;
1031 }
1032
1033
1034 static int rk3036_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1035                              int win_id, int blank_mode)
1036 {
1037         switch (blank_mode) {
1038         case FB_BLANK_UNBLANK:
1039                 rk3036_lcdc_early_resume(dev_drv);
1040                 break;
1041         case FB_BLANK_NORMAL:
1042                 rk3036_lcdc_early_suspend(dev_drv);
1043                 break;
1044         default:
1045                 rk3036_lcdc_early_suspend(dev_drv);
1046                 break;
1047         }
1048
1049         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1050
1051         return 0;
1052 }
1053
1054 static int rk3036_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1055 {
1056         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1057                                         struct lcdc_device, driver);
1058
1059         spin_lock(&lcdc_dev->reg_lock);
1060         if (lcdc_dev->clk_on) {
1061                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1062                              v_LCDC_STANDBY(lcdc_dev->standby));
1063                 lcdc_cfg_done(lcdc_dev);
1064         }
1065         spin_unlock(&lcdc_dev->reg_lock);
1066         return 0;
1067 }
1068
1069 /*
1070         a:[-30~0]:
1071             sin_hue = sin(a)*256 +0x100;
1072             cos_hue = cos(a)*256;
1073         a:[0~30]
1074             sin_hue = sin(a)*256;
1075             cos_hue = cos(a)*256;
1076 */
1077 static int rk3036_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1078                                     bcsh_hue_mode mode)
1079 {
1080         struct lcdc_device *lcdc_dev =
1081             container_of(dev_drv, struct lcdc_device, driver);
1082         u32 val;
1083
1084         spin_lock(&lcdc_dev->reg_lock);
1085         if (lcdc_dev->clk_on) {
1086                 val = lcdc_readl(lcdc_dev, BCSH_H);
1087                 switch (mode) {
1088                 case H_SIN:
1089                         val &= m_BCSH_SIN_HUE;
1090                         break;
1091                 case H_COS:
1092                         val &= m_BCSH_COS_HUE;
1093                         val >>= 8;
1094                         break;
1095                 default:
1096                         break;
1097                 }
1098         }
1099         spin_unlock(&lcdc_dev->reg_lock);
1100
1101         return val;
1102 }
1103
1104
1105 static int rk3036_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1106                                     int sin_hue, int cos_hue)
1107 {
1108         struct lcdc_device *lcdc_dev =
1109             container_of(dev_drv, struct lcdc_device, driver);
1110         u32 mask, val;
1111
1112         spin_lock(&lcdc_dev->reg_lock);
1113         if (lcdc_dev->clk_on) {
1114                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1115                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1116                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1117                 lcdc_cfg_done(lcdc_dev);
1118         }
1119         spin_unlock(&lcdc_dev->reg_lock);
1120
1121         return 0;
1122 }
1123
1124 static int rk3036_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1125                                     bcsh_bcs_mode mode, int value)
1126 {
1127         struct lcdc_device *lcdc_dev =
1128             container_of(dev_drv, struct lcdc_device, driver);
1129         u32 mask, val;
1130
1131         spin_lock(&lcdc_dev->reg_lock);
1132         if (lcdc_dev->clk_on) {
1133                 switch (mode) {
1134                 case BRIGHTNESS:
1135                 /*from 0 to 255,typical is 128*/
1136                         if (value < 0x20)
1137                                 value += 0x20;
1138                         else if (value >= 0x20)
1139                                 value = value - 0x20;
1140                         mask =  m_BCSH_BRIGHTNESS;
1141                         val = v_BCSH_BRIGHTNESS(value);
1142                         break;
1143                 case CONTRAST:
1144                 /*from 0 to 510,typical is 256*/
1145                         mask =  m_BCSH_CONTRAST;
1146                         val =  v_BCSH_CONTRAST(value);
1147                         break;
1148                 case SAT_CON:
1149                 /*from 0 to 1015,typical is 256*/
1150                         mask = m_BCSH_SAT_CON;
1151                         val = v_BCSH_SAT_CON(value);
1152                         break;
1153                 default:
1154                         break;
1155                 }
1156                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1157                 lcdc_cfg_done(lcdc_dev);
1158         }
1159         spin_unlock(&lcdc_dev->reg_lock);
1160         return val;
1161 }
1162
1163 static int rk3036_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1164                                     bcsh_bcs_mode mode)
1165 {
1166         struct lcdc_device *lcdc_dev =
1167             container_of(dev_drv, struct lcdc_device, driver);
1168         u32 val;
1169
1170         spin_lock(&lcdc_dev->reg_lock);
1171         if (lcdc_dev->clk_on) {
1172                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1173                 switch (mode) {
1174                 case BRIGHTNESS:
1175                         val &= m_BCSH_BRIGHTNESS;
1176                         if (val > 0x20)
1177                                 val -= 0x20;
1178                         else if (val == 0x20)
1179                                 val = -32;
1180                         break;
1181                 case CONTRAST:
1182                         val &= m_BCSH_CONTRAST;
1183                         val >>= 8;
1184                         break;
1185                 case SAT_CON:
1186                         val &= m_BCSH_SAT_CON;
1187                         val >>= 16;
1188                         break;
1189                 default:
1190                         break;
1191                 }
1192         }
1193         spin_unlock(&lcdc_dev->reg_lock);
1194         return val;
1195 }
1196
1197
1198 static int rk3036_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1199 {
1200         struct lcdc_device *lcdc_dev =
1201             container_of(dev_drv, struct lcdc_device, driver);
1202         u32 mask, val;
1203
1204         spin_lock(&lcdc_dev->reg_lock);
1205         if (lcdc_dev->clk_on) {
1206                 if (open) {
1207                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1208                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1209                         lcdc_writel(lcdc_dev, BCSH_BCS,
1210                                     v_BCSH_BRIGHTNESS(0x00) |
1211                                     v_BCSH_CONTRAST(0x80) |
1212                                     v_BCSH_SAT_CON(0x80));
1213                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1214                 } else {
1215                         mask = m_BCSH_EN;
1216                         val = v_BCSH_EN(0);
1217                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1218                 }
1219                 lcdc_cfg_done(lcdc_dev);
1220         }
1221         spin_unlock(&lcdc_dev->reg_lock);
1222         return 0;
1223 }
1224
1225 static int rk3036_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
1226                                     struct overscan *overscan)
1227 {
1228         int i;
1229
1230         dev_drv->overscan = *overscan;
1231         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1232                 if (dev_drv->win[i] && dev_drv->win[i]->state) {
1233                         rk3036_lcdc_set_par(dev_drv, i);
1234                         rk3036_lcdc_pan_display(dev_drv, i);
1235                 }
1236         }
1237         rk3036_lcdc_cfg_done(dev_drv);
1238         return 0;
1239 }
1240
1241 static int rk3036_fb_win_remap(struct rk_lcdc_driver *dev_drv,
1242                                enum fb_win_map_order order)
1243 {
1244         mutex_lock(&dev_drv->fb_win_id_mutex);
1245         if (order == FB_DEFAULT_ORDER)
1246                 order = FB0_WIN1_FB1_WIN0_FB2_WIN2;
1247         dev_drv->fb2_win_id = order / 100;
1248         dev_drv->fb1_win_id = (order / 10) % 10;
1249         dev_drv->fb0_win_id = order % 10;
1250         mutex_unlock(&dev_drv->fb_win_id_mutex);
1251
1252         return 0;
1253 }
1254
1255 static int rk3036_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1256                                bool set)
1257 {
1258         struct lcdc_device *lcdc_dev =
1259             container_of(dev_drv, struct lcdc_device, driver);
1260         struct rk_screen *screen = dev_drv->cur_screen;
1261         u64 ft = 0;
1262         u32 dotclk;
1263         int ret;
1264         u32 pixclock;
1265         u32 x_total, y_total;
1266
1267         if (set) {
1268                 ft = div_u64(1000000000000llu, fps);
1269                 x_total =
1270                     screen->mode.upper_margin + screen->mode.lower_margin +
1271                     screen->mode.yres + screen->mode.vsync_len;
1272                 y_total =
1273                     screen->mode.left_margin + screen->mode.right_margin +
1274                     screen->mode.xres + screen->mode.hsync_len;
1275                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1276                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1277                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1278         }
1279
1280         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1281         lcdc_dev->pixclock = pixclock;
1282         dev_drv->pixclock = pixclock;
1283         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1284         screen->ft = 1000 / fps;        /*one frame time in ms */
1285
1286         if (set)
1287                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1288                          clk_get_rate(lcdc_dev->dclk), fps);
1289
1290         return fps;
1291 }
1292
1293 static int rk3036_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1294 {
1295         struct lcdc_device *lcdc_dev =
1296             container_of(dev_drv, struct lcdc_device, driver);
1297         u32 int_reg;
1298         int ret;
1299
1300         if (lcdc_dev->clk_on) {
1301                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1302                 if (int_reg & m_LF_INT_STA) {
1303                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1304                                      v_LF_INT_CLEAR(1));
1305                         ret = RK_LF_STATUS_FC;
1306                 } else {
1307                         ret = RK_LF_STATUS_FR;
1308                 }
1309         } else {
1310                 ret = RK_LF_STATUS_NC;
1311         }
1312
1313         return ret;
1314 }
1315
1316 static int rk3036_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1317                                     unsigned int *dsp_addr)
1318 {
1319         struct lcdc_device *lcdc_dev =
1320             container_of(dev_drv, struct lcdc_device, driver);
1321
1322         if (lcdc_dev->clk_on) {
1323                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1324                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1325         }
1326         return 0;
1327 }
1328
1329 static ssize_t rk3036_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1330                                          char *buf, int win_id)
1331 {
1332         struct rk_lcdc_win *win = NULL;
1333         char fmt[9] = "NULL";
1334         u32     size;
1335
1336         if (win_id < ARRAY_SIZE(lcdc_win)) {
1337                 win = dev_drv->win[win_id];
1338         } else {
1339                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1340                 return 0;
1341         }
1342
1343         size = snprintf(buf, PAGE_SIZE, "win%d: %s\n", win_id,
1344                         get_format_string(win->format, fmt));
1345         size += snprintf(buf + size, PAGE_SIZE - size,
1346                          "      xact %d yact %d xvir %d yvir %d\n",
1347                 win->area[0].xact, win->area[0].yact,
1348                 win->area[0].xvir, win->area[0].yvir);
1349         size += snprintf(buf + size, PAGE_SIZE - size,
1350                          "      xpos %d ypos %d xsize %d ysize %d\n",
1351                 win->area[0].xpos, win->area[0].ypos,
1352                 win->area[0].xsize, win->area[0].ysize);
1353         size += snprintf(buf + size, PAGE_SIZE - size,
1354                          "      yaddr 0x%x uvaddr 0x%x\n",
1355                 win->area[0].y_addr, win->area[0].uv_addr);
1356         return size;
1357 }
1358
1359 static int rk3036_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1360 {
1361         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1362                                                 struct lcdc_device,
1363                                                 driver);
1364         int *cbase = (int *)lcdc_dev->regs;
1365         int *regsbak = (int *)lcdc_dev->regsbak;
1366         int i, j;
1367
1368         dev_info(dev_drv->dev, "back up reg:\n");
1369         for (i = 0; i <= (0xDC >> 4); i++) {
1370                 for (j = 0; j < 4; j++)
1371                         dev_info(dev_drv->dev, "%08x  ",
1372                                  *(regsbak + i * 4 + j));
1373                 dev_info(dev_drv->dev, "\n");
1374         }
1375
1376         dev_info(dev_drv->dev, "lcdc reg:\n");
1377         for (i = 0; i <= (0xDC >> 4); i++) {
1378                 for (j = 0; j < 4; j++)
1379                         dev_info(dev_drv->dev, "%08x  ",
1380                                  readl_relaxed(cbase + i * 4 + j));
1381                 dev_info(dev_drv->dev, "\n");
1382         }
1383         return 0;
1384 }
1385
1386 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1387         .open                   = rk3036_lcdc_open,
1388         .load_screen            = rk3036_load_screen,
1389         .set_par                = rk3036_lcdc_set_par,
1390         .pan_display            = rk3036_lcdc_pan_display,
1391         .blank                  = rk3036_lcdc_blank,
1392         .ioctl                  = rk3036_lcdc_ioctl,
1393         .get_win_state          = rk3036_lcdc_get_win_state,
1394         .ovl_mgr                = rk3036_lcdc_ovl_mgr,
1395         .get_disp_info          = rk3036_lcdc_get_disp_info,
1396         .fps_mgr                = rk3036_lcdc_fps_mgr,
1397         .fb_get_win_id          = rk3036_lcdc_get_win_id,
1398         .fb_win_remap           = rk3036_fb_win_remap,
1399         .poll_vblank            = rk3036_lcdc_poll_vblank,
1400         .get_dsp_addr           = rk3036_lcdc_get_dsp_addr,
1401         .cfg_done               = rk3036_lcdc_cfg_done,
1402         .dump_reg               = rk3036_lcdc_reg_dump,
1403         .set_dsp_bcsh_hue       = rk3036_lcdc_set_bcsh_hue,
1404         .set_dsp_bcsh_bcs       = rk3036_lcdc_set_bcsh_bcs,
1405         .get_dsp_bcsh_hue       = rk3036_lcdc_get_bcsh_hue,
1406         .get_dsp_bcsh_bcs       = rk3036_lcdc_get_bcsh_bcs,
1407         .open_bcsh              = rk3036_lcdc_open_bcsh,
1408         .set_overscan           = rk3036_lcdc_set_overscan,
1409 };
1410
1411 static int rk3036_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1412 {
1413 #if defined(CONFIG_ROCKCHIP_IOMMU)
1414         struct device_node *np = lcdc_dev->dev->of_node;
1415         int val;
1416
1417         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1418                 lcdc_dev->driver.iommu_enabled = 0;
1419         else
1420                 lcdc_dev->driver.iommu_enabled = val;
1421 #else
1422         lcdc_dev->driver.iommu_enabled = 0;
1423 #endif
1424         return 0;
1425 }
1426
1427 static int rk3036_lcdc_probe(struct platform_device *pdev)
1428 {
1429         struct lcdc_device *lcdc_dev = NULL;
1430         struct rk_lcdc_driver *dev_drv;
1431         struct device *dev = &pdev->dev;
1432         struct resource *res;
1433         int ret;
1434
1435         lcdc_dev = devm_kzalloc(dev,
1436                                 sizeof(struct lcdc_device), GFP_KERNEL);
1437         if (!lcdc_dev) {
1438                 dev_err(&pdev->dev, "rk3036 lcdc device kmalloc fail!");
1439                 return -ENOMEM;
1440         }
1441         platform_set_drvdata(pdev, lcdc_dev);
1442         lcdc_dev->dev = dev;
1443         rk3036_lcdc_parse_dt(lcdc_dev);
1444
1445         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1446         lcdc_dev->reg_phy_base = res->start;
1447         lcdc_dev->len = resource_size(res);
1448         lcdc_dev->regs = devm_ioremap_resource(dev, res);
1449         if (IS_ERR(lcdc_dev->regs))
1450                 return PTR_ERR(lcdc_dev->regs);
1451
1452         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1453         if (IS_ERR(lcdc_dev->regsbak))
1454                 return PTR_ERR(lcdc_dev->regsbak);
1455
1456         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1457         dev_drv = &lcdc_dev->driver;
1458         dev_drv->dev = dev;
1459         dev_drv->prop = PRMRY;
1460         dev_drv->id = lcdc_dev->id;
1461         dev_drv->ops = &lcdc_drv_ops;
1462         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1463         spin_lock_init(&lcdc_dev->reg_lock);
1464
1465         lcdc_dev->irq = platform_get_irq(pdev, 0);
1466         if (lcdc_dev->irq < 0) {
1467                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
1468                         lcdc_dev->id);
1469                 return -ENXIO;
1470         }
1471
1472         ret = devm_request_irq(dev, lcdc_dev->irq, rk3036_lcdc_isr,
1473                                IRQF_DISABLED | IRQF_SHARED,
1474                                dev_name(dev), lcdc_dev);
1475         if (ret) {
1476                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
1477                         lcdc_dev->irq, ret);
1478                 return ret;
1479         }
1480
1481         if (dev_drv->iommu_enabled)
1482                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
1483
1484         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
1485         if (ret < 0) {
1486                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
1487                 return ret;
1488         }
1489         lcdc_dev->screen = dev_drv->screen0;
1490
1491         dev_info(dev, "lcdc probe ok, iommu %s\n",
1492                  dev_drv->iommu_enabled ? "enabled" : "disabled");
1493
1494         return 0;
1495 }
1496
1497 #if defined(CONFIG_PM)
1498 static int rk3036_lcdc_suspend(struct platform_device *pdev,
1499                                pm_message_t state)
1500 {
1501         return 0;
1502 }
1503
1504 static int rk3036_lcdc_resume(struct platform_device *pdev)
1505 {
1506         return 0;
1507 }
1508 #else
1509 #define rk3036_lcdc_suspend NULL
1510 #define rk3036_lcdc_resume  NULL
1511 #endif
1512
1513 static int rk3036_lcdc_remove(struct platform_device *pdev)
1514 {
1515         return 0;
1516 }
1517
1518 static void rk3036_lcdc_shutdown(struct platform_device *pdev)
1519 {
1520 }
1521
1522 #if defined(CONFIG_OF)
1523 static const struct of_device_id rk3036_lcdc_dt_ids[] = {
1524         {.compatible = "rockchip,rk3036-lcdc",},
1525         {}
1526 };
1527 #endif
1528
1529 static struct platform_driver rk3036_lcdc_driver = {
1530         .probe = rk3036_lcdc_probe,
1531         .remove = rk3036_lcdc_remove,
1532         .driver = {
1533                 .name = "rk3036-lcdc",
1534                 .owner = THIS_MODULE,
1535                 .of_match_table = of_match_ptr(rk3036_lcdc_dt_ids),
1536         },
1537         .suspend = rk3036_lcdc_suspend,
1538         .resume = rk3036_lcdc_resume,
1539         .shutdown = rk3036_lcdc_shutdown,
1540 };
1541
1542 static int __init rk3036_lcdc_module_init(void)
1543 {
1544         return platform_driver_register(&rk3036_lcdc_driver);
1545 }
1546
1547 static void __exit rk3036_lcdc_module_exit(void)
1548 {
1549         platform_driver_unregister(&rk3036_lcdc_driver);
1550 }
1551
1552 fs_initcall(rk3036_lcdc_module_init);
1553 module_exit(rk3036_lcdc_module_exit);