1 #ifndef _RK3036_LCDC_H_
2 #define _RK3036_LCDC_H_
4 #include<linux/rk_fb.h>
8 /*******************register definition**********************/
10 #define SYS_CTRL (0x00)
11 #define m_WIN0_EN (1<<0)
12 #define m_WIN1_EN (1<<1)
13 #define m_HWC_EN (1<<2)
14 #define m_WIN0_FORMAT (7<<3)
15 #define m_WIN1_FORMAT (7<<6)
16 #define m_HWC_LUT_EN (1<<9)
17 #define m_HWC_SIZE (1<<10)
18 #define m_WIN0_RB_SWAP (1<<15)
19 #define m_WIN0_ALPHA_SWAP (1<<16)
20 #define m_WIN0_Y8_SWAP (1<<17)
21 #define m_WIN0_UV_SWAP (1<<18)
22 #define m_WIN1_RB_SWAP (1<<19)
23 #define m_WIN1_ALPHA_SWAP (1<<20)
24 #define m_WIN0_OTSD_DISABLE (1<<22)
25 #define m_WIN1_OTSD_DISABLE (1<<23)
26 #define m_DMA_BURST_LENGTH (3<<24)
27 #define m_HWC_LODAD_EN (1<<26)
28 #define m_DMA_STOP (1<<29)
29 #define m_LCDC_STANDBY (1<<30)
30 #define m_AUTO_GATING_EN (1<<31)
32 #define v_WIN0_EN(x) (((x)&1)<<0)
33 #define v_WIN1_EN(x) (((x)&1)<<1)
34 #define v_HWC_EN(x) (((x)&1)<<2)
35 #define v_WIN0_FORMAT(x) (((x)&7)<<3)
36 #define v_WIN1_FORMAT(x) (((x)&7)<<6)
37 #define v_HWC_LUT_EN(x) (((x)&1)<<9)
38 #define v_HWC_SIZE(x) (((x)&1)<<10)
39 #define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
40 #define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
41 #define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
42 #define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
43 #define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
44 #define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
45 #define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
46 #define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
47 #define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
48 #define v_HWC_LODAD_EN(x) (((x)&1)<<26)
49 #define v_WIN1_LUT_EN(x) (((x)&1)<<27)
50 #define v_DMA_STOP(x) (((x)&1)<<29)
51 #define v_LCDC_STANDBY(x) (((x)&1)<<30)
52 #define v_AUTO_GATING_EN(x) (((x)&1)<<31)
54 #define DSP_CTRL0 (0x04)
55 #define m_DSP_OUT_FORMAT (0x0f<<0)
56 #define m_HSYNC_POL (1<<4)
57 #define m_VSYNC_POL (1<<5)
58 #define m_DEN_POL (1<<6)
59 #define m_DCLK_POL (1<<7)
60 #define m_WIN0_TOP (1<<8)
61 #define m_DITHER_UP_EN (1<<9)
62 #define m_INTERLACE_DSP_EN (1<<12)
63 #define m_WIN1_INTERLACE_EN (1<<15)
64 #define m_WIN0_YRGB_DEFLICK_EN (1<<16)
65 #define m_WIN0_CBR_DEFLICK_EN (1<<17)
66 #define m_WIN0_ALPHA_MODE (1<<18)
67 #define m_WIN1_ALPHA_MODE (1<<19)
68 #define m_WIN0_CSC_MODE (3<<20)
69 #define m_WIN0_YUV_CLIP (1<<23)
70 #define m_TVE_MODE (1<<25)
71 #define m_HWC_ALPHA_MODE (1<<28)
72 #define m_PREMUL_ALPHA_ENABLE (1<<29)
73 #define m_ALPHA_MODE_SEL1 (1<<30)
74 #define m_WIN1_DIFF_DCLK_EN (1<<31)
76 #define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
77 #define v_HSYNC_POL(x) (((x)&1)<<4)
78 #define v_VSYNC_POL(x) (((x)&1)<<5)
79 #define v_DEN_POL(x) (((x)&1)<<6)
80 #define v_DCLK_POL(x) (((x)&1)<<7)
81 #define v_WIN0_TOP(x) (((x)&1)<<8)
82 #define v_DITHER_UP_EN(x) (((x)&1)<<9)
83 #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
84 #define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
85 #define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
86 #define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
87 #define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
88 #define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
89 #define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
90 #define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
91 #define v_TVE_MODE(x) (((x)&1)<<25)
92 #define v_HWC_ALPHA_MODE(x) (((x)&1)<<28)
93 #define v_PREMUL_ALPHA_ENABLE(x) (((x)&1)<<29)
94 #define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
95 #define v_WIN1_DIFF_DCLK_EN(x) (((x)&1)<<31)
97 #define DSP_CTRL1 (0x08)
98 #define m_BG_COLOR (0xffffff<<0)
99 #define m_BG_B (0xff<<0)
100 #define m_BG_G (0xff<<8)
101 #define m_BG_R (0xff<<16)
102 #define m_BLANK_EN (1<<24)
103 #define m_BLACK_EN (1<<25)
104 #define m_DSP_BG_SWAP (1<<26)
105 #define m_DSP_RB_SWAP (1<<27)
106 #define m_DSP_RG_SWAP (1<<28)
107 #define m_DSP_DELTA_SWAP (1<<29)
108 #define m_DSP_DUMMY_SWAP (1<<30)
109 #define m_DSP_OUT_ZERO (1<<31)
111 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
112 #define v_BG_B(x) (((x)&0xff)<<0)
113 #define v_BG_G(x) (((x)&0xff)<<8)
114 #define v_BG_R(x) (((x)&0xff)<<16)
115 #define v_BLANK_EN(x) (((x)&1)<<24)
116 #define v_BLACK_EN(x) (((x)&1)<<25)
117 #define v_DSP_BG_SWAP(x) (((x)&1)<<26)
118 #define v_DSP_RB_SWAP(x) (((x)&1)<<27)
119 #define v_DSP_RG_SWAP(x) (((x)&1)<<28)
120 #define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
121 #define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
122 #define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
124 #define INT_STATUS (0x10)
125 #define m_HS_INT_STA (1<<0) //status
126 #define m_FS_INT_STA (1<<1)
127 #define m_LF_INT_STA (1<<2)
128 #define m_BUS_ERR_INT_STA (1<<3)
129 #define m_HS_INT_EN (1<<4) //enable
130 #define m_FS_INT_EN (1<<5)
131 #define m_LF_INT_EN (1<<6)
132 #define m_BUS_ERR_INT_EN (1<<7)
133 #define m_HS_INT_CLEAR (1<<8) //auto clear
134 #define m_FS_INT_CLEAR (1<<9)
135 #define m_LF_INT_CLEAR (1<<10)
136 #define m_BUS_ERR_INT_CLEAR (1<<11)
137 #define m_LF_INT_NUM (0xfff<<12)
138 #define m_WIN0_EMPTY_INT_EN (1<<24)
139 #define m_WIN1_EMPTY_INT_EN (1<<25)
140 #define m_WIN0_EMPTY_INT_CLEAR (1<<26)
141 #define m_WIN1_EMPTY_INT_CLEAR (1<<27)
142 #define m_WIN0_EMPTY_INT_STA (1<<28)
143 #define m_WIN1_EMPTY_INT_STA (1<<29)
144 #define m_FS_RAW_STA (1<<30)
145 #define m_LF_RAW_STA (1<<31)
147 #define v_HS_INT_EN(x) (((x)&1)<<4)
148 #define v_FS_INT_EN(x) (((x)&1)<<5)
149 #define v_LF_INT_EN(x) (((x)&1)<<6)
150 #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
151 #define v_HS_INT_CLEAR(x) (((x)&1)<<8)
152 #define v_FS_INT_CLEAR(x) (((x)&1)<<9)
153 #define v_LF_INT_CLEAR(x) (((x)&1)<<10)
154 #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
155 #define v_LF_INT_NUM(x) (((x)&0xfff)<<12)
156 #define v_WIN0_EMPTY_INT_EN(x) (((x)&1)<<24)
157 #define v_WIN1_EMPTY_INT_EN(x) (((x)&1)<<25)
158 #define v_WIN0_EMPTY_INT_CLEAR(x) (((x)&1)<<26)
159 #define v_WIN1_EMPTY_INT_CLEAR(x) (((x)&1)<<27)
162 #define ALPHA_CTRL (0x14)
163 #define m_WIN0_ALPHA_EN (1<<0)
164 #define m_WIN1_ALPHA_EN (1<<1)
165 #define m_HWC_ALPAH_EN (1<<2)
166 #define m_WIN1_PREMUL_SCALE (1<<3)
167 #define m_WIN0_ALPHA_VAL (0xff<<4)
168 #define m_WIN1_ALPHA_VAL (0xff<<12)
169 #define m_HWC_ALPAH_VAL (0x0f<<20)
171 #define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
172 #define v_WIN1_ALPHA_EN(x) (((x)&1)<<1)
173 #define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
174 #define v_WIN1_PREMUL_SCALE(x) (((x)&1)<<3)
175 #define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
176 #define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
177 #define v_HWC_ALPAH_VAL(x) (((x)&0x0f)<<20)
179 #define WIN0_COLOR_KEY (0x18)
180 #define WIN1_COLOR_KEY (0x1C)
181 #define m_COLOR_KEY_VAL (0xffffff<<0)
182 #define m_COLOR_KEY_EN (1<<24)
183 #define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
184 #define v_COLOR_KEY_EN(x) (((x)&1)<<24)
186 /* Layer Registers */
187 #define WIN0_YRGB_MST (0x20)
188 #define WIN0_CBR_MST (0x24)
189 #define WIN1_MST (0xa0)
190 #define HWC_MST (0x58)
192 #define WIN1_VIR (0x28)
193 #define WIN0_VIR (0x30)
194 #define m_YRGB_VIR (0x1fff << 0)
195 #define m_CBBR_VIR (0x1fff << 16)
197 #define v_YRGB_VIR(x) ((x & 0x1fff) << 0)
198 #define v_CBBR_VIR(x) ((x & 0x1fff) << 16)
200 #define v_ARGB888_VIRWIDTH(x) (((x)&0x1fff)<<0)
201 #define v_RGB888_VIRWIDTH(x) (((((x*3)>>2)+((x)%3))&0x1fff)<<0)
202 #define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x,2)&0x1fff)<<0)
203 #define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x,4)&0x1fff)<<0)
204 #define v_CBCR_VIR(x) ((x & 0x1fff) << 16)
206 #define WIN0_ACT_INFO (0x34)
207 #define WIN1_ACT_INFO (0xB4)
208 #define m_ACT_WIDTH (0x1fff<<0)
209 #define m_ACT_HEIGHT (0x1fff<<16)
210 #define v_ACT_WIDTH(x) (((x-1)&0x1fff)<<0)
211 #define v_ACT_HEIGHT(x) (((x-1)&0x1fff)<<16)
213 #define WIN0_DSP_INFO (0x38)
214 #define WIN1_DSP_INFO (0xB8)
215 #define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
216 #define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
218 #define WIN0_DSP_ST (0x3C)
219 #define WIN1_DSP_ST (0xBC)
220 #define HWC_DSP_ST (0x5C)
221 #define v_DSP_STX(x) (((x)&0xfff)<<0)
222 #define v_DSP_STY(x) (((x)&0xfff)<<16)
224 #define WIN0_SCL_FACTOR_YRGB (0x40)
225 #define WIN0_SCL_FACTOR_CBR (0x44)
226 #define WIN1_SCL_FACTOR_YRGB (0xC0)
227 #define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
228 #define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
230 #define WIN0_SCL_OFFSET (0x48)
231 #define WIN1_SCL_OFFSET (0xC8)
234 #define WIN1_LUT_ADDR (0x0400)
235 #define HWC_LUT_ADDR (0x0800)
237 /* Display Infomation Registers */
238 #define DSP_HTOTAL_HS_END (0x6C)
239 #define v_HSYNC(x) (((x)&0xfff)<<0) //hsync pulse width
240 #define v_HORPRD(x) (((x)&0xfff)<<16) //horizontal period
242 #define DSP_HACT_ST_END (0x70)
243 #define v_HAEP(x) (((x)&0xfff)<<0) //horizontal active end point
244 #define v_HASP(x) (((x)&0xfff)<<16) //horizontal active start point
246 #define DSP_VTOTAL_VS_END (0x74)
247 #define v_VSYNC(x) (((x)&0xfff)<<0)
248 #define v_VERPRD(x) (((x)&0xfff)<<16)
250 #define DSP_VACT_ST_END (0x78)
251 #define v_VAEP(x) (((x)&0xfff)<<0)
252 #define v_VASP(x) (((x)&0xfff)<<16)
254 #define DSP_VS_ST_END_F1 (0x7C)
255 #define DSP_VACT_ST_END_F1 (0x80)
258 #define BCSH_COLOR_BAR (0xD0)
259 #define v_BCSH_EN(x) (((x)&1)<<0)
260 #define v_BCSH_COLOR_BAR_Y(x) (((x)&0x3ff)<<2)
261 #define v_BCSH_COLOR_BAR_U(x) (((x)&0x3ff)<<12)
262 #define v_BCSH_COLOR_BAR_V(x) (((x)&0x3ff)<<22)
264 #define m_BCSH_EN (1<<0)
265 #define m_BCSH_COLOR_BAR_Y (0x3ff<<2)
266 #define m_BCSH_COLOR_BAR_U (0x3ff<<12)
267 #define m_BCSH_COLOR_BAR_V ((u32)0x3ff<<22)
269 #define BCSH_BCS (0xD4)
270 #define v_BCSH_BRIGHTNESS(x) (((x)&0xff)<<0)
271 #define v_BCSH_CONTRAST(x) (((x)&0x1ff)<<8)
272 #define v_BCSH_SAT_CON(x) (((x)&0x3ff)<<20)
273 #define v_BCSH_OUT_MODE(x) (((x)&0x3)<<30)
275 #define m_BCSH_BRIGHTNESS (0xff<<0)
276 #define m_BCSH_CONTRAST (0x1ff<<8)
277 #define m_BCSH_SAT_CON (0x3ff<<20)
278 #define m_BCSH_OUT_MODE ((u32)0x3<<30)
281 #define BCSH_H (0xD8)
282 #define v_BCSH_SIN_HUE(x) (((x)&0x1ff)<<0)
283 #define v_BCSH_COS_HUE(x) (((x)&0x1ff)<<16)
285 #define m_BCSH_SIN_HUE (0x1ff<<0)
286 #define m_BCSH_COS_HUE (0x1ff<<16)
289 #define AXI_BUS_CTRL (0x2C)
290 #define m_IO_PAD_CLK (1 << 31)
291 #define m_CORE_CLK_DIV_EN (1 << 30)
292 #define m_HDMI_DCLK_INVERT (1 << 23)
293 #define m_HDMI_DCLK_EN (1 << 22)
294 #define m_TVE_DAC_DCLK_INVERT (1 << 21)
295 #define m_TVE_DAC_DCLK_EN (1 << 20)
296 #define m_HDMI_DCLK_DIV_EN (1 << 19)
297 #define m_AXI_OUTSTANDING_MAX_NUM (0x1f << 12)
298 #define m_AXI_MAX_OUTSTANDING_EN (1 << 11)
299 #define m_MMU_EN (1 << 10)
300 #define m_NOC_HURRY_THRESHOLD (0xf << 6)
301 #define m_NOC_HURRY_VALUE (3 << 4)
302 #define m_NOC_HURRY_EN (1 << 3)
303 #define m_NOC_QOS_VALUE (3 << 1)
304 #define m_NOC_QOS_EN (1 << 0)
306 #define v_IO_PAD_CLK(x) ((x&1) << 31)
307 #define v_CORE_CLK_DIV_EN(x) ((x&1) << 30)
308 #define v_HDMI_DCLK_INVERT(x) ((x&1) << 23)
309 #define v_HDMI_DCLK_EN(x) ((x&1) << 22)
310 #define v_TVE_DAC_DCLK_INVERT(x) ((x&1) << 21)
311 #define v_TVE_DAC_DCLK_EN(x) ((x&1) << 20)
312 #define v_HDMI_DCLK_DIV_EN(x) ((x&1) << 19)
313 #define v_AXI_OUTSTANDING_MAX_NUM(x) ((x&0x1f) << 12)
314 #define v_AXI_MAX_OUTSTANDING_EN(x) ((x&1) << 11)
315 #define v_MMU_EN(x) ((x&1) << 10)
316 #define v_NOC_HURRY_THRESHOLD(x) ((x&0xf) << 6)
317 #define v_NOC_HURRY_VALUE(x) ((x&3) << 4)
318 #define v_NOC_HURRY_EN(x) ((x&1) << 3)
319 #define v_NOC_QOS_VALUE(x) ((x&3) << 1)
320 #define v_NOC_QOS_EN(x) ((x&1) << 0)
322 #define GATHER_TRANSFER (0x84)
323 #define m_WIN1_AXI_GATHER_NUM (0xf << 12)
324 #define m_WIN0_CBCR_AXI_GATHER_NUM (0x7 << 8)
325 #define m_WIN0_YRGB_AXI_GATHER_NUM (0xf << 4)
326 #define m_WIN1_AXI_GAHTER_EN (1 << 2)
327 #define m_WIN0_CBCR_AXI_GATHER_EN (1 << 1)
328 #define m_WIN0_YRGB_AXI_GATHER_EN (1 << 0)
330 #define v_WIN1_AXI_GATHER_NUM(x) ((x & 0xf) << 12)
331 #define v_WIN0_CBCR_AXI_GATHER_NUM(x) ((x & 0x7) << 8)
332 #define v_WIN0_YRGB_AXI_GATHER_NUM(x) ((x & 0xf) << 4)
333 #define v_WIN1_AXI_GAHTER_EN(x) ((x & 1) << 2)
334 #define v_WIN0_CBCR_AXI_GATHER_EN(x) ((x & 1) << 1)
335 #define v_WIN0_YRGB_AXI_GATHER_EN(x) ((x & 1) << 0)
337 #define VERSION_INFO (0x94)
338 #define m_MAJOR (0xff << 24)
339 #define m_MINOR (0xff << 16)
340 #define m_BUILD (0xffff)
342 #define REG_CFG_DONE (0x90)
344 /* TV Control Registers */
345 #define TV_CTRL (0x200)
346 #define TV_SYNC_TIMING (0x204)
347 #define TV_ACT_TIMING (0x208)
348 #define TV_ADJ_TIMING (0x20c)
349 #define TV_FREQ_SC (0x210)
350 #define TV_FILTER0 (0x214)
351 #define TV_FILTER1 (0x218)
352 #define TV_FILTER2 (0x21C)
353 #define TV_ACT_ST (0x234)
354 #define TV_ROUTING (0x238)
355 #define TV_SYNC_ADJUST (0x250)
356 #define TV_STATUS (0x254)
357 #define TV_RESET (0x268)
358 #define TV_SATURATION (0x278)
359 #define TV_BW_CTRL (0x28C)
360 #define TV_BRIGHTNESS_CONTRAST (0x290)
364 #define MMU_DTE_ADDR (0x0300)
365 #define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0)
366 #define m_MMU_DTE_ADDR (0xffffffff<<0)
368 #define MMU_STATUS (0x0304)
369 #define v_PAGING_ENABLED(x) (((x)&1)<<0)
370 #define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1)
371 #define v_STAIL_ACTIVE(x) (((x)&1)<<2)
372 #define v_MMU_IDLE(x) (((x)&1)<<3)
373 #define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4)
374 #define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5)
375 #define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6)
376 #define m_PAGING_ENABLED (1<<0)
377 #define m_PAGE_FAULT_ACTIVE (1<<1)
378 #define m_STAIL_ACTIVE (1<<2)
379 #define m_MMU_IDLE (1<<3)
380 #define m_REPLAY_BUFFER_EMPTY (1<<4)
381 #define m_PAGE_FAULT_IS_WRITE (1<<5)
382 #define m_PAGE_FAULT_BUS_ID (0x1f<<6)
384 #define MMU_COMMAND (0x0308)
385 #define v_MMU_CMD(x) (((x)&0x3)<<0)
386 #define m_MMU_CMD (0x3<<0)
388 #define MMU_PAGE_FAULT_ADDR (0x030c)
389 #define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0)
390 #define m_PAGE_FAULT_ADDR (0xffffffff<<0)
392 #define MMU_ZAP_ONE_LINE (0x0310)
393 #define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0)
394 #define m_MMU_ZAP_ONE_LINE (0xffffffff<<0)
396 #define MMU_INT_RAWSTAT (0x0314)
397 #define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0)
398 #define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1)
399 #define m_PAGE_FAULT_RAWSTAT (1<<0)
400 #define m_READ_BUS_ERROR_RAWSTAT (1<<1)
402 #define MMU_INT_CLEAR (0x0318)
403 #define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0)
404 #define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1)
405 #define m_PAGE_FAULT_CLEAR (1<<0)
406 #define m_READ_BUS_ERROR_CLEAR (1<<1)
408 #define MMU_INT_MASK (0x031c)
409 #define v_PAGE_FAULT_MASK(x) (((x)&1)<<0)
410 #define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1)
411 #define m_PAGE_FAULT_MASK (1<<0)
412 #define m_READ_BUS_ERROR_MASK (1<<1)
414 #define MMU_INT_STATUS (0x0320)
415 #define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0)
416 #define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1)
417 #define m_PAGE_FAULT_STATUS (1<<0)
418 #define m_READ_BUS_ERROR_STATUS (1<<1)
420 #define MMU_AUTO_GATING (0x0324)
421 #define v_MMU_AUTO_GATING(x) (((x)&1)<<0)
422 #define m_MMU_AUTO_GATING (1<<0)
424 enum _vop_dma_burst {
431 VOP_FORMAT_ARGB888 = 0,
455 #define CalScale(x, y) ((((u32)(x-1))*0x1000)/(y-1))
459 struct rk_lcdc_driver driver;
461 struct rk_screen *screen;
464 void *regsbak; /*back up reg*/
465 u32 reg_phy_base; /* physical basic address of lcdc register*/
466 u32 len; /* physical map length of lcdc register*/
467 spinlock_t reg_lock; /*one time only one process allowed to config the register*/
469 int __iomem *dsp_lut_addr_base;
472 int prop; /*used for primary or extended display device*/
474 bool pwr18; /*if lcdc use 1.8v power supply*/
475 bool clk_on; /*if aclk or hclk is closed ,acess to register is not allowed*/
476 u8 atv_layer_cnt; /*active layer counter,when atv_layer_cnt = 0,disable lcdc*/
481 struct clk *pd; /*lcdc power domain*/
482 struct clk *hclk; /*lcdc AHP clk*/
483 struct clk *dclk; /*lcdc dclk*/
484 struct clk *aclk; /*lcdc share memory frequency*/
487 u32 standby; /*1:standby,0:wrok*/
490 static inline void lcdc_writel(struct lcdc_device *lcdc_dev,u32 offset,u32 v)
492 u32 *_pv = (u32*)lcdc_dev->regsbak;
493 _pv += (offset >> 2);
495 writel_relaxed(v,lcdc_dev->regs+offset);
498 static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev,u32 offset)
501 u32 *_pv = (u32*)lcdc_dev->regsbak;
502 _pv += (offset >> 2);
503 v = readl_relaxed(lcdc_dev->regs+offset);
508 static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
510 u32 _v = readl_relaxed(lcdc_dev->regs+offset);
515 static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
517 u32* _pv = (u32*)lcdc_dev->regsbak;
518 _pv += (offset >> 2);
520 writel_relaxed(*_pv,lcdc_dev->regs + offset);
523 static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev,u32 offset,u32 msk)
525 u32* _pv = (u32*)lcdc_dev->regsbak;
526 _pv += (offset >> 2);
528 writel_relaxed(*_pv,lcdc_dev->regs + offset);
531 static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev,u32 offset,u32 msk,u32 v)
533 u32 *_pv = (u32*)lcdc_dev->regsbak;
534 _pv += (offset >> 2);
537 writel_relaxed(*_pv,lcdc_dev->regs+offset);
540 static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
542 writel_relaxed(0x01,lcdc_dev->regs+REG_CFG_DONE);
546 #endif /* _RK3036_LCDC_H_ */