1 #ifndef _RK3036_LCDC_H_
2 #define _RK3036_LCDC_H_
4 #include<linux/rk_fb.h>
8 /*******************register definition**********************/
10 #define SYS_CTRL (0x00)
11 #define m_WIN0_EN (1<<0)
12 #define m_WIN1_EN (1<<1)
13 #define m_HWC_EN (1<<2)
14 #define m_WIN0_FORMAT (7<<3)
15 #define m_WIN1_FORMAT (7<<6)
16 #define m_HWC_LUT_EN (1<<9)
17 #define m_HWC_SIZE (1<<10)
18 #define m_WIN0_RB_SWAP (1<<15)
19 #define m_WIN0_ALPHA_SWAP (1<<16)
20 #define m_WIN0_Y8_SWAP (1<<17)
21 #define m_WIN0_UV_SWAP (1<<18)
22 #define m_WIN1_RB_SWAP (1<<19)
23 #define m_WIN1_ALPHA_SWAP (1<<20)
24 #define m_WIN0_OTSD_DISABLE (1<<22)
25 #define m_WIN1_OTSD_DISABLE (1<<23)
26 #define m_DMA_BURST_LENGTH (3<<24)
27 #define m_HWC_LODAD_EN (1<<26)
28 #define m_DMA_STOP (1<<29)
29 #define m_LCDC_STANDBY (1<<30)
30 #define m_AUTO_GATING_EN (1<<31)
32 #define v_WIN0_EN(x) (((x)&1)<<0)
33 #define v_WIN1_EN(x) (((x)&1)<<1)
34 #define v_HWC_EN(x) (((x)&1)<<2)
35 #define v_WIN0_FORMAT(x) (((x)&7)<<3)
36 #define v_WIN1_FORMAT(x) (((x)&7)<<6)
37 #define v_HWC_LUT_EN(x) (((x)&1)<<9)
38 #define v_HWC_SIZE(x) (((x)&1)<<10)
39 #define v_WIN0_RB_SWAP(x) (((x)&1)<<15)
40 #define v_WIN0_ALPHA_SWAP(x) (((x)&1)<<16)
41 #define v_WIN0_Y8_SWAP(x) (((x)&1)<<17)
42 #define v_WIN0_UV_SWAP(x) (((x)&1)<<18)
43 #define v_WIN1_RB_SWAP(x) (((x)&1)<<19)
44 #define v_WIN1_ALPHA_SWAP(x) (((x)&1)<<20)
45 #define v_WIN0_OTSD_DISABLE(x) (((x)&1)<<22)
46 #define v_WIN1_OTSD_DISABLE(x) (((x)&1)<<23)
47 #define v_DMA_BURST_LENGTH(x) (((x)&3)<<24)
48 #define v_HWC_LODAD_EN(x) (((x)&1)<<26)
49 #define v_WIN1_LUT_EN(x) (((x)&1)<<27)
50 #define v_DMA_STOP(x) (((x)&1)<<29)
51 #define v_LCDC_STANDBY(x) (((x)&1)<<30)
52 #define v_AUTO_GATING_EN(x) (((x)&1)<<31)
54 #define DSP_CTRL0 (0x04)
55 #define m_DSP_OUT_FORMAT (0x0f<<0)
56 #define m_HSYNC_POL (1<<4)
57 #define m_VSYNC_POL (1<<5)
58 #define m_DEN_POL (1<<6)
59 #define m_DCLK_POL (1<<7)
60 #define m_WIN0_TOP (1<<8)
61 #define m_DITHER_UP_EN (1<<9)
62 #define m_INTERLACE_DSP_EN (1<<12)
63 #define m_INTERLACE_DSP_POL (1<<13)
64 #define m_WIN0_INTERLACE_EN (1<<14)
65 #define m_WIN1_INTERLACE_EN (1<<15)
66 #define m_WIN0_YRGB_DEFLICK_EN (1<<16)
67 #define m_WIN0_CBR_DEFLICK_EN (1<<17)
68 #define m_WIN0_ALPHA_MODE (1<<18)
69 #define m_WIN1_ALPHA_MODE (1<<19)
70 #define m_WIN0_CSC_MODE (3<<20)
71 #define m_WIN0_YUV_CLIP (1<<23)
72 #define m_TVE_MODE (1<<25)
73 #define m_HWC_ALPHA_MODE (1<<28)
74 #define m_PREMUL_ALPHA_ENABLE (1<<29)
75 #define m_ALPHA_MODE_SEL1 (1<<30)
76 #define m_WIN1_DIFF_DCLK_EN (1<<31)
78 #define v_DSP_OUT_FORMAT(x) (((x)&0x0f)<<0)
79 #define v_HSYNC_POL(x) (((x)&1)<<4)
80 #define v_VSYNC_POL(x) (((x)&1)<<5)
81 #define v_DEN_POL(x) (((x)&1)<<6)
82 #define v_DCLK_POL(x) (((x)&1)<<7)
83 #define v_WIN0_TOP(x) (((x)&1)<<8)
84 #define v_DITHER_UP_EN(x) (((x)&1)<<9)
85 #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
86 #define v_INTERLACE_DSP_POL(x) (((x)&1)<<13)
87 #define v_WIN0_INTERLACE_EN(x) (((x)&1)<<14)
88 #define v_WIN1_INTERLACE_EN(x) (((x)&1)<<15)
89 #define v_WIN0_YRGB_DEFLICK_EN(x) (((x)&1)<<16)
90 #define v_WIN0_CBR_DEFLICK_EN(x) (((x)&1)<<17)
91 #define v_WIN0_ALPHA_MODE(x) (((x)&1)<<18)
92 #define v_WIN1_ALPHA_MODE(x) (((x)&1)<<19)
93 #define v_WIN0_CSC_MODE(x) (((x)&3)<<20)
94 #define v_WIN0_YUV_CLIP(x) (((x)&1)<<23)
95 #define v_TVE_MODE(x) (((x)&1)<<25)
96 #define v_HWC_ALPHA_MODE(x) (((x)&1)<<28)
97 #define v_PREMUL_ALPHA_ENABLE(x) (((x)&1)<<29)
98 #define v_ALPHA_MODE_SEL1(x) (((x)&1)<<30)
99 #define v_WIN1_DIFF_DCLK_EN(x) (((x)&1)<<31)
101 #define DSP_CTRL1 (0x08)
102 #define m_BG_COLOR (0xffffff<<0)
103 #define m_BG_B (0xff<<0)
104 #define m_BG_G (0xff<<8)
105 #define m_BG_R (0xff<<16)
106 #define m_BLANK_EN (1<<24)
107 #define m_BLACK_EN (1<<25)
108 #define m_DSP_BG_SWAP (1<<26)
109 #define m_DSP_RB_SWAP (1<<27)
110 #define m_DSP_RG_SWAP (1<<28)
111 #define m_DSP_DELTA_SWAP (1<<29)
112 #define m_DSP_DUMMY_SWAP (1<<30)
113 #define m_DSP_OUT_ZERO (1<<31)
115 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
116 #define v_BG_B(x) (((x)&0xff)<<0)
117 #define v_BG_G(x) (((x)&0xff)<<8)
118 #define v_BG_R(x) (((x)&0xff)<<16)
119 #define v_BLANK_EN(x) (((x)&1)<<24)
120 #define v_BLACK_EN(x) (((x)&1)<<25)
121 #define v_DSP_BG_SWAP(x) (((x)&1)<<26)
122 #define v_DSP_RB_SWAP(x) (((x)&1)<<27)
123 #define v_DSP_RG_SWAP(x) (((x)&1)<<28)
124 #define v_DSP_DELTA_SWAP(x) (((x)&1)<<29)
125 #define v_DSP_DUMMY_SWAP(x) (((x)&1)<<30)
126 #define v_DSP_OUT_ZERO(x) (((x)&1)<<31)
128 #define INT_STATUS (0x10)
129 #define m_HS_INT_STA (1<<0) /* status */
130 #define m_FS_INT_STA (1<<1)
131 #define m_LF_INT_STA (1<<2)
132 #define m_BUS_ERR_INT_STA (1<<3)
133 #define m_HS_INT_EN (1<<4) /* enable */
134 #define m_FS_INT_EN (1<<5)
135 #define m_LF_INT_EN (1<<6)
136 #define m_BUS_ERR_INT_EN (1<<7)
137 #define m_HS_INT_CLEAR (1<<8) /* auto clear*/
138 #define m_FS_INT_CLEAR (1<<9)
139 #define m_LF_INT_CLEAR (1<<10)
140 #define m_BUS_ERR_INT_CLEAR (1<<11)
141 #define m_LF_INT_NUM (0xfff<<12)
142 #define m_WIN0_EMPTY_INT_EN (1<<24)
143 #define m_WIN1_EMPTY_INT_EN (1<<25)
144 #define m_WIN0_EMPTY_INT_CLEAR (1<<26)
145 #define m_WIN1_EMPTY_INT_CLEAR (1<<27)
146 #define m_WIN0_EMPTY_INT_STA (1<<28)
147 #define m_WIN1_EMPTY_INT_STA (1<<29)
148 #define m_FS_RAW_STA (1<<30)
149 #define m_LF_RAW_STA (1<<31)
151 #define v_HS_INT_EN(x) (((x)&1)<<4)
152 #define v_FS_INT_EN(x) (((x)&1)<<5)
153 #define v_LF_INT_EN(x) (((x)&1)<<6)
154 #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
155 #define v_HS_INT_CLEAR(x) (((x)&1)<<8)
156 #define v_FS_INT_CLEAR(x) (((x)&1)<<9)
157 #define v_LF_INT_CLEAR(x) (((x)&1)<<10)
158 #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
159 #define v_LF_INT_NUM(x) (((x)&0xfff)<<12)
160 #define v_WIN0_EMPTY_INT_EN(x) (((x)&1)<<24)
161 #define v_WIN1_EMPTY_INT_EN(x) (((x)&1)<<25)
162 #define v_WIN0_EMPTY_INT_CLEAR(x) (((x)&1)<<26)
163 #define v_WIN1_EMPTY_INT_CLEAR(x) (((x)&1)<<27)
166 #define ALPHA_CTRL (0x14)
167 #define m_WIN0_ALPHA_EN (1<<0)
168 #define m_WIN1_ALPHA_EN (1<<1)
169 #define m_HWC_ALPAH_EN (1<<2)
170 #define m_WIN1_PREMUL_SCALE (1<<3)
171 #define m_WIN0_ALPHA_VAL (0xff<<4)
172 #define m_WIN1_ALPHA_VAL (0xff<<12)
173 #define m_HWC_ALPAH_VAL (0xff<<20)
175 #define v_WIN0_ALPHA_EN(x) (((x)&1)<<0)
176 #define v_WIN1_ALPHA_EN(x) (((x)&1)<<1)
177 #define v_HWC_ALPAH_EN(x) (((x)&1)<<2)
178 #define v_WIN1_PREMUL_SCALE(x) (((x)&1)<<3)
179 #define v_WIN0_ALPHA_VAL(x) (((x)&0xff)<<4)
180 #define v_WIN1_ALPHA_VAL(x) (((x)&0xff)<<12)
181 #define v_HWC_ALPAH_VAL(x) (((x)&0xff)<<20)
183 #define WIN0_COLOR_KEY (0x18)
184 #define WIN1_COLOR_KEY (0x1C)
185 #define m_COLOR_KEY_VAL (0xffffff<<0)
186 #define m_COLOR_KEY_EN (1<<24)
187 #define v_COLOR_KEY_VAL(x) (((x)&0xffffff)<<0)
188 #define v_COLOR_KEY_EN(x) (((x)&1)<<24)
190 /* Layer Registers */
191 #define WIN0_YRGB_MST (0x20)
192 #define WIN0_CBR_MST (0x24)
193 #define WIN1_MST (0xa0)
194 #define HWC_MST (0x58)
196 #define WIN1_VIR (0x28)
197 #define WIN0_VIR (0x30)
198 #define m_YRGB_VIR (0x1fff << 0)
199 #define m_CBBR_VIR (0x1fff << 16)
201 #define v_YRGB_VIR(x) ((x & 0x1fff) << 0)
202 #define v_CBBR_VIR(x) ((x & 0x1fff) << 16)
204 #define v_ARGB888_VIRWIDTH(x) (((x) & 0x1fff) << 0)
205 #define v_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+(x % 3))&0x1fff)<<0)
206 #define v_RGB565_VIRWIDTH(x) ((DIV_ROUND_UP(x, 2)&0x1fff)<<0)
207 #define v_YUV_VIRWIDTH(x) ((DIV_ROUND_UP(x, 4)&0x1fff)<<0)
208 #define v_CBCR_VIR(x) ((x & 0x1fff) << 16)
210 #define WIN0_ACT_INFO (0x34)
211 #define WIN1_ACT_INFO (0xB4)
212 #define m_ACT_WIDTH (0x1fff << 0)
213 #define m_ACT_HEIGHT (0x1fff << 16)
214 #define v_ACT_WIDTH(x) (((x-1) & 0x1fff)<<0)
215 #define v_ACT_HEIGHT(x) (((x-1) & 0x1fff)<<16)
217 #define WIN0_DSP_INFO (0x38)
218 #define WIN1_DSP_INFO (0xB8)
219 #define v_DSP_WIDTH(x) (((x-1)&0x7ff)<<0)
220 #define v_DSP_HEIGHT(x) (((x-1)&0x7ff)<<16)
222 #define WIN0_DSP_ST (0x3C)
223 #define WIN1_DSP_ST (0xBC)
224 #define HWC_DSP_ST (0x5C)
225 #define v_DSP_STX(x) (((x)&0xfff)<<0)
226 #define v_DSP_STY(x) (((x)&0xfff)<<16)
228 #define WIN0_SCL_FACTOR_YRGB (0x40)
229 #define WIN0_SCL_FACTOR_CBR (0x44)
230 #define WIN1_SCL_FACTOR_YRGB (0xC0)
231 #define v_X_SCL_FACTOR(x) (((x)&0xffff)<<0)
232 #define v_Y_SCL_FACTOR(x) (((x)&0xffff)<<16)
234 #define WIN0_SCL_OFFSET (0x48)
235 #define WIN1_SCL_OFFSET (0xC8)
238 #define WIN1_LUT_ADDR (0x0400)
239 #define HWC_LUT_ADDR (0x0800)
241 /* Display Infomation Registers */
242 #define DSP_HTOTAL_HS_END (0x6C)
243 /*hsync pulse width*/
244 #define v_HSYNC(x) (((x)&0xfff)<<0)
245 /*horizontal period*/
246 #define v_HORPRD(x) (((x)&0xfff)<<16)
248 #define DSP_HACT_ST_END (0x70)
249 /*horizontal active end point*/
250 #define v_HAEP(x) (((x)&0xfff)<<0)
251 /*horizontal active start point*/
252 #define v_HASP(x) (((x)&0xfff)<<16)
254 #define DSP_VTOTAL_VS_END (0x74)
255 #define v_VSYNC(x) (((x)&0xfff)<<0)
256 #define v_VERPRD(x) (((x)&0xfff)<<16)
258 #define DSP_VACT_ST_END (0x78)
259 #define v_VAEP(x) (((x)&0xfff)<<0)
260 #define v_VASP(x) (((x)&0xfff)<<16)
262 #define DSP_VS_ST_END_F1 (0x7C)
263 #define v_VSYNC_END_F1(x) (((x)&0xfff)<<0)
264 #define v_VSYNC_ST_F1(x) (((x)&0xfff)<<16)
265 #define DSP_VACT_ST_END_F1 (0x80)
268 #define BCSH_CTRL (0xD0)
269 #define m_BCSH_EN (1 << 0)
270 #define m_BCSH_OUT_MODE (3 << 2)
271 #define m_BCSH_CSC_MODE (3 << 4)
273 #define v_BCSH_EN(x) ((1 & x) << 0)
274 #define v_BCSH_OUT_MODE(x) ((3 & x) << 2)
275 #define v_BCSH_CSC_MODE(x) ((3 & x) << 4)
277 #define BCSH_COLOR_BAR (0xD4)
278 #define v_BCSH_COLOR_BAR_Y(x) (((x)&0xf) << 0)
279 #define v_BCSH_COLOR_BAR_U(x) (((x)&0xf) << 8)
280 #define v_BCSH_COLOR_BAR_V(x) (((x)&0xf) << 16)
282 #define m_BCSH_COLOR_BAR_Y (0xf << 0)
283 #define m_BCSH_COLOR_BAR_U (0xf << 8)
284 #define m_BCSH_COLOR_BAR_V (0xf << 16)
286 #define BCSH_BCS (0xD8)
287 #define v_BCSH_BRIGHTNESS(x) (((x)&0x3f) << 0)
288 #define v_BCSH_CONTRAST(x) (((x)&0xff) << 8)
289 #define v_BCSH_SAT_CON(x) (((x)&0x1ff) << 16)
291 #define m_BCSH_BRIGHTNESS (0x3f << 0)
292 #define m_BCSH_CONTRAST (0xff << 8)
293 #define m_BCSH_SAT_CON (0x1ff << 16)
295 #define BCSH_H (0xDC)
296 #define v_BCSH_SIN_HUE(x) (((x)&0xff) << 0)
297 #define v_BCSH_COS_HUE(x) (((x)&0xff) << 8)
299 #define m_BCSH_SIN_HUE (0xff << 0)
300 #define m_BCSH_COS_HUE (0xff << 8)
303 #define AXI_BUS_CTRL (0x2C)
304 #define m_IO_PAD_CLK (1 << 31)
305 #define m_CORE_CLK_DIV_EN (1 << 30)
306 #define m_HDMI_DCLK_INVERT (1 << 23)
307 #define m_HDMI_DCLK_EN (1 << 22)
308 #define m_TVE_DAC_DCLK_INVERT (1 << 21)
309 #define m_TVE_DAC_DCLK_EN (1 << 20)
310 #define m_HDMI_DCLK_DIV_EN (1 << 19)
311 #define m_AXI_OUTSTANDING_MAX_NUM (0x1f << 12)
312 #define m_AXI_MAX_OUTSTANDING_EN (1 << 11)
313 #define m_MMU_EN (1 << 10)
314 #define m_NOC_HURRY_THRESHOLD (0xf << 6)
315 #define m_NOC_HURRY_VALUE (3 << 4)
316 #define m_NOC_HURRY_EN (1 << 3)
317 #define m_NOC_QOS_VALUE (3 << 1)
318 #define m_NOC_QOS_EN (1 << 0)
320 #define v_IO_PAD_CLK(x) ((x&1) << 31)
321 #define v_CORE_CLK_DIV_EN(x) ((x&1) << 30)
322 #define v_HDMI_DCLK_INVERT(x) ((x&1) << 23)
323 #define v_HDMI_DCLK_EN(x) ((x&1) << 22)
324 #define v_TVE_DAC_DCLK_INVERT(x) ((x&1) << 21)
325 #define v_TVE_DAC_DCLK_EN(x) ((x&1) << 20)
326 #define v_HDMI_DCLK_DIV_EN(x) ((x&1) << 19)
327 #define v_AXI_OUTSTANDING_MAX_NUM(x) ((x&0x1f) << 12)
328 #define v_AXI_MAX_OUTSTANDING_EN(x) ((x&1) << 11)
329 #define v_MMU_EN(x) ((x&1) << 10)
330 #define v_NOC_HURRY_THRESHOLD(x) ((x&0xf) << 6)
331 #define v_NOC_HURRY_VALUE(x) ((x&3) << 4)
332 #define v_NOC_HURRY_EN(x) ((x&1) << 3)
333 #define v_NOC_QOS_VALUE(x) ((x&3) << 1)
334 #define v_NOC_QOS_EN(x) ((x&1) << 0)
336 #define GATHER_TRANSFER (0x84)
337 #define m_WIN1_AXI_GATHER_NUM (0xf << 12)
338 #define m_WIN0_CBCR_AXI_GATHER_NUM (0x7 << 8)
339 #define m_WIN0_YRGB_AXI_GATHER_NUM (0xf << 4)
340 #define m_WIN1_AXI_GAHTER_EN (1 << 2)
341 #define m_WIN0_CBCR_AXI_GATHER_EN (1 << 1)
342 #define m_WIN0_YRGB_AXI_GATHER_EN (1 << 0)
344 #define v_WIN1_AXI_GATHER_NUM(x) ((x & 0xf) << 12)
345 #define v_WIN0_CBCR_AXI_GATHER_NUM(x) ((x & 0x7) << 8)
346 #define v_WIN0_YRGB_AXI_GATHER_NUM(x) ((x & 0xf) << 4)
347 #define v_WIN1_AXI_GAHTER_EN(x) ((x & 1) << 2)
348 #define v_WIN0_CBCR_AXI_GATHER_EN(x) ((x & 1) << 1)
349 #define v_WIN0_YRGB_AXI_GATHER_EN(x) ((x & 1) << 0)
351 #define VERSION_INFO (0x94)
352 #define m_MAJOR (0xff << 24)
353 #define m_MINOR (0xff << 16)
354 #define m_BUILD (0xffff)
356 #define REG_CFG_DONE (0x90)
358 /* TV Control Registers */
359 #define TV_CTRL (0x200)
360 #define TV_SYNC_TIMING (0x204)
361 #define TV_ACT_TIMING (0x208)
362 #define TV_ADJ_TIMING (0x20c)
363 #define TV_FREQ_SC (0x210)
364 #define TV_FILTER0 (0x214)
365 #define TV_FILTER1 (0x218)
366 #define TV_FILTER2 (0x21C)
367 #define TV_ACT_ST (0x234)
368 #define TV_ROUTING (0x238)
369 #define TV_SYNC_ADJUST (0x250)
370 #define TV_STATUS (0x254)
371 #define TV_RESET (0x268)
372 #define TV_SATURATION (0x278)
373 #define TV_BW_CTRL (0x28C)
374 #define TV_BRIGHTNESS_CONTRAST (0x290)
378 #define MMU_DTE_ADDR (0x0300)
379 #define v_MMU_DTE_ADDR(x) (((x)&0xffffffff)<<0)
380 #define m_MMU_DTE_ADDR (0xffffffff<<0)
382 #define MMU_STATUS (0x0304)
383 #define v_PAGING_ENABLED(x) (((x)&1)<<0)
384 #define v_PAGE_FAULT_ACTIVE(x) (((x)&1)<<1)
385 #define v_STAIL_ACTIVE(x) (((x)&1)<<2)
386 #define v_MMU_IDLE(x) (((x)&1)<<3)
387 #define v_REPLAY_BUFFER_EMPTY(x) (((x)&1)<<4)
388 #define v_PAGE_FAULT_IS_WRITE(x) (((x)&1)<<5)
389 #define v_PAGE_FAULT_BUS_ID(x) (((x)&0x1f)<<6)
390 #define m_PAGING_ENABLED (1<<0)
391 #define m_PAGE_FAULT_ACTIVE (1<<1)
392 #define m_STAIL_ACTIVE (1<<2)
393 #define m_MMU_IDLE (1<<3)
394 #define m_REPLAY_BUFFER_EMPTY (1<<4)
395 #define m_PAGE_FAULT_IS_WRITE (1<<5)
396 #define m_PAGE_FAULT_BUS_ID (0x1f<<6)
398 #define MMU_COMMAND (0x0308)
399 #define v_MMU_CMD(x) (((x)&0x3)<<0)
400 #define m_MMU_CMD (0x3<<0)
402 #define MMU_PAGE_FAULT_ADDR (0x030c)
403 #define v_PAGE_FAULT_ADDR(x) (((x)&0xffffffff)<<0)
404 #define m_PAGE_FAULT_ADDR (0xffffffff<<0)
406 #define MMU_ZAP_ONE_LINE (0x0310)
407 #define v_MMU_ZAP_ONE_LINE(x) (((x)&0xffffffff)<<0)
408 #define m_MMU_ZAP_ONE_LINE (0xffffffff<<0)
410 #define MMU_INT_RAWSTAT (0x0314)
411 #define v_PAGE_FAULT_RAWSTAT(x) (((x)&1)<<0)
412 #define v_READ_BUS_ERROR_RAWSTAT(x) (((x)&1)<<1)
413 #define m_PAGE_FAULT_RAWSTAT (1<<0)
414 #define m_READ_BUS_ERROR_RAWSTAT (1<<1)
416 #define MMU_INT_CLEAR (0x0318)
417 #define v_PAGE_FAULT_CLEAR(x) (((x)&1)<<0)
418 #define v_READ_BUS_ERROR_CLEAR(x) (((x)&1)<<1)
419 #define m_PAGE_FAULT_CLEAR (1<<0)
420 #define m_READ_BUS_ERROR_CLEAR (1<<1)
422 #define MMU_INT_MASK (0x031c)
423 #define v_PAGE_FAULT_MASK(x) (((x)&1)<<0)
424 #define v_READ_BUS_ERROR_MASK(x) (((x)&1)<<1)
425 #define m_PAGE_FAULT_MASK (1<<0)
426 #define m_READ_BUS_ERROR_MASK (1<<1)
428 #define MMU_INT_STATUS (0x0320)
429 #define v_PAGE_FAULT_STATUS(x) (((x)&1)<<0)
430 #define v_READ_BUS_ERROR_STATUS(x) (((x)&1)<<1)
431 #define m_PAGE_FAULT_STATUS (1<<0)
432 #define m_READ_BUS_ERROR_STATUS (1<<1)
434 #define MMU_AUTO_GATING (0x0324)
435 #define v_MMU_AUTO_GATING(x) (((x)&1)<<0)
436 #define m_MMU_AUTO_GATING (1<<0)
438 enum _vop_dma_burst {
445 VOP_FORMAT_ARGB888 = 0,
448 VOP_FORMAT_YCBCR420 = 4,
469 #define calscale(x, y) ((((u32)(x-1))*0x1000)/(y-1))
473 struct rk_lcdc_driver driver;
475 struct rk_screen *screen;
478 void *regsbak; /* back up reg */
479 u32 reg_phy_base; /* physical basic address of lcdc register*/
480 u32 len; /* physical map length of lcdc register*/
481 spinlock_t reg_lock; /* one time only one process allowed to
482 config the register*/
484 int __iomem *hwc_lut_addr_base;
485 int __iomem *dsp_lut_addr_base;
488 int prop; /*used for primary or */
489 /*extended display device*/
491 bool pwr18; /*if lcdc use 1.8v power supply*/
492 bool clk_on; /*if aclk or hclk is closed,
493 acess to register is not allowed*/
494 u8 atv_layer_cnt; /*active layer counter, when
495 atv_layer_cnt = 0,disable lcdc*/
499 struct clk *pd; /*lcdc power domain*/
500 struct clk *hclk; /*lcdc AHP clk*/
501 struct clk *dclk; /*lcdc dclk*/
502 struct clk *aclk; /*lcdc share memory frequency*/
505 u32 standby; /*1:standby,0:work*/
510 void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
512 u32 *_pv = (u32 *)lcdc_dev->regsbak;
514 _pv += (offset >> 2);
516 writel_relaxed(v, lcdc_dev->regs + offset);
520 u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
523 u32 *_pv = (u32 *)lcdc_dev->regsbak;
525 _pv += (offset >> 2);
526 v = readl_relaxed(lcdc_dev->regs + offset);
532 u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
534 u32 _v = readl_relaxed(lcdc_dev->regs + offset);
541 void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
543 u32 *_pv = (u32 *)lcdc_dev->regsbak;
545 _pv += (offset >> 2);
547 writel_relaxed(*_pv, lcdc_dev->regs + offset);
551 void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset, u32 msk)
553 u32 *_pv = (u32 *)lcdc_dev->regsbak;
555 _pv += (offset >> 2);
557 writel_relaxed(*_pv, lcdc_dev->regs + offset);
561 void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset, u32 msk, u32 v)
563 u32 *_pv = (u32 *)lcdc_dev->regsbak;
565 _pv += (offset >> 2);
568 writel_relaxed(*_pv, lcdc_dev->regs + offset);
571 static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
573 writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE);
577 #endif /* _RK3036_LCDC_H_ */