drivers/video/rockchip/lcdc/rk312x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk312x_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:      zhuangwenlong<zwl@rock-chips.com>
   6  *              zhengyang<zhengyang@rock-chips.com>
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/slab.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37 #include <linux/rockchip-iovmm.h>
  38 #include "rk312x_lcdc.h"
  39
  40 static int dbg_thresd;
  41 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  42
  43 #define DBG(level, x...) do {                   \
  44         if (unlikely(dbg_thresd >= level))      \
  45                 printk(KERN_INFO x); } while (0)
  46
  47 #define grf_writel(offset, v)   do { \
  48                         writel_relaxed(v, RK_GRF_VIRT + offset); \
  49                         dsb(); \
  50                         } while (0)
  51
  52 static struct rk_lcdc_win lcdc_win[] = {
  53         [0] = {
  54                .name = "win0",
  55                .id = 0,
  56                .support_3d = false,
  57                },
  58         [1] = {
  59                .name = "win1",
  60                .id = 1,
  61                .support_3d = false,
  62                },
  63         [2] = {
  64                .name = "hwc",
  65                .id = 2,
  66                .support_3d = false,
  67                },
  68 };
  69
  70 static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id)
  71 {
  72         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
  73         ktime_t timestamp = ktime_get();
  74         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  75
  76         if (int_reg & m_FS_INT_STA) {
  77                 timestamp = ktime_get();
  78                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  79                              v_FS_INT_CLEAR(1));
  80                 //if (lcdc_dev->driver.wait_fs) {
  81                 if (0) {
  82                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  83                         complete(&(lcdc_dev->driver.frame_done));
  84                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  85                 }
  86                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  87                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  88
  89         } else if (int_reg & m_LF_INT_STA) {
  90                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  91                              v_LF_INT_CLEAR(1));
  92         }
  93         return IRQ_HANDLED;
  94 }
  95
  96 static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
  97 {
  98 #ifdef CONFIG_RK_FPGA
  99         lcdc_dev->clk_on = 1;
 100         return 0;
 101 #endif
 102         if (!lcdc_dev->clk_on) {
 103                 clk_prepare_enable(lcdc_dev->hclk);
 104                 clk_prepare_enable(lcdc_dev->dclk);
 105                 clk_prepare_enable(lcdc_dev->aclk);
 106                 clk_prepare_enable(lcdc_dev->pd);
 107                 spin_lock(&lcdc_dev->reg_lock);
 108                 lcdc_dev->clk_on = 1;
 109                 spin_unlock(&lcdc_dev->reg_lock);
 110         }
 111
 112         return 0;
 113 }
 114
 115 static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 116 {
 117 #ifdef CONFIG_RK_FPGA
 118         lcdc_dev->clk_on = 0;
 119         return 0;
 120 #endif
 121         if (lcdc_dev->clk_on) {
 122                 spin_lock(&lcdc_dev->reg_lock);
 123                 lcdc_dev->clk_on = 0;
 124                 spin_unlock(&lcdc_dev->reg_lock);
 125                 mdelay(25);
 126                 clk_disable_unprepare(lcdc_dev->dclk);
 127                 clk_disable_unprepare(lcdc_dev->hclk);
 128                 clk_disable_unprepare(lcdc_dev->aclk);
 129                 clk_disable_unprepare(lcdc_dev->pd);
 130         }
 131
 132         return 0;
 133 }
 134
 135 static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 136 {
 137         u32 mask, val;
 138         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 139                                                     struct lcdc_device, driver);
 140         struct rk_screen *screen = dev_drv->cur_screen;
 141
 142         spin_lock(&lcdc_dev->reg_lock);
 143         if (likely(lcdc_dev->clk_on)) {
 144                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 145                         m_LF_INT_CLEAR | m_LF_INT_EN | m_LF_INT_NUM |
 146                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 147                 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) |
 148                         v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) |
 149                         v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0) |
 150                         v_LF_INT_NUM(screen->mode.vsync_len +
 151                                      screen->mode.upper_margin +
 152                                      screen->mode.yres);
 153                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 154                 spin_unlock(&lcdc_dev->reg_lock);
 155         } else {
 156                 spin_unlock(&lcdc_dev->reg_lock);
 157         }
 158         return 0;
 159 }
 160
 161 static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 162 {
 163         u32 mask, val;
 164
 165         spin_lock(&lcdc_dev->reg_lock);
 166         if (likely(lcdc_dev->clk_on)) {
 167                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 168                         m_LF_INT_CLEAR | m_LF_INT_EN |
 169                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 170                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 171                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 172                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 173                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 174                 spin_unlock(&lcdc_dev->reg_lock);
 175         } else {
 176                 spin_unlock(&lcdc_dev->reg_lock);
 177         }
 178         mdelay(1);
 179         return 0;
 180 }
 181
 182 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 183 {
 184         int reg = 0;
 185         u32 value = 0;
 186
 187         spin_lock(&lcdc_dev->reg_lock);
 188         for (reg = 0; reg < 0xdc; reg += 4) {
 189                 value = lcdc_readl(lcdc_dev, reg);
 190         }
 191         spin_unlock(&lcdc_dev->reg_lock);
 192 }
 193
 194 static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 195 {
 196         int win0_top = 0;
 197         u32 mask, val;
 198         enum data_format win0_format = lcdc_dev->driver.win[0]->format;
 199         enum data_format win1_format = lcdc_dev->driver.win[1]->format;
 200
 201         int win0_alpha_en = ((win0_format == ARGB888)
 202                              || (win0_format == ABGR888)) ? 1 : 0;
 203         int win1_alpha_en = ((win1_format == ARGB888)
 204                              || (win1_format == ABGR888)) ? 1 : 0;
 205         u32 *_pv = (u32 *) lcdc_dev->regsbak;
 206
 207         _pv += (DSP_CTRL0 >> 2);
 208         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 209         if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) {
 210                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 211                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0);
 212                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 213
 214                 mask = m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 215                 val = v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 216                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 217         } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2)
 218                    && (win1_alpha_en)) {
 219                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 220                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1);
 221                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 222
 223                 mask = m_WIN1_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 224                 val = v_WIN1_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 225                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 226         } else {
 227                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 228                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 229                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 230         }
 231
 232         return 0;
 233 }
 234
 235 static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev,
 236                                       struct rk_lcdc_win *win)
 237 {
 238         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
 239         struct rk_screen *screen = dev_drv->cur_screen;
 240
 241         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
 242                 switch (win->fmt_cfg) {
 243                 case VOP_FORMAT_ARGB888:
 244                 case VOP_FORMAT_RGB888:
 245                 case VOP_FORMAT_RGB565:
 246                         if ((screen->mode.xres < 1280 ) &&
 247                             (screen->mode.yres < 720)) {
 248                                 win->csc_mode = VOP_R2Y_CSC_BT601;
 249                         } else {
 250                                 win->csc_mode = VOP_R2Y_CSC_BT709;
 251                         }
 252                         break;
 253                 default:
 254                         break;
 255                 }
 256                 if (win->id  == 0) {
 257                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 258                                      v_WIN0_CSC_MODE(win->csc_mode));
 259                 } else if (win->id  == 1) {
 260                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE,
 261                                      v_WIN1_CSC_MODE(win->csc_mode));
 262                 }
 263         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
 264                 switch (win->fmt_cfg) {
 265                 case VOP_FORMAT_YCBCR420:
 266                         if (win->id  == 0) {
 267                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
 268                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 269                                              v_WIN0_CSC_MODE(win->csc_mode));
 270                         }
 271                         break;
 272                 default:
 273                         break;
 274                 }
 275         }
 276
 277 }
 278
 279
 280 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 281                                    struct rk_lcdc_win *win)
 282 {
 283         u32 mask, val;
 284
 285         if (win->state == 1) {
 286                 if (lcdc_dev->soc_type == VOP_RK312X)
 287                         lcdc_layer_csc_mode(lcdc_dev, win);
 288
 289                 if (win->id == 0) {
 290                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 291                         val = v_WIN0_EN(win->state) |
 292                                 v_WIN0_FORMAT(win->fmt_cfg) |
 293                                 v_WIN0_RB_SWAP(win->swap_rb);
 294                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 295                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 296                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 297                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 298                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 299                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 300                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 301
 302                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 303                                      m_YRGB_VIR | m_CBBR_VIR,
 304                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 305                                      v_CBCR_VIR(win->area[0].uv_vir_stride));
 306                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 307                                     v_ACT_WIDTH(win->area[0].xact) |
 308                                     v_ACT_HEIGHT(win->area[0].yact));
 309                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 310                                     v_DSP_STX(win->area[0].dsp_stx) |
 311                                     v_DSP_STY(win->area[0].dsp_sty));
 312                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 313                                     v_DSP_WIDTH(win->area[0].xsize) |
 314                                     v_DSP_HEIGHT(win->area[0].ysize));
 315
 316                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 317                                     win->area[0].y_addr);
 318                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 319                                     win->area[0].uv_addr);
 320                 } else if (win->id == 1) {
 321                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 322                         val = v_WIN1_EN(win->state) |
 323                                 v_WIN1_FORMAT(win->fmt_cfg) |
 324                                 v_WIN1_RB_SWAP(win->swap_rb);
 325                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 326                         /* rk312x unsupport win1 scale */
 327                         if (lcdc_dev->soc_type == VOP_RK3036) {
 328                                 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 329                                         v_X_SCL_FACTOR(win->scale_yrgb_x) |
 330                                         v_Y_SCL_FACTOR(win->scale_yrgb_y));
 331                                 lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 332                                             v_ACT_WIDTH(win->area[0].xact) |
 333                                             v_ACT_HEIGHT(win->area[0].yact));
 334                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 335                                             v_DSP_WIDTH(win->area[0].xsize) |
 336                                             v_DSP_HEIGHT(win->area[0].ysize));
 337                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 338                                             v_DSP_STX(win->area[0].dsp_stx) |
 339                                             v_DSP_STY(win->area[0].dsp_sty));
 340                                 lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 341                         } else {
 342                                 lcdc_writel(lcdc_dev, WIN1_DSP_INFO_RK312X,
 343                                             v_DSP_WIDTH(win->area[0].xsize) |
 344                                             v_DSP_HEIGHT(win->area[0].ysize));
 345                                 lcdc_writel(lcdc_dev, WIN1_DSP_ST_RK312X,
 346                                             v_DSP_STX(win->area[0].dsp_stx) |
 347                                             v_DSP_STY(win->area[0].dsp_sty));
 348
 349                                 lcdc_writel(lcdc_dev, WIN1_MST_RK312X, win->area[0].y_addr);
 350                         }
 351
 352                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 353                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 354
 355
 356                 } else if (win->id == 2) {
 357                 }
 358         } else {
 359                 win->area[0].y_addr = 0;
 360                 win->area[0].uv_addr = 0;
 361                 if (win->id == 0)
 362                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN,
 363                                      v_WIN0_EN(0));
 364                 else if (win->id == 1)
 365                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN,
 366                                      v_WIN1_EN(0));
 367                 else if (win->id == 2)
 368                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
 369         }
 370         rk312x_lcdc_alpha_cfg(lcdc_dev);
 371 }
 372
 373 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id,
 374                               bool open)
 375 {
 376         spin_lock(&lcdc_dev->reg_lock);
 377         if (likely(lcdc_dev->clk_on)
 378             && lcdc_dev->driver.win[win_id]->state != open) {
 379                 if (open) {
 380                         if (!lcdc_dev->atv_layer_cnt) {
 381                                 dev_info(lcdc_dev->dev,
 382                                          "wakeup from standby!\n");
 383                                 lcdc_dev->standby = 0;
 384                         }
 385                         lcdc_dev->atv_layer_cnt++;
 386                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
 387                         lcdc_dev->atv_layer_cnt--;
 388                 }
 389                 lcdc_dev->driver.win[win_id]->state = open;
 390                 if (!open) {
 391                         lcdc_layer_update_regs(lcdc_dev,
 392                                                lcdc_dev->driver.win[win_id]);
 393                         lcdc_cfg_done(lcdc_dev);
 394                 }
 395                 /*if no layer used,disable lcdc */
 396                 if (!lcdc_dev->atv_layer_cnt) {
 397                         dev_info(lcdc_dev->dev,
 398                                  "no layer is used,go to standby!\n");
 399                         lcdc_dev->standby = 1;
 400                 }
 401         }
 402         spin_unlock(&lcdc_dev->reg_lock);
 403 }
 404
 405 static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 406 {
 407         struct lcdc_device *lcdc_dev =
 408             container_of(dev_drv, struct lcdc_device, driver);
 409         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 410         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 411         int timeout;
 412         unsigned long flags;
 413         spin_lock(&lcdc_dev->reg_lock);
 414         if (likely(lcdc_dev->clk_on)) {
 415                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 416                              v_LCDC_STANDBY(lcdc_dev->standby));
 417                 lcdc_layer_update_regs(lcdc_dev, win0);
 418                 lcdc_layer_update_regs(lcdc_dev, win1);
 419                 rk312x_lcdc_alpha_cfg(lcdc_dev);
 420                 lcdc_cfg_done(lcdc_dev);
 421
 422         }
 423         spin_unlock(&lcdc_dev->reg_lock);
 424         //if (dev_drv->wait_fs) {
 425         if (0) {
 426                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 427                 init_completion(&dev_drv->frame_done);
 428                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 429                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 430                                                       msecs_to_jiffies
 431                                                       (dev_drv->cur_screen->ft +
 432                                                        5));
 433                 if (!timeout && (!dev_drv->frame_done.done)) {
 434                         dev_warn(lcdc_dev->dev,
 435                                  "wait for new frame start time out!\n");
 436                         return -ETIMEDOUT;
 437                 }
 438         }
 439         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 440         return 0;
 441
 442 }
 443
 444 static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 445 {
 446         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0xdc);
 447 }
 448
 449 static void rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 450 {
 451         u32 mask, val;
 452         struct lcdc_device *lcdc_dev =
 453             container_of(dev_drv, struct lcdc_device, driver);
 454
 455         spin_lock(&lcdc_dev->reg_lock);
 456         if (likely(lcdc_dev->clk_on)) {
 457                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 458                         m_AXI_OUTSTANDING_MAX_NUM;
 459                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 460                         v_AXI_MAX_OUTSTANDING_EN(1);
 461                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 462         }
 463         spin_unlock(&lcdc_dev->reg_lock);
 464 }
 465
 466 static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
 467 {
 468         int i = 0;
 469         int __iomem *c;
 470         int v;
 471         struct lcdc_device *lcdc_dev =
 472                 container_of(dev_drv, struct lcdc_device, driver);
 473
 474         spin_lock(&lcdc_dev->reg_lock);
 475         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 476         lcdc_cfg_done(lcdc_dev);
 477         mdelay(25);
 478         for (i = 0; i < 256; i++) {
 479                 v = dev_drv->cur_screen->dsp_lut[i];
 480                 c = lcdc_dev->dsp_lut_addr_base + i;
 481                 writel_relaxed(v, c);
 482
 483         }
 484         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 485         lcdc_cfg_done(lcdc_dev);
 486         spin_unlock(&lcdc_dev->reg_lock);
 487         return 0;
 488
 489 }
 490
 491 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 492 {
 493 #ifdef CONFIG_RK_FPGA
 494         return 0;
 495 #endif
 496         int ret, fps;
 497         struct lcdc_device *lcdc_dev =
 498             container_of(dev_drv, struct lcdc_device, driver);
 499         struct rk_screen *screen = dev_drv->cur_screen;
 500
 501         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 502         if (ret)
 503                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
 504         lcdc_dev->pixclock =
 505             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 506         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 507
 508         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 509         screen->ft = 1000 / fps;
 510         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 511                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 512         return 0;
 513
 514 }
 515
 516 /********do basic init*********/
 517 static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 518 {
 519         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 520                                                     struct lcdc_device, driver);
 521         if (lcdc_dev->pre_init)
 522                 return 0;
 523
 524         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 525         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 526         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 527         lcdc_dev->sclk = devm_clk_get(lcdc_dev->dev, "sclk_lcdc");
 528         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 529         lcdc_dev->pll_sclk = devm_clk_get(lcdc_dev->dev, "sclk_pll");
 530
 531         if ( /*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) ||
 532             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 533                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 534                         lcdc_dev->id);
 535         }
 536
 537         rk_disp_pwr_enable(dev_drv);
 538         rk312x_lcdc_clk_enable(lcdc_dev);
 539
 540         /* backup reg config at uboot */
 541         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 542
 543         /* config for the FRC mode of dither down */
 544         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 545         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 546         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55);
 547         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55);
 548         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 549         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 550
 551         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0));
 552         lcdc_cfg_done(lcdc_dev);
 553         if (dev_drv->iommu_enabled)     /* disable win0 to workaround iommu pagefault */
 554                 lcdc_layer_enable(lcdc_dev, 0, 0);
 555         lcdc_dev->pre_init = true;
 556
 557         return 0;
 558 }
 559
 560 static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev)
 561 {
 562         u32 mask, val;
 563
 564         spin_lock(&lcdc_dev->reg_lock);
 565         if (likely(lcdc_dev->clk_on)) {
 566                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 567                         m_LF_INT_CLEAR | m_LF_INT_EN |
 568                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 569                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 570                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 571                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 572                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 573                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY);
 574                 lcdc_cfg_done(lcdc_dev);
 575                 spin_unlock(&lcdc_dev->reg_lock);
 576         } else {
 577                 spin_unlock(&lcdc_dev->reg_lock);
 578         }
 579         mdelay(1);
 580
 581 }
 582
 583 static u32 calc_sclk_freq(struct rk_screen *src_screen, struct rk_screen *dst_screen)
 584 {
 585         u32 dsp_vtotal;
 586         u64 dsp_htotal;
 587         u32 dsp_in_vtotal;
 588         u64 dsp_in_htotal;
 589         u64 sclk_freq;
 590
 591         if (!src_screen || !dst_screen)
 592                 return 0;
 593
 594         dsp_vtotal = dst_screen->mode.yres;
 595         dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len +
 596                      dst_screen->mode.xres + dst_screen->mode.right_margin;
 597         dsp_in_vtotal = src_screen->mode.yres;
 598         dsp_in_htotal = src_screen->mode.left_margin +
 599                         src_screen->mode.hsync_len +
 600                         src_screen->mode.xres + src_screen->mode.right_margin;
 601         sclk_freq = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock;
 602         do_div(sclk_freq, dsp_in_vtotal * dsp_in_htotal);
 603
 604         return (u32)sclk_freq;
 605 }
 606
 607 #define SCLK_PLL_LIMIT  594000000
 608 static u32 calc_sclk_pll_freq(u32 sclk_freq)
 609 {
 610 #define ACCURACY_LEV    100
 611         u32 pll_freq = 0;
 612         u32 decimal_num = 0;
 613         u16 max_multi_num = 0, multi_num = 0, remainder_num = 0;
 614         u32 less_delta = 0, greater_delta = 0;
 615
 616         if (sclk_freq == 0)
 617                 return 0;
 618
 619         max_multi_num = SCLK_PLL_LIMIT / sclk_freq;
 620         decimal_num = (sclk_freq / (1000000 / ACCURACY_LEV)) % ACCURACY_LEV;
 621         multi_num = ACCURACY_LEV / decimal_num;
 622
 623         if (multi_num > max_multi_num) {
 624                 multi_num = max_multi_num;
 625         } else if (decimal_num != 0) {
 626                 remainder_num = ACCURACY_LEV % decimal_num;
 627                 if (remainder_num != 0) {
 628                         less_delta = ACCURACY_LEV - (decimal_num * multi_num);
 629                         greater_delta = decimal_num * (multi_num + 1) - ACCURACY_LEV;
 630                         multi_num = (less_delta < greater_delta) ? multi_num : (multi_num + 1);
 631                 }
 632         }
 633
 634         pll_freq = sclk_freq * multi_num;
 635         return pll_freq;
 636 }
 637
 638 static int calc_dsp_frm_vst_hst(struct rk_screen *src, struct rk_screen *dst)
 639 {
 640         u32 BP_in, BP_out;
 641         u32 v_scale_ratio;
 642         long long  T_frm_st;
 643         u64 T_BP_in, T_BP_out, T_Delta, Tin;
 644         u64 rate = (1 << 16);
 645         u64 temp;
 646         u32 dsp_htotal, src_htotal, src_vtotal;
 647
 648         if (unlikely(!src) || unlikely(!dst))
 649                 return -1;
 650
 651         dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len +
 652                      dst->mode.xres + dst->mode.right_margin;
 653         src_htotal = src->mode.left_margin + src->mode.hsync_len +
 654                      src->mode.xres + src->mode.right_margin;
 655         src_vtotal = src->mode.upper_margin + src->mode.vsync_len +
 656                      src->mode.yres + src->mode.lower_margin;
 657         BP_in  = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal;
 658         BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal;
 659
 660         v_scale_ratio = dst->mode.yres / src->mode.yres;
 661
 662         T_BP_in = rate * BP_in;
 663         do_div(T_BP_in, src->mode.pixclock);
 664         T_BP_out = rate * BP_out;
 665         do_div(T_BP_out, dst->mode.pixclock);
 666         if (v_scale_ratio < 2)
 667                 T_Delta = rate * 4 * src_htotal;
 668         else
 669                 T_Delta = rate * 12 * src_htotal;
 670
 671         do_div(T_Delta, src->mode.pixclock);
 672         Tin = rate * src_vtotal * src_htotal;
 673         do_div(Tin, src->mode.pixclock);
 674
 675         T_frm_st = (T_BP_in + T_Delta - T_BP_out);
 676         if (T_frm_st < 0)
 677                 T_frm_st  += Tin;
 678
 679         temp = T_frm_st * src->mode.pixclock;
 680         dst->scl_hst = do_div(temp, src_htotal * rate);
 681         dst->scl_vst = temp;
 682         dst->scl_hst = (T_frm_st * src->mode.pixclock / rate - dst->scl_vst * src_htotal);
 683
 684         return 0;
 685 }
 686
 687 static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 688                                   struct rk_screen *dst_screen, bool enable)
 689 {
 690         u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
 691         u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
 692         u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
 693         u32 scl_v_factor, scl_h_factor;
 694         u32 dst_frame_hst, dst_frame_vst;
 695         u32 src_w, src_h, dst_w, dst_h;
 696         u16 bor_right = 0;
 697         u16 bor_left = 0;
 698         u16 bor_up = 0;
 699         u16 bor_down = 0;
 700         u32 pll_freq = 0;
 701         struct rk_screen *src;
 702         struct rk_screen *dst;
 703         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 704                                                     struct lcdc_device, driver);
 705
 706         if (unlikely(!lcdc_dev->clk_on))
 707                 return 0;
 708
 709         if (!enable) {
 710                 spin_lock(&lcdc_dev->reg_lock);
 711                 lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 712                                 m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 713                                 v_SCALER_EN(0) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(0));
 714                 spin_unlock(&lcdc_dev->reg_lock);
 715                 if (lcdc_dev->sclk_on) {
 716                         clk_disable_unprepare(lcdc_dev->sclk);
 717                         lcdc_dev->sclk_on = false;
 718                 }
 719                 dev_dbg(lcdc_dev->dev, "%s: disable\n", __func__);
 720                 return 0;
 721         }
 722
 723         /* rk312x used one lcdc to apply dual disp
 724          * hdmi screen is used for scaler src
 725          * prmry screen is used for scaler dst
 726          */
 727         dst = dst_screen;
 728         src = dev_drv->cur_screen;
 729         if (!dst || !src) {
 730                 dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__);
 731                 return -EINVAL;
 732         }
 733
 734         if (!lcdc_dev->sclk_on) {
 735                 clk_prepare_enable(lcdc_dev->sclk);
 736                 lcdc_dev->s_pixclock = calc_sclk_freq(src, dst);
 737                 pll_freq = calc_sclk_pll_freq(lcdc_dev->s_pixclock);
 738                 clk_set_rate(lcdc_dev->pll_sclk, pll_freq);
 739                 clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock);
 740                 lcdc_dev->sclk_on = true;
 741                 dev_info(lcdc_dev->dev, "%s:sclk=%d\n", __func__,
 742                          lcdc_dev->s_pixclock);
 743         }
 744
 745         /* config scale timing */
 746         calc_dsp_frm_vst_hst(src, dst);
 747         dst_frame_vst = dst->scl_vst;
 748         dst_frame_hst = dst->scl_hst;
 749
 750         dsp_htotal    = dst->mode.hsync_len + dst->mode.left_margin +
 751                         dst->mode.xres + dst->mode.right_margin;
 752         dsp_hs_end    = dst->mode.hsync_len;
 753
 754         dsp_vtotal    = dst->mode.vsync_len + dst->mode.upper_margin +
 755                         dst->mode.yres + dst->mode.lower_margin;
 756         dsp_vs_end    = dst->mode.vsync_len;
 757
 758         dsp_hbor_end  = dst->mode.hsync_len + dst->mode.left_margin +
 759                         dst->mode.xres;
 760         dsp_hbor_st   = dst->mode.hsync_len + dst->mode.left_margin;
 761         dsp_vbor_end  = dst->mode.vsync_len + dst->mode.upper_margin +
 762                         dst->mode.yres;
 763         dsp_vbor_st   = dst->mode.vsync_len + dst->mode.upper_margin;
 764
 765         dsp_hact_st   = dsp_hbor_st  + bor_left;
 766         dsp_hact_end  = dsp_hbor_end - bor_right;
 767         dsp_vact_st   = dsp_vbor_st  + bor_up;
 768         dsp_vact_end  = dsp_vbor_end - bor_down;
 769
 770         src_w = src->mode.xres;
 771         src_h = src->mode.yres;
 772         dst_w = dsp_hact_end - dsp_hact_st;
 773         dst_h = dsp_vact_end - dsp_vact_st;
 774
 775         /* calc scale factor */
 776         scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1);
 777         scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1);
 778
 779         spin_lock(&lcdc_dev->reg_lock);
 780         if (dst->color_mode != src->color_mode) {
 781                 dev_drv->output_color = dst->color_mode;
 782                 if (dev_drv->output_color == COLOR_YCBCR)
 783                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 784                 else
 785                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 786                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 787                              v_SW_OVERLAY_MODE(dev_drv->overlay_mode));
 788         }
 789
 790         lcdc_writel(lcdc_dev, SCALER_FACTOR,
 791                     v_SCALER_H_FACTOR(scl_h_factor) |
 792                     v_SCALER_V_FACTOR(scl_v_factor));
 793
 794         lcdc_writel(lcdc_dev, SCALER_FRAME_ST,
 795                     v_SCALER_FRAME_HST(dst_frame_hst) |
 796                     v_SCALER_FRAME_VST(dst_frame_vst));
 797         lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING,
 798                     v_SCALER_HS_END(dsp_hs_end) |
 799                     v_SCALER_HTOTAL(dsp_htotal));
 800         lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END,
 801                     v_SCALER_HAEP(dsp_hact_end) |
 802                     v_SCALER_HASP(dsp_hact_st));
 803         lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING,
 804                     v_SCALER_VS_END(dsp_vs_end) |
 805                     v_SCALER_VTOTAL(dsp_vtotal));
 806         lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END,
 807                     v_SCALER_VAEP(dsp_vact_end) |
 808                     v_SCALER_VASP(dsp_vact_st));
 809         lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING,
 810                     v_SCALER_HBOR_END(dsp_hbor_end) |
 811                     v_SCALER_HBOR_ST(dsp_hbor_st));
 812         lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING,
 813                     v_SCALER_VBOR_END(dsp_vbor_end) |
 814                     v_SCALER_VBOR_ST(dsp_vbor_st));
 815         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 816                     m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 817                     v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(1));
 818
 819         lcdc_cfg_done(lcdc_dev);
 820         spin_unlock(&lcdc_dev->reg_lock);
 821
 822         return 0;
 823 }
 824
 825 static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 826 {
 827         u16 face = 0;
 828         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 829                                                     struct lcdc_device, driver);
 830         struct rk_screen *screen = dev_drv->cur_screen;
 831         u16 right_margin = screen->mode.right_margin;
 832         u16 left_margin = screen->mode.left_margin;
 833         u16 lower_margin = screen->mode.lower_margin;
 834         u16 upper_margin = screen->mode.upper_margin;
 835         u16 x_res = screen->mode.xres;
 836         u16 y_res = screen->mode.yres;
 837         u32 mask, val;
 838
 839         spin_lock(&lcdc_dev->reg_lock);
 840         if (likely(lcdc_dev->clk_on)) {
 841                 /* Select output color domain */
 842                 dev_drv->output_color = screen->color_mode;
 843                 if (lcdc_dev->soc_type == VOP_RK312X) {
 844                         if (dev_drv->output_color == COLOR_YCBCR)
 845                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 846                         else
 847                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 848                 } else {
 849                         dev_drv->output_color = COLOR_RGB;
 850                         dev_drv->overlay_mode = VOP_RGB_DOMAIN;
 851                 }
 852
 853                 switch (screen->type) {
 854                 case SCREEN_RGB:
 855                         if (lcdc_dev->soc_type == VOP_RK312X) {
 856                                 mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT;
 857                                 val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0);
 858                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 859                         }
 860                         break;
 861                 case SCREEN_LVDS:
 862                         if (lcdc_dev->soc_type == VOP_RK312X) {
 863                                 mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT;
 864                                 val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(1);
 865                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 866                         }
 867                         break;
 868                 case SCREEN_MIPI:
 869                         if (lcdc_dev->soc_type == VOP_RK312X) {
 870                                 mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT;
 871                                 val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0);
 872                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 873                         }
 874                         break;
 875                 case SCREEN_HDMI:
 876                         mask = m_HDMI_DCLK_EN;
 877                         val = v_HDMI_DCLK_EN(1);
 878                         if (screen->pixelrepeat) {
 879                                 mask |= m_CORE_CLK_DIV_EN;
 880                                 val |= v_CORE_CLK_DIV_EN(1);
 881                         } else {
 882                                 mask |= m_CORE_CLK_DIV_EN;
 883                                 val |= v_CORE_CLK_DIV_EN(0);
 884                         }
 885                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 886                         if (lcdc_dev->soc_type == VOP_RK312X) {
 887                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 888                                              m_SW_UV_OFFSET_EN,
 889                                              v_SW_UV_OFFSET_EN(0));
 890                                 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
 891                                        m_HDMI_DEN_POL;
 892                                 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
 893                                       v_HDMI_VSYNC_POL(screen->pin_vsync) |
 894                                       v_HDMI_DEN_POL(screen->pin_den);
 895                                 lcdc_msk_reg(lcdc_dev, INT_SCALER, mask, val);
 896                         } else {
 897                                 mask = (1 << 4) | (1 << 5) | (1 << 6);
 898                                 val = (screen->pin_hsync << 4) |
 899                                         (screen->pin_vsync << 5) |
 900                                         (screen->pin_den << 6);
 901                                 grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
 902                         }
 903                         break;
 904                 case SCREEN_TVOUT:
 905                         mask = m_TVE_DAC_DCLK_EN;
 906                         val = v_TVE_DAC_DCLK_EN(1);
 907                         if (screen->pixelrepeat) {
 908                                 mask |= m_CORE_CLK_DIV_EN;
 909                                 val |= v_CORE_CLK_DIV_EN(1);
 910                         }
 911                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 912                         if (x_res == 720 && y_res == 576)
 913                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 914                                              v_TVE_MODE(TV_PAL));
 915                         else if (x_res == 720 && y_res == 480)
 916                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 917                                              v_TVE_MODE(TV_NTSC));
 918                         else {
 919                                 dev_err(lcdc_dev->dev,
 920                                         "unsupported video timing!\n");
 921                                 return -1;
 922                         }
 923                         if (lcdc_dev->soc_type == VOP_RK312X) {
 924                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
 925                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 926                                              m_SW_UV_OFFSET_EN,
 927                                              v_SW_UV_OFFSET_EN(1));
 928                         }
 929                         break;
 930                 default:
 931                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 932                         break;
 933                 }
 934                 if (lcdc_dev->soc_type == VOP_RK312X) {
 935                         switch (screen->face) {
 936                         case OUT_P565:
 937                                 face = OUT_P565;
 938                                 mask = m_DITHER_DOWN_EN |
 939                                         m_DITHER_DOWN_MODE |
 940                                         m_DITHER_DOWN_SEL;
 941                                 val = v_DITHER_DOWN_EN(1) |
 942                                         v_DITHER_DOWN_MODE(0) |
 943                                         v_DITHER_DOWN_SEL(1);
 944                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 945                                 break;
 946                         case OUT_P666:
 947                                 face = OUT_P666;
 948                                 mask = m_DITHER_DOWN_EN |
 949                                         m_DITHER_DOWN_MODE |
 950                                         m_DITHER_DOWN_SEL;
 951                                 val = v_DITHER_DOWN_EN(1) |
 952                                         v_DITHER_DOWN_MODE(1) |
 953                                         v_DITHER_DOWN_SEL(1);
 954                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 955                                 break;
 956                         case OUT_D888_P565:
 957                                 face = OUT_P888;
 958                                 mask = m_DITHER_DOWN_EN |
 959                                         m_DITHER_DOWN_MODE |
 960                                         m_DITHER_DOWN_SEL;
 961                                 val = v_DITHER_DOWN_EN(1) |
 962                                         v_DITHER_DOWN_MODE(0) |
 963                                         v_DITHER_DOWN_SEL(1);
 964                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 965                                 break;
 966                         case OUT_D888_P666:
 967                                 face = OUT_P888;
 968                                 mask = m_DITHER_DOWN_EN |
 969                                         m_DITHER_DOWN_MODE |
 970                                         m_DITHER_DOWN_SEL;
 971                                 val = v_DITHER_DOWN_EN(1) |
 972                                         v_DITHER_DOWN_MODE(1) |
 973                                         v_DITHER_DOWN_SEL(1);
 974                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 975                                 break;
 976                         case OUT_P888:
 977                                 face = OUT_P888;
 978                                 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
 979                                 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
 980                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 981                                 break;
 982                         default:
 983                                 dev_err(lcdc_dev->dev, "un supported interface!\n");
 984                                 break;
 985                         }
 986                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 987                                      v_SW_OVERLAY_MODE(dev_drv->overlay_mode));
 988                 }
 989
 990                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 991                     m_DEN_POL | m_DCLK_POL;
 992                 val = v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) |
 993                     v_VSYNC_POL(screen->pin_vsync) |
 994                     v_DEN_POL(screen->pin_den) |
 995                     v_DCLK_POL(screen->pin_dclk);
 996                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 997
 998                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 999                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1000                     m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN;
1001
1002                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
1003                     v_DSP_RB_SWAP(screen->swap_rb) |
1004                     v_DSP_RG_SWAP(screen->swap_rg) |
1005                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1006                     v_DSP_DUMMY_SWAP(screen->swap_dumy) |
1007                     v_BLANK_EN(0) | v_BLACK_EN(0);
1008                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1009
1010                 /* config timing */
1011                 val = v_HSYNC(screen->mode.hsync_len) |
1012                     v_HORPRD(screen->mode.hsync_len + left_margin + x_res +
1013                              right_margin);
1014                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
1015                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
1016                     v_HASP(screen->mode.hsync_len + left_margin);
1017                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
1018
1019                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1020                         /* First Field Timing */
1021                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
1022                                     v_VSYNC(screen->mode.vsync_len) |
1023                                     v_VERPRD(2 * (screen->mode.vsync_len + upper_margin + lower_margin) +
1024                                              y_res + 1));
1025                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
1026                                     v_VAEP(screen->mode.vsync_len +
1027                                            upper_margin + y_res / 2) |
1028                                     v_VASP(screen->mode.vsync_len +
1029                                            upper_margin));
1030                         /* Second Field Timing */
1031                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
1032                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
1033                                                   upper_margin + y_res / 2 +
1034                                                   lower_margin) |
1035                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len +
1036                                                    upper_margin + y_res / 2 +
1037                                                    lower_margin));
1038                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
1039                                     v_VAEP(2 * (screen->mode.vsync_len + upper_margin) +
1040                                            y_res + lower_margin + 1) |
1041                                     v_VASP(2 * (screen->mode.vsync_len + upper_margin) +
1042                                            y_res / 2 + lower_margin + 1));
1043
1044                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1045                                      m_INTERLACE_DSP_EN |
1046                                      m_WIN0_YRGB_DEFLICK_EN |
1047                                      m_WIN0_CBR_DEFLICK_EN |
1048                                      m_INTERLACE_FIELD_POL |
1049                                      m_WIN0_INTERLACE_EN |
1050                                      m_WIN1_INTERLACE_EN,
1051                                      v_INTERLACE_DSP_EN(1) |
1052                                      v_WIN0_YRGB_DEFLICK_EN(1) |
1053                                      v_WIN0_CBR_DEFLICK_EN(1) |
1054                                      v_INTERLACE_FIELD_POL(0) |
1055                                      v_WIN0_INTERLACE_EN(1) |
1056                                      v_WIN1_INTERLACE_EN(1));
1057                 } else {
1058                         val = v_VSYNC(screen->mode.vsync_len) |
1059                             v_VERPRD(screen->mode.vsync_len + upper_margin +
1060                                      y_res + lower_margin);
1061                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
1062
1063                         val = v_VAEP(screen->mode.vsync_len + upper_margin + y_res) |
1064                             v_VASP(screen->mode.vsync_len + upper_margin);
1065                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
1066
1067                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1068                                      m_INTERLACE_DSP_EN |
1069                                      m_WIN0_YRGB_DEFLICK_EN |
1070                                      m_WIN0_CBR_DEFLICK_EN |
1071                                      m_INTERLACE_FIELD_POL |
1072                                      m_WIN0_INTERLACE_EN |
1073                                      m_WIN1_INTERLACE_EN,
1074                                      v_INTERLACE_DSP_EN(0) |
1075                                      v_WIN0_YRGB_DEFLICK_EN(0) |
1076                                      v_WIN0_CBR_DEFLICK_EN(0) |
1077                                      v_INTERLACE_FIELD_POL(0) |
1078                                      v_WIN0_INTERLACE_EN(0) |
1079                                      v_WIN1_INTERLACE_EN(0));
1080                 }
1081
1082         }
1083         spin_unlock(&lcdc_dev->reg_lock);
1084
1085         rk312x_lcdc_set_dclk(dev_drv);
1086         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1087                 dev_drv->trsm_ops->enable();
1088         if (screen->init)
1089                 screen->init();
1090
1091         return 0;
1092 }
1093
1094 static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1095                             bool open)
1096 {
1097         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1098                                                     struct lcdc_device, driver);
1099
1100         /* enable clk,when first layer open */
1101         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1102                 rockchip_set_system_status(SYS_STATUS_LCDC0);
1103                 rk312x_lcdc_pre_init(dev_drv);
1104 #if defined(CONFIG_ROCKCHIP_IOMMU)
1105                 if (dev_drv->iommu_enabled) {
1106                         if (!dev_drv->mmu_dev) {
1107                                 dev_drv->mmu_dev =
1108                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1109                                 if (dev_drv->mmu_dev) {
1110                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1111                                                                   dev_drv->dev);
1112                                         rockchip_iovmm_activate(dev_drv->dev);
1113                                 } else {
1114                                         dev_err(dev_drv->dev,
1115                                                 "failed to get rockchip iommu device\n");
1116                                         return -1;
1117                                 }
1118                         }
1119                 }
1120 #endif
1121                 rk312x_lcdc_reg_restore(lcdc_dev);
1122                 if (dev_drv->iommu_enabled)
1123                         rk312x_lcdc_mmu_en(dev_drv);
1124                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1125                         rk312x_lcdc_set_dclk(dev_drv);
1126                         rk312x_lcdc_enable_irq(dev_drv);
1127                 } else {
1128                         rk312x_load_screen(dev_drv, 1);
1129                 }
1130
1131                 /* set screen lut */
1132                 if (dev_drv->cur_screen->dsp_lut)
1133                         rk312x_lcdc_set_lut(dev_drv);
1134         }
1135
1136         if (win_id < ARRAY_SIZE(lcdc_win))
1137                 lcdc_layer_enable(lcdc_dev, win_id, open);
1138         else
1139                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1140
1141         /* when all layer closed,disable clk */
1142         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1143                 rk312x_lcdc_disable_irq(lcdc_dev);
1144                 rk312x_lcdc_reg_update(dev_drv);
1145 #if defined(CONFIG_ROCKCHIP_IOMMU)
1146                 if (dev_drv->iommu_enabled) {
1147                         if (dev_drv->mmu_dev)
1148                                 rockchip_iovmm_deactivate(dev_drv->dev);
1149                 }
1150 #endif
1151                 rk312x_lcdc_clk_disable(lcdc_dev);
1152                 rockchip_clear_system_status(SYS_STATUS_LCDC0);
1153         }
1154
1155         return 0;
1156 }
1157
1158 static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
1159 {
1160         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1161                                                     struct lcdc_device, driver);
1162         struct rk_screen *screen = dev_drv->cur_screen;
1163         struct rk_lcdc_win *win = NULL;
1164         char fmt[9] = "NULL";
1165
1166         if (!screen) {
1167                 dev_err(dev_drv->dev, "screen is null!\n");
1168                 return -ENOENT;
1169         }
1170
1171         if (win_id == 0) {
1172                 win = dev_drv->win[0];
1173         } else if (win_id == 1) {
1174                 win = dev_drv->win[1];
1175         } else {
1176                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
1177                 return -EINVAL;
1178         }
1179
1180         spin_lock(&lcdc_dev->reg_lock);
1181         win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin +
1182                                 screen->mode.hsync_len;
1183         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1184                 win->area[0].ysize /= 2;
1185                 win->area[0].dsp_sty = win->area[0].ypos / 2 +
1186                                         screen->mode.upper_margin +
1187                                         screen->mode.vsync_len;
1188         } else {
1189                 win->area[0].dsp_sty = win->area[0].ypos +
1190                                         screen->mode.upper_margin +
1191                                         screen->mode.vsync_len;
1192         }
1193         win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize);
1194         win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize);
1195
1196         switch (win->format) {
1197         case ARGB888:
1198                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1199                 win->swap_rb = 0;
1200                 break;
1201         case XBGR888:
1202                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1203                 win->swap_rb = 1;
1204                 break;
1205         case ABGR888:
1206                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1207                 win->swap_rb = 1;
1208                 break;
1209         case RGB888:
1210                 win->fmt_cfg = VOP_FORMAT_RGB888;
1211                 win->swap_rb = 0;
1212                 break;
1213         case RGB565:
1214                 win->fmt_cfg = VOP_FORMAT_RGB565;
1215                 win->swap_rb = 0;
1216                 break;
1217         case YUV444:
1218                 if (win_id == 0) {
1219                         win->fmt_cfg = VOP_FORMAT_YCBCR444;
1220                         win->scale_cbcr_x =
1221                             CalScale(win->area[0].xact, win->area[0].xsize);
1222                         win->scale_cbcr_y =
1223                             CalScale(win->area[0].yact, win->area[0].ysize);
1224                         win->swap_rb = 0;
1225                 } else {
1226                         dev_err(lcdc_dev->driver.dev,
1227                                 "%s:un supported format!\n", __func__);
1228                 }
1229                 break;
1230         case YUV422:
1231                 if (win_id == 0) {
1232                         win->fmt_cfg = VOP_FORMAT_YCBCR422;
1233                         win->scale_cbcr_x = CalScale((win->area[0].xact / 2),
1234                                                      win->area[0].xsize);
1235                         win->scale_cbcr_y =
1236                             CalScale(win->area[0].yact, win->area[0].ysize);
1237                         win->swap_rb = 0;
1238                 } else {
1239                         dev_err(lcdc_dev->driver.dev,
1240                                 "%s:un supported format!\n", __func__);
1241                 }
1242                 break;
1243         case YUV420:
1244                 if (win_id == 0) {
1245                         win->fmt_cfg = VOP_FORMAT_YCBCR420;
1246                         win->scale_cbcr_x =
1247                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1248                         win->scale_cbcr_y =
1249                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1250                         win->swap_rb = 0;
1251                 } else {
1252                         dev_err(lcdc_dev->driver.dev,
1253                                 "%s:un supported format!\n", __func__);
1254                 }
1255                 break;
1256         default:
1257                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1258                         __func__);
1259                 break;
1260         }
1261         spin_unlock(&lcdc_dev->reg_lock);
1262
1263         DBG(1,
1264             "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
1265             ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__,
1266             get_format_string(win->format, fmt), win->area[0].xact,
1267             win->area[0].yact, win->area[0].xsize, win->area[0].ysize,
1268             win->area[0].xvir, win->area[0].yvir, win->area[0].xpos,
1269             win->area[0].ypos);
1270         return 0;
1271 }
1272
1273 static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1274 {
1275         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1276                                                     struct lcdc_device, driver);
1277         struct rk_lcdc_win *win = NULL;
1278         struct rk_screen *screen = dev_drv->cur_screen;
1279
1280         if (!screen) {
1281                 dev_err(dev_drv->dev, "screen is null!\n");
1282                 return -ENOENT;
1283         }
1284
1285         if (win_id == 0) {
1286                 win = dev_drv->win[0];
1287         } else if (win_id == 1) {
1288                 win = dev_drv->win[1];
1289         } else {
1290                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1291                 return -EINVAL;
1292         }
1293
1294         spin_lock(&lcdc_dev->reg_lock);
1295         if (likely(lcdc_dev->clk_on)) {
1296                 win->area[0].y_addr =
1297                     win->area[0].smem_start + win->area[0].y_offset;
1298                 win->area[0].uv_addr =
1299                     win->area[0].cbr_start + win->area[0].c_offset;
1300                 if (win->area[0].y_addr)
1301                         lcdc_layer_update_regs(lcdc_dev, win);
1302                 /* lcdc_cfg_done(lcdc_dev); */
1303         }
1304         spin_unlock(&lcdc_dev->reg_lock);
1305
1306         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1307             lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr,
1308             win->area[0].y_offset);
1309         /* this is the first frame of the system,enable frame start interrupt */
1310         if ((dev_drv->first_frame)) {
1311                 dev_drv->first_frame = 0;
1312                 rk312x_lcdc_enable_irq(dev_drv);
1313
1314         }
1315
1316         return 0;
1317 }
1318
1319 static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
1320                              unsigned long arg, int win_id)
1321 {
1322         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1323                                                     struct lcdc_device, driver);
1324         u32 panel_size[2];
1325         void __user *argp = (void __user *)arg;
1326         struct color_key_cfg clr_key_cfg;
1327
1328         switch (cmd) {
1329         case RK_FBIOGET_PANEL_SIZE:
1330                 panel_size[0] = lcdc_dev->screen->mode.xres;
1331                 panel_size[1] = lcdc_dev->screen->mode.yres;
1332                 if (copy_to_user(argp, panel_size, 8))
1333                         return -EFAULT;
1334                 break;
1335         case RK_FBIOPUT_COLOR_KEY_CFG:
1336                 if (copy_from_user(&clr_key_cfg, argp,
1337                                    sizeof(struct color_key_cfg)))
1338                         return -EFAULT;
1339                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
1340                             clr_key_cfg.win0_color_key_cfg);
1341                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
1342                             clr_key_cfg.win1_color_key_cfg);
1343                 break;
1344
1345         default:
1346                 break;
1347         }
1348         return 0;
1349 }
1350
1351 static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
1352                                   const char *id)
1353 {
1354         int win_id = 0;
1355         mutex_lock(&dev_drv->fb_win_id_mutex);
1356         if (!strcmp(id, "fb0"))
1357                 win_id = dev_drv->fb0_win_id;
1358         else if (!strcmp(id, "fb1"))
1359                 win_id = dev_drv->fb1_win_id;
1360         else if (!strcmp(id, "fb2"))
1361                 win_id = dev_drv->fb2_win_id;
1362         mutex_unlock(&dev_drv->fb_win_id_mutex);
1363
1364         return win_id;
1365 }
1366
1367 static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
1368 {
1369         return 0;
1370 }
1371
1372 static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1373                                bool set)
1374 {
1375         struct lcdc_device *lcdc_dev =
1376             container_of(dev_drv, struct lcdc_device, driver);
1377         int ovl;
1378         spin_lock(&lcdc_dev->reg_lock);
1379         if (lcdc_dev->clk_on) {
1380                 if (set) {
1381                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1382                                      v_WIN0_TOP(swap));
1383                         ovl = swap;
1384                 } else {
1385                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1386                 }
1387         } else {
1388                 ovl = -EPERM;
1389         }
1390         spin_unlock(&lcdc_dev->reg_lock);
1391
1392         return ovl;
1393 }
1394
1395 static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1396 {
1397
1398         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1399                                                     struct lcdc_device, driver);
1400         if (dev_drv->suspend_flag)
1401                 return 0;
1402         dev_drv->suspend_flag = 1;
1403         flush_kthread_worker(&dev_drv->update_regs_worker);
1404
1405         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1406                 dev_drv->trsm_ops->disable();
1407         spin_lock(&lcdc_dev->reg_lock);
1408         if (likely(lcdc_dev->clk_on)) {
1409                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1));
1410                 lcdc_msk_reg(lcdc_dev, INT_STATUS,
1411                              m_FS_INT_CLEAR | m_LF_INT_CLEAR,
1412                              v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1));
1413                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1414                              v_DSP_OUT_ZERO(1));
1415                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1416                              v_LCDC_STANDBY(1));
1417                 lcdc_cfg_done(lcdc_dev);
1418
1419                 if (dev_drv->iommu_enabled) {
1420                         if (dev_drv->mmu_dev)
1421                                 rockchip_iovmm_deactivate(dev_drv->dev);
1422                 }
1423
1424                 spin_unlock(&lcdc_dev->reg_lock);
1425         } else {
1426                 spin_unlock(&lcdc_dev->reg_lock);
1427                 return 0;
1428         }
1429         rk312x_lcdc_clk_disable(lcdc_dev);
1430         rk_disp_pwr_disable(dev_drv);
1431         return 0;
1432 }
1433
1434 static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1435 {
1436         struct lcdc_device *lcdc_dev =
1437             container_of(dev_drv, struct lcdc_device, driver);
1438
1439         if (!dev_drv->suspend_flag)
1440                 return 0;
1441         rk_disp_pwr_enable(dev_drv);
1442         dev_drv->suspend_flag = 0;
1443
1444         if (lcdc_dev->atv_layer_cnt) {
1445                 rk312x_lcdc_clk_enable(lcdc_dev);
1446                 rk312x_lcdc_reg_restore(lcdc_dev);
1447                 /* set screen lut */
1448                 if (dev_drv->cur_screen->dsp_lut)
1449                         rk312x_lcdc_set_lut(dev_drv);
1450
1451                 spin_lock(&lcdc_dev->reg_lock);
1452
1453                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1454                              v_DSP_OUT_ZERO(0));
1455                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1456                              v_LCDC_STANDBY(0));
1457                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0));
1458                 lcdc_cfg_done(lcdc_dev);
1459
1460                 if (dev_drv->iommu_enabled) {
1461                         if (dev_drv->mmu_dev)
1462                                 rockchip_iovmm_activate(dev_drv->dev);
1463                 }
1464
1465                 spin_unlock(&lcdc_dev->reg_lock);
1466         }
1467
1468         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1469                 dev_drv->trsm_ops->enable();
1470         return 0;
1471 }
1472
1473 static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1474                              int win_id, int blank_mode)
1475 {
1476         switch (blank_mode) {
1477         case FB_BLANK_UNBLANK:
1478                 rk312x_lcdc_early_resume(dev_drv);
1479                 break;
1480         case FB_BLANK_NORMAL:
1481                 rk312x_lcdc_early_suspend(dev_drv);
1482                 break;
1483         default:
1484                 rk312x_lcdc_early_suspend(dev_drv);
1485                 break;
1486         }
1487
1488         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1489
1490         return 0;
1491 }
1492
1493 static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1494 {
1495         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1496                                                     struct lcdc_device, driver);
1497         spin_lock(&lcdc_dev->reg_lock);
1498         if (lcdc_dev->clk_on)
1499                 lcdc_cfg_done(lcdc_dev);
1500         spin_unlock(&lcdc_dev->reg_lock);
1501         return 0;
1502 }
1503
1504 /*
1505         a:[-30~0]:
1506             sin_hue = sin(a)*256 +0x100;
1507             cos_hue = cos(a)*256;
1508         a:[0~30]
1509             sin_hue = sin(a)*256;
1510             cos_hue = cos(a)*256;
1511 */
1512 static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1513                                     bcsh_hue_mode mode)
1514 {
1515
1516         struct lcdc_device *lcdc_dev =
1517             container_of(dev_drv, struct lcdc_device, driver);
1518         u32 val;
1519
1520         spin_lock(&lcdc_dev->reg_lock);
1521         if (lcdc_dev->clk_on) {
1522                 val = lcdc_readl(lcdc_dev, BCSH_H);
1523                 switch (mode) {
1524                 case H_SIN:
1525                         val &= m_BCSH_SIN_HUE;
1526                         break;
1527                 case H_COS:
1528                         val &= m_BCSH_COS_HUE;
1529                         val >>= 16;
1530                         break;
1531                 default:
1532                         break;
1533                 }
1534         }
1535         spin_unlock(&lcdc_dev->reg_lock);
1536
1537         return val;
1538 }
1539
1540 static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue,
1541                                     int cos_hue)
1542 {
1543
1544         struct lcdc_device *lcdc_dev =
1545             container_of(dev_drv, struct lcdc_device, driver);
1546         u32 mask, val;
1547
1548         spin_lock(&lcdc_dev->reg_lock);
1549         if (lcdc_dev->clk_on) {
1550                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1551                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1552                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1553                 lcdc_cfg_done(lcdc_dev);
1554         }
1555         spin_unlock(&lcdc_dev->reg_lock);
1556
1557         return 0;
1558 }
1559
1560 static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1561                                     bcsh_bcs_mode mode, int value)
1562 {
1563         struct lcdc_device *lcdc_dev =
1564             container_of(dev_drv, struct lcdc_device, driver);
1565         u32 mask, val;
1566
1567         spin_lock(&lcdc_dev->reg_lock);
1568         if (lcdc_dev->clk_on) {
1569                 switch (mode) {
1570                 case BRIGHTNESS:
1571                         /* from 0 to 255,typical is 128 */
1572                         if (value < 0x80)
1573                                 value += 0x80;
1574                         else if (value >= 0x80)
1575                                 value = value - 0x80;
1576                         mask = m_BCSH_BRIGHTNESS;
1577                         val = v_BCSH_BRIGHTNESS(value);
1578                         break;
1579                 case CONTRAST:
1580                         /* from 0 to 510,typical is 256 */
1581                         mask = m_BCSH_CONTRAST;
1582                         val = v_BCSH_CONTRAST(value);
1583                         break;
1584                 case SAT_CON:
1585                         /* from 0 to 1015,typical is 256 */
1586                         mask = m_BCSH_SAT_CON;
1587                         val = v_BCSH_SAT_CON(value);
1588                         break;
1589                 default:
1590                         break;
1591                 }
1592                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1593                 lcdc_cfg_done(lcdc_dev);
1594         }
1595         spin_unlock(&lcdc_dev->reg_lock);
1596         return val;
1597 }
1598
1599 static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1600                                     bcsh_bcs_mode mode)
1601 {
1602         struct lcdc_device *lcdc_dev =
1603             container_of(dev_drv, struct lcdc_device, driver);
1604         u32 val;
1605
1606         spin_lock(&lcdc_dev->reg_lock);
1607         if (lcdc_dev->clk_on) {
1608                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1609                 switch (mode) {
1610                 case BRIGHTNESS:
1611                         val &= m_BCSH_BRIGHTNESS;
1612                         if (val > 0x80)
1613                                 val -= 0x80;
1614                         else
1615                                 val += 0x80;
1616                         break;
1617                 case CONTRAST:
1618                         val &= m_BCSH_CONTRAST;
1619                         val >>= 8;
1620                         break;
1621                 case SAT_CON:
1622                         val &= m_BCSH_SAT_CON;
1623                         val >>= 20;
1624                         break;
1625                 default:
1626                         break;
1627                 }
1628         }
1629         spin_unlock(&lcdc_dev->reg_lock);
1630         return val;
1631 }
1632
1633 static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1634 {
1635         struct lcdc_device *lcdc_dev =
1636             container_of(dev_drv, struct lcdc_device, driver);
1637         u32 mask, val;
1638
1639         spin_lock(&lcdc_dev->reg_lock);
1640         if (lcdc_dev->clk_on) {
1641                 if (open) {
1642                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1643                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1644                         lcdc_writel(lcdc_dev, BCSH_BCS,
1645                                     v_BCSH_BRIGHTNESS(0x00) |
1646                                     v_BCSH_CONTRAST(0x80) |
1647                                     v_BCSH_SAT_CON(0x80));
1648                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1649                 } else {
1650                         mask = m_BCSH_EN;
1651                         val = v_BCSH_EN(0);
1652                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1653                 }
1654                 lcdc_cfg_done(lcdc_dev);
1655         }
1656
1657         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1658                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1659                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_Y2R_EN,
1660                                         v_BCSH_Y2R_EN(0));
1661                 else    /* YUV2RGB */
1662                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1663                                         m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE,
1664                                         v_BCSH_Y2R_EN(1) | v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG));
1665         } else {        /* overlay_mode=VOP_RGB_DOMAIN */
1666                 if (dev_drv->output_color == COLOR_RGB) /* bypass */
1667                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_EN,
1668                                         v_BCSH_R2Y_EN(0));
1669                 else    /* RGB2YUV */
1670                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1671                                         m_BCSH_R2Y_EN | m_BCSH_R2Y_CSC_MODE,
1672                                         v_BCSH_R2Y_EN(1) | v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
1673         }
1674
1675         spin_unlock(&lcdc_dev->reg_lock);
1676         return 0;
1677 }
1678
1679 static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
1680 {
1681         mutex_lock(&dev_drv->fb_win_id_mutex);
1682         if (order == FB_DEFAULT_ORDER)
1683                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;    /*  FB0_WIN1_FB1_WIN0_FB2_WIN2; for box */
1684         dev_drv->fb2_win_id = order / 100;
1685         dev_drv->fb1_win_id = (order / 10) % 10;
1686         dev_drv->fb0_win_id = order % 10;
1687         mutex_unlock(&dev_drv->fb_win_id_mutex);
1688
1689         return 0;
1690 }
1691
1692 static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1693                                bool set)
1694 {
1695         struct lcdc_device *lcdc_dev =
1696             container_of(dev_drv, struct lcdc_device, driver);
1697         struct rk_screen *screen = dev_drv->cur_screen;
1698         u64 ft = 0;
1699         u32 dotclk;
1700         int ret;
1701         u32 pixclock;
1702         u32 x_total, y_total;
1703         if (set) {
1704                 ft = div_u64(1000000000000llu, fps);
1705                 x_total =
1706                     screen->mode.upper_margin + screen->mode.lower_margin +
1707                     screen->mode.yres + screen->mode.vsync_len;
1708                 y_total =
1709                     screen->mode.left_margin + screen->mode.right_margin +
1710                     screen->mode.xres + screen->mode.hsync_len;
1711                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1712                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1713                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1714         }
1715
1716         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1717         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
1718         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1719         screen->ft = 1000 / fps;        /*one frame time in ms */
1720
1721         if (set)
1722                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1723                          clk_get_rate(lcdc_dev->dclk), fps);
1724
1725         return fps;
1726 }
1727
1728 static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1729 {
1730         struct lcdc_device *lcdc_dev =
1731             container_of(dev_drv, struct lcdc_device, driver);
1732         u32 int_reg;
1733         int ret;
1734
1735         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
1736                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1737                 if (int_reg & m_LF_INT_STA) {
1738                         dev_drv->frame_time.last_framedone_t =
1739                                         dev_drv->frame_time.framedone_t;
1740                         dev_drv->frame_time.framedone_t = cpu_clock(0);
1741                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1742                                      v_LF_INT_CLEAR(1));
1743                         ret = RK_LF_STATUS_FC;
1744                 } else
1745                         ret = RK_LF_STATUS_FR;
1746         } else {
1747                 ret = RK_LF_STATUS_NC;
1748         }
1749
1750         return ret;
1751 }
1752
1753 static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1754                                     unsigned int *dsp_addr)
1755 {
1756         struct lcdc_device *lcdc_dev =
1757             container_of(dev_drv, struct lcdc_device, driver);
1758
1759         if (lcdc_dev->clk_on) {
1760                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1761                 if (lcdc_dev->soc_type == VOP_RK3036)
1762                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1763                 else if (lcdc_dev->soc_type == VOP_RK312X)
1764                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1765         }
1766         return 0;
1767 }
1768
1769 static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1770                                          char *buf, int win_id)
1771 {
1772         struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device,
1773                                                     driver);
1774         char format_w0[9] = "NULL";
1775         char format_w1[9] = "NULL";
1776         char status_w0[9] = "NULL";
1777         char status_w1[9] = "NULL";
1778         u32 fmt_id, act_info, dsp_info, dsp_st, factor;
1779         u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0;
1780         u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1;
1781         u16 x_factor, y_factor, x_scale, y_scale;
1782         u16 ovl;
1783         u32 win1_dsp_yaddr = 0;
1784
1785         spin_lock(&lcdc_dev->reg_lock);
1786         if (lcdc_dev->clk_on) {
1787                 /* data format */
1788                 fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL);
1789                 get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0);
1790                 get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1);
1791
1792                 /* win status */
1793                 if (fmt_id & m_WIN0_EN)
1794                         strcpy(status_w0, "enabled");
1795                 else
1796                         strcpy(status_w0, "disabled");
1797
1798                 if ((fmt_id & m_WIN1_EN) >> 1)
1799                         strcpy(status_w1, "enabled");
1800                 else
1801                         strcpy(status_w1, "disabled");
1802
1803                 /* ovl */
1804                 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1805
1806                 /* xvir */
1807                 xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR;
1808                 xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR;
1809
1810                 /* xact/yact */
1811                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1812                 x_act_w0 = (act_info & m_ACT_WIDTH) + 1;
1813                 y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1814
1815                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
1816                 x_act_w1 = (act_info & m_ACT_WIDTH) + 1;
1817                 y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1818
1819                 /* xsize/ysize */
1820                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
1821                 x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1;
1822                 y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1823
1824                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
1825                 x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1;
1826                 y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1827
1828                 /* xpos/ypos */
1829                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
1830                 x_st_w0 = dsp_st & m_DSP_STX;
1831                 y_st_w0 = (dsp_st & m_DSP_STY) >> 16;
1832
1833                 if (lcdc_dev->soc_type == VOP_RK3036)
1834                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
1835                 else if (lcdc_dev->soc_type == VOP_RK312X)
1836                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X);
1837
1838                 x_st_w1 = dsp_st & m_DSP_STX;
1839                 y_st_w1 = (dsp_st & m_DSP_STY) >> 16;
1840
1841                 /* scale factor */
1842                 factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
1843                 x_factor = factor & m_X_SCL_FACTOR;
1844                 y_factor = (factor & m_Y_SCL_FACTOR) >> 16;
1845                 x_scale = 4096 * 100 / x_factor;
1846                 y_scale = 4096 * 100 / y_factor;
1847
1848                 /* dsp addr */
1849                 if (lcdc_dev->soc_type == VOP_RK3036)
1850                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST);
1851                 else if (lcdc_dev->soc_type == VOP_RK312X)
1852                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1853         } else {
1854                 spin_unlock(&lcdc_dev->reg_lock);
1855                 return -EPERM;
1856         }
1857         spin_unlock(&lcdc_dev->reg_lock);
1858         return snprintf(buf, PAGE_SIZE,
1859                         "win0:%s\n"
1860                         "xvir:%d\n"
1861                         "xact:%d\n"
1862                         "yact:%d\n"
1863                         "xdsp:%d\n"
1864                         "ydsp:%d\n"
1865                         "x_st:%d\n"
1866                         "y_st:%d\n"
1867                         "x_scale:%d.%d\n"
1868                         "y_scale:%d.%d\n"
1869                         "format:%s\n"
1870                         "YRGB buffer addr:0x%08x\n"
1871                         "CBR buffer addr:0x%08x\n\n"
1872                         "win1:%s\n"
1873                         "xvir:%d\n"
1874                         "xact:%d\n"
1875                         "yact:%d\n"
1876                         "xdsp:%d\n"
1877                         "ydsp:%d\n"
1878                         "x_st:%d\n"
1879                         "y_st:%d\n"
1880                         "format:%s\n"
1881                         "YRGB buffer addr:0x%08x\n"
1882                         "overlay:%s\n",
1883                         status_w0,
1884                         xvir_w0,
1885                         x_act_w0,
1886                         y_act_w0,
1887                         x_dsp_w0,
1888                         y_dsp_w0,
1889                         x_st_w0,
1890                         y_st_w0,
1891                         x_scale / 100,
1892                         x_scale % 100,
1893                         y_scale / 100,
1894                         y_scale % 100,
1895                         format_w0,
1896                         lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
1897                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
1898                         status_w1,
1899                         xvir_w1,
1900                         x_act_w1,
1901                         y_act_w1,
1902                         x_dsp_w1,
1903                         y_dsp_w1,
1904                         x_st_w1,
1905                         y_st_w1,
1906                         format_w1,
1907                         win1_dsp_yaddr,
1908                         ovl ? "win0 on the top of win1\n" :
1909                         "win1 on the top of win0\n");
1910 }
1911
1912 static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1913 {
1914         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1915                                                     struct lcdc_device,
1916                                                     driver);
1917         int *cbase = (int *)lcdc_dev->regs;
1918         int *regsbak = (int *)lcdc_dev->regsbak;
1919         int i, j;
1920
1921         printk("back up reg:\n");
1922         for (i = 0; i <= (0xDC >> 4); i++) {
1923                 for (j = 0; j < 4; j++)
1924                         printk("%08x  ", *(regsbak + i * 4 + j));
1925                 printk("\n");
1926         }
1927
1928         printk("lcdc reg:\n");
1929         for (i = 0; i <= (0xDC >> 4); i++) {
1930                 for (j = 0; j < 4; j++)
1931                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
1932                 printk("\n");
1933         }
1934         return 0;
1935 }
1936
1937 static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
1938 {
1939         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1940                                                     struct lcdc_device, driver);
1941         if (lcdc_dev->soc_type == VOP_RK312X) {
1942                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
1943                              v_DIRECT_PATH_EN(open));
1944                 lcdc_cfg_done(lcdc_dev);
1945         }
1946         return 0;
1947 }
1948
1949 static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
1950 {
1951         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1952                                                     struct lcdc_device, driver);
1953
1954         if (lcdc_dev->soc_type == VOP_RK312X) {
1955                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER,
1956                              v_DIRECT_PATH_LAYER(win_id));
1957                 lcdc_cfg_done(lcdc_dev);
1958         }
1959         return 0;
1960
1961 }
1962
1963 static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
1964 {
1965         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1966                                                     struct lcdc_device, driver);
1967         int ovl = 0;
1968
1969         if (lcdc_dev->soc_type == VOP_RK312X)
1970                 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
1971
1972         return ovl;
1973 }
1974
1975 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1976         .open = rk312x_lcdc_open,
1977         .load_screen = rk312x_load_screen,
1978         .set_par = rk312x_lcdc_set_par,
1979         .pan_display = rk312x_lcdc_pan_display,
1980         .blank = rk312x_lcdc_blank,
1981         .ioctl = rk312x_lcdc_ioctl,
1982         .get_win_state = rk312x_lcdc_get_win_state,
1983         .ovl_mgr = rk312x_lcdc_ovl_mgr,
1984         .get_disp_info = rk312x_lcdc_get_disp_info,
1985         .fps_mgr = rk312x_lcdc_fps_mgr,
1986         .fb_get_win_id = rk312x_lcdc_get_win_id,
1987         .fb_win_remap = rk312x_fb_win_remap,
1988         .poll_vblank = rk312x_lcdc_poll_vblank,
1989         .get_dsp_addr = rk312x_lcdc_get_dsp_addr,
1990         .cfg_done = rk312x_lcdc_cfg_done,
1991         .dump_reg = rk312x_lcdc_reg_dump,
1992         .dpi_open = rk312x_lcdc_dpi_open,
1993         .dpi_win_sel = rk312x_lcdc_dpi_win_sel,
1994         .dpi_status = rk312x_lcdc_dpi_status,
1995         .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue,
1996         .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs,
1997         .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue,
1998         .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs,
1999         .open_bcsh = rk312x_lcdc_open_bcsh,
2000         .set_screen_scaler = rk312x_lcdc_set_scaler,
2001 };
2002 #if 0
2003 static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = {
2004         .soc_type = VOP_RK3036,
2005 };
2006 #endif
2007 static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = {
2008         .soc_type = VOP_RK312X,
2009 };
2010
2011 #if defined(CONFIG_OF)
2012 static const struct of_device_id rk312x_lcdc_dt_ids[] = {
2013 #if 0
2014         {
2015                 .compatible = "rockchip,rk3036-lcdc",
2016                 .data = (void *)&rk3036_lcdc_drvdata,
2017         },
2018 #endif
2019         {
2020                 .compatible = "rockchip,rk312x-lcdc",
2021                 .data = (void *)&rk312x_lcdc_drvdata,
2022         },
2023 };
2024 #endif
2025
2026 static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
2027 {
2028         struct device_node *np = lcdc_dev->dev->of_node;
2029         const struct of_device_id *match;
2030         const struct rk_lcdc_drvdata *lcdc_drvdata;
2031
2032 #if defined(CONFIG_ROCKCHIP_IOMMU)
2033         int val;
2034         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
2035                 lcdc_dev->driver.iommu_enabled = 0;
2036         else
2037                 lcdc_dev->driver.iommu_enabled = val;
2038 #else
2039         lcdc_dev->driver.iommu_enabled = 0;
2040 #endif
2041
2042         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
2043                 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
2044         else
2045                 lcdc_dev->driver.fb_win_map = val;
2046
2047         match = of_match_node(rk312x_lcdc_dt_ids, np);
2048         if (match) {
2049                 lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data;
2050                 lcdc_dev->soc_type = lcdc_drvdata->soc_type;
2051         } else {
2052                 return PTR_ERR(match);
2053         }
2054
2055         return 0;
2056 }
2057
2058 static int rk312x_lcdc_probe(struct platform_device *pdev)
2059 {
2060         struct lcdc_device *lcdc_dev = NULL;
2061         struct rk_lcdc_driver *dev_drv;
2062         struct device *dev = &pdev->dev;
2063         struct resource *res;
2064         int ret;
2065
2066         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
2067         if (!lcdc_dev) {
2068                 dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n");
2069                 return -ENOMEM;
2070         }
2071         platform_set_drvdata(pdev, lcdc_dev);
2072         lcdc_dev->dev = dev;
2073         if (rk312x_lcdc_parse_dt(lcdc_dev)) {
2074                 dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n");
2075                 goto err_parse_dt;
2076         }
2077
2078         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2079         lcdc_dev->reg_phy_base = res->start;
2080         lcdc_dev->len = resource_size(res);
2081         lcdc_dev->regs = devm_ioremap_resource(dev, res);
2082         if (IS_ERR(lcdc_dev->regs)) {
2083                 ret = PTR_ERR(lcdc_dev->regs);
2084                 goto err_remap_reg;
2085         }
2086
2087         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
2088         if (IS_ERR(lcdc_dev->regsbak)) {
2089                 dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n");
2090                 ret = PTR_ERR(lcdc_dev->regsbak);
2091                 goto err_remap_reg;
2092         }
2093
2094         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
2095         dev_drv = &lcdc_dev->driver;
2096         dev_drv->dev = dev;
2097         dev_drv->prop = PRMRY;
2098         dev_drv->id = lcdc_dev->id;
2099         dev_drv->ops = &lcdc_drv_ops;
2100         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
2101         spin_lock_init(&lcdc_dev->reg_lock);
2102
2103         lcdc_dev->irq = platform_get_irq(pdev, 0);
2104         if (lcdc_dev->irq < 0) {
2105                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
2106                         lcdc_dev->id);
2107                 ret = -ENXIO;
2108                 goto err_request_irq;
2109         }
2110
2111         ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr,
2112                                IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
2113         if (ret) {
2114                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
2115                         lcdc_dev->irq, ret);
2116                 goto err_request_irq;
2117         }
2118
2119         if (dev_drv->iommu_enabled)
2120                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
2121
2122         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
2123         if (ret < 0) {
2124                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
2125                 goto err_register_fb;
2126         }
2127         lcdc_dev->screen = dev_drv->screen0;
2128
2129         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
2130                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
2131         return 0;
2132
2133 err_register_fb:
2134 err_request_irq:
2135         devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak);
2136 err_remap_reg:
2137 err_parse_dt:
2138         devm_kfree(&pdev->dev, lcdc_dev);
2139         return ret;
2140 }
2141
2142 #if defined(CONFIG_PM)
2143 static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
2144 {
2145         return 0;
2146 }
2147
2148 static int rk312x_lcdc_resume(struct platform_device *pdev)
2149 {
2150         return 0;
2151 }
2152 #else
2153 #define rk312x_lcdc_suspend NULL
2154 #define rk312x_lcdc_resume  NULL
2155 #endif
2156
2157 static int rk312x_lcdc_remove(struct platform_device *pdev)
2158 {
2159         return 0;
2160 }
2161
2162 static void rk312x_lcdc_shutdown(struct platform_device *pdev)
2163 {
2164         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
2165
2166         rk312x_lcdc_deinit(lcdc_dev);
2167         rk312x_lcdc_clk_disable(lcdc_dev);
2168         rk_disp_pwr_disable(&lcdc_dev->driver);
2169 }
2170
2171 static struct platform_driver rk312x_lcdc_driver = {
2172         .probe = rk312x_lcdc_probe,
2173         .remove = rk312x_lcdc_remove,
2174         .driver = {
2175                    .name = "rk312x-lcdc",
2176                    .owner = THIS_MODULE,
2177                    .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids),
2178                    },
2179         .suspend = rk312x_lcdc_suspend,
2180         .resume = rk312x_lcdc_resume,
2181         .shutdown = rk312x_lcdc_shutdown,
2182 };
2183
2184 static int __init rk312x_lcdc_module_init(void)
2185 {
2186         return platform_driver_register(&rk312x_lcdc_driver);
2187 }
2188
2189 static void __exit rk312x_lcdc_module_exit(void)
2190 {
2191         platform_driver_unregister(&rk312x_lcdc_driver);
2192 }
2193
2194 fs_initcall(rk312x_lcdc_module_init);
2195 module_exit(rk312x_lcdc_module_exit);