drivers/video/rockchip/lcdc/rk312x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk312x_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:      zhuangwenlong<zwl@rock-chips.com>
   6  *              zhengyang<zhengyang@rock-chips.com>
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/slab.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37 #if defined(CONFIG_ION_ROCKCHIP)
  38 #include <linux/rockchip/iovmm.h>
  39 #include <linux/rockchip/sysmmu.h>
  40 #endif
  41 #include "rk312x_lcdc.h"
  42
  43 static int dbg_thresd;
  44 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  45
  46 #define DBG(level, x...) do {                   \
  47         if (unlikely(dbg_thresd >= level))      \
  48                 printk(KERN_INFO x); } while (0)
  49
  50 static struct rk_lcdc_win lcdc_win[] = {
  51         [0] = {
  52                .name = "win0",
  53                .id = 0,
  54                .support_3d = false,
  55                },
  56         [1] = {
  57                .name = "win1",
  58                .id = 1,
  59                .support_3d = false,
  60                },
  61         [2] = {
  62                .name = "hwc",
  63                .id = 2,
  64                .support_3d = false,
  65                },
  66 };
  67
  68 static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id)
  69 {
  70         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
  71         ktime_t timestamp = ktime_get();
  72         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  73
  74         if (int_reg & m_FS_INT_STA) {
  75                 timestamp = ktime_get();
  76                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  77                              v_FS_INT_CLEAR(1));
  78                 //if (lcdc_dev->driver.wait_fs) {
  79                 if (0) {
  80                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  81                         complete(&(lcdc_dev->driver.frame_done));
  82                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  83                 }
  84                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  85                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  86
  87         } else if (int_reg & m_LF_INT_STA) {
  88                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  89                              v_LF_INT_CLEAR(1));
  90         }
  91         return IRQ_HANDLED;
  92 }
  93
  94 static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
  95 {
  96 #ifdef CONFIG_RK_FPGA
  97         lcdc_dev->clk_on = 1;
  98         return 0;
  99 #endif
 100         if (!lcdc_dev->clk_on) {
 101                 clk_prepare_enable(lcdc_dev->hclk);
 102                 clk_prepare_enable(lcdc_dev->dclk);
 103                 clk_prepare_enable(lcdc_dev->aclk);
 104 //              clk_prepare_enable(lcdc_dev->pd);
 105                 spin_lock(&lcdc_dev->reg_lock);
 106                 lcdc_dev->clk_on = 1;
 107                 spin_unlock(&lcdc_dev->reg_lock);
 108         }
 109
 110         return 0;
 111 }
 112
 113 static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 114 {
 115 #ifdef CONFIG_RK_FPGA
 116         lcdc_dev->clk_on = 0;
 117         return 0;
 118 #endif
 119         if (lcdc_dev->clk_on) {
 120                 spin_lock(&lcdc_dev->reg_lock);
 121                 lcdc_dev->clk_on = 0;
 122                 spin_unlock(&lcdc_dev->reg_lock);
 123                 mdelay(25);
 124                 clk_disable_unprepare(lcdc_dev->dclk);
 125                 clk_disable_unprepare(lcdc_dev->hclk);
 126                 clk_disable_unprepare(lcdc_dev->aclk);
 127 //              clk_disable_unprepare(lcdc_dev->pd);
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 134 {
 135         u32 mask, val;
 136         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 137                                                     struct lcdc_device, driver);
 138         struct rk_screen *screen = dev_drv->cur_screen;
 139
 140         spin_lock(&lcdc_dev->reg_lock);
 141         if (likely(lcdc_dev->clk_on)) {
 142                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 143                         m_LF_INT_CLEAR | m_LF_INT_EN | m_LF_INT_NUM |
 144                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 145                 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) |
 146                         v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) |
 147                         v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0) |
 148                         v_LF_INT_NUM(screen->mode.vsync_len +
 149                                      screen->mode.upper_margin +
 150                                      screen->mode.yres);
 151                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 152                 spin_unlock(&lcdc_dev->reg_lock);
 153         } else {
 154                 spin_unlock(&lcdc_dev->reg_lock);
 155         }
 156         return 0;
 157 }
 158
 159 static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 160 {
 161         u32 mask, val;
 162
 163         spin_lock(&lcdc_dev->reg_lock);
 164         if (likely(lcdc_dev->clk_on)) {
 165                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 166                         m_LF_INT_CLEAR | m_LF_INT_EN |
 167                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 168                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 169                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 170                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 171                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 172                 spin_unlock(&lcdc_dev->reg_lock);
 173         } else {
 174                 spin_unlock(&lcdc_dev->reg_lock);
 175         }
 176         mdelay(1);
 177         return 0;
 178 }
 179
 180 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 181 {
 182         int reg = 0;
 183         u32 value = 0;
 184
 185         spin_lock(&lcdc_dev->reg_lock);
 186         for (reg = 0; reg < 0xdc; reg += 4) {
 187                 value = lcdc_readl(lcdc_dev, reg);
 188         }
 189         spin_unlock(&lcdc_dev->reg_lock);
 190 }
 191
 192 static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 193 {
 194         int win0_top = 0;
 195         u32 mask, val;
 196         enum data_format win0_format = lcdc_dev->driver.win[0]->format;
 197         enum data_format win1_format = lcdc_dev->driver.win[1]->format;
 198
 199         int win0_alpha_en = ((win0_format == ARGB888)
 200                              || (win0_format == ABGR888)) ? 1 : 0;
 201         int win1_alpha_en = ((win1_format == ARGB888)
 202                              || (win1_format == ABGR888)) ? 1 : 0;
 203         u32 *_pv = (u32 *) lcdc_dev->regsbak;
 204
 205         _pv += (DSP_CTRL0 >> 2);
 206         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 207         if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) {
 208                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 209                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0);
 210                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 211
 212                 mask = m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 213                 val = v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 214                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 215         } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2)
 216                    && (win1_alpha_en)) {
 217                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 218                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1);
 219                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 220
 221                 mask = m_WIN1_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 222                 val = v_WIN1_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 223                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 224         } else {
 225                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 226                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 227                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 228         }
 229
 230         return 0;
 231 }
 232
 233 static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev,
 234                                       struct rk_lcdc_win *win)
 235 {
 236         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 237
 238         if (lcdc_dev->overlay_mode == VOP_YUV_DOMAIN) {
 239                 switch (win->fmt_cfg) {
 240                 case VOP_FORMAT_ARGB888:
 241                 case VOP_FORMAT_RGB888:
 242                 case VOP_FORMAT_RGB565:
 243                         if ((screen->mode.xres < 1280 ) &&
 244                             (screen->mode.yres < 720)) {
 245                                 win->csc_mode = VOP_R2Y_CSC_BT601;
 246                         } else {
 247                                 win->csc_mode = VOP_R2Y_CSC_BT709;
 248                         }
 249                         break;
 250                 default:
 251                         break;
 252                 }
 253                 if (win->id  == 0) {
 254                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 255                                      v_WIN0_CSC_MODE(win->csc_mode));
 256                 } else if (win->id  == 1) {
 257                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE,
 258                                      v_WIN1_CSC_MODE(win->csc_mode));
 259                 }
 260         } else if (lcdc_dev->overlay_mode == VOP_RGB_DOMAIN) {
 261                 switch (win->fmt_cfg) {
 262                 case VOP_FORMAT_YCBCR420:
 263                         if (win->id  == 0) {
 264                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
 265                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 266                                              v_WIN0_CSC_MODE(win->csc_mode));
 267                         }
 268                         break;
 269                 default:
 270                         break;
 271                 }
 272         }
 273
 274 }
 275
 276
 277 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 278                                    struct rk_lcdc_win *win)
 279 {
 280         u32 mask, val;
 281
 282         if (win->state == 1) {
 283                 if (lcdc_dev->soc_type == VOP_RK312X)
 284                         lcdc_layer_csc_mode(lcdc_dev,win);
 285
 286                 if (win->id == 0) {
 287                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 288                         val = v_WIN0_EN(win->state) |
 289                                 v_WIN0_FORMAT(win->fmt_cfg) |
 290                                 v_WIN0_RB_SWAP(win->swap_rb);
 291                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 292
 293                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 294                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 295                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 296                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 297                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 298                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 299
 300                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 301                                      m_YRGB_VIR | m_CBBR_VIR,
 302                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 303                                      v_CBCR_VIR(win->area[0].uv_vir_stride));
 304                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 305                                     v_ACT_WIDTH(win->area[0].xact) |
 306                                     v_ACT_HEIGHT(win->area[0].yact));
 307                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 308                                     v_DSP_STX(win->area[0].dsp_stx) |
 309                                     v_DSP_STY(win->area[0].dsp_sty));
 310                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 311                                     v_DSP_WIDTH(win->area[0].xsize) |
 312                                     v_DSP_HEIGHT(win->area[0].ysize));
 313
 314                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 315                                     win->area[0].y_addr);
 316                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 317                                     win->area[0].uv_addr);
 318                 } else if (win->id == 1) {
 319                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 320                         val = v_WIN1_EN(win->state) |
 321                                 v_WIN1_FORMAT(win->fmt_cfg) |
 322                                 v_WIN1_RB_SWAP(win->swap_rb);
 323                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 324
 325                         /* rk312x unsupport win1 scale */
 326                         if (lcdc_dev->soc_type == VOP_RK3036)
 327                                 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 328                                         v_X_SCL_FACTOR(win->scale_yrgb_x) |
 329                                         v_Y_SCL_FACTOR(win->scale_yrgb_y));
 330
 331                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 332                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 333                         lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 334                                     v_ACT_WIDTH(win->area[0].xact) |
 335                                     v_ACT_HEIGHT(win->area[0].yact));
 336                         lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 337                                     v_DSP_WIDTH(win->area[0].xsize) |
 338                                     v_DSP_HEIGHT(win->area[0].ysize));
 339                         lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 340                                     v_DSP_STX(win->area[0].dsp_stx) |
 341                                     v_DSP_STY(win->area[0].dsp_sty));
 342
 343                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 344
 345                 } else if (win->id == 2) {
 346                 }
 347         } else {
 348                 win->area[0].y_addr = 0;
 349                 win->area[0].uv_addr = 0;
 350                 if (win->id == 0)
 351                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN,
 352                                      v_WIN0_EN(0));
 353                 else if (win->id == 1)
 354                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN,
 355                                      v_WIN1_EN(0));
 356                 else if (win->id == 2)
 357                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
 358         }
 359 }
 360
 361 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id,
 362                               bool open)
 363 {
 364         spin_lock(&lcdc_dev->reg_lock);
 365         if (likely(lcdc_dev->clk_on)
 366             && lcdc_dev->driver.win[win_id]->state != open) {
 367                 if (open) {
 368                         if (!lcdc_dev->atv_layer_cnt) {
 369                                 dev_info(lcdc_dev->dev,
 370                                          "wakeup from standby!\n");
 371                                 lcdc_dev->standby = 0;
 372                         }
 373                         lcdc_dev->atv_layer_cnt++;
 374                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
 375                         lcdc_dev->atv_layer_cnt--;
 376                 }
 377                 lcdc_dev->driver.win[win_id]->state = open;
 378                 if (!open) {
 379                         lcdc_layer_update_regs(lcdc_dev,
 380                                                lcdc_dev->driver.win[win_id]);
 381                         lcdc_cfg_done(lcdc_dev);
 382                 }
 383                 /*if no layer used,disable lcdc */
 384                 if (!lcdc_dev->atv_layer_cnt) {
 385                         dev_info(lcdc_dev->dev,
 386                                  "no layer is used,go to standby!\n");
 387                         lcdc_dev->standby = 1;
 388                 }
 389         }
 390         spin_unlock(&lcdc_dev->reg_lock);
 391 }
 392
 393 static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 394 {
 395         struct lcdc_device *lcdc_dev =
 396             container_of(dev_drv, struct lcdc_device, driver);
 397         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 398         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 399         int timeout;
 400         unsigned long flags;
 401         spin_lock(&lcdc_dev->reg_lock);
 402         if (likely(lcdc_dev->clk_on)) {
 403                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 404                              v_LCDC_STANDBY(lcdc_dev->standby));
 405                 lcdc_layer_update_regs(lcdc_dev, win0);
 406                 lcdc_layer_update_regs(lcdc_dev, win1);
 407                 rk312x_lcdc_alpha_cfg(lcdc_dev);
 408                 lcdc_cfg_done(lcdc_dev);
 409
 410         }
 411         spin_unlock(&lcdc_dev->reg_lock);
 412         //if (dev_drv->wait_fs) {
 413         if (0) {
 414                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 415                 init_completion(&dev_drv->frame_done);
 416                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 417                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 418                                                       msecs_to_jiffies
 419                                                       (dev_drv->cur_screen->ft +
 420                                                        5));
 421                 if (!timeout && (!dev_drv->frame_done.done)) {
 422                         dev_warn(lcdc_dev->dev,
 423                                  "wait for new frame start time out!\n");
 424                         return -ETIMEDOUT;
 425                 }
 426         }
 427         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 428         return 0;
 429
 430 }
 431
 432 static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 433 {
 434         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0xdc);
 435 }
 436
 437 static void rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 438 {
 439         u32 mask, val;
 440         struct lcdc_device *lcdc_dev =
 441             container_of(dev_drv, struct lcdc_device, driver);
 442
 443         spin_lock(&lcdc_dev->reg_lock);
 444         if (likely(lcdc_dev->clk_on)) {
 445                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 446                         m_AXI_OUTSTANDING_MAX_NUM;
 447                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 448                         v_AXI_MAX_OUTSTANDING_EN(1);
 449                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 450         }
 451         spin_unlock(&lcdc_dev->reg_lock);
 452 }
 453
 454 static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
 455 {
 456         int i = 0;
 457         int __iomem *c;
 458         int v;
 459         struct lcdc_device *lcdc_dev =
 460                 container_of(dev_drv, struct lcdc_device, driver);
 461
 462         spin_lock(&lcdc_dev->reg_lock);
 463         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 464         lcdc_cfg_done(lcdc_dev);
 465         mdelay(25);
 466         for (i = 0; i < 256; i++) {
 467                 v = dev_drv->cur_screen->dsp_lut[i];
 468                 c = lcdc_dev->dsp_lut_addr_base + i;
 469                 writel_relaxed(v, c);
 470
 471         }
 472         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 473         lcdc_cfg_done(lcdc_dev);
 474         spin_unlock(&lcdc_dev->reg_lock);
 475         return 0;
 476
 477 }
 478
 479 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 480 {
 481 #ifdef CONFIG_RK_FPGA
 482         return 0;
 483 #endif
 484         int ret, fps;
 485         struct lcdc_device *lcdc_dev =
 486             container_of(dev_drv, struct lcdc_device, driver);
 487         struct rk_screen *screen = dev_drv->cur_screen;
 488
 489         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 490         if (ret)
 491                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
 492         lcdc_dev->pixclock =
 493             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 494         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 495
 496         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 497         screen->ft = 1000 / fps;
 498         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 499                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 500         return 0;
 501
 502 }
 503
 504 /********do basic init*********/
 505 static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 506 {
 507         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 508                                                     struct lcdc_device, driver);
 509         if (lcdc_dev->pre_init)
 510                 return 0;
 511
 512         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 513         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 514         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 515         lcdc_dev->sclk = devm_clk_get(lcdc_dev->dev, "sclk_lcdc");
 516 //      lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 517
 518         if ( /*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) ||
 519             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 520                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 521                         lcdc_dev->id);
 522         }
 523
 524         rk_disp_pwr_enable(dev_drv);
 525         rk312x_lcdc_clk_enable(lcdc_dev);
 526
 527         /* backup reg config at uboot */
 528         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 529
 530         /* config for the FRC mode of dither down */
 531         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 532         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 533         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0x55aaaa55);
 534         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x55aaaa55);
 535         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 536         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 537
 538         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0));
 539         lcdc_cfg_done(lcdc_dev);
 540         if (dev_drv->iommu_enabled)     /* disable win0 to workaround iommu pagefault */
 541                 lcdc_layer_enable(lcdc_dev, 0, 0);
 542         lcdc_dev->pre_init = true;
 543
 544         return 0;
 545 }
 546
 547 static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev)
 548 {
 549         u32 mask, val;
 550
 551         spin_lock(&lcdc_dev->reg_lock);
 552         if (likely(lcdc_dev->clk_on)) {
 553                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 554                         m_LF_INT_CLEAR | m_LF_INT_EN |
 555                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 556                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 557                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 558                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 559                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 560                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY);
 561                 lcdc_cfg_done(lcdc_dev);
 562                 spin_unlock(&lcdc_dev->reg_lock);
 563         } else {
 564                 spin_unlock(&lcdc_dev->reg_lock);
 565         }
 566         mdelay(1);
 567
 568 }
 569
 570 static u32 calc_sclk(struct rk_screen *src_screen, struct rk_screen *dst_screen)
 571 {
 572         u32 dsp_vtotal;
 573         u64 dsp_htotal;
 574         u32 dsp_in_vtotal;
 575         u64 dsp_in_htotal;
 576         u32 sclk;
 577
 578         if (!src_screen || !dst_screen)
 579                 return 0;
 580
 581         dsp_vtotal = dst_screen->mode.yres;
 582         dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len +
 583                      dst_screen->mode.xres + dst_screen->mode.right_margin;
 584         dsp_in_vtotal = src_screen->mode.yres;
 585         dsp_in_htotal = src_screen->mode.left_margin +
 586                         src_screen->mode.hsync_len +
 587                         src_screen->mode.xres + src_screen->mode.right_margin;
 588         sclk = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock;
 589         do_div(sclk, dsp_in_vtotal * dsp_in_htotal);
 590
 591         return sclk;
 592 }
 593
 594 static int calc_dsp_frm_vst_hst(struct rk_screen *src, struct rk_screen *dst)
 595 {
 596         u32 BP_in, BP_out;
 597         u32 v_scale_ratio;
 598 #if defined(FLOAT_CALC) /* use float */
 599         double T_frm_st;
 600         double T_BP_in, T_BP_out, T_Delta, Tin;
 601 #else
 602         long long  T_frm_st;
 603         u64 T_BP_in, T_BP_out, T_Delta, Tin;
 604         u64 rate = (1 << 16);
 605         u64 temp;
 606 #endif
 607         u32 dsp_htotal, src_htotal, src_vtotal;
 608
 609         if (unlikely(!src) || unlikely(!dst))
 610                 return -1;
 611
 612         dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len +
 613                      dst->mode.xres + dst->mode.right_margin;
 614         src_htotal = src->mode.left_margin + src->mode.hsync_len +
 615                      src->mode.xres + src->mode.right_margin;
 616         src_vtotal = src->mode.upper_margin + src->mode.vsync_len +
 617                      src->mode.yres + src->mode.lower_margin;
 618         BP_in  = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal;
 619         BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal;
 620
 621         v_scale_ratio = dst->mode.yres / src->mode.yres;
 622
 623 #if defined(FLOAT_CALC)
 624         T_BP_in = 1.0 * BP_in / src->mode.pixclock;
 625         T_BP_out = 1.0 * BP_out / dst->mode.pixclock;
 626         if (v_scale_ratio < 2)
 627                 T_Delta = 4.0 * src_htotal / src->mode.pixclock;
 628         else
 629                 T_Delta = 12.0 * src_htotal / src->mode.pixclock;
 630
 631         Tin = 1.0 * src_vtotal * src_htotal / src->mode.pixclock;
 632 #else
 633         T_BP_in = rate * BP_in;
 634         do_div(T_BP_in, src->mode.pixclock);
 635         T_BP_out = rate * BP_out;
 636         do_div(T_BP_out, dst->mode.pixclock);
 637         if (v_scale_ratio < 2)
 638                 T_Delta = rate * 4 * src_htotal;
 639         else
 640                 T_Delta = rate * 12 * src_htotal;
 641
 642         do_div(T_Delta, src->mode.pixclock);
 643         Tin = rate * src_vtotal * src_htotal;
 644         do_div(Tin, src->mode.pixclock);
 645 #endif
 646
 647         T_frm_st = (T_BP_in + T_Delta - T_BP_out);
 648         if (T_frm_st < 0)
 649                 T_frm_st  += Tin;
 650
 651 #if defined(FLOAT_CALC)
 652         dst->scl_vst = (u16)(T_frm_st * src->mode.pixclock / src_htotal);
 653         dst->scl_hst = (u32)(T_frm_st * src->mode.pixclock) % src_htotal;
 654 #else
 655         temp = T_frm_st * src->mode.pixclock;
 656         dst->scl_hst = do_div(temp, src_htotal * rate);
 657         dst->scl_vst = temp;
 658 #endif
 659
 660         return 0;
 661 }
 662
 663 static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 664                                   struct rk_screen *dst_screen, bool enable)
 665 {
 666         u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
 667         u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
 668         u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
 669         u32 scl_v_factor, scl_h_factor;
 670         u32 dst_frame_hst, dst_frame_vst;
 671         u32 src_w, src_h, dst_w, dst_h;
 672         u16 bor_right = 0;
 673         u16 bor_left = 0;
 674         u16 bor_up = 0;
 675         u16 bor_down = 0;
 676         struct rk_screen *src;
 677         struct rk_screen *dst;
 678         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 679                                                     struct lcdc_device, driver);
 680
 681         if (unlikely(!lcdc_dev->clk_on))
 682                 return 0;
 683
 684         if(!enable) {
 685                 clk_disable_unprepare(lcdc_dev->sclk);
 686                 dev_info(lcdc_dev->dev, "%s: disable\n", __func__);
 687                 return 0;
 688         }
 689
 690         /* rk312x used one lcdc to apply dual disp
 691          * hdmi screen is used for scaler src
 692          * prmry screen is used for scaler dst
 693          */
 694         dst = dst_screen;
 695         if (!dst) {
 696                 dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__);
 697                 return -EINVAL;
 698         }
 699
 700         src = dst_screen->ext_screen;
 701
 702         clk_prepare_enable(lcdc_dev->sclk);
 703         lcdc_dev->s_pixclock = calc_sclk(src, dst);
 704         clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock);
 705
 706         /* config scale timing */
 707         calc_dsp_frm_vst_hst(src, dst);
 708         dst_frame_vst = dst->scl_vst;
 709         dst_frame_hst = dst->scl_hst;
 710
 711         dsp_htotal    = dst->mode.hsync_len + dst->mode.left_margin +
 712                         dst->mode.xres + dst->mode.right_margin;
 713         dsp_hs_end    = dst->mode.hsync_len;
 714
 715         dsp_vtotal    = dst->mode.vsync_len + dst->mode.upper_margin +
 716                         dst->mode.yres + dst->mode.lower_margin;
 717         dsp_vs_end    = dst->mode.vsync_len;
 718
 719         dsp_hbor_end  = dst->mode.hsync_len + dst->mode.left_margin +
 720                         dst->mode.xres;
 721         dsp_hbor_st   = dst->mode.hsync_len + dst->mode.left_margin;
 722         dsp_vbor_end  = dst->mode.vsync_len + dst->mode.upper_margin +
 723                         dst->mode.yres;
 724         dsp_vbor_st   = dst->mode.vsync_len + dst->mode.upper_margin;
 725
 726         dsp_hact_st   = dsp_hbor_st  + bor_left;
 727         dsp_hact_end  = dsp_hbor_end - bor_right;
 728         dsp_vact_st   = dsp_vbor_st  + bor_up;
 729         dsp_vact_end  = dsp_vbor_end - bor_down;
 730
 731         src_w = src->mode.xres;
 732         src_h = src->mode.yres;
 733         dst_w = dsp_hact_end - dsp_hact_st;
 734         dst_h = dsp_vact_end - dsp_vact_st;
 735
 736         /* calc scale factor */
 737         scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1);
 738         scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1);
 739
 740         spin_lock(&lcdc_dev->reg_lock);
 741         lcdc_writel(lcdc_dev, SCALER_FACTOR,
 742                     v_SCALER_H_FACTOR(scl_h_factor) |
 743                     v_SCALER_V_FACTOR(scl_v_factor));
 744
 745         lcdc_writel(lcdc_dev, SCALER_FRAME_ST,
 746                     v_SCALER_FRAME_HST(dst_frame_hst) |
 747                     v_SCALER_FRAME_VST(dst_frame_hst));
 748         lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING,
 749                     v_SCALER_HS_END(dsp_hs_end) |
 750                     v_SCALER_HTOTAL(dsp_htotal));
 751         lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END,
 752                     v_SCALER_HAEP(dsp_hact_end) |
 753                     v_SCALER_HASP(dsp_hact_st));
 754         lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING,
 755                     v_SCALER_VS_END(dsp_vs_end) |
 756                     v_SCALER_VTOTAL(dsp_vtotal));
 757         lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END,
 758                     v_SCALER_VAEP(dsp_vact_end) |
 759                     v_SCALER_VASP(dsp_vact_st));
 760         lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING,
 761                     v_SCALER_HBOR_END(dsp_hbor_end) |
 762                     v_SCALER_HBOR_ST(dsp_hbor_st));
 763         lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING,
 764                     v_SCALER_VBOR_END(dsp_vbor_end) |
 765                     v_SCALER_VBOR_ST(dsp_vbor_st));
 766         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 767                     m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 768                     v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(1));
 769         spin_unlock(&lcdc_dev->reg_lock);
 770
 771         return 0;
 772 }
 773
 774 static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 775 {
 776         u16 face = 0;
 777         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 778                                                     struct lcdc_device, driver);
 779         struct rk_screen *screen = dev_drv->cur_screen;
 780         u16 right_margin = screen->mode.right_margin;
 781         u16 left_margin = screen->mode.left_margin;
 782         u16 lower_margin = screen->mode.lower_margin;
 783         u16 upper_margin = screen->mode.upper_margin;
 784         u16 x_res = screen->mode.xres;
 785         u16 y_res = screen->mode.yres;
 786         u32 mask, val;
 787
 788         spin_lock(&lcdc_dev->reg_lock);
 789         if (likely(lcdc_dev->clk_on)) {
 790                 switch (screen->type) {
 791                 case SCREEN_RGB:
 792                         if (lcdc_dev->soc_type == VOP_RK312X) {
 793                                 mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT;
 794                                 val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0);
 795                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 796                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 797                         }
 798                         break;
 799                 case SCREEN_LVDS:
 800                         if (lcdc_dev->soc_type == VOP_RK312X) {
 801                                 mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT;
 802                                 val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(1);
 803                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 804                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 805                         }
 806                         break;
 807                 case SCREEN_MIPI:
 808                         if (lcdc_dev->soc_type == VOP_RK312X) {
 809                                 mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT;
 810                                 val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0);
 811                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 812                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 813                         }
 814                         break;
 815                 case SCREEN_HDMI:
 816                         mask = m_HDMI_DCLK_EN;
 817                         val = v_HDMI_DCLK_EN(1);
 818                         if (screen->pixelrepeat) {
 819                                 mask |= m_CORE_CLK_DIV_EN;
 820                                 val |= v_CORE_CLK_DIV_EN(1);
 821                         }
 822                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 823                         if (lcdc_dev->soc_type == VOP_RK312X) {
 824                                 lcdc_dev->overlay_mode = VOP_YUV_DOMAIN;
 825                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 826                                              m_SW_UV_OFFSET_EN,
 827                                              v_SW_UV_OFFSET_EN(0));
 828                         }
 829                         break;
 830                 case SCREEN_TVOUT:
 831                         mask = m_TVE_DAC_DCLK_EN;
 832                         val = v_TVE_DAC_DCLK_EN(1);
 833                         if (screen->pixelrepeat) {
 834                                 mask |= m_CORE_CLK_DIV_EN;
 835                                 val |= v_CORE_CLK_DIV_EN(1);
 836                         }
 837                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 838                         if (x_res == 720 && y_res == 576)
 839                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 840                                              v_TVE_MODE(TV_PAL));
 841                         else if (x_res == 720 && y_res == 480)
 842                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 843                                              v_TVE_MODE(TV_NTSC));
 844                         else {
 845                                 dev_err(lcdc_dev->dev,
 846                                         "unsupported video timing!\n");
 847                                 return -1;
 848                         }
 849                         if (lcdc_dev->soc_type == VOP_RK312X) {
 850                                 lcdc_dev->overlay_mode = VOP_YUV_DOMAIN;
 851                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 852                                              m_SW_UV_OFFSET_EN,
 853                                              v_SW_UV_OFFSET_EN(1));
 854                         }
 855                         break;
 856                 default:
 857                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 858                         break;
 859                 }
 860                 if (lcdc_dev->soc_type == VOP_RK312X) {
 861                         switch (screen->face) {
 862                         case OUT_P565:
 863                                 face = OUT_P565;
 864                                 mask = m_DITHER_DOWN_EN |
 865                                         m_DITHER_DOWN_MODE |
 866                                         m_DITHER_DOWN_SEL;
 867                                 val = v_DITHER_DOWN_EN(1) |
 868                                         v_DITHER_DOWN_MODE(0) |
 869                                         v_DITHER_DOWN_SEL(1);
 870                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 871                                 break;
 872                         case OUT_P666:
 873                                 face = OUT_P666;
 874                                 mask = m_DITHER_DOWN_EN |
 875                                         m_DITHER_DOWN_MODE |
 876                                         m_DITHER_DOWN_SEL;
 877                                 val = v_DITHER_DOWN_EN(1) |
 878                                         v_DITHER_DOWN_MODE(1) |
 879                                         v_DITHER_DOWN_SEL(1);
 880                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 881                                 break;
 882                         case OUT_D888_P565:
 883                                 face = OUT_P888;
 884                                 mask = m_DITHER_DOWN_EN |
 885                                         m_DITHER_DOWN_MODE |
 886                                         m_DITHER_DOWN_SEL;
 887                                 val = v_DITHER_DOWN_EN(1) |
 888                                         v_DITHER_DOWN_MODE(0) |
 889                                         v_DITHER_DOWN_SEL(1);
 890                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 891                                 break;
 892                         case OUT_D888_P666:
 893                                 face = OUT_P888;
 894                                 mask = m_DITHER_DOWN_EN |
 895                                         m_DITHER_DOWN_MODE |
 896                                         m_DITHER_DOWN_SEL;
 897                                 val = v_DITHER_DOWN_EN(1) |
 898                                         v_DITHER_DOWN_MODE(1) |
 899                                         v_DITHER_DOWN_SEL(1);
 900                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 901                                 break;
 902                         case OUT_P888:
 903                                 face = OUT_P888;
 904                                 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
 905                                 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
 906                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 907                                 break;
 908                         default:
 909                                 dev_err(lcdc_dev->dev, "un supported interface!\n");
 910                                 break;
 911                         }
 912                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 913                                      v_SW_OVERLAY_MODE(lcdc_dev->overlay_mode));
 914                 }
 915
 916                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 917                     m_DEN_POL | m_DCLK_POL;
 918                 val = v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) |
 919                     v_VSYNC_POL(screen->pin_vsync) |
 920                     v_DEN_POL(screen->pin_den) |
 921                     v_DCLK_POL(screen->pin_dclk);
 922                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 923
 924                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 925                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
 926                     m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN;
 927
 928                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
 929                     v_DSP_RB_SWAP(screen->swap_rb) |
 930                     v_DSP_RG_SWAP(screen->swap_rg) |
 931                     v_DSP_DELTA_SWAP(screen->swap_delta) |
 932                     v_DSP_DUMMY_SWAP(screen->swap_dumy) |
 933                     v_BLANK_EN(0) | v_BLACK_EN(0);
 934                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 935
 936                 /* config timing */
 937                 val = v_HSYNC(screen->mode.hsync_len) |
 938                     v_HORPRD(screen->mode.hsync_len + left_margin + x_res +
 939                              right_margin);
 940                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
 941                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
 942                     v_HASP(screen->mode.hsync_len + left_margin);
 943                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
 944
 945                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 946                         /* First Field Timing */
 947                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
 948                                     v_VSYNC(screen->mode.vsync_len) |
 949                                     v_VERPRD(2 * (screen->mode.vsync_len + upper_margin + lower_margin) +
 950                                              y_res + 1));
 951                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
 952                                     v_VAEP(screen->mode.vsync_len +
 953                                            upper_margin + y_res / 2) |
 954                                     v_VASP(screen->mode.vsync_len +
 955                                            upper_margin));
 956                         /* Second Field Timing */
 957                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
 958                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
 959                                                   upper_margin + y_res / 2 +
 960                                                   lower_margin) |
 961                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len +
 962                                                    upper_margin + y_res / 2 +
 963                                                    lower_margin));
 964                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
 965                                     v_VAEP(2 * (screen->mode.vsync_len + upper_margin) +
 966                                            y_res + lower_margin + 1) |
 967                                     v_VASP(2 * (screen->mode.vsync_len + upper_margin) +
 968                                            y_res / 2 + lower_margin + 1));
 969
 970                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 971                                      m_INTERLACE_DSP_EN |
 972                                      m_WIN0_YRGB_DEFLICK_EN |
 973                                      m_WIN0_CBR_DEFLICK_EN |
 974                                      m_INTERLACE_FIELD_POL,
 975                                      v_INTERLACE_DSP_EN(1) |
 976                                      v_WIN0_YRGB_DEFLICK_EN(1) |
 977                                      v_WIN0_CBR_DEFLICK_EN(1) |
 978                                      v_INTERLACE_FIELD_POL(0));
 979                 } else {
 980                         val = v_VSYNC(screen->mode.vsync_len) |
 981                             v_VERPRD(screen->mode.vsync_len + upper_margin +
 982                                      y_res + lower_margin);
 983                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
 984
 985                         val = v_VAEP(screen->mode.vsync_len + upper_margin + y_res) |
 986                             v_VASP(screen->mode.vsync_len + upper_margin);
 987                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
 988
 989                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 990                                      m_INTERLACE_DSP_EN |
 991                                      m_WIN0_YRGB_DEFLICK_EN |
 992                                      m_WIN0_CBR_DEFLICK_EN |
 993                                      m_INTERLACE_FIELD_POL,
 994                                      v_INTERLACE_DSP_EN(0) |
 995                                      v_WIN0_YRGB_DEFLICK_EN(0) |
 996                                      v_WIN0_CBR_DEFLICK_EN(0) |
 997                                      v_INTERLACE_FIELD_POL(0));
 998                 }
 999
1000         }
1001         spin_unlock(&lcdc_dev->reg_lock);
1002
1003         rk312x_lcdc_set_dclk(dev_drv);
1004         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1005                 dev_drv->trsm_ops->enable();
1006         if (screen->init)
1007                 screen->init();
1008
1009         return 0;
1010 }
1011
1012 static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1013                             bool open)
1014 {
1015         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1016                                                     struct lcdc_device, driver);
1017
1018         /* enable clk,when first layer open */
1019         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1020                 rockchip_set_system_status(SYS_STATUS_LCDC0);
1021                 rk312x_lcdc_pre_init(dev_drv);
1022 #if defined(CONFIG_ROCKCHIP_IOMMU)
1023                 if (dev_drv->iommu_enabled) {
1024                         if (!dev_drv->mmu_dev) {
1025                                 dev_drv->mmu_dev =
1026                                     rockchip_get_sysmmu_device_by_compatible
1027                                     (dev_drv->mmu_dts_name);
1028                                 if (dev_drv->mmu_dev)
1029                                         platform_set_sysmmu(dev_drv->mmu_dev,
1030                                                             dev_drv->dev);
1031                                 else {
1032                                         dev_err(dev_drv->dev,
1033                                                 "failed to get rockchip iommu device\n");
1034                                         return -1;
1035                                 }
1036                         }
1037                         iovmm_activate(dev_drv->dev);
1038                 }
1039 #endif
1040                 rk312x_lcdc_reg_restore(lcdc_dev);
1041                 if (dev_drv->iommu_enabled)
1042                         rk312x_lcdc_mmu_en(dev_drv);
1043                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1044                         rk312x_lcdc_set_dclk(dev_drv);
1045                         rk312x_lcdc_enable_irq(dev_drv);
1046                 } else {
1047                         rk312x_load_screen(dev_drv, 1);
1048                 }
1049
1050                 /* set screen lut */
1051                 if (dev_drv->cur_screen->dsp_lut)
1052                         rk312x_lcdc_set_lut(dev_drv);
1053         }
1054
1055         if (win_id < ARRAY_SIZE(lcdc_win))
1056                 lcdc_layer_enable(lcdc_dev, win_id, open);
1057         else
1058                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1059
1060         /* when all layer closed,disable clk */
1061         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1062                 rk312x_lcdc_disable_irq(lcdc_dev);
1063                 rk312x_lcdc_reg_update(dev_drv);
1064 #if defined(CONFIG_ROCKCHIP_IOMMU)
1065                 if (dev_drv->iommu_enabled) {
1066                         if (dev_drv->mmu_dev)
1067                                 iovmm_deactivate(dev_drv->dev);
1068                 }
1069 #endif
1070                 rk312x_lcdc_clk_disable(lcdc_dev);
1071                 rockchip_clear_system_status(SYS_STATUS_LCDC0);
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
1078 {
1079         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1080                                                     struct lcdc_device, driver);
1081         struct rk_screen *screen = dev_drv->cur_screen;
1082         struct rk_lcdc_win *win = NULL;
1083         char fmt[9] = "NULL";
1084
1085         if (!screen) {
1086                 dev_err(dev_drv->dev, "screen is null!\n");
1087                 return -ENOENT;
1088         }
1089
1090         if (win_id == 0) {
1091                 win = dev_drv->win[0];
1092         } else if (win_id == 1) {
1093                 win = dev_drv->win[1];
1094         } else {
1095                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
1096                 return -EINVAL;
1097         }
1098
1099         spin_lock(&lcdc_dev->reg_lock);
1100         win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin +
1101                                 screen->mode.hsync_len;
1102         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1103                 win->area[0].ysize /= 2;
1104                 win->area[0].dsp_sty = win->area[0].ypos / 2 +
1105                                         screen->mode.upper_margin +
1106                                         screen->mode.vsync_len;
1107         } else {
1108                 win->area[0].dsp_sty = win->area[0].ypos +
1109                                         screen->mode.upper_margin +
1110                                         screen->mode.vsync_len;
1111         }
1112         win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize);
1113         win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize);
1114         switch (win->format) {
1115         case ARGB888:
1116                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1117                 win->swap_rb = 0;
1118                 break;
1119         case XBGR888:
1120                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1121                 win->swap_rb = 1;
1122                 break;
1123         case ABGR888:
1124                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1125                 win->swap_rb = 1;
1126                 break;
1127         case RGB888:
1128                 win->fmt_cfg = VOP_FORMAT_RGB888;
1129                 win->swap_rb = 0;
1130                 break;
1131         case RGB565:
1132                 win->fmt_cfg = VOP_FORMAT_RGB565;
1133                 win->swap_rb = 0;
1134                 break;
1135         case YUV444:
1136                 if (win_id == 0) {
1137                         win->fmt_cfg = VOP_FORMAT_YCBCR444;
1138                         win->scale_cbcr_x =
1139                             CalScale(win->area[0].xact, win->area[0].xsize);
1140                         win->scale_cbcr_y =
1141                             CalScale(win->area[0].yact, win->area[0].ysize);
1142                         win->swap_rb = 0;
1143                 } else {
1144                         dev_err(lcdc_dev->driver.dev,
1145                                 "%s:un supported format!\n", __func__);
1146                 }
1147                 break;
1148         case YUV422:
1149                 if (win_id == 0) {
1150                         win->fmt_cfg = VOP_FORMAT_YCBCR422;
1151                         win->scale_cbcr_x = CalScale((win->area[0].xact / 2),
1152                                                      win->area[0].xsize);
1153                         win->scale_cbcr_y =
1154                             CalScale(win->area[0].yact, win->area[0].ysize);
1155                         win->swap_rb = 0;
1156                 } else {
1157                         dev_err(lcdc_dev->driver.dev,
1158                                 "%s:un supported format!\n", __func__);
1159                 }
1160                 break;
1161         case YUV420:
1162                 if (win_id == 0) {
1163                         win->fmt_cfg = VOP_FORMAT_YCBCR420;
1164                         win->scale_cbcr_x =
1165                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1166                         win->scale_cbcr_y =
1167                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1168                         win->swap_rb = 0;
1169                 } else {
1170                         dev_err(lcdc_dev->driver.dev,
1171                                 "%s:un supported format!\n", __func__);
1172                 }
1173                 break;
1174         default:
1175                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1176                         __func__);
1177                 break;
1178         }
1179         spin_unlock(&lcdc_dev->reg_lock);
1180
1181         DBG(1,
1182             "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
1183             ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__,
1184             get_format_string(win->format, fmt), win->area[0].xact,
1185             win->area[0].yact, win->area[0].xsize, win->area[0].ysize,
1186             win->area[0].xvir, win->area[0].yvir, win->area[0].xpos,
1187             win->area[0].ypos);
1188         return 0;
1189 }
1190
1191 static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1192 {
1193         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1194                                                     struct lcdc_device, driver);
1195         struct rk_lcdc_win *win = NULL;
1196         struct rk_screen *screen = dev_drv->cur_screen;
1197
1198         if (!screen) {
1199                 dev_err(dev_drv->dev, "screen is null!\n");
1200                 return -ENOENT;
1201         }
1202
1203         if (win_id == 0) {
1204                 win = dev_drv->win[0];
1205         } else if (win_id == 1) {
1206                 win = dev_drv->win[1];
1207         } else {
1208                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1209                 return -EINVAL;
1210         }
1211
1212         spin_lock(&lcdc_dev->reg_lock);
1213         if (likely(lcdc_dev->clk_on)) {
1214                 win->area[0].y_addr =
1215                     win->area[0].smem_start + win->area[0].y_offset;
1216                 win->area[0].uv_addr =
1217                     win->area[0].cbr_start + win->area[0].c_offset;
1218                 if (win->area[0].y_addr)
1219                         lcdc_layer_update_regs(lcdc_dev, win);
1220                 /* lcdc_cfg_done(lcdc_dev); */
1221         }
1222         spin_unlock(&lcdc_dev->reg_lock);
1223
1224         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1225             lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr,
1226             win->area[0].y_offset);
1227         /* this is the first frame of the system,enable frame start interrupt */
1228         if ((dev_drv->first_frame)) {
1229                 dev_drv->first_frame = 0;
1230                 rk312x_lcdc_enable_irq(dev_drv);
1231
1232         }
1233
1234         return 0;
1235 }
1236
1237 static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
1238                              unsigned long arg, int win_id)
1239 {
1240         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1241                                                     struct lcdc_device, driver);
1242         u32 panel_size[2];
1243         void __user *argp = (void __user *)arg;
1244         struct color_key_cfg clr_key_cfg;
1245
1246         switch (cmd) {
1247         case RK_FBIOGET_PANEL_SIZE:
1248                 panel_size[0] = lcdc_dev->screen->mode.xres;
1249                 panel_size[1] = lcdc_dev->screen->mode.yres;
1250                 if (copy_to_user(argp, panel_size, 8))
1251                         return -EFAULT;
1252                 break;
1253         case RK_FBIOPUT_COLOR_KEY_CFG:
1254                 if (copy_from_user(&clr_key_cfg, argp,
1255                                    sizeof(struct color_key_cfg)))
1256                         return -EFAULT;
1257                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
1258                             clr_key_cfg.win0_color_key_cfg);
1259                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
1260                             clr_key_cfg.win1_color_key_cfg);
1261                 break;
1262
1263         default:
1264                 break;
1265         }
1266         return 0;
1267 }
1268
1269 static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
1270                                   const char *id)
1271 {
1272         int win_id = 0;
1273         mutex_lock(&dev_drv->fb_win_id_mutex);
1274         if (!strcmp(id, "fb0"))
1275                 win_id = dev_drv->fb0_win_id;
1276         else if (!strcmp(id, "fb1"))
1277                 win_id = dev_drv->fb1_win_id;
1278         else if (!strcmp(id, "fb2"))
1279                 win_id = dev_drv->fb2_win_id;
1280         mutex_unlock(&dev_drv->fb_win_id_mutex);
1281
1282         return win_id;
1283 }
1284
1285 static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
1286 {
1287         return 0;
1288 }
1289
1290 static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1291                                bool set)
1292 {
1293         struct lcdc_device *lcdc_dev =
1294             container_of(dev_drv, struct lcdc_device, driver);
1295         int ovl;
1296         spin_lock(&lcdc_dev->reg_lock);
1297         if (lcdc_dev->clk_on) {
1298                 if (set) {
1299                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1300                                      v_WIN0_TOP(swap));
1301                         ovl = swap;
1302                 } else {
1303                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1304                 }
1305         } else {
1306                 ovl = -EPERM;
1307         }
1308         spin_unlock(&lcdc_dev->reg_lock);
1309
1310         return ovl;
1311 }
1312
1313 static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1314 {
1315
1316         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1317                                                     struct lcdc_device, driver);
1318         if (dev_drv->suspend_flag)
1319                 return 0;
1320         dev_drv->suspend_flag = 1;
1321         flush_kthread_worker(&dev_drv->update_regs_worker);
1322
1323         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1324                 dev_drv->trsm_ops->disable();
1325         spin_lock(&lcdc_dev->reg_lock);
1326         if (likely(lcdc_dev->clk_on)) {
1327                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1));
1328                 lcdc_msk_reg(lcdc_dev, INT_STATUS,
1329                              m_FS_INT_CLEAR | m_LF_INT_CLEAR,
1330                              v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1));
1331                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1332                              v_DSP_OUT_ZERO(1));
1333                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1334                              v_LCDC_STANDBY(1));
1335                 lcdc_cfg_done(lcdc_dev);
1336 #if defined(CONFIG_ROCKCHIP_IOMMU)
1337                 if (dev_drv->iommu_enabled) {
1338                         if (dev_drv->mmu_dev)
1339                                 iovmm_deactivate(dev_drv->dev);
1340                 }
1341 #endif
1342                 spin_unlock(&lcdc_dev->reg_lock);
1343         } else {
1344                 spin_unlock(&lcdc_dev->reg_lock);
1345                 return 0;
1346         }
1347         rk312x_lcdc_clk_disable(lcdc_dev);
1348         rk_disp_pwr_disable(dev_drv);
1349         return 0;
1350 }
1351
1352 static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1353 {
1354         struct lcdc_device *lcdc_dev =
1355             container_of(dev_drv, struct lcdc_device, driver);
1356
1357         if (!dev_drv->suspend_flag)
1358                 return 0;
1359         rk_disp_pwr_enable(dev_drv);
1360         dev_drv->suspend_flag = 0;
1361
1362         if (lcdc_dev->atv_layer_cnt) {
1363                 rk312x_lcdc_clk_enable(lcdc_dev);
1364                 rk312x_lcdc_reg_restore(lcdc_dev);
1365                 /* set screen lut */
1366                 if (dev_drv->cur_screen->dsp_lut)
1367                         rk312x_lcdc_set_lut(dev_drv);
1368
1369                 spin_lock(&lcdc_dev->reg_lock);
1370
1371                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1372                              v_DSP_OUT_ZERO(0));
1373                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1374                              v_LCDC_STANDBY(0));
1375                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0));
1376                 lcdc_cfg_done(lcdc_dev);
1377
1378                 spin_unlock(&lcdc_dev->reg_lock);
1379         }
1380
1381         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1382                 dev_drv->trsm_ops->enable();
1383         return 0;
1384 }
1385
1386 static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1387                              int win_id, int blank_mode)
1388 {
1389         switch (blank_mode) {
1390         case FB_BLANK_UNBLANK:
1391                 rk312x_lcdc_early_resume(dev_drv);
1392                 break;
1393         case FB_BLANK_NORMAL:
1394                 rk312x_lcdc_early_suspend(dev_drv);
1395                 break;
1396         default:
1397                 rk312x_lcdc_early_suspend(dev_drv);
1398                 break;
1399         }
1400
1401         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1402
1403         return 0;
1404 }
1405
1406 static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1407 {
1408         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1409                                                     struct lcdc_device, driver);
1410         spin_lock(&lcdc_dev->reg_lock);
1411         if (lcdc_dev->clk_on)
1412                 lcdc_cfg_done(lcdc_dev);
1413         spin_unlock(&lcdc_dev->reg_lock);
1414         return 0;
1415 }
1416
1417 /*
1418         a:[-30~0]:
1419             sin_hue = sin(a)*256 +0x100;
1420             cos_hue = cos(a)*256;
1421         a:[0~30]
1422             sin_hue = sin(a)*256;
1423             cos_hue = cos(a)*256;
1424 */
1425 static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1426                                     bcsh_hue_mode mode)
1427 {
1428
1429         struct lcdc_device *lcdc_dev =
1430             container_of(dev_drv, struct lcdc_device, driver);
1431         u32 val;
1432
1433         spin_lock(&lcdc_dev->reg_lock);
1434         if (lcdc_dev->clk_on) {
1435                 val = lcdc_readl(lcdc_dev, BCSH_H);
1436                 switch (mode) {
1437                 case H_SIN:
1438                         val &= m_BCSH_SIN_HUE;
1439                         break;
1440                 case H_COS:
1441                         val &= m_BCSH_COS_HUE;
1442                         val >>= 16;
1443                         break;
1444                 default:
1445                         break;
1446                 }
1447         }
1448         spin_unlock(&lcdc_dev->reg_lock);
1449
1450         return val;
1451 }
1452
1453 static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue,
1454                                     int cos_hue)
1455 {
1456
1457         struct lcdc_device *lcdc_dev =
1458             container_of(dev_drv, struct lcdc_device, driver);
1459         u32 mask, val;
1460
1461         spin_lock(&lcdc_dev->reg_lock);
1462         if (lcdc_dev->clk_on) {
1463                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1464                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1465                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1466                 lcdc_cfg_done(lcdc_dev);
1467         }
1468         spin_unlock(&lcdc_dev->reg_lock);
1469
1470         return 0;
1471 }
1472
1473 static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1474                                     bcsh_bcs_mode mode, int value)
1475 {
1476         struct lcdc_device *lcdc_dev =
1477             container_of(dev_drv, struct lcdc_device, driver);
1478         u32 mask, val;
1479
1480         spin_lock(&lcdc_dev->reg_lock);
1481         if (lcdc_dev->clk_on) {
1482                 switch (mode) {
1483                 case BRIGHTNESS:
1484                         /* from 0 to 255,typical is 128 */
1485                         if (value < 0x80)
1486                                 value += 0x80;
1487                         else if (value >= 0x80)
1488                                 value = value - 0x80;
1489                         mask = m_BCSH_BRIGHTNESS;
1490                         val = v_BCSH_BRIGHTNESS(value);
1491                         break;
1492                 case CONTRAST:
1493                         /* from 0 to 510,typical is 256 */
1494                         mask = m_BCSH_CONTRAST;
1495                         val = v_BCSH_CONTRAST(value);
1496                         break;
1497                 case SAT_CON:
1498                         /* from 0 to 1015,typical is 256 */
1499                         mask = m_BCSH_SAT_CON;
1500                         val = v_BCSH_SAT_CON(value);
1501                         break;
1502                 default:
1503                         break;
1504                 }
1505                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1506                 lcdc_cfg_done(lcdc_dev);
1507         }
1508         spin_unlock(&lcdc_dev->reg_lock);
1509         return val;
1510 }
1511
1512 static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1513                                     bcsh_bcs_mode mode)
1514 {
1515         struct lcdc_device *lcdc_dev =
1516             container_of(dev_drv, struct lcdc_device, driver);
1517         u32 val;
1518
1519         spin_lock(&lcdc_dev->reg_lock);
1520         if (lcdc_dev->clk_on) {
1521                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1522                 switch (mode) {
1523                 case BRIGHTNESS:
1524                         val &= m_BCSH_BRIGHTNESS;
1525                         if (val > 0x80)
1526                                 val -= 0x80;
1527                         else
1528                                 val += 0x80;
1529                         break;
1530                 case CONTRAST:
1531                         val &= m_BCSH_CONTRAST;
1532                         val >>= 8;
1533                         break;
1534                 case SAT_CON:
1535                         val &= m_BCSH_SAT_CON;
1536                         val >>= 20;
1537                         break;
1538                 default:
1539                         break;
1540                 }
1541         }
1542         spin_unlock(&lcdc_dev->reg_lock);
1543         return val;
1544 }
1545
1546 static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1547 {
1548         struct lcdc_device *lcdc_dev =
1549             container_of(dev_drv, struct lcdc_device, driver);
1550         u32 mask, val;
1551
1552         spin_lock(&lcdc_dev->reg_lock);
1553         if (lcdc_dev->clk_on) {
1554                 if (open) {
1555                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1556                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1557                         lcdc_writel(lcdc_dev, BCSH_BCS,
1558                                     v_BCSH_BRIGHTNESS(0x00) |
1559                                     v_BCSH_CONTRAST(0x80) |
1560                                     v_BCSH_SAT_CON(0x80));
1561                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1562                 } else {
1563                         mask = m_BCSH_EN;
1564                         val = v_BCSH_EN(0);
1565                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1566                 }
1567                 lcdc_cfg_done(lcdc_dev);
1568         }
1569
1570         if (lcdc_dev->overlay_mode == VOP_YUV_DOMAIN) {
1571                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_CSC_MODE,
1572                              v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_BYPASS));
1573         } else {
1574                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_CSC_MODE,
1575                              v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
1576         }
1577
1578         spin_unlock(&lcdc_dev->reg_lock);
1579         return 0;
1580 }
1581
1582 static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv,
1583                                enum fb_win_map_order order)
1584 {
1585         mutex_lock(&dev_drv->fb_win_id_mutex);
1586         if (order == FB_DEFAULT_ORDER)
1587                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;     /* FB0_WIN1_FB1_WIN0_FB2_WIN2; for box */
1588         dev_drv->fb2_win_id = order / 100;
1589         dev_drv->fb1_win_id = (order / 10) % 10;
1590         dev_drv->fb0_win_id = order % 10;
1591         mutex_unlock(&dev_drv->fb_win_id_mutex);
1592
1593         return 0;
1594 }
1595
1596 static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1597                                bool set)
1598 {
1599         struct lcdc_device *lcdc_dev =
1600             container_of(dev_drv, struct lcdc_device, driver);
1601         struct rk_screen *screen = dev_drv->cur_screen;
1602         u64 ft = 0;
1603         u32 dotclk;
1604         int ret;
1605         u32 pixclock;
1606         u32 x_total, y_total;
1607         if (set) {
1608                 ft = div_u64(1000000000000llu, fps);
1609                 x_total =
1610                     screen->mode.upper_margin + screen->mode.lower_margin +
1611                     screen->mode.yres + screen->mode.vsync_len;
1612                 y_total =
1613                     screen->mode.left_margin + screen->mode.right_margin +
1614                     screen->mode.xres + screen->mode.hsync_len;
1615                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1616                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1617                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1618         }
1619
1620         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1621         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
1622         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1623         screen->ft = 1000 / fps;        /*one frame time in ms */
1624
1625         if (set)
1626                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1627                          clk_get_rate(lcdc_dev->dclk), fps);
1628
1629         return fps;
1630 }
1631
1632 static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1633 {
1634         struct lcdc_device *lcdc_dev =
1635             container_of(dev_drv, struct lcdc_device, driver);
1636         u32 int_reg;
1637         int ret;
1638
1639         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
1640                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1641                 if (int_reg & m_LF_INT_STA) {
1642                         dev_drv->frame_time.last_framedone_t =
1643                                         dev_drv->frame_time.framedone_t;
1644                         dev_drv->frame_time.framedone_t = cpu_clock(0);
1645                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1646                                      v_LF_INT_CLEAR(1));
1647                         ret = RK_LF_STATUS_FC;
1648                 } else
1649                         ret = RK_LF_STATUS_FR;
1650         } else {
1651                 ret = RK_LF_STATUS_NC;
1652         }
1653
1654         return ret;
1655 }
1656
1657 static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1658                                     unsigned int *dsp_addr)
1659 {
1660         struct lcdc_device *lcdc_dev =
1661             container_of(dev_drv, struct lcdc_device, driver);
1662
1663         if (lcdc_dev->clk_on) {
1664                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1665                 if (lcdc_dev->soc_type == VOP_RK3036)
1666                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1667                 else if (lcdc_dev->soc_type == VOP_RK312X)
1668                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1669         }
1670         return 0;
1671 }
1672
1673 static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1674                                          char *buf, int win_id)
1675 {
1676         struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device,
1677                                                     driver);
1678         char format_w0[9] = "NULL";
1679         char format_w1[9] = "NULL";
1680         char status_w0[9] = "NULL";
1681         char status_w1[9] = "NULL";
1682         u32 fmt_id, act_info, dsp_info, dsp_st, factor;
1683         u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0;
1684         u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1;
1685         u16 x_factor, y_factor, x_scale, y_scale;
1686         u16 ovl;
1687         u32 win1_dsp_yaddr = 0;
1688
1689         spin_lock(&lcdc_dev->reg_lock);
1690         if (lcdc_dev->clk_on) {
1691                 /* data format */
1692                 fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL);
1693                 get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0);
1694                 get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1);
1695
1696                 /* win status */
1697                 if (fmt_id & m_WIN0_EN)
1698                         strcpy(status_w0, "enabled");
1699                 else
1700                         strcpy(status_w0, "disabled");
1701
1702                 if ((fmt_id & m_WIN1_EN) >> 1)
1703                         strcpy(status_w1, "enabled");
1704                 else
1705                         strcpy(status_w1, "disabled");
1706
1707                 /* ovl */
1708                 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1709
1710                 /* xvir */
1711                 xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR;
1712                 xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR;
1713
1714                 /* xact/yact */
1715                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1716                 x_act_w0 = (act_info & m_ACT_WIDTH) + 1;
1717                 y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1718
1719                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
1720                 x_act_w1 = (act_info & m_ACT_WIDTH) + 1;
1721                 y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1722
1723                 /* xsize/ysize */
1724                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
1725                 x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1;
1726                 y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1727
1728                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
1729                 x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1;
1730                 y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1731
1732                 /* xpos/ypos */
1733                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
1734                 x_st_w0 = dsp_st & m_DSP_STX;
1735                 y_st_w0 = (dsp_st & m_DSP_STY) >> 16;
1736
1737                 if (lcdc_dev->soc_type == VOP_RK3036)
1738                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
1739                 else if (lcdc_dev->soc_type == VOP_RK312X)
1740                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X);
1741
1742                 x_st_w1 = dsp_st & m_DSP_STX;
1743                 y_st_w1 = (dsp_st & m_DSP_STY) >> 16;
1744
1745                 /* scale factor */
1746                 factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
1747                 x_factor = factor & m_X_SCL_FACTOR;
1748                 y_factor = (factor & m_Y_SCL_FACTOR) >> 16;
1749                 x_scale = 4096 * 100 / x_factor;
1750                 y_scale = 4096 * 100 / y_factor;
1751
1752                 /* dsp addr */
1753                 if (lcdc_dev->soc_type == VOP_RK3036)
1754                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST);
1755                 else if (lcdc_dev->soc_type == VOP_RK312X)
1756                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1757         } else {
1758                 spin_unlock(&lcdc_dev->reg_lock);
1759                 return -EPERM;
1760         }
1761         spin_unlock(&lcdc_dev->reg_lock);
1762         return snprintf(buf, PAGE_SIZE,
1763                         "win0:%s\n"
1764                         "xvir:%d\n"
1765                         "xact:%d\n"
1766                         "yact:%d\n"
1767                         "xdsp:%d\n"
1768                         "ydsp:%d\n"
1769                         "x_st:%d\n"
1770                         "y_st:%d\n"
1771                         "x_scale:%d.%d\n"
1772                         "y_scale:%d.%d\n"
1773                         "format:%s\n"
1774                         "YRGB buffer addr:0x%08x\n"
1775                         "CBR buffer addr:0x%08x\n\n"
1776                         "win1:%s\n"
1777                         "xvir:%d\n"
1778                         "xact:%d\n"
1779                         "yact:%d\n"
1780                         "xdsp:%d\n"
1781                         "ydsp:%d\n"
1782                         "x_st:%d\n"
1783                         "y_st:%d\n"
1784                         "format:%s\n"
1785                         "YRGB buffer addr:0x%08x\n"
1786                         "overlay:%s\n",
1787                         status_w0,
1788                         xvir_w0,
1789                         x_act_w0,
1790                         y_act_w0,
1791                         x_dsp_w0,
1792                         y_dsp_w0,
1793                         x_st_w0,
1794                         y_st_w0,
1795                         x_scale / 100,
1796                         x_scale % 100,
1797                         y_scale / 100,
1798                         y_scale % 100,
1799                         format_w0,
1800                         lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
1801                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
1802                         status_w1,
1803                         xvir_w1,
1804                         x_act_w1,
1805                         y_act_w1,
1806                         x_dsp_w1,
1807                         y_dsp_w1,
1808                         x_st_w1,
1809                         y_st_w1,
1810                         format_w1,
1811                         win1_dsp_yaddr,
1812                         ovl ? "win0 on the top of win1\n" :
1813                         "win1 on the top of win0\n");
1814 }
1815
1816 static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1817 {
1818         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1819                                                     struct lcdc_device,
1820                                                     driver);
1821         int *cbase = (int *)lcdc_dev->regs;
1822         int *regsbak = (int *)lcdc_dev->regsbak;
1823         int i, j;
1824
1825         printk("back up reg:\n");
1826         for (i = 0; i <= (0xDC >> 4); i++) {
1827                 for (j = 0; j < 4; j++)
1828                         printk("%08x  ", *(regsbak + i * 4 + j));
1829                 printk("\n");
1830         }
1831
1832         printk("lcdc reg:\n");
1833         for (i = 0; i <= (0xDC >> 4); i++) {
1834                 for (j = 0; j < 4; j++)
1835                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
1836                 printk("\n");
1837         }
1838         return 0;
1839 }
1840
1841 static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
1842 {
1843         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1844                                                     struct lcdc_device, driver);
1845         if (lcdc_dev->soc_type == VOP_RK312X) {
1846                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
1847                              v_DIRECT_PATH_EN(open));
1848                 lcdc_cfg_done(lcdc_dev);
1849         }
1850         return 0;
1851 }
1852
1853 static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
1854 {
1855         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1856                                                     struct lcdc_device, driver);
1857
1858         if (lcdc_dev->soc_type == VOP_RK312X) {
1859                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER,
1860                              v_DIRECT_PATH_LAYER(win_id));
1861                 lcdc_cfg_done(lcdc_dev);
1862         }
1863         return 0;
1864
1865 }
1866
1867 static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
1868 {
1869         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1870                                                     struct lcdc_device, driver);
1871         int ovl = 0;
1872
1873         if (lcdc_dev->soc_type == VOP_RK312X)
1874                 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
1875
1876         return ovl;
1877 }
1878
1879 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1880         .open = rk312x_lcdc_open,
1881         .load_screen = rk312x_load_screen,
1882         .set_par = rk312x_lcdc_set_par,
1883         .pan_display = rk312x_lcdc_pan_display,
1884         .blank = rk312x_lcdc_blank,
1885         .ioctl = rk312x_lcdc_ioctl,
1886         .get_win_state = rk312x_lcdc_get_win_state,
1887         .ovl_mgr = rk312x_lcdc_ovl_mgr,
1888         .get_disp_info = rk312x_lcdc_get_disp_info,
1889         .fps_mgr = rk312x_lcdc_fps_mgr,
1890         .fb_get_win_id = rk312x_lcdc_get_win_id,
1891         .fb_win_remap = rk312x_fb_win_remap,
1892         .poll_vblank = rk312x_lcdc_poll_vblank,
1893         .get_dsp_addr = rk312x_lcdc_get_dsp_addr,
1894         .cfg_done = rk312x_lcdc_cfg_done,
1895         .dump_reg = rk312x_lcdc_reg_dump,
1896         .dpi_open = rk312x_lcdc_dpi_open,
1897         .dpi_win_sel = rk312x_lcdc_dpi_win_sel,
1898         .dpi_status = rk312x_lcdc_dpi_status,
1899         .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue,
1900         .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs,
1901         .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue,
1902         .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs,
1903         .open_bcsh = rk312x_lcdc_open_bcsh,
1904         .set_screen_scaler = rk312x_lcdc_set_scaler,
1905 };
1906 #if 0
1907 static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = {
1908         .soc_type = VOP_RK3036,
1909 };
1910 #endif
1911 static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = {
1912         .soc_type = VOP_RK312X,
1913 };
1914
1915 #if defined(CONFIG_OF)
1916 static const struct of_device_id rk312x_lcdc_dt_ids[] = {
1917 #if 0
1918         {
1919                 .compatible = "rockchip,rk3036-lcdc",
1920                 .data = (void *)&rk3036_lcdc_drvdata,
1921         },
1922 #endif
1923         {
1924                 .compatible = "rockchip,rk312x-lcdc",
1925                 .data = (void *)&rk312x_lcdc_drvdata,
1926         },
1927 };
1928 #endif
1929
1930 static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1931 {
1932         struct device_node *np = lcdc_dev->dev->of_node;
1933         const struct of_device_id *match;
1934         const struct rk_lcdc_drvdata *lcdc_drvdata;
1935
1936 #if defined(CONFIG_ROCKCHIP_IOMMU)
1937         int val;
1938         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1939                 lcdc_dev->driver.iommu_enabled = 0;
1940         else
1941                 lcdc_dev->driver.iommu_enabled = val;
1942 #else
1943         lcdc_dev->driver.iommu_enabled = 0;
1944 #endif
1945         match = of_match_node(rk312x_lcdc_dt_ids, np);
1946         if (match) {
1947                 lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data;
1948                 lcdc_dev->soc_type = lcdc_drvdata->soc_type;
1949         } else {
1950                 return PTR_ERR(match);
1951         }
1952
1953         return 0;
1954 }
1955
1956 static int rk312x_lcdc_probe(struct platform_device *pdev)
1957 {
1958         struct lcdc_device *lcdc_dev = NULL;
1959         struct rk_lcdc_driver *dev_drv;
1960         struct device *dev = &pdev->dev;
1961         struct resource *res;
1962         int ret;
1963
1964         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
1965         if (!lcdc_dev) {
1966                 dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n");
1967                 return -ENOMEM;
1968         }
1969         platform_set_drvdata(pdev, lcdc_dev);
1970         lcdc_dev->dev = dev;
1971         if (rk312x_lcdc_parse_dt(lcdc_dev)) {
1972                 dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n");
1973                 goto err_parse_dt;
1974         }
1975
1976         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1977         lcdc_dev->reg_phy_base = res->start;
1978         lcdc_dev->len = resource_size(res);
1979         lcdc_dev->regs = devm_ioremap_resource(dev, res);
1980         if (IS_ERR(lcdc_dev->regs)) {
1981                 ret = PTR_ERR(lcdc_dev->regs);
1982                 goto err_remap_reg;
1983         }
1984
1985         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1986         if (IS_ERR(lcdc_dev->regsbak)) {
1987                 dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n");
1988                 ret = PTR_ERR(lcdc_dev->regsbak);
1989                 goto err_remap_reg;
1990         }
1991
1992         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1993         dev_drv = &lcdc_dev->driver;
1994         dev_drv->dev = dev;
1995         dev_drv->prop = PRMRY;
1996         dev_drv->id = lcdc_dev->id;
1997         dev_drv->ops = &lcdc_drv_ops;
1998         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1999         spin_lock_init(&lcdc_dev->reg_lock);
2000
2001         lcdc_dev->irq = platform_get_irq(pdev, 0);
2002         if (lcdc_dev->irq < 0) {
2003                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
2004                         lcdc_dev->id);
2005                 ret = -ENXIO;
2006                 goto err_request_irq;
2007         }
2008
2009         ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr,
2010                                IRQF_DISABLED, dev_name(dev), lcdc_dev);
2011         if (ret) {
2012                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
2013                         lcdc_dev->irq, ret);
2014                 goto err_request_irq;
2015         }
2016
2017         if (dev_drv->iommu_enabled)
2018                 strcpy(dev_drv->mmu_dts_name, "iommu,vop_mmu");
2019
2020         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
2021         if (ret < 0) {
2022                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
2023                 goto err_register_fb;
2024         }
2025         lcdc_dev->screen = dev_drv->screen0;
2026
2027         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
2028                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
2029         return 0;
2030
2031 err_register_fb:
2032 err_request_irq:
2033         devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak);
2034 err_remap_reg:
2035 err_parse_dt:
2036         devm_kfree(&pdev->dev, lcdc_dev);
2037         return ret;
2038 }
2039
2040 #if defined(CONFIG_PM)
2041 static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
2042 {
2043         return 0;
2044 }
2045
2046 static int rk312x_lcdc_resume(struct platform_device *pdev)
2047 {
2048         return 0;
2049 }
2050 #else
2051 #define rk312x_lcdc_suspend NULL
2052 #define rk312x_lcdc_resume  NULL
2053 #endif
2054
2055 static int rk312x_lcdc_remove(struct platform_device *pdev)
2056 {
2057         return 0;
2058 }
2059
2060 static void rk312x_lcdc_shutdown(struct platform_device *pdev)
2061 {
2062         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
2063
2064         rk312x_lcdc_deinit(lcdc_dev);
2065         rk312x_lcdc_clk_disable(lcdc_dev);
2066         rk_disp_pwr_disable(&lcdc_dev->driver);
2067 }
2068
2069 static struct platform_driver rk312x_lcdc_driver = {
2070         .probe = rk312x_lcdc_probe,
2071         .remove = rk312x_lcdc_remove,
2072         .driver = {
2073                    .name = "rk312x-lcdc",
2074                    .owner = THIS_MODULE,
2075                    .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids),
2076                    },
2077         .suspend = rk312x_lcdc_suspend,
2078         .resume = rk312x_lcdc_resume,
2079         .shutdown = rk312x_lcdc_shutdown,
2080 };
2081
2082 static int __init rk312x_lcdc_module_init(void)
2083 {
2084         return platform_driver_register(&rk312x_lcdc_driver);
2085 }
2086
2087 static void __exit rk312x_lcdc_module_exit(void)
2088 {
2089         platform_driver_unregister(&rk312x_lcdc_driver);
2090 }
2091
2092 fs_initcall(rk312x_lcdc_module_init);
2093 module_exit(rk312x_lcdc_module_exit);