drivers/video/rockchip/lcdc/rk312x_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk312x_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:      zhuangwenlong<zwl@rock-chips.com>
   6  *              zhengyang<zhengyang@rock-chips.com>
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/slab.h>
  24 #include <linux/device.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/clk.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37 #if defined(CONFIG_ION_ROCKCHIP)
  38 #include <linux/rockchip/iovmm.h>
  39 #include <linux/rockchip/sysmmu.h>
  40 #endif
  41 #include "rk312x_lcdc.h"
  42
  43 static int dbg_thresd;
  44 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  45
  46 #define DBG(level, x...) do {                   \
  47         if (unlikely(dbg_thresd >= level))      \
  48                 printk(KERN_INFO x); } while (0)
  49
  50 static struct rk_lcdc_win lcdc_win[] = {
  51         [0] = {
  52                .name = "win0",
  53                .id = 0,
  54                .support_3d = false,
  55                },
  56         [1] = {
  57                .name = "win1",
  58                .id = 1,
  59                .support_3d = false,
  60                },
  61         [2] = {
  62                .name = "hwc",
  63                .id = 2,
  64                .support_3d = false,
  65                },
  66 };
  67
  68 static irqreturn_t rk312x_lcdc_isr(int irq, void *dev_id)
  69 {
  70         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
  71         ktime_t timestamp = ktime_get();
  72         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  73
  74         if (int_reg & m_FS_INT_STA) {
  75                 timestamp = ktime_get();
  76                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  77                              v_FS_INT_CLEAR(1));
  78                 //if (lcdc_dev->driver.wait_fs) {
  79                 if (0) {
  80                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  81                         complete(&(lcdc_dev->driver.frame_done));
  82                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  83                 }
  84                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  85                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  86
  87         } else if (int_reg & m_LF_INT_STA) {
  88                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  89                              v_LF_INT_CLEAR(1));
  90         }
  91         return IRQ_HANDLED;
  92 }
  93
  94 static int rk312x_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
  95 {
  96 #ifdef CONFIG_RK_FPGA
  97         lcdc_dev->clk_on = 1;
  98         return 0;
  99 #endif
 100         if (!lcdc_dev->clk_on) {
 101                 clk_prepare_enable(lcdc_dev->hclk);
 102                 clk_prepare_enable(lcdc_dev->dclk);
 103                 clk_prepare_enable(lcdc_dev->aclk);
 104 //              clk_prepare_enable(lcdc_dev->pd);
 105                 spin_lock(&lcdc_dev->reg_lock);
 106                 lcdc_dev->clk_on = 1;
 107                 spin_unlock(&lcdc_dev->reg_lock);
 108         }
 109
 110         return 0;
 111 }
 112
 113 static int rk312x_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 114 {
 115 #ifdef CONFIG_RK_FPGA
 116         lcdc_dev->clk_on = 0;
 117         return 0;
 118 #endif
 119         if (lcdc_dev->clk_on) {
 120                 spin_lock(&lcdc_dev->reg_lock);
 121                 lcdc_dev->clk_on = 0;
 122                 spin_unlock(&lcdc_dev->reg_lock);
 123                 mdelay(25);
 124                 clk_disable_unprepare(lcdc_dev->dclk);
 125                 clk_disable_unprepare(lcdc_dev->hclk);
 126                 clk_disable_unprepare(lcdc_dev->aclk);
 127 //              clk_disable_unprepare(lcdc_dev->pd);
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int rk312x_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 134 {
 135         u32 mask, val;
 136         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 137                                                     struct lcdc_device, driver);
 138         struct rk_screen *screen = dev_drv->cur_screen;
 139
 140         spin_lock(&lcdc_dev->reg_lock);
 141         if (likely(lcdc_dev->clk_on)) {
 142                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 143                         m_LF_INT_CLEAR | m_LF_INT_EN | m_LF_INT_NUM |
 144                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 145                 val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1) |
 146                         v_LF_INT_CLEAR(1) | v_LF_INT_EN(1) |
 147                         v_BUS_ERR_INT_CLEAR(1) | v_BUS_ERR_INT_EN(0) |
 148                         v_LF_INT_NUM(screen->mode.vsync_len +
 149                                      screen->mode.upper_margin +
 150                                      screen->mode.yres);
 151                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 152                 spin_unlock(&lcdc_dev->reg_lock);
 153         } else {
 154                 spin_unlock(&lcdc_dev->reg_lock);
 155         }
 156         return 0;
 157 }
 158
 159 static int rk312x_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 160 {
 161         u32 mask, val;
 162
 163         spin_lock(&lcdc_dev->reg_lock);
 164         if (likely(lcdc_dev->clk_on)) {
 165                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 166                         m_LF_INT_CLEAR | m_LF_INT_EN |
 167                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 168                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 169                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 170                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 171                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 172                 spin_unlock(&lcdc_dev->reg_lock);
 173         } else {
 174                 spin_unlock(&lcdc_dev->reg_lock);
 175         }
 176         mdelay(1);
 177         return 0;
 178 }
 179
 180 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 181 {
 182         int reg = 0;
 183         u32 value = 0;
 184
 185         spin_lock(&lcdc_dev->reg_lock);
 186         for (reg = 0; reg < 0xdc; reg += 4) {
 187                 value = lcdc_readl(lcdc_dev, reg);
 188         }
 189         spin_unlock(&lcdc_dev->reg_lock);
 190 }
 191
 192 static int rk312x_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 193 {
 194         int win0_top = 0;
 195         u32 mask, val;
 196         enum data_format win0_format = lcdc_dev->driver.win[0]->format;
 197         enum data_format win1_format = lcdc_dev->driver.win[1]->format;
 198
 199         int win0_alpha_en = ((win0_format == ARGB888)
 200                              || (win0_format == ABGR888)) ? 1 : 0;
 201         int win1_alpha_en = ((win1_format == ARGB888)
 202                              || (win1_format == ABGR888)) ? 1 : 0;
 203         u32 *_pv = (u32 *) lcdc_dev->regsbak;
 204
 205         _pv += (DSP_CTRL0 >> 2);
 206         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 207         if (win0_top && (lcdc_dev->atv_layer_cnt >= 2) && (win0_alpha_en)) {
 208                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 209                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0);
 210                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 211
 212                 mask = m_WIN0_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 213                 val = v_WIN0_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 214                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 215         } else if ((!win0_top) && (lcdc_dev->atv_layer_cnt >= 2)
 216                    && (win1_alpha_en)) {
 217                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 218                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1);
 219                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 220
 221                 mask = m_WIN1_ALPHA_MODE | m_ALPHA_MODE_SEL0 | m_ALPHA_MODE_SEL1;
 222                 val = v_WIN1_ALPHA_MODE(1) | v_ALPHA_MODE_SEL0(1) | v_ALPHA_MODE_SEL1(0);
 223                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 224         } else {
 225                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 226                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 227                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 228         }
 229
 230         return 0;
 231 }
 232
 233 static void lcdc_layer_csc_mode(struct lcdc_device *lcdc_dev,
 234                                       struct rk_lcdc_win *win)
 235 {
 236         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 237
 238         if (lcdc_dev->overlay_mode == VOP_YUV_DOMAIN) {
 239                 switch (win->fmt_cfg) {
 240                 case VOP_FORMAT_ARGB888:
 241                 case VOP_FORMAT_RGB888:
 242                 case VOP_FORMAT_RGB565:
 243                         if ((screen->mode.xres < 1280 ) &&
 244                             (screen->mode.yres < 720)) {
 245                                 win->csc_mode = VOP_R2Y_CSC_BT601;
 246                         } else {
 247                                 win->csc_mode = VOP_R2Y_CSC_BT709;
 248                         }
 249                         break;
 250                 default:
 251                         break;
 252                 }
 253                 if (win->id  == 0) {
 254                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 255                                      v_WIN0_CSC_MODE(win->csc_mode));
 256                 } else if (win->id  == 1) {
 257                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN1_CSC_MODE,
 258                                      v_WIN1_CSC_MODE(win->csc_mode));
 259                 }
 260         } else if (lcdc_dev->overlay_mode == VOP_RGB_DOMAIN) {
 261                 switch (win->fmt_cfg) {
 262                 case VOP_FORMAT_YCBCR420:
 263                         if (win->id  == 0) {
 264                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
 265                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_CSC_MODE,
 266                                              v_WIN0_CSC_MODE(win->csc_mode));
 267                         }
 268                         break;
 269                 default:
 270                         break;
 271                 }
 272         }
 273
 274 }
 275
 276
 277 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 278                                    struct rk_lcdc_win *win)
 279 {
 280         u32 mask, val;
 281
 282         if (win->state == 1) {
 283                 if (lcdc_dev->soc_type == VOP_RK312X)
 284                         lcdc_layer_csc_mode(lcdc_dev,win);
 285
 286                 if (win->id == 0) {
 287                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 288                         val = v_WIN0_EN(win->state) |
 289                                 v_WIN0_FORMAT(win->fmt_cfg) |
 290                                 v_WIN0_RB_SWAP(win->swap_rb);
 291                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 292
 293                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 294                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 295                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 296                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 297                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 298                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 299
 300                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 301                                      m_YRGB_VIR | m_CBBR_VIR,
 302                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 303                                      v_CBCR_VIR(win->area[0].uv_vir_stride));
 304                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 305                                     v_ACT_WIDTH(win->area[0].xact) |
 306                                     v_ACT_HEIGHT(win->area[0].yact));
 307                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 308                                     v_DSP_STX(win->area[0].dsp_stx) |
 309                                     v_DSP_STY(win->area[0].dsp_sty));
 310                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 311                                     v_DSP_WIDTH(win->area[0].xsize) |
 312                                     v_DSP_HEIGHT(win->area[0].ysize));
 313
 314                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 315                                     win->area[0].y_addr);
 316                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 317                                     win->area[0].uv_addr);
 318                 } else if (win->id == 1) {
 319                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 320                         val = v_WIN1_EN(win->state) |
 321                                 v_WIN1_FORMAT(win->fmt_cfg) |
 322                                 v_WIN1_RB_SWAP(win->swap_rb);
 323                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 324
 325                         /* rk312x unsupport win1 scale */
 326                         if (lcdc_dev->soc_type == VOP_RK3036)
 327                                 lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 328                                         v_X_SCL_FACTOR(win->scale_yrgb_x) |
 329                                         v_Y_SCL_FACTOR(win->scale_yrgb_y));
 330
 331                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 332                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 333                         lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 334                                     v_ACT_WIDTH(win->area[0].xact) |
 335                                     v_ACT_HEIGHT(win->area[0].yact));
 336                         lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 337                                     v_DSP_WIDTH(win->area[0].xsize) |
 338                                     v_DSP_HEIGHT(win->area[0].ysize));
 339                         lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 340                                     v_DSP_STX(win->area[0].dsp_stx) |
 341                                     v_DSP_STY(win->area[0].dsp_sty));
 342
 343                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 344
 345                 } else if (win->id == 2) {
 346                 }
 347         } else {
 348                 win->area[0].y_addr = 0;
 349                 win->area[0].uv_addr = 0;
 350                 if (win->id == 0)
 351                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN0_EN,
 352                                      v_WIN0_EN(0));
 353                 else if (win->id == 1)
 354                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_WIN1_EN,
 355                                      v_WIN1_EN(0));
 356                 else if (win->id == 2)
 357                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_EN, v_HWC_EN(0));
 358         }
 359 }
 360
 361 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev, unsigned int win_id,
 362                               bool open)
 363 {
 364         spin_lock(&lcdc_dev->reg_lock);
 365         if (likely(lcdc_dev->clk_on)
 366             && lcdc_dev->driver.win[win_id]->state != open) {
 367                 if (open) {
 368                         if (!lcdc_dev->atv_layer_cnt) {
 369                                 dev_info(lcdc_dev->dev,
 370                                          "wakeup from standby!\n");
 371                                 lcdc_dev->standby = 0;
 372                         }
 373                         lcdc_dev->atv_layer_cnt++;
 374                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
 375                         lcdc_dev->atv_layer_cnt--;
 376                 }
 377                 lcdc_dev->driver.win[win_id]->state = open;
 378                 if (!open) {
 379                         lcdc_layer_update_regs(lcdc_dev,
 380                                                lcdc_dev->driver.win[win_id]);
 381                         lcdc_cfg_done(lcdc_dev);
 382                 }
 383                 /*if no layer used,disable lcdc */
 384                 if (!lcdc_dev->atv_layer_cnt) {
 385                         dev_info(lcdc_dev->dev,
 386                                  "no layer is used,go to standby!\n");
 387                         lcdc_dev->standby = 1;
 388                 }
 389         }
 390         spin_unlock(&lcdc_dev->reg_lock);
 391 }
 392
 393 static int rk312x_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 394 {
 395         struct lcdc_device *lcdc_dev =
 396             container_of(dev_drv, struct lcdc_device, driver);
 397         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 398         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 399         int timeout;
 400         unsigned long flags;
 401         spin_lock(&lcdc_dev->reg_lock);
 402         if (likely(lcdc_dev->clk_on)) {
 403                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 404                              v_LCDC_STANDBY(lcdc_dev->standby));
 405                 lcdc_layer_update_regs(lcdc_dev, win0);
 406                 lcdc_layer_update_regs(lcdc_dev, win1);
 407                 rk312x_lcdc_alpha_cfg(lcdc_dev);
 408                 lcdc_cfg_done(lcdc_dev);
 409
 410         }
 411         spin_unlock(&lcdc_dev->reg_lock);
 412         //if (dev_drv->wait_fs) {
 413         if (0) {
 414                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 415                 init_completion(&dev_drv->frame_done);
 416                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 417                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 418                                                       msecs_to_jiffies
 419                                                       (dev_drv->cur_screen->ft +
 420                                                        5));
 421                 if (!timeout && (!dev_drv->frame_done.done)) {
 422                         dev_warn(lcdc_dev->dev,
 423                                  "wait for new frame start time out!\n");
 424                         return -ETIMEDOUT;
 425                 }
 426         }
 427         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 428         return 0;
 429
 430 }
 431
 432 static void rk312x_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 433 {
 434         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0xdc);
 435 }
 436
 437 static void rk312x_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 438 {
 439         u32 mask, val;
 440         struct lcdc_device *lcdc_dev =
 441             container_of(dev_drv, struct lcdc_device, driver);
 442
 443         spin_lock(&lcdc_dev->reg_lock);
 444         if (likely(lcdc_dev->clk_on)) {
 445                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 446                         m_AXI_OUTSTANDING_MAX_NUM;
 447                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 448                         v_AXI_MAX_OUTSTANDING_EN(1);
 449                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 450         }
 451         spin_unlock(&lcdc_dev->reg_lock);
 452 }
 453
 454 static int rk312x_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
 455 {
 456         int i = 0;
 457         int __iomem *c;
 458         int v;
 459         struct lcdc_device *lcdc_dev =
 460                 container_of(dev_drv, struct lcdc_device, driver);
 461
 462         spin_lock(&lcdc_dev->reg_lock);
 463         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 464         lcdc_cfg_done(lcdc_dev);
 465         mdelay(25);
 466         for (i = 0; i < 256; i++) {
 467                 v = dev_drv->cur_screen->dsp_lut[i];
 468                 c = lcdc_dev->dsp_lut_addr_base + i;
 469                 writel_relaxed(v, c);
 470
 471         }
 472         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 473         lcdc_cfg_done(lcdc_dev);
 474         spin_unlock(&lcdc_dev->reg_lock);
 475         return 0;
 476
 477 }
 478
 479 static int rk312x_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 480 {
 481 #ifdef CONFIG_RK_FPGA
 482         return 0;
 483 #endif
 484         int ret, fps;
 485         struct lcdc_device *lcdc_dev =
 486             container_of(dev_drv, struct lcdc_device, driver);
 487         struct rk_screen *screen = dev_drv->cur_screen;
 488
 489         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 490         if (ret)
 491                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
 492         lcdc_dev->pixclock =
 493             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 494         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 495
 496         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 497         screen->ft = 1000 / fps;
 498         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 499                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 500         return 0;
 501
 502 }
 503
 504 /********do basic init*********/
 505 static int rk312x_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 506 {
 507         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 508                                                     struct lcdc_device, driver);
 509         if (lcdc_dev->pre_init)
 510                 return 0;
 511
 512         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 513         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 514         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 515 //      lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 516
 517         if ( /*IS_ERR(lcdc_dev->pd) || */ (IS_ERR(lcdc_dev->aclk)) ||
 518             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 519                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 520                         lcdc_dev->id);
 521         }
 522
 523         rk_disp_pwr_enable(dev_drv);
 524         rk312x_lcdc_clk_enable(lcdc_dev);
 525
 526         /* backup reg config at uboot */
 527         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 528         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN, v_AUTO_GATING_EN(0));
 529         lcdc_cfg_done(lcdc_dev);
 530         if (dev_drv->iommu_enabled)     /* disable win0 to workaround iommu pagefault */
 531                 lcdc_layer_enable(lcdc_dev, 0, 0);
 532         lcdc_dev->pre_init = true;
 533
 534         return 0;
 535 }
 536
 537 static void rk312x_lcdc_deinit(struct lcdc_device *lcdc_dev)
 538 {
 539         u32 mask, val;
 540
 541         spin_lock(&lcdc_dev->reg_lock);
 542         if (likely(lcdc_dev->clk_on)) {
 543                 mask = m_FS_INT_CLEAR | m_FS_INT_EN |
 544                         m_LF_INT_CLEAR | m_LF_INT_EN |
 545                         m_BUS_ERR_INT_CLEAR | m_BUS_ERR_INT_EN;
 546                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0) |
 547                         v_LF_INT_CLEAR(0) | v_LF_INT_EN(0) |
 548                         v_BUS_ERR_INT_CLEAR(0) | v_BUS_ERR_INT_EN(0);
 549                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 550                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY);
 551                 lcdc_cfg_done(lcdc_dev);
 552                 spin_unlock(&lcdc_dev->reg_lock);
 553         } else {
 554                 spin_unlock(&lcdc_dev->reg_lock);
 555         }
 556         mdelay(1);
 557
 558 }
 559
 560 static u32 calc_sclk(struct rk_screen *src_screen, struct rk_screen *dst_screen)
 561 {
 562         u32 dsp_vtotal;
 563         u64 dsp_htotal;
 564         u32 dsp_in_vtotal;
 565         u64 dsp_in_htotal;
 566         u32 sclk;
 567
 568         if (!src_screen || !dst_screen)
 569                 return 0;
 570
 571         dsp_vtotal = dst_screen->mode.yres;
 572         dsp_htotal = dst_screen->mode.left_margin + dst_screen->mode.hsync_len +
 573                      dst_screen->mode.xres + dst_screen->mode.right_margin;
 574         dsp_in_vtotal = src_screen->mode.yres;
 575         dsp_in_htotal = src_screen->mode.left_margin +
 576                         src_screen->mode.hsync_len +
 577                         src_screen->mode.xres + src_screen->mode.right_margin;
 578         sclk = dsp_vtotal * dsp_htotal * src_screen->mode.pixclock;
 579         do_div(sclk, dsp_in_vtotal * dsp_in_htotal);
 580
 581         return sclk;
 582 }
 583
 584 static int calc_dsp_frm_vst_hst(struct rk_screen *src, struct rk_screen *dst)
 585 {
 586         u32 BP_in, BP_out;
 587         u32 v_scale_ratio;
 588 #if defined(FLOAT_CALC) /* use float */
 589         double T_frm_st;
 590         double T_BP_in, T_BP_out, T_Delta, Tin;
 591 #else
 592         long long  T_frm_st;
 593         u64 T_BP_in, T_BP_out, T_Delta, Tin;
 594         u64 rate = (1 << 16);
 595         u64 temp;
 596 #endif
 597         u32 dsp_htotal, src_htotal, src_vtotal;
 598
 599         if (unlikely(!src) || unlikely(!dst))
 600                 return -1;
 601
 602         dsp_htotal = dst->mode.left_margin + dst->mode.hsync_len +
 603                      dst->mode.xres + dst->mode.right_margin;
 604         src_htotal = src->mode.left_margin + src->mode.hsync_len +
 605                      src->mode.xres + src->mode.right_margin;
 606         src_vtotal = src->mode.upper_margin + src->mode.vsync_len +
 607                      src->mode.yres + src->mode.lower_margin;
 608         BP_in  = (src->mode.upper_margin + src->mode.vsync_len) * src_htotal;
 609         BP_out = (dst->mode.upper_margin + dst->mode.vsync_len) * dsp_htotal;
 610
 611         v_scale_ratio = dst->mode.yres / src->mode.yres;
 612
 613 #if defined(FLOAT_CALC)
 614         T_BP_in = 1.0 * BP_in / src->mode.pixclock;
 615         T_BP_out = 1.0 * BP_out / dst->mode.pixclock;
 616         if (v_scale_ratio < 2)
 617                 T_Delta = 4.0 * src_htotal / src->mode.pixclock;
 618         else
 619                 T_Delta = 12.0 * src_htotal / src->mode.pixclock;
 620
 621         Tin = 1.0 * src_vtotal * src_htotal / src->mode.pixclock;
 622 #else
 623         T_BP_in = rate * BP_in;
 624         do_div(T_BP_in, src->mode.pixclock);
 625         T_BP_out = rate * BP_out;
 626         do_div(T_BP_out, dst->mode.pixclock);
 627         if (v_scale_ratio < 2)
 628                 T_Delta = rate * 4 * src_htotal;
 629         else
 630                 T_Delta = rate * 12 * src_htotal;
 631
 632         do_div(T_Delta, src->mode.pixclock);
 633         Tin = rate * src_vtotal * src_htotal;
 634         do_div(Tin, src->mode.pixclock);
 635 #endif
 636
 637         T_frm_st = (T_BP_in + T_Delta - T_BP_out);
 638         if (T_frm_st < 0)
 639                 T_frm_st  += Tin;
 640
 641 #if defined(FLOAT_CALC)
 642         dst->scl_vst = (u16)(T_frm_st * src->mode.pixclock / src_htotal);
 643         dst->scl_hst = (u32)(T_frm_st * src->mode.pixclock) % src_htotal;
 644 #else
 645         temp = T_frm_st * src->mode.pixclock;
 646         dst->scl_hst = do_div(temp, src_htotal * rate);
 647         dst->scl_vst = temp;
 648 #endif
 649
 650         return 0;
 651 }
 652
 653 static int rk312x_lcdc_set_scaler(struct rk_lcdc_driver *dev_drv,
 654                                   struct rk_screen *dst_screen, bool enable)
 655 {
 656         u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
 657         u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
 658         u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
 659         u32 scl_v_factor, scl_h_factor;
 660         u32 dst_frame_hst, dst_frame_vst;
 661         u32 src_w, src_h, dst_w, dst_h;
 662         u16 bor_right = 0;
 663         u16 bor_left = 0;
 664         u16 bor_up = 0;
 665         u16 bor_down = 0;
 666         struct rk_screen *src;
 667         struct rk_screen *dst;
 668         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 669                                                     struct lcdc_device, driver);
 670
 671         if (unlikely(!lcdc_dev->clk_on))
 672                 return 0;
 673
 674         if(!enable) {
 675                 dev_info(lcdc_dev->dev, "%s: disable\n", __func__);
 676                 return 0;
 677         }
 678
 679         /* rk312x used one lcdc to apply dual disp
 680          * hdmi screen is used for scaler src
 681          * prmry screen is used for scaler dst
 682          */
 683         dst = dst_screen;
 684         if (!dst) {
 685                 dev_err(lcdc_dev->dev, "%s: dst screen is null!\n", __func__);
 686                 return -EINVAL;
 687         }
 688
 689         src = dst_screen->ext_screen;
 690
 691         lcdc_dev->s_pixclock = calc_sclk(src, dst);
 692         clk_set_rate(lcdc_dev->sclk, lcdc_dev->s_pixclock);
 693
 694         /* config scale timing */
 695         calc_dsp_frm_vst_hst(src, dst);
 696         dst_frame_vst = dst->scl_vst;
 697         dst_frame_hst = dst->scl_hst;
 698
 699         dsp_htotal    = dst->mode.hsync_len + dst->mode.left_margin +
 700                         dst->mode.xres + dst->mode.right_margin;
 701         dsp_hs_end    = dst->mode.hsync_len;
 702
 703         dsp_vtotal    = dst->mode.vsync_len + dst->mode.upper_margin +
 704                         dst->mode.yres + dst->mode.lower_margin;
 705         dsp_vs_end    = dst->mode.vsync_len;
 706
 707         dsp_hbor_end  = dst->mode.hsync_len + dst->mode.left_margin +
 708                         dst->mode.xres;
 709         dsp_hbor_st   = dst->mode.hsync_len + dst->mode.left_margin;
 710         dsp_vbor_end  = dst->mode.vsync_len + dst->mode.upper_margin +
 711                         dst->mode.yres;
 712         dsp_vbor_st   = dst->mode.vsync_len + dst->mode.upper_margin;
 713
 714         dsp_hact_st   = dsp_hbor_st  + bor_left;
 715         dsp_hact_end  = dsp_hbor_end - bor_right;
 716         dsp_vact_st   = dsp_vbor_st  + bor_up;
 717         dsp_vact_end  = dsp_vbor_end - bor_down;
 718
 719         src_w = src->mode.xres;
 720         src_h = src->mode.yres;
 721         dst_w = dsp_hact_end - dsp_hact_st;
 722         dst_h = dsp_vact_end - dsp_vact_st;
 723
 724         /* calc scale factor */
 725         scl_h_factor = ((src_w - 1) << 12) / (dst_w - 1);
 726         scl_v_factor = ((src_h - 1) << 12) / (dst_h - 1);
 727
 728         spin_lock(&lcdc_dev->reg_lock);
 729         lcdc_writel(lcdc_dev, SCALER_FACTOR,
 730                     v_SCALER_H_FACTOR(scl_h_factor) |
 731                     v_SCALER_V_FACTOR(scl_v_factor));
 732
 733         lcdc_writel(lcdc_dev, SCALER_FRAME_ST,
 734                     v_SCALER_FRAME_HST(dst_frame_hst) |
 735                     v_SCALER_FRAME_VST(dst_frame_hst));
 736         lcdc_writel(lcdc_dev, SCALER_DSP_HOR_TIMING,
 737                     v_SCALER_HS_END(dsp_hs_end) |
 738                     v_SCALER_HTOTAL(dsp_htotal));
 739         lcdc_writel(lcdc_dev, SCALER_DSP_HACT_ST_END,
 740                     v_SCALER_HAEP(dsp_hact_end) |
 741                     v_SCALER_HASP(dsp_hact_st));
 742         lcdc_writel(lcdc_dev, SCALER_DSP_VER_TIMING,
 743                     v_SCALER_VS_END(dsp_vs_end) |
 744                     v_SCALER_VTOTAL(dsp_vtotal));
 745         lcdc_writel(lcdc_dev, SCALER_DSP_VACT_ST_END,
 746                     v_SCALER_VAEP(dsp_vact_end) |
 747                     v_SCALER_VASP(dsp_vact_st));
 748         lcdc_writel(lcdc_dev, SCALER_DSP_HBOR_TIMING,
 749                     v_SCALER_HBOR_END(dsp_hbor_end) |
 750                     v_SCALER_HBOR_ST(dsp_hbor_st));
 751         lcdc_writel(lcdc_dev, SCALER_DSP_VBOR_TIMING,
 752                     v_SCALER_VBOR_END(dsp_vbor_end) |
 753                     v_SCALER_VBOR_ST(dsp_vbor_st));
 754         lcdc_msk_reg(lcdc_dev, SCALER_CTRL,
 755                     m_SCALER_EN | m_SCALER_OUT_ZERO | m_SCALER_OUT_EN,
 756                     v_SCALER_EN(1) | v_SCALER_OUT_ZERO(0) | v_SCALER_OUT_EN(1));
 757         spin_unlock(&lcdc_dev->reg_lock);
 758
 759         return 0;
 760 }
 761
 762 static int rk312x_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 763 {
 764         u16 face = 0;
 765         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 766                                                     struct lcdc_device, driver);
 767         struct rk_screen *screen = dev_drv->cur_screen;
 768         u16 right_margin = screen->mode.right_margin;
 769         u16 left_margin = screen->mode.left_margin;
 770         u16 lower_margin = screen->mode.lower_margin;
 771         u16 upper_margin = screen->mode.upper_margin;
 772         u16 x_res = screen->mode.xres;
 773         u16 y_res = screen->mode.yres;
 774         u32 mask, val;
 775
 776         spin_lock(&lcdc_dev->reg_lock);
 777         if (likely(lcdc_dev->clk_on)) {
 778                 switch (screen->type) {
 779                 case SCREEN_RGB:
 780                         if (lcdc_dev->soc_type == VOP_RK312X) {
 781                                 mask = m_RGB_DCLK_EN | m_RGB_DCLK_INVERT;
 782                                 val = v_RGB_DCLK_EN(1) | v_RGB_DCLK_INVERT(0);
 783                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 784                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 785                         }
 786                         break;
 787                 case SCREEN_LVDS:
 788                         if (lcdc_dev->soc_type == VOP_RK312X) {
 789                                 mask = m_LVDS_DCLK_EN | m_LVDS_DCLK_INVERT;
 790                                 val = v_LVDS_DCLK_EN(1) | v_LVDS_DCLK_INVERT(0);
 791                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 792                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 793                         }
 794                         break;
 795                 case SCREEN_MIPI:
 796                         if (lcdc_dev->soc_type == VOP_RK312X) {
 797                                 mask = m_MIPI_DCLK_EN | m_MIPI_DCLK_INVERT;
 798                                 val = v_MIPI_DCLK_EN(1) | v_MIPI_DCLK_INVERT(0);
 799                                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 800                                 lcdc_dev->overlay_mode = VOP_RGB_DOMAIN;
 801                         }
 802                         break;
 803                 case SCREEN_HDMI:
 804                         mask = m_HDMI_DCLK_EN;
 805                         val = v_HDMI_DCLK_EN(1);
 806                         if (screen->pixelrepeat) {
 807                                 mask |= m_CORE_CLK_DIV_EN;
 808                                 val |= v_CORE_CLK_DIV_EN(1);
 809                         }
 810                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 811                         if (lcdc_dev->soc_type == VOP_RK312X) {
 812                                 lcdc_dev->overlay_mode = VOP_YUV_DOMAIN;
 813                         }
 814                         break;
 815                 case SCREEN_TVOUT:
 816                         mask = m_TVE_DAC_DCLK_EN;
 817                         val = v_TVE_DAC_DCLK_EN(1);
 818                         if (screen->pixelrepeat) {
 819                                 mask |= m_CORE_CLK_DIV_EN;
 820                                 val |= v_CORE_CLK_DIV_EN(1);
 821                         }
 822                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 823                         if (x_res == 720 && y_res == 576)
 824                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 825                                              v_TVE_MODE(TV_PAL));
 826                         else if (x_res == 720 && y_res == 480)
 827                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_TVE_MODE,
 828                                              v_TVE_MODE(TV_NTSC));
 829                         else {
 830                                 dev_err(lcdc_dev->dev,
 831                                         "unsupported video timing!\n");
 832                                 return -1;
 833                         }
 834                         if (lcdc_dev->soc_type == VOP_RK312X) {
 835                                 lcdc_dev->overlay_mode = VOP_YUV_DOMAIN;
 836                         }
 837                         break;
 838                 default:
 839                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 840                         break;
 841                 }
 842                 if (lcdc_dev->soc_type == VOP_RK312X) {
 843                         switch (screen->face) {
 844                         case OUT_P565:
 845                                 face = OUT_P565;
 846                                 mask = m_DITHER_DOWN_EN |
 847                                         m_DITHER_DOWN_MODE |
 848                                         m_DITHER_DOWN_SEL;
 849                                 val = v_DITHER_DOWN_EN(1) |
 850                                         v_DITHER_DOWN_MODE(0) |
 851                                         v_DITHER_DOWN_SEL(1);
 852                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 853                                 break;
 854                         case OUT_P666:
 855                                 face = OUT_P666;
 856                                 mask = m_DITHER_DOWN_EN |
 857                                         m_DITHER_DOWN_MODE |
 858                                         m_DITHER_DOWN_SEL;
 859                                 val = v_DITHER_DOWN_EN(1) |
 860                                         v_DITHER_DOWN_MODE(1) |
 861                                         v_DITHER_DOWN_SEL(1);
 862                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 863                                 break;
 864                         case OUT_D888_P565:
 865                                 face = OUT_P888;
 866                                 mask = m_DITHER_DOWN_EN |
 867                                         m_DITHER_DOWN_MODE |
 868                                         m_DITHER_DOWN_SEL;
 869                                 val = v_DITHER_DOWN_EN(1) |
 870                                         v_DITHER_DOWN_MODE(0) |
 871                                         v_DITHER_DOWN_SEL(1);
 872                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 873                                 break;
 874                         case OUT_D888_P666:
 875                                 face = OUT_P888;
 876                                 mask = m_DITHER_DOWN_EN |
 877                                         m_DITHER_DOWN_MODE |
 878                                         m_DITHER_DOWN_SEL;
 879                                 val = v_DITHER_DOWN_EN(1) |
 880                                         v_DITHER_DOWN_MODE(1) |
 881                                         v_DITHER_DOWN_SEL(1);
 882                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 883                                 break;
 884                         case OUT_P888:
 885                                 face = OUT_P888;
 886                                 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
 887                                 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
 888                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 889                                 break;
 890                         default:
 891                                 dev_err(lcdc_dev->dev, "un supported interface!\n");
 892                                 break;
 893                         }
 894                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_SW_OVERLAY_MODE,
 895                                      v_SW_OVERLAY_MODE(lcdc_dev->overlay_mode));
 896                 }
 897
 898                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 899                     m_DEN_POL | m_DCLK_POL;
 900                 val = v_DSP_OUT_FORMAT(face) | v_HSYNC_POL(screen->pin_hsync) |
 901                     v_VSYNC_POL(screen->pin_vsync) |
 902                     v_DEN_POL(screen->pin_den) |
 903                     v_DCLK_POL(screen->pin_dclk);
 904                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 905
 906                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 907                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
 908                     m_DSP_DUMMY_SWAP | m_BLANK_EN | m_BLACK_EN;
 909
 910                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
 911                     v_DSP_RB_SWAP(screen->swap_rb) |
 912                     v_DSP_RG_SWAP(screen->swap_rg) |
 913                     v_DSP_DELTA_SWAP(screen->swap_delta) |
 914                     v_DSP_DUMMY_SWAP(screen->swap_dumy) |
 915                     v_BLANK_EN(0) | v_BLACK_EN(0);
 916                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 917
 918                 /* config timing */
 919                 val = v_HSYNC(screen->mode.hsync_len) |
 920                     v_HORPRD(screen->mode.hsync_len + left_margin + x_res +
 921                              right_margin);
 922                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
 923                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
 924                     v_HASP(screen->mode.hsync_len + left_margin);
 925                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
 926
 927                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 928                         /* First Field Timing */
 929                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
 930                                     v_VSYNC(screen->mode.vsync_len) |
 931                                     v_VERPRD(2 * (screen->mode.vsync_len + upper_margin + lower_margin) +
 932                                              y_res + 1));
 933                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
 934                                     v_VAEP(screen->mode.vsync_len +
 935                                            upper_margin + y_res / 2) |
 936                                     v_VASP(screen->mode.vsync_len +
 937                                            upper_margin));
 938                         /* Second Field Timing */
 939                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
 940                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
 941                                                   upper_margin + y_res / 2 +
 942                                                   lower_margin) |
 943                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len +
 944                                                    upper_margin + y_res / 2 +
 945                                                    lower_margin));
 946                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
 947                                     v_VAEP(2 * (screen->mode.vsync_len + upper_margin) +
 948                                            y_res + lower_margin + 1) |
 949                                     v_VASP(2 * (screen->mode.vsync_len + upper_margin) +
 950                                            y_res / 2 + lower_margin + 1));
 951
 952                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 953                                      m_INTERLACE_DSP_EN |
 954                                      m_WIN0_YRGB_DEFLICK_EN |
 955                                      m_WIN0_CBR_DEFLICK_EN |
 956                                      m_INTERLACE_FIELD_POL,
 957                                      v_INTERLACE_DSP_EN(1) |
 958                                      v_WIN0_YRGB_DEFLICK_EN(1) |
 959                                      v_WIN0_CBR_DEFLICK_EN(1) |
 960                                      v_INTERLACE_FIELD_POL(0));
 961                 } else {
 962                         val = v_VSYNC(screen->mode.vsync_len) |
 963                             v_VERPRD(screen->mode.vsync_len + upper_margin +
 964                                      y_res + lower_margin);
 965                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
 966
 967                         val = v_VAEP(screen->mode.vsync_len + upper_margin + y_res) |
 968                             v_VASP(screen->mode.vsync_len + upper_margin);
 969                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
 970
 971                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 972                                      m_INTERLACE_DSP_EN |
 973                                      m_WIN0_YRGB_DEFLICK_EN |
 974                                      m_WIN0_CBR_DEFLICK_EN |
 975                                      m_INTERLACE_FIELD_POL,
 976                                      v_INTERLACE_DSP_EN(0) |
 977                                      v_WIN0_YRGB_DEFLICK_EN(0) |
 978                                      v_WIN0_CBR_DEFLICK_EN(0) |
 979                                      v_INTERLACE_FIELD_POL(0));
 980                 }
 981
 982         }
 983         spin_unlock(&lcdc_dev->reg_lock);
 984
 985         rk312x_lcdc_set_dclk(dev_drv);
 986         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
 987                 dev_drv->trsm_ops->enable();
 988         if (screen->init)
 989                 screen->init();
 990
 991         return 0;
 992 }
 993
 994 static int rk312x_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
 995                             bool open)
 996 {
 997         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 998                                                     struct lcdc_device, driver);
 999
1000         /* enable clk,when first layer open */
1001         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1002                 rockchip_set_system_status(SYS_STATUS_LCDC0);
1003                 rk312x_lcdc_pre_init(dev_drv);
1004 #if defined(CONFIG_ROCKCHIP_IOMMU)
1005                 if (dev_drv->iommu_enabled) {
1006                         if (!dev_drv->mmu_dev) {
1007                                 dev_drv->mmu_dev =
1008                                     rockchip_get_sysmmu_device_by_compatible
1009                                     (dev_drv->mmu_dts_name);
1010                                 if (dev_drv->mmu_dev)
1011                                         platform_set_sysmmu(dev_drv->mmu_dev,
1012                                                             dev_drv->dev);
1013                                 else {
1014                                         dev_err(dev_drv->dev,
1015                                                 "failed to get rockchip iommu device\n");
1016                                         return -1;
1017                                 }
1018                         }
1019                         iovmm_activate(dev_drv->dev);
1020                 }
1021 #endif
1022                 rk312x_lcdc_reg_restore(lcdc_dev);
1023                 if (dev_drv->iommu_enabled)
1024                         rk312x_lcdc_mmu_en(dev_drv);
1025                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1026                         rk312x_lcdc_set_dclk(dev_drv);
1027                         rk312x_lcdc_enable_irq(dev_drv);
1028                 } else {
1029                         rk312x_load_screen(dev_drv, 1);
1030                 }
1031
1032                 /* set screen lut */
1033                 if (dev_drv->cur_screen->dsp_lut)
1034                         rk312x_lcdc_set_lut(dev_drv);
1035         }
1036
1037         if (win_id < ARRAY_SIZE(lcdc_win))
1038                 lcdc_layer_enable(lcdc_dev, win_id, open);
1039         else
1040                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1041
1042         /* when all layer closed,disable clk */
1043         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1044                 rk312x_lcdc_disable_irq(lcdc_dev);
1045                 rk312x_lcdc_reg_update(dev_drv);
1046 #if defined(CONFIG_ROCKCHIP_IOMMU)
1047                 if (dev_drv->iommu_enabled) {
1048                         if (dev_drv->mmu_dev)
1049                                 iovmm_deactivate(dev_drv->dev);
1050                 }
1051 #endif
1052                 rk312x_lcdc_clk_disable(lcdc_dev);
1053                 rockchip_clear_system_status(SYS_STATUS_LCDC0);
1054         }
1055
1056         return 0;
1057 }
1058
1059 static int rk312x_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
1060 {
1061         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1062                                                     struct lcdc_device, driver);
1063         struct rk_screen *screen = dev_drv->cur_screen;
1064         struct rk_lcdc_win *win = NULL;
1065         char fmt[9] = "NULL";
1066
1067         if (!screen) {
1068                 dev_err(dev_drv->dev, "screen is null!\n");
1069                 return -ENOENT;
1070         }
1071
1072         if (win_id == 0) {
1073                 win = dev_drv->win[0];
1074         } else if (win_id == 1) {
1075                 win = dev_drv->win[1];
1076         } else {
1077                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
1078                 return -EINVAL;
1079         }
1080
1081         spin_lock(&lcdc_dev->reg_lock);
1082         win->area[0].dsp_stx = win->area[0].xpos + screen->mode.left_margin +
1083                                 screen->mode.hsync_len;
1084         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1085                 win->area[0].ysize /= 2;
1086                 win->area[0].dsp_sty = win->area[0].ypos / 2 +
1087                                         screen->mode.upper_margin +
1088                                         screen->mode.vsync_len;
1089         } else {
1090                 win->area[0].dsp_sty = win->area[0].ypos +
1091                                         screen->mode.upper_margin +
1092                                         screen->mode.vsync_len;
1093         }
1094         win->scale_yrgb_x = CalScale(win->area[0].xact, win->area[0].xsize);
1095         win->scale_yrgb_y = CalScale(win->area[0].yact, win->area[0].ysize);
1096         switch (win->format) {
1097         case ARGB888:
1098                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1099                 win->swap_rb = 0;
1100                 break;
1101         case XBGR888:
1102                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1103                 win->swap_rb = 1;
1104                 break;
1105         case ABGR888:
1106                 win->fmt_cfg = VOP_FORMAT_ARGB888;
1107                 win->swap_rb = 1;
1108                 break;
1109         case RGB888:
1110                 win->fmt_cfg = VOP_FORMAT_RGB888;
1111                 win->swap_rb = 0;
1112                 break;
1113         case RGB565:
1114                 win->fmt_cfg = VOP_FORMAT_RGB565;
1115                 win->swap_rb = 0;
1116                 break;
1117         case YUV444:
1118                 if (win_id == 0) {
1119                         win->fmt_cfg = VOP_FORMAT_YCBCR444;
1120                         win->scale_cbcr_x =
1121                             CalScale(win->area[0].xact, win->area[0].xsize);
1122                         win->scale_cbcr_y =
1123                             CalScale(win->area[0].yact, win->area[0].ysize);
1124                         win->swap_rb = 0;
1125                 } else {
1126                         dev_err(lcdc_dev->driver.dev,
1127                                 "%s:un supported format!\n", __func__);
1128                 }
1129                 break;
1130         case YUV422:
1131                 if (win_id == 0) {
1132                         win->fmt_cfg = VOP_FORMAT_YCBCR422;
1133                         win->scale_cbcr_x = CalScale((win->area[0].xact / 2),
1134                                                      win->area[0].xsize);
1135                         win->scale_cbcr_y =
1136                             CalScale(win->area[0].yact, win->area[0].ysize);
1137                         win->swap_rb = 0;
1138                 } else {
1139                         dev_err(lcdc_dev->driver.dev,
1140                                 "%s:un supported format!\n", __func__);
1141                 }
1142                 break;
1143         case YUV420:
1144                 if (win_id == 0) {
1145                         win->fmt_cfg = VOP_FORMAT_YCBCR420;
1146                         win->scale_cbcr_x =
1147                             CalScale(win->area[0].xact / 2, win->area[0].xsize);
1148                         win->scale_cbcr_y =
1149                             CalScale(win->area[0].yact / 2, win->area[0].ysize);
1150                         win->swap_rb = 0;
1151                 } else {
1152                         dev_err(lcdc_dev->driver.dev,
1153                                 "%s:un supported format!\n", __func__);
1154                 }
1155                 break;
1156         default:
1157                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
1158                         __func__);
1159                 break;
1160         }
1161         spin_unlock(&lcdc_dev->reg_lock);
1162
1163         DBG(1,
1164             "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
1165             ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id, __func__,
1166             get_format_string(win->format, fmt), win->area[0].xact,
1167             win->area[0].yact, win->area[0].xsize, win->area[0].ysize,
1168             win->area[0].xvir, win->area[0].yvir, win->area[0].xpos,
1169             win->area[0].ypos);
1170         return 0;
1171 }
1172
1173 static int rk312x_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1174 {
1175         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1176                                                     struct lcdc_device, driver);
1177         struct rk_lcdc_win *win = NULL;
1178         struct rk_screen *screen = dev_drv->cur_screen;
1179
1180         if (!screen) {
1181                 dev_err(dev_drv->dev, "screen is null!\n");
1182                 return -ENOENT;
1183         }
1184
1185         if (win_id == 0) {
1186                 win = dev_drv->win[0];
1187         } else if (win_id == 1) {
1188                 win = dev_drv->win[1];
1189         } else {
1190                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1191                 return -EINVAL;
1192         }
1193
1194         spin_lock(&lcdc_dev->reg_lock);
1195         if (likely(lcdc_dev->clk_on)) {
1196                 win->area[0].y_addr =
1197                     win->area[0].smem_start + win->area[0].y_offset;
1198                 win->area[0].uv_addr =
1199                     win->area[0].cbr_start + win->area[0].c_offset;
1200                 if (win->area[0].y_addr)
1201                         lcdc_layer_update_regs(lcdc_dev, win);
1202                 /* lcdc_cfg_done(lcdc_dev); */
1203         }
1204         spin_unlock(&lcdc_dev->reg_lock);
1205
1206         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1207             lcdc_dev->id, __func__, win->area[0].y_addr, win->area[0].uv_addr,
1208             win->area[0].y_offset);
1209         /* this is the first frame of the system,enable frame start interrupt */
1210         if ((dev_drv->first_frame)) {
1211                 dev_drv->first_frame = 0;
1212                 rk312x_lcdc_enable_irq(dev_drv);
1213
1214         }
1215
1216         return 0;
1217 }
1218
1219 static int rk312x_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
1220                              unsigned long arg, int win_id)
1221 {
1222         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1223                                                     struct lcdc_device, driver);
1224         u32 panel_size[2];
1225         void __user *argp = (void __user *)arg;
1226         struct color_key_cfg clr_key_cfg;
1227
1228         switch (cmd) {
1229         case RK_FBIOGET_PANEL_SIZE:
1230                 panel_size[0] = lcdc_dev->screen->mode.xres;
1231                 panel_size[1] = lcdc_dev->screen->mode.yres;
1232                 if (copy_to_user(argp, panel_size, 8))
1233                         return -EFAULT;
1234                 break;
1235         case RK_FBIOPUT_COLOR_KEY_CFG:
1236                 if (copy_from_user(&clr_key_cfg, argp,
1237                                    sizeof(struct color_key_cfg)))
1238                         return -EFAULT;
1239                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
1240                             clr_key_cfg.win0_color_key_cfg);
1241                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
1242                             clr_key_cfg.win1_color_key_cfg);
1243                 break;
1244
1245         default:
1246                 break;
1247         }
1248         return 0;
1249 }
1250
1251 static int rk312x_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
1252                                   const char *id)
1253 {
1254         int win_id = 0;
1255         mutex_lock(&dev_drv->fb_win_id_mutex);
1256         if (!strcmp(id, "fb0"))
1257                 win_id = dev_drv->fb0_win_id;
1258         else if (!strcmp(id, "fb1"))
1259                 win_id = dev_drv->fb1_win_id;
1260         else if (!strcmp(id, "fb2"))
1261                 win_id = dev_drv->fb2_win_id;
1262         mutex_unlock(&dev_drv->fb_win_id_mutex);
1263
1264         return win_id;
1265 }
1266
1267 static int rk312x_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
1268 {
1269         return 0;
1270 }
1271
1272 static int rk312x_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1273                                bool set)
1274 {
1275         struct lcdc_device *lcdc_dev =
1276             container_of(dev_drv, struct lcdc_device, driver);
1277         int ovl;
1278         spin_lock(&lcdc_dev->reg_lock);
1279         if (lcdc_dev->clk_on) {
1280                 if (set) {
1281                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1282                                      v_WIN0_TOP(swap));
1283                         ovl = swap;
1284                 } else {
1285                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1286                 }
1287         } else {
1288                 ovl = -EPERM;
1289         }
1290         spin_unlock(&lcdc_dev->reg_lock);
1291
1292         return ovl;
1293 }
1294
1295 static int rk312x_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1296 {
1297
1298         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1299                                                     struct lcdc_device, driver);
1300         if (dev_drv->suspend_flag)
1301                 return 0;
1302         dev_drv->suspend_flag = 1;
1303         flush_kthread_worker(&dev_drv->update_regs_worker);
1304
1305         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1306                 dev_drv->trsm_ops->disable();
1307         spin_lock(&lcdc_dev->reg_lock);
1308         if (likely(lcdc_dev->clk_on)) {
1309                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(1));
1310                 lcdc_msk_reg(lcdc_dev, INT_STATUS,
1311                              m_FS_INT_CLEAR | m_LF_INT_CLEAR,
1312                              v_FS_INT_CLEAR(1) | v_LF_INT_CLEAR(1));
1313                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1314                              v_DSP_OUT_ZERO(1));
1315                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1316                              v_LCDC_STANDBY(1));
1317                 lcdc_cfg_done(lcdc_dev);
1318 #if defined(CONFIG_ROCKCHIP_IOMMU)
1319                 if (dev_drv->iommu_enabled) {
1320                         if (dev_drv->mmu_dev)
1321                                 iovmm_deactivate(dev_drv->dev);
1322                 }
1323 #endif
1324                 spin_unlock(&lcdc_dev->reg_lock);
1325         } else {
1326                 spin_unlock(&lcdc_dev->reg_lock);
1327                 return 0;
1328         }
1329         rk312x_lcdc_clk_disable(lcdc_dev);
1330         rk_disp_pwr_disable(dev_drv);
1331         return 0;
1332 }
1333
1334 static int rk312x_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1335 {
1336         struct lcdc_device *lcdc_dev =
1337             container_of(dev_drv, struct lcdc_device, driver);
1338
1339         if (!dev_drv->suspend_flag)
1340                 return 0;
1341         rk_disp_pwr_enable(dev_drv);
1342         dev_drv->suspend_flag = 0;
1343
1344         if (lcdc_dev->atv_layer_cnt) {
1345                 rk312x_lcdc_clk_enable(lcdc_dev);
1346                 rk312x_lcdc_reg_restore(lcdc_dev);
1347                 /* set screen lut */
1348                 if (dev_drv->cur_screen->dsp_lut)
1349                         rk312x_lcdc_set_lut(dev_drv);
1350
1351                 spin_lock(&lcdc_dev->reg_lock);
1352
1353                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1354                              v_DSP_OUT_ZERO(0));
1355                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1356                              v_LCDC_STANDBY(0));
1357                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN, v_BLANK_EN(0));
1358                 lcdc_cfg_done(lcdc_dev);
1359
1360                 spin_unlock(&lcdc_dev->reg_lock);
1361         }
1362
1363         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1364                 dev_drv->trsm_ops->enable();
1365         return 0;
1366 }
1367
1368 static int rk312x_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1369                              int win_id, int blank_mode)
1370 {
1371         switch (blank_mode) {
1372         case FB_BLANK_UNBLANK:
1373                 rk312x_lcdc_early_resume(dev_drv);
1374                 break;
1375         case FB_BLANK_NORMAL:
1376                 rk312x_lcdc_early_suspend(dev_drv);
1377                 break;
1378         default:
1379                 rk312x_lcdc_early_suspend(dev_drv);
1380                 break;
1381         }
1382
1383         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1384
1385         return 0;
1386 }
1387
1388 static int rk312x_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1389 {
1390         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1391                                                     struct lcdc_device, driver);
1392         spin_lock(&lcdc_dev->reg_lock);
1393         if (lcdc_dev->clk_on)
1394                 lcdc_cfg_done(lcdc_dev);
1395         spin_unlock(&lcdc_dev->reg_lock);
1396         return 0;
1397 }
1398
1399 /*
1400         a:[-30~0]:
1401             sin_hue = sin(a)*256 +0x100;
1402             cos_hue = cos(a)*256;
1403         a:[0~30]
1404             sin_hue = sin(a)*256;
1405             cos_hue = cos(a)*256;
1406 */
1407 static int rk312x_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1408                                     bcsh_hue_mode mode)
1409 {
1410
1411         struct lcdc_device *lcdc_dev =
1412             container_of(dev_drv, struct lcdc_device, driver);
1413         u32 val;
1414
1415         spin_lock(&lcdc_dev->reg_lock);
1416         if (lcdc_dev->clk_on) {
1417                 val = lcdc_readl(lcdc_dev, BCSH_H);
1418                 switch (mode) {
1419                 case H_SIN:
1420                         val &= m_BCSH_SIN_HUE;
1421                         break;
1422                 case H_COS:
1423                         val &= m_BCSH_COS_HUE;
1424                         val >>= 16;
1425                         break;
1426                 default:
1427                         break;
1428                 }
1429         }
1430         spin_unlock(&lcdc_dev->reg_lock);
1431
1432         return val;
1433 }
1434
1435 static int rk312x_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv, int sin_hue,
1436                                     int cos_hue)
1437 {
1438
1439         struct lcdc_device *lcdc_dev =
1440             container_of(dev_drv, struct lcdc_device, driver);
1441         u32 mask, val;
1442
1443         spin_lock(&lcdc_dev->reg_lock);
1444         if (lcdc_dev->clk_on) {
1445                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1446                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1447                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1448                 lcdc_cfg_done(lcdc_dev);
1449         }
1450         spin_unlock(&lcdc_dev->reg_lock);
1451
1452         return 0;
1453 }
1454
1455 static int rk312x_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1456                                     bcsh_bcs_mode mode, int value)
1457 {
1458         struct lcdc_device *lcdc_dev =
1459             container_of(dev_drv, struct lcdc_device, driver);
1460         u32 mask, val;
1461
1462         spin_lock(&lcdc_dev->reg_lock);
1463         if (lcdc_dev->clk_on) {
1464                 switch (mode) {
1465                 case BRIGHTNESS:
1466                         /* from 0 to 255,typical is 128 */
1467                         if (value < 0x80)
1468                                 value += 0x80;
1469                         else if (value >= 0x80)
1470                                 value = value - 0x80;
1471                         mask = m_BCSH_BRIGHTNESS;
1472                         val = v_BCSH_BRIGHTNESS(value);
1473                         break;
1474                 case CONTRAST:
1475                         /* from 0 to 510,typical is 256 */
1476                         mask = m_BCSH_CONTRAST;
1477                         val = v_BCSH_CONTRAST(value);
1478                         break;
1479                 case SAT_CON:
1480                         /* from 0 to 1015,typical is 256 */
1481                         mask = m_BCSH_SAT_CON;
1482                         val = v_BCSH_SAT_CON(value);
1483                         break;
1484                 default:
1485                         break;
1486                 }
1487                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1488                 lcdc_cfg_done(lcdc_dev);
1489         }
1490         spin_unlock(&lcdc_dev->reg_lock);
1491         return val;
1492 }
1493
1494 static int rk312x_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1495                                     bcsh_bcs_mode mode)
1496 {
1497         struct lcdc_device *lcdc_dev =
1498             container_of(dev_drv, struct lcdc_device, driver);
1499         u32 val;
1500
1501         spin_lock(&lcdc_dev->reg_lock);
1502         if (lcdc_dev->clk_on) {
1503                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1504                 switch (mode) {
1505                 case BRIGHTNESS:
1506                         val &= m_BCSH_BRIGHTNESS;
1507                         if (val > 0x80)
1508                                 val -= 0x80;
1509                         else
1510                                 val += 0x80;
1511                         break;
1512                 case CONTRAST:
1513                         val &= m_BCSH_CONTRAST;
1514                         val >>= 8;
1515                         break;
1516                 case SAT_CON:
1517                         val &= m_BCSH_SAT_CON;
1518                         val >>= 20;
1519                         break;
1520                 default:
1521                         break;
1522                 }
1523         }
1524         spin_unlock(&lcdc_dev->reg_lock);
1525         return val;
1526 }
1527
1528 static int rk312x_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1529 {
1530         struct lcdc_device *lcdc_dev =
1531             container_of(dev_drv, struct lcdc_device, driver);
1532         u32 mask, val;
1533
1534         spin_lock(&lcdc_dev->reg_lock);
1535         if (lcdc_dev->clk_on) {
1536                 if (open) {
1537                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1538                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1539                         lcdc_writel(lcdc_dev, BCSH_BCS,
1540                                     v_BCSH_BRIGHTNESS(0x00) |
1541                                     v_BCSH_CONTRAST(0x80) |
1542                                     v_BCSH_SAT_CON(0x80));
1543                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1544                 } else {
1545                         mask = m_BCSH_EN;
1546                         val = v_BCSH_EN(0);
1547                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1548                 }
1549                 lcdc_cfg_done(lcdc_dev);
1550         }
1551
1552         if (lcdc_dev->overlay_mode == VOP_YUV_DOMAIN) {
1553                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_CSC_MODE,
1554                              v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_BYPASS));
1555         } else {
1556                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL, m_BCSH_R2Y_CSC_MODE,
1557                              v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG));
1558         }
1559
1560         spin_unlock(&lcdc_dev->reg_lock);
1561         return 0;
1562 }
1563
1564 static int rk312x_fb_win_remap(struct rk_lcdc_driver *dev_drv,
1565                                enum fb_win_map_order order)
1566 {
1567         mutex_lock(&dev_drv->fb_win_id_mutex);
1568         if (order == FB_DEFAULT_ORDER)
1569                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;     /* FB0_WIN1_FB1_WIN0_FB2_WIN2; for box */
1570         dev_drv->fb2_win_id = order / 100;
1571         dev_drv->fb1_win_id = (order / 10) % 10;
1572         dev_drv->fb0_win_id = order % 10;
1573         mutex_unlock(&dev_drv->fb_win_id_mutex);
1574
1575         return 0;
1576 }
1577
1578 static int rk312x_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1579                                bool set)
1580 {
1581         struct lcdc_device *lcdc_dev =
1582             container_of(dev_drv, struct lcdc_device, driver);
1583         struct rk_screen *screen = dev_drv->cur_screen;
1584         u64 ft = 0;
1585         u32 dotclk;
1586         int ret;
1587         u32 pixclock;
1588         u32 x_total, y_total;
1589         if (set) {
1590                 ft = div_u64(1000000000000llu, fps);
1591                 x_total =
1592                     screen->mode.upper_margin + screen->mode.lower_margin +
1593                     screen->mode.yres + screen->mode.vsync_len;
1594                 y_total =
1595                     screen->mode.left_margin + screen->mode.right_margin +
1596                     screen->mode.xres + screen->mode.hsync_len;
1597                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1598                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1599                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1600         }
1601
1602         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1603         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
1604         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1605         screen->ft = 1000 / fps;        /*one frame time in ms */
1606
1607         if (set)
1608                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1609                          clk_get_rate(lcdc_dev->dclk), fps);
1610
1611         return fps;
1612 }
1613
1614 static int rk312x_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1615 {
1616         struct lcdc_device *lcdc_dev =
1617             container_of(dev_drv, struct lcdc_device, driver);
1618         u32 int_reg;
1619         int ret;
1620
1621         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
1622                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1623                 if (int_reg & m_LF_INT_STA) {
1624                         dev_drv->frame_time.last_framedone_t =
1625                                         dev_drv->frame_time.framedone_t;
1626                         dev_drv->frame_time.framedone_t = cpu_clock(0);
1627                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1628                                      v_LF_INT_CLEAR(1));
1629                         ret = RK_LF_STATUS_FC;
1630                 } else
1631                         ret = RK_LF_STATUS_FR;
1632         } else {
1633                 ret = RK_LF_STATUS_NC;
1634         }
1635
1636         return ret;
1637 }
1638
1639 static int rk312x_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1640                                     unsigned int *dsp_addr)
1641 {
1642         struct lcdc_device *lcdc_dev =
1643             container_of(dev_drv, struct lcdc_device, driver);
1644
1645         if (lcdc_dev->clk_on) {
1646                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1647                 if (lcdc_dev->soc_type == VOP_RK3036)
1648                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1649                 else if (lcdc_dev->soc_type == VOP_RK312X)
1650                         dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1651         }
1652         return 0;
1653 }
1654
1655 static ssize_t rk312x_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1656                                          char *buf, int win_id)
1657 {
1658         struct lcdc_device *lcdc_dev = container_of(dev_drv, struct lcdc_device,
1659                                                     driver);
1660         char format_w0[9] = "NULL";
1661         char format_w1[9] = "NULL";
1662         char status_w0[9] = "NULL";
1663         char status_w1[9] = "NULL";
1664         u32 fmt_id, act_info, dsp_info, dsp_st, factor;
1665         u16 xvir_w0, x_act_w0, y_act_w0, x_dsp_w0, y_dsp_w0, x_st_w0, y_st_w0;
1666         u16 xvir_w1, x_act_w1, y_act_w1, x_dsp_w1, y_dsp_w1, x_st_w1, y_st_w1;
1667         u16 x_factor, y_factor, x_scale, y_scale;
1668         u16 ovl;
1669         u32 win1_dsp_yaddr = 0;
1670
1671         spin_lock(&lcdc_dev->reg_lock);
1672         if (lcdc_dev->clk_on) {
1673                 /* data format */
1674                 fmt_id = lcdc_readl(lcdc_dev, SYS_CTRL);
1675                 get_format_string((fmt_id & m_WIN0_FORMAT) >> 3, format_w0);
1676                 get_format_string((fmt_id & m_WIN1_FORMAT) >> 6, format_w1);
1677
1678                 /* win status */
1679                 if (fmt_id & m_WIN0_EN)
1680                         strcpy(status_w0, "enabled");
1681                 else
1682                         strcpy(status_w0, "disabled");
1683
1684                 if ((fmt_id & m_WIN1_EN) >> 1)
1685                         strcpy(status_w1, "enabled");
1686                 else
1687                         strcpy(status_w1, "disabled");
1688
1689                 /* ovl */
1690                 ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1691
1692                 /* xvir */
1693                 xvir_w0 = lcdc_readl(lcdc_dev, WIN0_VIR) & m_YRGB_VIR;
1694                 xvir_w1 = lcdc_readl(lcdc_dev, WIN1_VIR) & m_YRGB_VIR;
1695
1696                 /* xact/yact */
1697                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1698                 x_act_w0 = (act_info & m_ACT_WIDTH) + 1;
1699                 y_act_w0 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1700
1701                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
1702                 x_act_w1 = (act_info & m_ACT_WIDTH) + 1;
1703                 y_act_w1 = ((act_info & m_ACT_HEIGHT) >> 16) + 1;
1704
1705                 /* xsize/ysize */
1706                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
1707                 x_dsp_w0 = (dsp_info & m_DSP_WIDTH) + 1;
1708                 y_dsp_w0 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1709
1710                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
1711                 x_dsp_w1 = (dsp_info & m_DSP_WIDTH) + 1;
1712                 y_dsp_w1 = ((dsp_info & m_DSP_HEIGHT) >> 16) + 1;
1713
1714                 /* xpos/ypos */
1715                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
1716                 x_st_w0 = dsp_st & m_DSP_STX;
1717                 y_st_w0 = (dsp_st & m_DSP_STY) >> 16;
1718
1719                 if (lcdc_dev->soc_type == VOP_RK3036)
1720                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
1721                 else if (lcdc_dev->soc_type == VOP_RK312X)
1722                         dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST_RK312X);
1723
1724                 x_st_w1 = dsp_st & m_DSP_STX;
1725                 y_st_w1 = (dsp_st & m_DSP_STY) >> 16;
1726
1727                 /* scale factor */
1728                 factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
1729                 x_factor = factor & m_X_SCL_FACTOR;
1730                 y_factor = (factor & m_Y_SCL_FACTOR) >> 16;
1731                 x_scale = 4096 * 100 / x_factor;
1732                 y_scale = 4096 * 100 / y_factor;
1733
1734                 /* dsp addr */
1735                 if (lcdc_dev->soc_type == VOP_RK3036)
1736                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST);
1737                 else if (lcdc_dev->soc_type == VOP_RK312X)
1738                         win1_dsp_yaddr = lcdc_readl(lcdc_dev, WIN1_MST_RK312X);
1739         } else {
1740                 spin_unlock(&lcdc_dev->reg_lock);
1741                 return -EPERM;
1742         }
1743         spin_unlock(&lcdc_dev->reg_lock);
1744         return snprintf(buf, PAGE_SIZE,
1745                         "win0:%s\n"
1746                         "xvir:%d\n"
1747                         "xact:%d\n"
1748                         "yact:%d\n"
1749                         "xdsp:%d\n"
1750                         "ydsp:%d\n"
1751                         "x_st:%d\n"
1752                         "y_st:%d\n"
1753                         "x_scale:%d.%d\n"
1754                         "y_scale:%d.%d\n"
1755                         "format:%s\n"
1756                         "YRGB buffer addr:0x%08x\n"
1757                         "CBR buffer addr:0x%08x\n\n"
1758                         "win1:%s\n"
1759                         "xvir:%d\n"
1760                         "xact:%d\n"
1761                         "yact:%d\n"
1762                         "xdsp:%d\n"
1763                         "ydsp:%d\n"
1764                         "x_st:%d\n"
1765                         "y_st:%d\n"
1766                         "format:%s\n"
1767                         "YRGB buffer addr:0x%08x\n"
1768                         "overlay:%s\n",
1769                         status_w0,
1770                         xvir_w0,
1771                         x_act_w0,
1772                         y_act_w0,
1773                         x_dsp_w0,
1774                         y_dsp_w0,
1775                         x_st_w0,
1776                         y_st_w0,
1777                         x_scale / 100,
1778                         x_scale % 100,
1779                         y_scale / 100,
1780                         y_scale % 100,
1781                         format_w0,
1782                         lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
1783                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
1784                         status_w1,
1785                         xvir_w1,
1786                         x_act_w1,
1787                         y_act_w1,
1788                         x_dsp_w1,
1789                         y_dsp_w1,
1790                         x_st_w1,
1791                         y_st_w1,
1792                         format_w1,
1793                         win1_dsp_yaddr,
1794                         ovl ? "win0 on the top of win1\n" :
1795                         "win1 on the top of win0\n");
1796 }
1797
1798 static int rk312x_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1799 {
1800         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1801                                                     struct lcdc_device,
1802                                                     driver);
1803         int *cbase = (int *)lcdc_dev->regs;
1804         int *regsbak = (int *)lcdc_dev->regsbak;
1805         int i, j;
1806
1807         printk("back up reg:\n");
1808         for (i = 0; i <= (0xDC >> 4); i++) {
1809                 for (j = 0; j < 4; j++)
1810                         printk("%08x  ", *(regsbak + i * 4 + j));
1811                 printk("\n");
1812         }
1813
1814         printk("lcdc reg:\n");
1815         for (i = 0; i <= (0xDC >> 4); i++) {
1816                 for (j = 0; j < 4; j++)
1817                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
1818                 printk("\n");
1819         }
1820         return 0;
1821 }
1822
1823 static int rk312x_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
1824 {
1825         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1826                                                     struct lcdc_device, driver);
1827         if (lcdc_dev->soc_type == VOP_RK312X) {
1828                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
1829                              v_DIRECT_PATH_EN(open));
1830                 lcdc_cfg_done(lcdc_dev);
1831         }
1832         return 0;
1833 }
1834
1835 static int rk312x_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
1836 {
1837         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1838                                                     struct lcdc_device, driver);
1839
1840         if (lcdc_dev->soc_type == VOP_RK312X) {
1841                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_LAYER,
1842                              v_DIRECT_PATH_LAYER(win_id));
1843                 lcdc_cfg_done(lcdc_dev);
1844         }
1845         return 0;
1846
1847 }
1848
1849 static int rk312x_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
1850 {
1851         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1852                                                     struct lcdc_device, driver);
1853         int ovl = 0;
1854
1855         if (lcdc_dev->soc_type == VOP_RK312X)
1856                 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
1857
1858         return ovl;
1859 }
1860
1861 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1862         .open = rk312x_lcdc_open,
1863         .load_screen = rk312x_load_screen,
1864         .set_par = rk312x_lcdc_set_par,
1865         .pan_display = rk312x_lcdc_pan_display,
1866         .blank = rk312x_lcdc_blank,
1867         .ioctl = rk312x_lcdc_ioctl,
1868         .get_win_state = rk312x_lcdc_get_win_state,
1869         .ovl_mgr = rk312x_lcdc_ovl_mgr,
1870         .get_disp_info = rk312x_lcdc_get_disp_info,
1871         .fps_mgr = rk312x_lcdc_fps_mgr,
1872         .fb_get_win_id = rk312x_lcdc_get_win_id,
1873         .fb_win_remap = rk312x_fb_win_remap,
1874         .poll_vblank = rk312x_lcdc_poll_vblank,
1875         .get_dsp_addr = rk312x_lcdc_get_dsp_addr,
1876         .cfg_done = rk312x_lcdc_cfg_done,
1877         .dump_reg = rk312x_lcdc_reg_dump,
1878         .dpi_open = rk312x_lcdc_dpi_open,
1879         .dpi_win_sel = rk312x_lcdc_dpi_win_sel,
1880         .dpi_status = rk312x_lcdc_dpi_status,
1881         .set_dsp_bcsh_hue = rk312x_lcdc_set_bcsh_hue,
1882         .set_dsp_bcsh_bcs = rk312x_lcdc_set_bcsh_bcs,
1883         .get_dsp_bcsh_hue = rk312x_lcdc_get_bcsh_hue,
1884         .get_dsp_bcsh_bcs = rk312x_lcdc_get_bcsh_bcs,
1885         .open_bcsh = rk312x_lcdc_open_bcsh,
1886         .set_screen_scaler = rk312x_lcdc_set_scaler,
1887 };
1888 #if 0
1889 static const struct rk_lcdc_drvdata rk3036_lcdc_drvdata = {
1890         .soc_type = VOP_RK3036,
1891 };
1892 #endif
1893 static const struct rk_lcdc_drvdata rk312x_lcdc_drvdata = {
1894         .soc_type = VOP_RK312X,
1895 };
1896
1897 #if defined(CONFIG_OF)
1898 static const struct of_device_id rk312x_lcdc_dt_ids[] = {
1899 #if 0
1900         {
1901                 .compatible = "rockchip,rk3036-lcdc",
1902                 .data = (void *)&rk3036_lcdc_drvdata,
1903         },
1904 #endif
1905         {
1906                 .compatible = "rockchip,rk312x-lcdc",
1907                 .data = (void *)&rk312x_lcdc_drvdata,
1908         },
1909 };
1910 #endif
1911
1912 static int rk312x_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1913 {
1914         struct device_node *np = lcdc_dev->dev->of_node;
1915         const struct of_device_id *match;
1916         const struct rk_lcdc_drvdata *lcdc_drvdata;
1917
1918 #if defined(CONFIG_ROCKCHIP_IOMMU)
1919         int val;
1920         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1921                 lcdc_dev->driver.iommu_enabled = 0;
1922         else
1923                 lcdc_dev->driver.iommu_enabled = val;
1924 #else
1925         lcdc_dev->driver.iommu_enabled = 0;
1926 #endif
1927         match = of_match_node(rk312x_lcdc_dt_ids, np);
1928         if (match) {
1929                 lcdc_drvdata = (const struct rk_lcdc_drvdata *)match->data;
1930                 lcdc_dev->soc_type = lcdc_drvdata->soc_type;
1931         } else {
1932                 return PTR_ERR(match);
1933         }
1934
1935         return 0;
1936 }
1937
1938 static int rk312x_lcdc_probe(struct platform_device *pdev)
1939 {
1940         struct lcdc_device *lcdc_dev = NULL;
1941         struct rk_lcdc_driver *dev_drv;
1942         struct device *dev = &pdev->dev;
1943         struct resource *res;
1944         int ret;
1945
1946         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
1947         if (!lcdc_dev) {
1948                 dev_err(&pdev->dev, "rk312x lcdc device kzalloc fail!\n");
1949                 return -ENOMEM;
1950         }
1951         platform_set_drvdata(pdev, lcdc_dev);
1952         lcdc_dev->dev = dev;
1953         if (rk312x_lcdc_parse_dt(lcdc_dev)) {
1954                 dev_err(lcdc_dev->dev, "rk312x lcdc parse dt failed!\n");
1955                 goto err_parse_dt;
1956         }
1957
1958         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1959         lcdc_dev->reg_phy_base = res->start;
1960         lcdc_dev->len = resource_size(res);
1961         lcdc_dev->regs = devm_ioremap_resource(dev, res);
1962         if (IS_ERR(lcdc_dev->regs)) {
1963                 ret = PTR_ERR(lcdc_dev->regs);
1964                 goto err_remap_reg;
1965         }
1966
1967         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1968         if (IS_ERR(lcdc_dev->regsbak)) {
1969                 dev_err(&pdev->dev, "rk312x lcdc device kmalloc fail!\n");
1970                 ret = PTR_ERR(lcdc_dev->regsbak);
1971                 goto err_remap_reg;
1972         }
1973
1974         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1975         dev_drv = &lcdc_dev->driver;
1976         dev_drv->dev = dev;
1977         dev_drv->prop = PRMRY;
1978         dev_drv->id = lcdc_dev->id;
1979         dev_drv->ops = &lcdc_drv_ops;
1980         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1981         spin_lock_init(&lcdc_dev->reg_lock);
1982
1983         lcdc_dev->irq = platform_get_irq(pdev, 0);
1984         if (lcdc_dev->irq < 0) {
1985                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
1986                         lcdc_dev->id);
1987                 ret = -ENXIO;
1988                 goto err_request_irq;
1989         }
1990
1991         ret = devm_request_irq(dev, lcdc_dev->irq, rk312x_lcdc_isr,
1992                                IRQF_DISABLED, dev_name(dev), lcdc_dev);
1993         if (ret) {
1994                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
1995                         lcdc_dev->irq, ret);
1996                 goto err_request_irq;
1997         }
1998
1999         if (dev_drv->iommu_enabled)
2000                 strcpy(dev_drv->mmu_dts_name, "iommu,vop_mmu");
2001
2002         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
2003         if (ret < 0) {
2004                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
2005                 goto err_register_fb;
2006         }
2007         lcdc_dev->screen = dev_drv->screen0;
2008
2009         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
2010                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
2011         return 0;
2012
2013 err_register_fb:
2014 err_request_irq:
2015         devm_kfree(lcdc_dev->dev, lcdc_dev->regsbak);
2016 err_remap_reg:
2017 err_parse_dt:
2018         devm_kfree(&pdev->dev, lcdc_dev);
2019         return ret;
2020 }
2021
2022 #if defined(CONFIG_PM)
2023 static int rk312x_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
2024 {
2025         return 0;
2026 }
2027
2028 static int rk312x_lcdc_resume(struct platform_device *pdev)
2029 {
2030         return 0;
2031 }
2032 #else
2033 #define rk312x_lcdc_suspend NULL
2034 #define rk312x_lcdc_resume  NULL
2035 #endif
2036
2037 static int rk312x_lcdc_remove(struct platform_device *pdev)
2038 {
2039         return 0;
2040 }
2041
2042 static void rk312x_lcdc_shutdown(struct platform_device *pdev)
2043 {
2044         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
2045
2046         rk312x_lcdc_deinit(lcdc_dev);
2047         rk312x_lcdc_clk_disable(lcdc_dev);
2048         rk_disp_pwr_disable(&lcdc_dev->driver);
2049 }
2050
2051 static struct platform_driver rk312x_lcdc_driver = {
2052         .probe = rk312x_lcdc_probe,
2053         .remove = rk312x_lcdc_remove,
2054         .driver = {
2055                    .name = "rk312x-lcdc",
2056                    .owner = THIS_MODULE,
2057                    .of_match_table = of_match_ptr(rk312x_lcdc_dt_ids),
2058                    },
2059         .suspend = rk312x_lcdc_suspend,
2060         .resume = rk312x_lcdc_resume,
2061         .shutdown = rk312x_lcdc_shutdown,
2062 };
2063
2064 static int __init rk312x_lcdc_module_init(void)
2065 {
2066         return platform_driver_register(&rk312x_lcdc_driver);
2067 }
2068
2069 static void __exit rk312x_lcdc_module_exit(void)
2070 {
2071         platform_driver_unregister(&rk312x_lcdc_driver);
2072 }
2073
2074 fs_initcall(rk312x_lcdc_module_init);
2075 module_exit(rk312x_lcdc_module_exit);