1 #ifndef _RK312X_LCDC_H_
2 #define _RK312X_LCDC_H_
4 #include<linux/rk_fb.h>
14 #define BITS(x, bit) ((x) << (bit))
15 #define BITS_MASK(x, mask, bit) BITS((x) & (mask), bit)
17 /*******************register definition**********************/
19 #define SYS_CTRL (0x00)
20 #define m_WIN0_EN BITS(1, 0)
21 #define m_WIN1_EN BITS(1, 1)
22 #define m_HWC_EN BITS(1, 2)
23 #define m_WIN0_FORMAT BITS(7, 3)
24 #define m_WIN1_FORMAT BITS(7, 6)
25 #define m_HWC_LUT_EN BITS(1, 9)
26 #define m_HWC_SIZE BITS(1, 10)
27 #define m_DIRECT_PATH_EN BITS(1, 11) /* rk312x */
28 #define m_DIRECT_PATH_LAYER BITS(1, 12) /* rk312x */
29 #define m_TVE_MODE_SEL BITS(1, 13) /* rk312x */
30 #define m_TVE_DAC_EN BITS(1, 14) /* rk312x */
31 #define m_WIN0_RB_SWAP BITS(1, 15)
32 #define m_WIN0_ALPHA_SWAP BITS(1, 16)
33 #define m_WIN0_Y8_SWAP BITS(1, 17)
34 #define m_WIN0_UV_SWAP BITS(1, 18)
35 #define m_WIN1_RB_SWAP BITS(1, 19)
36 #define m_WIN1_ALPHA_SWAP BITS(1, 20)
37 #define m_WIN1_ENDIAN_SWAP BITS(1, 21) /* rk312x */
38 #define m_WIN0_OTSD_DISABLE BITS(1, 22)
39 #define m_WIN1_OTSD_DISABLE BITS(1, 23)
40 #define m_DMA_BURST_LENGTH BITS(3, 24)
41 #define m_HWC_LODAD_EN BITS(1, 26)
42 #define m_WIN1_LUT_EN BITS(1, 27) /* rk312x */
43 #define m_DSP_LUT_EN BITS(1, 28) /* rk312x */
44 #define m_DMA_STOP BITS(1, 29)
45 #define m_LCDC_STANDBY BITS(1, 30)
46 #define m_AUTO_GATING_EN BITS(1, 31)
48 #define v_WIN0_EN(x) BITS_MASK(x, 1, 0)
49 #define v_WIN1_EN(x) BITS_MASK(x, 1, 1)
50 #define v_HWC_EN(x) BITS_MASK(x, 1, 2)
51 #define v_WIN0_FORMAT(x) BITS_MASK(x, 7, 3)
52 #define v_WIN1_FORMAT(x) BITS_MASK(x, 7, 6)
53 #define v_HWC_LUT_EN(x) BITS_MASK(x, 1, 9)
54 #define v_HWC_SIZE(x) BITS_MASK(x, 1, 10)
55 #define v_DIRECT_PATH_EN(x) BITS_MASK(x, 1, 11)
56 #define v_DIRECT_PATH_LAYER(x) BITS_MASK(x, 1, 12)
57 #define v_TVE_MODE_SEL(x) BITS_MASK(x, 1, 13)
58 #define v_TVE_DAC_EN(x) BITS_MASK(x, 1, 14)
59 #define v_WIN0_RB_SWAP(x) BITS_MASK(x, 1, 15)
60 #define v_WIN0_ALPHA_SWAP(x) BITS_MASK(x, 1, 16)
61 #define v_WIN0_Y8_SWAP(x) BITS_MASK(x, 1, 17)
62 #define v_WIN0_UV_SWAP(x) BITS_MASK(x, 1, 18)
63 #define v_WIN1_RB_SWAP(x) BITS_MASK(x, 1, 19)
64 #define v_WIN1_ALPHA_SWAP(x) BITS_MASK(x, 1, 20)
65 #define v_WIN1_ENDIAN_SWAP(x) BITS_MASK(x, 1, 21)
66 #define v_WIN0_OTSD_DISABLE(x) BITS_MASK(x, 1, 22)
67 #define v_WIN1_OTSD_DISABLE(x) BITS_MASK(x, 1, 23)
68 #define v_DMA_BURST_LENGTH(x) BITS_MASK(x, 3, 24)
69 #define v_HWC_LODAD_EN(x) BITS_MASK(x, 1, 26)
70 #define v_WIN1_LUT_EN(x) BITS_MASK(x, 1, 27)
71 #define v_DSP_LUT_EN(x) BITS_MASK(x, 1, 28)
72 #define v_DMA_STOP(x) BITS_MASK(x, 1, 29)
73 #define v_LCDC_STANDBY(x) BITS_MASK(x, 1, 30)
74 #define v_AUTO_GATING_EN(x) BITS_MASK(x, 1, 31)
76 #define DSP_CTRL0 (0x04)
77 #define m_DSP_OUT_FORMAT BITS(0x0f, 0)
78 #define m_HSYNC_POL BITS(1, 4)
79 #define m_VSYNC_POL BITS(1, 5)
80 #define m_DEN_POL BITS(1, 6)
81 #define m_DCLK_POL BITS(1, 7)
82 #define m_WIN0_TOP BITS(1, 8)
83 #define m_DITHER_UP_EN BITS(1, 9)
84 #define m_DITHER_DOWN_MODE BITS(1, 10) /* use for rk312x */
85 #define m_DITHER_DOWN_EN BITS(1, 11) /* use for rk312x */
86 #define m_INTERLACE_DSP_EN BITS(1, 12)
87 #define m_INTERLACE_FIELD_POL BITS(1, 13) /* use for rk312x */
88 #define m_WIN0_INTERLACE_EN BITS(1, 14) /* use for rk312x */
89 #define m_WIN1_INTERLACE_EN BITS(1, 15)
90 #define m_WIN0_YRGB_DEFLICK_EN BITS(1, 16)
91 #define m_WIN0_CBR_DEFLICK_EN BITS(1, 17)
92 #define m_WIN0_ALPHA_MODE BITS(1, 18)
93 #define m_WIN1_ALPHA_MODE BITS(1, 19)
94 #define m_WIN0_CSC_MODE BITS(3, 20)
95 #define m_WIN1_CSC_MODE BITS(1, 22)
96 #define m_WIN0_YUV_CLIP BITS(1, 23)
97 #define m_TVE_MODE BITS(1, 25)
98 #define m_SW_UV_OFFSET_EN BITS(1, 26) /* use for rk312x */
99 #define m_DITHER_DOWN_SEL BITS(1, 27) /* use for rk312x */
100 #define m_HWC_ALPHA_MODE BITS(1, 28)
101 #define m_ALPHA_MODE_SEL0 BITS(1, 29)
102 #define m_ALPHA_MODE_SEL1 BITS(1, 30)
103 #define m_WIN1_DIFF_DCLK_EN BITS(1, 31) /* use for rk3036 */
104 #define m_SW_OVERLAY_MODE BITS(1, 31) /* use for rk312x */
106 #define v_DSP_OUT_FORMAT(x) BITS_MASK(x, 0x0f, 0)
107 #define v_HSYNC_POL(x) BITS_MASK(x, 1, 4)
108 #define v_VSYNC_POL(x) BITS_MASK(x, 1, 5)
109 #define v_DEN_POL(x) BITS_MASK(x, 1, 6)
110 #define v_DCLK_POL(x) BITS_MASK(x, 1, 7)
111 #define v_WIN0_TOP(x) BITS_MASK(x, 1, 8)
112 #define v_DITHER_UP_EN(x) BITS_MASK(x, 1, 9)
113 #define v_DITHER_DOWN_MODE(x) BITS_MASK(x, 1, 10) /* rk312x */
114 #define v_DITHER_DOWN_EN(x) BITS_MASK(x, 1, 11) /* rk312x */
115 #define v_INTERLACE_DSP_EN(x) BITS_MASK(x, 1, 12)
116 #define v_INTERLACE_FIELD_POL(x) BITS_MASK(x, 1, 13) /* rk312x */
117 #define v_WIN0_INTERLACE_EN(x) BITS_MASK(x, 1, 14) /* rk312x */
118 #define v_WIN1_INTERLACE_EN(x) BITS_MASK(x, 1, 15)
119 #define v_WIN0_YRGB_DEFLICK_EN(x) BITS_MASK(x, 1, 16)
120 #define v_WIN0_CBR_DEFLICK_EN(x) BITS_MASK(x, 1, 17)
121 #define v_WIN0_ALPHA_MODE(x) BITS_MASK(x, 1, 18)
122 #define v_WIN1_ALPHA_MODE(x) BITS_MASK(x, 1, 19)
123 #define v_WIN0_CSC_MODE(x) BITS_MASK(x, 3, 20)
124 #define v_WIN1_CSC_MODE(x) BITS_MASK(x, 1, 22)
125 #define v_WIN0_YUV_CLIP(x) BITS_MASK(x, 1, 23)
126 #define v_TVE_MODE(x) BITS_MASK(x, 1, 25)
127 #define v_SW_UV_OFFSET_EN(x) BITS_MASK(x, 1, 26) /* rk312x */
128 #define v_DITHER_DOWN_SEL(x) BITS_MASK(x, 1, 27) /* rk312x */
129 #define v_HWC_ALPHA_MODE(x) BITS_MASK(x, 1, 28)
130 #define v_ALPHA_MODE_SEL0(x) BITS_MASK(x, 1, 29)
131 #define v_ALPHA_MODE_SEL1(x) BITS_MASK(x, 1, 30)
132 #define v_WIN1_DIFF_DCLK_EN(x) BITS_MASK(x, 1, 31) /* rk3036 */
133 #define v_SW_OVERLAY_MODE(x) BITS_MASK(x, 1, 31) /* rk312x */
135 #define DSP_CTRL1 (0x08)
136 #define m_BG_COLOR BITS(0xffffff, 0)
137 #define m_BG_B BITS(0xff, 0)
138 #define m_BG_G BITS(0xff, 8)
139 #define m_BG_R BITS(0xff, 16)
140 #define m_BLANK_EN BITS(1, 24)
141 #define m_BLACK_EN BITS(1, 25)
142 #define m_DSP_BG_SWAP BITS(1, 26)
143 #define m_DSP_RB_SWAP BITS(1, 27)
144 #define m_DSP_RG_SWAP BITS(1, 28)
145 #define m_DSP_DELTA_SWAP BITS(1, 29) /* rk3036 */
146 #define m_DSP_DUMMY_SWAP BITS(1, 30) /* rk3036 */
147 #define m_DSP_OUT_ZERO BITS(1, 31)
149 #define v_BG_COLOR(x) BITS_MASK(x, 0xffffff, 0)
150 #define v_BG_B(x) BITS_MASK(x, 0xff, 0)
151 #define v_BG_G(x) BITS_MASK(x, 0xff, 8)
152 #define v_BG_R(x) BITS_MASK(x, 0xff, 16)
153 #define v_BLANK_EN(x) BITS_MASK(x, 1, 24)
154 #define v_BLACK_EN(x) BITS_MASK(x, 1, 25)
155 #define v_DSP_BG_SWAP(x) BITS_MASK(x, 1, 26)
156 #define v_DSP_RB_SWAP(x) BITS_MASK(x, 1, 27)
157 #define v_DSP_RG_SWAP(x) BITS_MASK(x, 1, 28)
158 #define v_DSP_DELTA_SWAP(x) BITS_MASK(x, 1, 29) /* rk3036 */
159 #define v_DSP_DUMMY_SWAP(x) BITS_MASK(x, 1, 30) /* rk3036 */
160 #define v_DSP_OUT_ZERO(x) BITS_MASK(x, 1, 31)
162 #define INT_SCALER (0x0c) /* only use for rk312x */
163 #define m_SCALER_EMPTY_INTR_EN BITS(1, 0)
164 #define m_SCLAER_EMPTY_INTR_CLR BITS(1, 1)
165 #define m_SCLAER_EMPTY_INTR_STA BITS(1, 2)
166 #define m_FS_MASK_EN BITS(1, 3)
167 #define m_HDMI_HSYNC_POL BITS(1, 4)
168 #define m_HDMI_VSYNC_POL BITS(1, 5)
169 #define m_HDMI_DEN_POL BITS(1, 6)
171 #define v_SCALER_EMPTY_INTR_EN(x) BITS_MASK(x, 1, 0)
172 #define v_SCLAER_EMPTY_INTR_CLR(x) BITS_MASK(x, 1, 1)
173 #define v_SCLAER_EMPTY_INTR_STA(x) BITS_MASK(x, 1, 2)
174 #define v_FS_MASK_EN(x) BITS_MASK(x, 1, 3)
175 #define v_HDMI_HSYNC_POL(x) BITS_MASK(x, 1, 4)
176 #define v_HDMI_VSYNC_POL(x) BITS_MASK(x, 1, 5)
177 #define v_HDMI_DEN_POL(x) BITS_MASK(x, 1, 6)
179 #define INT_STATUS (0x10)
180 #define m_HS_INT_STA BITS(1, 0)
181 #define m_FS_INT_STA BITS(1, 1)
182 #define m_LF_INT_STA BITS(1, 2)
183 #define m_BUS_ERR_INT_STA BITS(1, 3)
184 #define m_HS_INT_EN BITS(1, 4)
185 #define m_FS_INT_EN BITS(1, 5)
186 #define m_LF_INT_EN BITS(1, 6)
187 #define m_BUS_ERR_INT_EN BITS(1, 7)
188 #define m_HS_INT_CLEAR BITS(1, 8)
189 #define m_FS_INT_CLEAR BITS(1, 9)
190 #define m_LF_INT_CLEAR BITS(1, 10)
191 #define m_BUS_ERR_INT_CLEAR BITS(1, 11)
192 #define m_LF_INT_NUM BITS(0xfff, 12)
193 #define m_WIN0_EMPTY_INT_EN BITS(1, 24)
194 #define m_WIN1_EMPTY_INT_EN BITS(1, 25)
195 #define m_WIN0_EMPTY_INT_CLEAR BITS(1, 26)
196 #define m_WIN1_EMPTY_INT_CLEAR BITS(1, 27)
197 #define m_WIN0_EMPTY_INT_STA BITS(1, 28)
198 #define m_WIN1_EMPTY_INT_STA BITS(1, 29)
199 #define m_FS_RAW_STA BITS(1, 30)
200 #define m_LF_RAW_STA BITS(1, 31)
202 #define v_HS_INT_EN(x) BITS_MASK(x, 1, 4)
203 #define v_FS_INT_EN(x) BITS_MASK(x, 1, 5)
204 #define v_LF_INT_EN(x) BITS_MASK(x, 1, 6)
205 #define v_BUS_ERR_INT_EN(x) BITS_MASK(x, 1, 7)
206 #define v_HS_INT_CLEAR(x) BITS_MASK(x, 1, 8)
207 #define v_FS_INT_CLEAR(x) BITS_MASK(x, 1, 9)
208 #define v_LF_INT_CLEAR(x) BITS_MASK(x, 1, 10)
209 #define v_BUS_ERR_INT_CLEAR(x) BITS_MASK(x, 1, 11)
210 #define v_LF_INT_NUM(x) BITS_MASK(x, 0xfff, 12)
211 #define v_WIN0_EMPTY_INT_EN(x) BITS_MASK(x, 1, 24)
212 #define v_WIN1_EMPTY_INT_EN(x) BITS_MASK(x, 1, 25)
213 #define v_WIN0_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 26)
214 #define v_WIN1_EMPTY_INT_CLEAR(x) BITS_MASK(x, 1, 27)
216 #define ALPHA_CTRL (0x14)
217 #define m_WIN0_ALPHA_EN BITS(1, 0)
218 #define m_WIN1_ALPHA_EN BITS(1, 1)
219 #define m_HWC_ALPAH_EN BITS(1, 2)
220 #define m_WIN1_PREMUL_SCALE BITS(1, 3) /* rk3036 */
221 #define m_WIN0_ALPHA_VAL BITS(0xff, 4)
222 #define m_WIN1_ALPHA_VAL BITS(0xff, 12)
223 #define m_HWC_ALPAH_VAL BITS(0xff, 20)
225 #define v_WIN0_ALPHA_EN(x) BITS_MASK(x, 1, 0)
226 #define v_WIN1_ALPHA_EN(x) BITS_MASK(x, 1, 1)
227 #define v_HWC_ALPAH_EN(x) BITS_MASK(x, 1, 2)
228 #define v_WIN1_PREMUL_SCALE(x) BITS_MASK(x, 1, 3) /* rk3036 */
229 #define v_WIN0_ALPHA_VAL(x) BITS_MASK(x, 0xff, 4)
230 #define v_WIN1_ALPHA_VAL(x) BITS_MASK(x, 0xff, 12)
231 #define v_HWC_ALPAH_VAL(x) BITS_MASK(x, 0xff, 20)
233 #define WIN0_COLOR_KEY (0x18)
234 #define WIN1_COLOR_KEY (0x1c)
235 #define m_COLOR_KEY_VAL BITS(0xffffff, 0)
236 #define m_COLOR_KEY_EN BITS(1, 24)
238 #define v_COLOR_KEY_VAL(x) BITS_MASK(x, 0xffffff, 0)
239 #define v_COLOR_KEY_EN(x) BITS_MASK(x, 1, 24)
241 /* Layer Registers */
242 #define WIN0_YRGB_MST (0x20)
243 #define WIN0_CBR_MST (0x24)
244 #define WIN1_MST (0xa0) /* rk3036 */
245 #define WIN1_MST_RK312X (0x4c) /* rk312x */
246 #define HWC_MST (0x58)
248 #define WIN1_VIR (0x28)
249 #define WIN0_VIR (0x30)
250 #define m_YRGB_VIR BITS(0x1fff, 0)
251 #define m_CBBR_VIR BITS(0x1fff, 16)
253 #define v_YRGB_VIR(x) BITS_MASK(x, 0x1fff, 0)
254 #define v_CBBR_VIR(x) BITS_MASK(x, 0x1fff, 16)
256 #define v_ARGB888_VIRWIDTH(x) BITS_MASK(x, 0x1fff, 0)
257 #define v_RGB888_VIRWIDTH(x) BITS_MASK(((x*3)>>2)+((x)%3), 0x1fff, 0)
258 #define v_RGB565_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 2), 0x1fff, 0)
259 #define v_YUV_VIRWIDTH(x) BITS_MASK(DIV_ROUND_UP(x, 4), 0x1fff, 0)
260 #define v_CBCR_VIR(x) BITS_MASK(x, 0x1fff, 16)
262 #define WIN0_ACT_INFO (0x34)
263 #define WIN1_ACT_INFO (0xb4) /* rk3036 */
264 #define m_ACT_WIDTH BITS(0x1fff, 0)
265 #define m_ACT_HEIGHT BITS(0x1fff, 16)
267 #define v_ACT_WIDTH(x) BITS_MASK(x - 1, 0x1fff, 0)
268 #define v_ACT_HEIGHT(x) BITS_MASK(x - 1, 0x1fff, 16)
270 #define WIN0_DSP_INFO (0x38)
271 #define WIN1_DSP_INFO (0xb8) /* rk3036 */
272 #define WIN1_DSP_INFO_RK312X (0x50) /* rk312x */
273 #define m_DSP_WIDTH BITS(0x7ff, 0)
274 #define m_DSP_HEIGHT BITS(0x7ff, 16)
276 #define v_DSP_WIDTH(x) BITS_MASK(x - 1, 0x7ff, 0)
277 #define v_DSP_HEIGHT(x) BITS_MASK(x - 1, 0x7ff, 16)
279 #define WIN0_DSP_ST (0x3c)
280 #define WIN1_DSP_ST (0xbc) /* rk3036 */
281 #define WIN1_DSP_ST_RK312X (0x54) /* rk312x */
282 #define HWC_DSP_ST (0x5c)
283 #define m_DSP_STX BITS(0xfff, 0)
284 #define m_DSP_STY BITS(0xfff, 16)
286 #define v_DSP_STX(x) BITS_MASK(x, 0xfff, 0)
287 #define v_DSP_STY(x) BITS_MASK(x, 0xfff, 16)
289 #define WIN0_SCL_FACTOR_YRGB (0x40)
290 #define WIN0_SCL_FACTOR_CBR (0x44)
291 #define WIN1_SCL_FACTOR_YRGB (0xc0) /* rk3036 */
292 #define m_X_SCL_FACTOR BITS(0xffff, 0)
293 #define m_Y_SCL_FACTOR BITS(0xffff, 16)
295 #define v_X_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 0)
296 #define v_Y_SCL_FACTOR(x) BITS_MASK(x, 0xffff, 16)
298 #define WIN0_SCL_OFFSET (0x48)
299 #define WIN1_SCL_OFFSET (0xc8) /* rk3036 */
302 #define WIN1_LUT_ADDR (0x0400) /* rk3036 */
303 #define HWC_LUT_ADDR (0x0800)
304 #define DSP_LUT_ADDR (0x0c00) /* rk312x */
306 /* Display Infomation Registers */
307 #define DSP_HTOTAL_HS_END (0x6c)
308 #define v_HSYNC(x) BITS_MASK(x, 0xfff, 0) /* hsync pulse width */
309 #define v_HORPRD(x) BITS_MASK(x, 0xfff, 16) /* horizontal period */
311 #define DSP_HACT_ST_END (0x70)
312 #define v_HAEP(x) BITS_MASK(x, 0xfff, 0) /* horizontal active end point */
313 #define v_HASP(x) BITS_MASK(x, 0xfff, 16) /* horizontal active start point */
315 #define DSP_VTOTAL_VS_END (0x74)
316 #define v_VSYNC(x) BITS_MASK(x, 0xfff, 0)
317 #define v_VERPRD(x) BITS_MASK(x, 0xfff, 16)
319 #define DSP_VACT_ST_END (0x78)
320 #define v_VAEP(x) BITS_MASK(x, 0xfff, 0)
321 #define v_VASP(x) BITS_MASK(x, 0xfff, 16)
323 #define DSP_VS_ST_END_F1 (0x7c)
324 #define v_VSYNC_END_F1(x) BITS_MASK(x, 0xfff, 0)
325 #define v_VSYNC_ST_F1(x) BITS_MASK(x, 0xfff, 16)
326 #define DSP_VACT_ST_END_F1 (0x80)
327 #define v_VAEP_F1(x) BITS_MASK(x, 0xfff, 0)
328 #define v_VASP_F1(x) BITS_MASK(x, 0xfff, 16)
331 * Only used for rk312x
333 #define SCALER_CTRL (0xa0)
334 #define m_SCALER_EN BITS(1, 0)
335 #define m_SCALER_SYNC_INVERT BITS(1, 2)
336 #define m_SCALER_DEN_INVERT BITS(1, 3)
337 #define m_SCALER_OUT_ZERO BITS(1, 4)
338 #define m_SCALER_OUT_EN BITS(1, 5)
339 #define m_SCALER_VSYNC_MODE BITS(3, 6)
340 #define m_SCALER_VSYNC_VST BITS(0xff, 8)
342 #define v_SCALER_EN(x) BITS_MASK(x, 1, 0)
343 #define v_SCALER_SYNC_INVERT(x) BITS_MASK(x, 1, 2)
344 #define v_SCALER_DEN_INVERT(x) BITS_MASK(x, 1, 3)
345 #define v_SCALER_OUT_ZERO(x) BITS_MASK(x, 1, 4)
346 #define v_SCALER_OUT_EN(x) BITS_MASK(x, 1, 5)
347 #define v_SCALER_VSYNC_MODE(x) BITS_MASK(x, 3, 6)
348 #define v_SCALER_VSYNC_VST(x) BITS_MASK(x, 0xff, 8)
350 #define SCALER_FACTOR (0xa4)
351 #define m_SCALER_H_FACTOR BITS(0x3fff, 0)
352 #define m_SCALER_V_FACTOR BITS(0x3fff, 16)
354 #define v_SCALER_H_FACTOR(x) BITS_MASK(x, 0x3fff, 0)
355 #define v_SCALER_V_FACTOR(x) BITS_MASK(x, 0x3fff, 16)
357 #define SCALER_FRAME_ST (0xa8)
358 #define m_SCALER_FRAME_HST BITS(0xfff, 0)
359 #define m_SCALER_FRAME_VST BITS(0xfff, 16)
361 #define v_SCALER_FRAME_HST(x) BITS_MASK(x, 0xfff, 0)
362 #define v_SCALER_FRAME_VST(x) BITS_MASK(x, 0xfff, 16)
364 #define SCALER_DSP_HOR_TIMING (0xac)
365 #define m_SCALER_HTOTAL BITS(0xfff, 0)
366 #define m_SCALER_HS_END BITS(0xff, 16)
368 #define v_SCALER_HTOTAL(x) BITS_MASK(x, 0xfff, 0)
369 #define v_SCALER_HS_END(x) BITS_MASK(x, 0xff, 16)
371 #define SCALER_DSP_HACT_ST_END (0xb0)
372 #define m_SCALER_HAEP BITS(0xfff, 0)
373 #define m_SCALER_HASP BITS(0x3ff, 16)
375 #define v_SCALER_HAEP(x) BITS_MASK(x, 0xfff, 0)
376 #define v_SCALER_HASP(x) BITS_MASK(x, 0x3ff, 16)
378 #define SCALER_DSP_VER_TIMING (0xb4)
379 #define m_SCALER_VTOTAL BITS(0xfff, 0)
380 #define m_SCALER_VS_END BITS(0xff, 16)
382 #define v_SCALER_VTOTAL(x) BITS_MASK(x, 0xfff, 0)
383 #define v_SCALER_VS_END(x) BITS_MASK(x, 0xff, 16)
385 #define SCALER_DSP_VACT_ST_END (0xb8)
386 #define m_SCALER_VAEP BITS(0xfff, 0)
387 #define m_SCALER_VASP BITS(0xff, 16)
389 #define v_SCALER_VAEP(x) BITS_MASK(x, 0xfff, 0)
390 #define v_SCALER_VASP(x) BITS_MASK(x, 0xff, 16)
392 #define SCALER_DSP_HBOR_TIMING (0xbc)
393 #define m_SCALER_HBOR_END BITS(0xfff, 0)
394 #define m_SCALER_HBOR_ST BITS(0x3ff, 16)
396 #define v_SCALER_HBOR_END(x) BITS_MASK(x, 0xfff, 0)
397 #define v_SCALER_HBOR_ST(x) BITS_MASK(x, 0x3ff, 16)
399 #define SCALER_DSP_VBOR_TIMING (0xc0)
400 #define m_SCALER_VBOR_END BITS(0xfff, 0)
401 #define m_SCALER_VBOR_ST BITS(0xff, 16)
403 #define v_SCALER_VBOR_END(x) BITS_MASK(x, 0xfff, 0)
404 #define v_SCALER_VBOR_ST(x) BITS_MASK(x, 0xff, 16)
407 #define BCSH_CTRL (0xd0)
408 #define m_BCSH_EN BITS(1, 0)
409 #define m_BCSH_R2Y_CSC_MODE BITS(1, 1) /* rk312x */
410 #define m_BCSH_OUT_MODE BITS(3, 2)
411 #define m_BCSH_Y2R_CSC_MODE BITS(3, 4)
412 #define m_BCSH_Y2R_EN BITS(1, 6) /* rk312x */
413 #define m_BCSH_R2Y_EN BITS(1, 7) /* rk312x */
415 #define v_BCSH_EN(x) BITS_MASK(x, 1, 0)
416 #define v_BCSH_R2Y_CSC_MODE(x) BITS_MASK(x, 1, 1) /* rk312x */
417 #define v_BCSH_OUT_MODE(x) BITS_MASK(x, 3, 2)
418 #define v_BCSH_Y2R_CSC_MODE(x) BITS_MASK(x, 3, 4)
419 #define v_BCSH_Y2R_EN(x) BITS_MASK(x, 1, 6) /* rk312x */
420 #define v_BCSH_R2Y_EN(x) BITS_MASK(x, 1, 7) /* rk312x */
422 #define BCSH_COLOR_BAR (0xd4)
423 #define m_BCSH_COLOR_BAR_Y BITS(0xff, 0)
424 #define m_BCSH_COLOR_BAR_U BITS(0xff, 8)
425 #define m_BCSH_COLOR_BAR_V BITS(0xff, 16)
427 #define v_BCSH_COLOR_BAR_Y(x) BITS_MASK(x, 0xff, 0)
428 #define v_BCSH_COLOR_BAR_U(x) BITS_MASK(x, 0xff, 8)
429 #define v_BCSH_COLOR_BAR_V(x) BITS_MASK(x, 0xff, 16)
431 #define BCSH_BCS (0xd8)
432 #define m_BCSH_BRIGHTNESS BITS(0x1f, 0)
433 #define m_BCSH_CONTRAST BITS(0xff, 8)
434 #define m_BCSH_SAT_CON BITS(0x1ff, 16)
436 #define v_BCSH_BRIGHTNESS(x) BITS_MASK(x, 0x1f, 0)
437 #define v_BCSH_CONTRAST(x) BITS_MASK(x, 0xff, 8)
438 #define v_BCSH_SAT_CON(x) BITS_MASK(x, 0x1ff, 16)
440 #define BCSH_H (0xdc)
441 #define m_BCSH_SIN_HUE BITS(0xff, 0)
442 #define m_BCSH_COS_HUE BITS(0xff, 8)
444 #define v_BCSH_SIN_HUE(x) BITS_MASK(x, 0xff, 0)
445 #define v_BCSH_COS_HUE(x) BITS_MASK(x, 0xff, 8)
447 #define FRC_LOWER01_0 (0xe0)
448 #define FRC_LOWER01_1 (0xe4)
449 #define FRC_LOWER10_0 (0xe8)
450 #define FRC_LOWER10_1 (0xec)
451 #define FRC_LOWER11_0 (0xf0)
452 #define FRC_LOWER11_1 (0xf4)
455 #define AXI_BUS_CTRL (0x2c)
456 #define m_IO_PAD_CLK BITS(1, 31)
457 #define m_CORE_CLK_DIV_EN BITS(1, 30)
458 #define m_MIPI_DCLK_INVERT BITS(1, 29) /* rk312x */
459 #define m_MIPI_DCLK_EN BITS(1, 28) /* rk312x */
460 #define m_LVDS_DCLK_INVERT BITS(1, 27) /* rk312x */
461 #define m_LVDS_DCLK_EN BITS(1, 26) /* rk312x */
462 #define m_RGB_DCLK_INVERT BITS(1, 25) /* rk312x */
463 #define m_RGB_DCLK_EN BITS(1, 24) /* rk312x */
464 #define m_HDMI_DCLK_INVERT BITS(1, 23)
465 #define m_HDMI_DCLK_EN BITS(1, 22)
466 #define m_TVE_DAC_DCLK_INVERT BITS(1, 21)
467 #define m_TVE_DAC_DCLK_EN BITS(1, 20)
468 #define m_HDMI_DCLK_DIV_EN BITS(1, 19)
469 #define m_AXI_OUTSTANDING_MAX_NUM BITS(0x1f, 12)
470 #define m_AXI_MAX_OUTSTANDING_EN BITS(1, 11)
471 #define m_MMU_EN BITS(1, 10)
472 #define m_NOC_HURRY_THRESHOLD BITS(0xf, 6)
473 #define m_NOC_HURRY_VALUE BITS(3, 4)
474 #define m_NOC_HURRY_EN BITS(1, 3)
475 #define m_NOC_QOS_VALUE BITS(3, 1)
476 #define m_NOC_QOS_EN BITS(1, 0)
478 #define v_IO_PAD_CLK(x) BITS_MASK(x, 1, 31)
479 #define v_CORE_CLK_DIV_EN(x) BITS_MASK(x, 1, 30)
480 #define v_MIPI_DCLK_INVERT(x) BITS_MASK(x, 1, 29)
481 #define v_MIPI_DCLK_EN(x) BITS_MASK(x, 1, 28)
482 #define v_LVDS_DCLK_INVERT(x) BITS_MASK(x, 1, 27)
483 #define v_LVDS_DCLK_EN(x) BITS_MASK(x, 1, 26)
484 #define v_RGB_DCLK_INVERT(x) BITS_MASK(x, 1, 25)
485 #define v_RGB_DCLK_EN(x) BITS_MASK(x, 1, 24)
486 #define v_HDMI_DCLK_INVERT(x) BITS_MASK(x, 1, 23)
487 #define v_HDMI_DCLK_EN(x) BITS_MASK(x, 1, 22)
488 #define v_TVE_DAC_DCLK_INVERT(x) BITS_MASK(x, 1, 21)
489 #define v_TVE_DAC_DCLK_EN(x) BITS_MASK(x, 1, 20)
490 #define v_HDMI_DCLK_DIV_EN(x) BITS_MASK(x, 1, 19)
491 #define v_AXI_OUTSTANDING_MAX_NUM(x) BITS_MASK(x, 0x1f, 12)
492 #define v_AXI_MAX_OUTSTANDING_EN(x) BITS_MASK(x, 1, 11)
493 #define v_MMU_EN(x) BITS_MASK(x, 1, 10)
494 #define v_NOC_HURRY_THRESHOLD(x) BITS_MASK(x, 0xf, 6)
495 #define v_NOC_HURRY_VALUE(x) BITS_MASK(x, 3, 4)
496 #define v_NOC_HURRY_EN(x) BITS_MASK(x, 1, 3)
497 #define v_NOC_QOS_VALUE(x) BITS_MASK(x, 3, 1)
498 #define v_NOC_QOS_EN(x) BITS_MASK(x, 1, 0)
500 #define GATHER_TRANSFER (0x84)
501 #define m_WIN1_AXI_GATHER_NUM BITS(0xf, 12)
502 #define m_WIN0_CBCR_AXI_GATHER_NUM BITS(0x7, 8)
503 #define m_WIN0_YRGB_AXI_GATHER_NUM BITS(0xf, 4)
504 #define m_WIN1_AXI_GAHTER_EN BITS(1, 2)
505 #define m_WIN0_CBCR_AXI_GATHER_EN BITS(1, 1)
506 #define m_WIN0_YRGB_AXI_GATHER_EN BITS(1, 0)
508 #define v_WIN1_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 12)
509 #define v_WIN0_CBCR_AXI_GATHER_NUM(x) BITS_MASK(x, 0x7, 8)
510 #define v_WIN0_YRGB_AXI_GATHER_NUM(x) BITS_MASK(x, 0xf, 4)
511 #define v_WIN1_AXI_GAHTER_EN(x) BITS_MASK(x, 1, 2)
512 #define v_WIN0_CBCR_AXI_GATHER_EN(x) BITS_MASK(x, 1, 1)
513 #define v_WIN0_YRGB_AXI_GATHER_EN(x) BITS_MASK(x, 1, 0)
515 #define VERSION_INFO (0x94)
516 #define m_MAJOR BITS(0xff, 24)
517 #define m_MINOR BITS(0xff, 16)
518 #define m_BUILD BITS(0xffff)
520 #define REG_CFG_DONE (0x90)
522 /* TV Control Registers */
523 #define TV_CTRL (0x200)
524 #define TV_SYNC_TIMING (0x204)
525 #define TV_ACT_TIMING (0x208)
526 #define TV_ADJ_TIMING (0x20c)
527 #define TV_FREQ_SC (0x210)
528 #define TV_FILTER0 (0x214)
529 #define TV_FILTER1 (0x218)
530 #define TV_FILTER2 (0x21C)
531 #define TV_ACT_ST (0x234)
532 #define TV_ROUTING (0x238)
533 #define TV_SYNC_ADJUST (0x250)
534 #define TV_STATUS (0x254)
535 #define TV_RESET (0x268)
536 #define TV_SATURATION (0x278)
537 #define TV_BW_CTRL (0x28C)
538 #define TV_BRIGHTNESS_CONTRAST (0x290)
542 #define MMU_DTE_ADDR (0x0300)
543 #define m_MMU_DTE_ADDR BITS(0xffffffff, 0)
544 #define v_MMU_DTE_ADDR(x) BITS_MASK(x, 0xffffffff, 0)
546 #define MMU_STATUS (0x0304)
547 #define m_PAGING_ENABLED BITS(1, 0)
548 #define m_PAGE_FAULT_ACTIVE BITS(1, 1)
549 #define m_STAIL_ACTIVE BITS(1, 2)
550 #define m_MMU_IDLE BITS(1, 3)
551 #define m_REPLAY_BUFFER_EMPTY BITS(1, 4)
552 #define m_PAGE_FAULT_IS_WRITE BITS(1, 5)
553 #define m_PAGE_FAULT_BUS_ID BITS(0x1f, 6)
555 #define v_PAGING_ENABLED(x) BITS_MASK(x, 1, 0)
556 #define v_PAGE_FAULT_ACTIVE(x) BITS_MASK(x, 1, 1)
557 #define v_STAIL_ACTIVE(x) BITS_MASK(x, 1, 2)
558 #define v_MMU_IDLE(x) BITS_MASK(x, 1, 3)
559 #define v_REPLAY_BUFFER_EMPTY(x) BITS_MASK(x, 1, 4)
560 #define v_PAGE_FAULT_IS_WRITE(x) BITS_MASK(x, 1, 5)
561 #define v_PAGE_FAULT_BUS_ID(x) BITS_MASK(x, 0x1f, 6)
563 #define MMU_COMMAND (0x0308)
564 #define m_MMU_CMD BITS(0x7, 0)
565 #define v_MMU_CMD(x) BITS_MASK(x, 0x7, 0)
567 #define MMU_PAGE_FAULT_ADDR (0x030c)
568 #define m_PAGE_FAULT_ADDR BITS(0xffffffff, 0)
569 #define v_PAGE_FAULT_ADDR(x) BITS_MASK(x, 0xffffffff, 0)
571 #define MMU_ZAP_ONE_LINE (0x0310)
572 #define m_MMU_ZAP_ONE_LINE BITS(0xffffffff, 0)
573 #define v_MMU_ZAP_ONE_LINE(x) BITS_MASK(x, 0xffffffff, 0)
575 #define MMU_INT_RAWSTAT (0x0314)
576 #define m_PAGE_FAULT_RAWSTAT BITS(1, 0)
577 #define m_READ_BUS_ERROR_RAWSTAT BITS(1, 1)
579 #define v_PAGE_FAULT_RAWSTAT(x) BITS(x, 1, 0)
580 #define v_READ_BUS_ERROR_RAWSTAT(x) BITS(x, 1, 1)
582 #define MMU_INT_CLEAR (0x0318)
583 #define m_PAGE_FAULT_CLEAR BITS(1, 0)
584 #define m_READ_BUS_ERROR_CLEAR BITS(1, 1)
586 #define v_PAGE_FAULT_CLEAR(x) BITS(x, 1, 0)
587 #define v_READ_BUS_ERROR_CLEAR(x) BITS(x, 1, 1)
589 #define MMU_INT_MASK (0x031c)
590 #define m_PAGE_FAULT_MASK BITS(1, 0)
591 #define m_READ_BUS_ERROR_MASK BITS(1, 1)
593 #define v_PAGE_FAULT_MASK(x) BITS(x, 1, 0)
594 #define v_READ_BUS_ERROR_MASK(x) BITS(x, 1, 1)
596 #define MMU_INT_STATUS (0x0320)
597 #define m_PAGE_FAULT_STATUS BITS(1, 0)
598 #define m_READ_BUS_ERROR_STATUS BITS(1, 1)
600 #define v_PAGE_FAULT_STATUS(x) BITS(x, 1, 0)
601 #define v_READ_BUS_ERROR_STATUS(x) BITS(x, 1, 1)
603 #define MMU_AUTO_GATING (0x0324)
604 #define m_MMU_AUTO_GATING BITS(1, 0)
605 #define v_MMU_AUTO_GATING(x) BITS(x, 1, 0)
608 enum _vop_dma_burst {
615 VOP_FORMAT_ARGB888 = 0,
618 VOP_FORMAT_YCBCR420 = 4,
628 enum _vop_r2y_csc_mode {
629 VOP_R2Y_CSC_BT601 = 0,
633 enum _vop_y2r_csc_mode {
634 VOP_Y2R_CSC_MPEG = 0,
645 enum _vop_overlay_mode {
651 #define CalScale(x, y) ((((u32)(x - 1)) * 0x1000) / (y - 1))
652 #define INT_STA_MSK (m_HS_INT_STA | m_FS_INT_STA | \
653 m_LF_INT_STA | m_BUS_ERR_INT_STA)
654 #define INT_CLR_SHIFT 8
656 struct rk_lcdc_drvdata {
664 struct rk_lcdc_driver driver;
666 struct rk_screen *screen;
669 void *regsbak; /* back up reg */
670 u32 reg_phy_base; /* physical basic address of lcdc register */
671 u32 len; /* physical map length of lcdc register */
672 spinlock_t reg_lock; /* one time only one process allowed to config the register */
674 int __iomem *hwc_lut_addr_base;
675 int __iomem *dsp_lut_addr_base;
677 int prop; /* used for primary or extended display device */
679 bool pwr18; /* if lcdc use 1.8v power supply */
680 bool clk_on; /* if aclk or hclk is closed ,acess to register is not allowed */
681 bool sclk_on; /* if sclk is open or closed */
682 u8 atv_layer_cnt; /* active layer counter,when atv_layer_cnt = 0,lcdc is disable*/
686 struct clk *pd; /* lcdc power domain */
687 struct clk *hclk; /* lcdc AHP clk */
688 struct clk *dclk; /* lcdc dclk */
689 struct clk *aclk; /* lcdc share memory frequency */
690 struct clk *sclk; /* scaler clk */
691 struct clk *pll_sclk;
695 u32 standby; /* 1:standby,0:work */
696 struct backlight_device *backlight;
700 static inline void lcdc_writel(struct lcdc_device *lcdc_dev, u32 offset, u32 v)
702 u32 *_pv = (u32*)lcdc_dev->regsbak;
703 _pv += (offset >> 2);
705 writel_relaxed(v, lcdc_dev->regs + offset);
708 static inline u32 lcdc_readl(struct lcdc_device *lcdc_dev, u32 offset)
711 v = readl_relaxed(lcdc_dev->regs + offset);
715 static inline u32 lcdc_readl_backup(struct lcdc_device *lcdc_dev, u32 offset)
718 u32 *_pv = (u32*)lcdc_dev->regsbak;
719 _pv += (offset >> 2);
720 v = readl_relaxed(lcdc_dev->regs + offset);
725 static inline u32 lcdc_read_bit(struct lcdc_device *lcdc_dev, u32 offset,
728 u32 _v = readl_relaxed(lcdc_dev->regs + offset);
733 static inline void lcdc_set_bit(struct lcdc_device *lcdc_dev, u32 offset,
736 u32* _pv = (u32*)lcdc_dev->regsbak;
737 _pv += (offset >> 2);
739 writel_relaxed(*_pv, lcdc_dev->regs + offset);
742 static inline void lcdc_clr_bit(struct lcdc_device *lcdc_dev, u32 offset,
745 u32* _pv = (u32*)lcdc_dev->regsbak;
746 _pv += (offset >> 2);
748 writel_relaxed(*_pv, lcdc_dev->regs + offset);
751 static inline void lcdc_msk_reg(struct lcdc_device *lcdc_dev, u32 offset,
754 u32 *_pv = (u32*)lcdc_dev->regsbak;
755 _pv += (offset >> 2);
758 writel_relaxed(*_pv, lcdc_dev->regs + offset);
761 static inline void lcdc_cfg_done(struct lcdc_device *lcdc_dev)
763 writel_relaxed(0x01, lcdc_dev->regs + REG_CFG_DONE);
767 #endif /* _RK312X_LCDC_H_ */