2 * drivers/video/rockchip/lcdc/rk322x_lcdc.c
4 * Copyright (C) 2015 ROCKCHIP, Inc.
5 * Author: Mark Yao <mark.yao@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/of_device.h>
28 #include <linux/platform_device.h>
29 #include <linux/clk.h>
30 #include <linux/rockchip-iovmm.h>
31 #include <asm/div64.h>
32 #include <linux/uaccess.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk322x_lcdc.h"
40 /*#define CONFIG_RK_FPGA 1*/
41 #define VOP_CHIP(dev) (dev->data->chip_type)
43 static int dbg_thresd;
44 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
46 #define DBG(level, x...) do { \
47 if (unlikely(dbg_thresd >= level)) \
51 static struct rk_lcdc_win rk322x_vop_win[] = {
54 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
55 SUPPORT_SCALE | SUPPORT_YUV |
57 .property.max_input_x = 4096,
58 .property.max_input_y = 2304},
61 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
62 SUPPORT_SCALE | SUPPORT_YUV |
64 .property.max_input_x = 4096,
65 .property.max_input_y = 2304},
69 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
71 .property.max_input_x = 128,
72 .property.max_input_y = 128
76 static struct rk_lcdc_win rk3399_vop_win[] = {
79 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
80 SUPPORT_SCALE | SUPPORT_YUV |
82 .property.max_input_x = 4096,
83 .property.max_input_y = 2304},
86 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
87 SUPPORT_SCALE | SUPPORT_YUV |
89 .property.max_input_x = 4096,
90 .property.max_input_y = 2304},
93 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
95 .property.max_input_x = 4096,
96 .property.max_input_y = 2304},
99 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
101 .property.max_input_x = 4096,
102 .property.max_input_y = 2304},
106 .property.feature = SUPPORT_WIN_IDENTIFY | SUPPORT_HW_EXIST |
108 .property.max_input_x = 128,
109 .property.max_input_y = 128
113 static const struct vop_data rk322x_data = {
114 .chip_type = VOP_RK322X,
115 .win = rk322x_vop_win,
116 .n_wins = ARRAY_SIZE(rk322x_vop_win),
119 static const struct vop_data rk3399_data = {
120 .chip_type = VOP_RK3399,
121 .win = rk3399_vop_win,
122 .n_wins = ARRAY_SIZE(rk3399_vop_win),
125 #if defined(CONFIG_OF)
126 static const struct of_device_id vop_dt_ids[] = {
127 {.compatible = "rockchip,rk322x-lcdc",
128 .data = &rk322x_data, },
129 {.compatible = "rockchip,rk3399-lcdc",
130 .data = &rk3399_data, },
135 static const u32 csc_y2r_bt601_limit[12] = {
136 0x04a8, 0, 0x0662, 0xfffc8654,
137 0x04a8, 0xfe6f, 0xfcbf, 0x00022056,
138 0x04a8, 0x0812, 0, 0xfffbaeac,
141 static const u32 csc_y2r_bt709_full[12] = {
142 0x04a8, 0, 0x072c, 0xfffc219e,
143 0x04a8, 0xff26, 0xfdde, 0x0001357b,
144 0x04a8, 0x0873, 0, 0xfffb7dee,
147 static const u32 csc_y2r_bt601_full[12] = {
148 0x0400, 0, 0x059c, 0xfffd342d,
149 0x0400, 0xfea0, 0xfd25, 0x00021fcc,
150 0x0400, 0x0717, 0, 0xfffc76bc,
153 static const u32 csc_y2r_bt601_limit_10[12] = {
154 0x04a8, 0, 0x0662, 0xfff2134e,
155 0x04a8, 0xfe6f, 0xfcbf, 0x00087b58,
156 0x04a8, 0x0812, 0, 0xffeeb4b0,
159 static const u32 csc_y2r_bt709_full_10[12] = {
160 0x04a8, 0, 0x072c, 0xfff08077,
161 0x04a8, 0xff26, 0xfdde, 0x0004cfed,
162 0x04a8, 0x0873, 0, 0xffedf1b8,
165 static const u32 csc_y2r_bt601_full_10[12] = {
166 0x0400, 0, 0x059c, 0xfff4cab4,
167 0x0400, 0xfea0, 0xfd25, 0x00087932,
168 0x0400, 0x0717, 0, 0xfff1d4f2,
171 static const u32 csc_y2r_bt2020[12] = {
172 0x04a8, 0, 0x06b6, 0xfff16bfc,
173 0x04a8, 0xff40, 0xfd66, 0x58ae9,
174 0x04a8, 0x0890, 0, 0xffedb828,
177 static const u32 csc_r2y_bt601_limit[12] = {
178 0x0107, 0x0204, 0x0064, 0x04200,
179 0xff68, 0xfed6, 0x01c2, 0x20200,
180 0x01c2, 0xfe87, 0xffb7, 0x20200,
183 static const u32 csc_r2y_bt709_full[12] = {
184 0x00bb, 0x0275, 0x003f, 0x04200,
185 0xff99, 0xfea5, 0x01c2, 0x20200,
186 0x01c2, 0xfe68, 0xffd7, 0x20200,
189 static const u32 csc_r2y_bt601_full[12] = {
190 0x0132, 0x0259, 0x0075, 0x200,
191 0xff53, 0xfead, 0x0200, 0x20200,
192 0x0200, 0xfe53, 0xffad, 0x20200,
195 static const u32 csc_r2y_bt601_limit_10[12] = {
196 0x0107, 0x0204, 0x0064, 0x10200,
197 0xff68, 0xfed6, 0x01c2, 0x80200,
198 0x01c2, 0xfe87, 0xffb7, 0x80200,
201 static const u32 csc_r2y_bt709_full_10[12] = {
202 0x00bb, 0x0275, 0x003f, 0x10200,
203 0xff99, 0xfea5, 0x01c2, 0x80200,
204 0x01c2, 0xfe68, 0xffd7, 0x80200,
207 static const u32 csc_r2y_bt601_full_10[12] = {
208 0x0132, 0x0259, 0x0075, 0x200,
209 0xff53, 0xfead, 0x0200, 0x80200,
210 0x0200, 0xfe53, 0xffad, 0x80200,
213 static const u32 csc_r2y_bt2020[12] = {
214 0x00e6, 0x0253, 0x0034, 0x10200,
215 0xff83, 0xfebd, 0x01c1, 0x80200,
216 0x01c1, 0xfe64, 0xffdc, 0x80200,
219 static const u32 csc_r2r_bt2020to709[12] = {
220 0x06a4, 0xfda6, 0xffb5, 0x200,
221 0xff80, 0x0488, 0xfff8, 0x200,
222 0xffed, 0xff99, 0x047a, 0x200,
225 static const u32 csc_r2r_bt709to2020[12] = {
226 0x282, 0x151, 0x02c, 0x200,
227 0x047, 0x3ae, 0x00c, 0x200,
228 0x011, 0x05a, 0x395, 0x200,
231 static int vop_get_id(struct vop_device *vop_dev, u32 phy_base)
233 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
234 if (phy_base == 0xff900000) /* vop big */
236 else if (phy_base == 0xff8f0000) /* vop lit */
245 static void vop_load_csc_table(struct vop_device *vop_dev, u32 offset,
250 csc_val = table[1] << 16 | table[0];
251 vop_writel(vop_dev, offset, csc_val);
252 csc_val = table[4] << 16 | table[2];
253 vop_writel(vop_dev, offset + 4, csc_val);
254 csc_val = table[6] << 16 | table[5];
255 vop_writel(vop_dev, offset + 8, csc_val);
256 csc_val = table[9] << 16 | table[8];
257 vop_writel(vop_dev, offset + 0xc, csc_val);
259 vop_writel(vop_dev, offset + 0x10, csc_val);
261 vop_writel(vop_dev, offset + 0x14, csc_val);
263 vop_writel(vop_dev, offset + 0x18, csc_val);
265 vop_writel(vop_dev, offset + 0x1c, csc_val);
268 #define LOAD_CSC(dev, mode, table, win_id) \
269 vop_load_csc_table(dev, \
270 WIN0_YUV2YUV_##mode + 0x60 * win_id, \
273 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
275 static int vop_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
277 struct vop_device *vop_dev =
278 container_of(dev_drv, struct vop_device, driver);
281 if (!vop_dev->dsp_lut_addr_base) {
282 dev_warn(vop_dev->dev, "not support dsp lut config\n");
287 dev_err(vop_dev->dev, "dsp lut table is null\n");
291 spin_lock(&vop_dev->reg_lock);
292 for (i = 0; i < 256; i++) {
297 c = vop_dev->dsp_lut_addr_base + (i << 2);
299 g = (v & 0xff00) << 4;
300 r = (v & 0xff0000) << 6;
302 for (j = 0; j < 4; j++) {
303 writel_relaxed(v, c);
304 v += (1 + (1 << 10) + (1 << 20));
308 vop_msk_reg(vop_dev, DSP_CTRL1, V_DSP_LUT_EN(1));
310 * update_gamma value auto clean to 0 by HW, should not
313 vop_msk_reg_nobak(vop_dev, DSP_CTRL1, V_UPDATE_GAMMA_LUT(1));
315 vop_cfg_done(vop_dev);
316 spin_unlock(&vop_dev->reg_lock);
321 static int vop_set_cabc(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
323 struct vop_device *vop_dev =
324 container_of(dev_drv, struct vop_device, driver);
327 if (!vop_dev->cabc_lut_addr_base) {
328 dev_warn(vop_dev->dev, "not support cabc config\n");
333 dev_err(vop_dev->dev, "cabc lut table is null\n");
336 spin_lock(&vop_dev->reg_lock);
337 vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(0));
338 vop_cfg_done(vop_dev);
339 spin_unlock(&vop_dev->reg_lock);
343 spin_lock(&vop_dev->reg_lock);
344 for (i = 0; i < 128; i++) {
349 writel_relaxed(v, vop_dev->cabc_lut_addr_base + i);
351 vop_msk_reg(vop_dev, CABC_CTRL1, V_CABC_LUT_EN(1));
352 spin_unlock(&vop_dev->reg_lock);
357 static int vop_clk_enable(struct vop_device *vop_dev)
359 if (!vop_dev->clk_on) {
360 clk_prepare_enable(vop_dev->hclk);
361 clk_prepare_enable(vop_dev->dclk);
362 clk_prepare_enable(vop_dev->aclk);
363 if (vop_dev->hclk_noc)
364 clk_prepare_enable(vop_dev->hclk_noc);
365 if (vop_dev->aclk_noc)
366 clk_prepare_enable(vop_dev->aclk_noc);
367 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
368 pm_runtime_get_sync(vop_dev->dev);
370 spin_lock(&vop_dev->reg_lock);
372 spin_unlock(&vop_dev->reg_lock);
378 static int vop_clk_disable(struct vop_device *vop_dev)
380 if (vop_dev->clk_on) {
381 spin_lock(&vop_dev->reg_lock);
383 spin_unlock(&vop_dev->reg_lock);
385 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
386 pm_runtime_put(vop_dev->dev);
388 clk_disable_unprepare(vop_dev->dclk);
389 clk_disable_unprepare(vop_dev->hclk);
390 clk_disable_unprepare(vop_dev->aclk);
391 if (vop_dev->hclk_noc)
392 clk_disable_unprepare(vop_dev->hclk_noc);
393 if (vop_dev->aclk_noc)
394 clk_disable_unprepare(vop_dev->aclk_noc);
400 static int __maybe_unused vop_disable_irq(struct vop_device *vop_dev)
402 if (likely(vop_dev->clk_on)) {
403 spin_lock(&vop_dev->reg_lock);
404 vop_writel(vop_dev, INTR_EN0, 0xffff0000);
405 vop_writel(vop_dev, INTR_EN1, 0xffff0000);
406 vop_writel(vop_dev, INTR_CLEAR0, 0xffffffff);
407 vop_writel(vop_dev, INTR_CLEAR1, 0xffffffff);
408 vop_cfg_done(vop_dev);
409 spin_unlock(&vop_dev->reg_lock);
415 static int vop_reg_dump(struct rk_lcdc_driver *dev_drv)
417 struct vop_device *vop_dev =
418 container_of(dev_drv, struct vop_device, driver);
419 int *cbase = (int *)vop_dev->regs;
420 int *regsbak = (int *)vop_dev->regsbak;
422 char dbg_message[30];
425 pr_info("lcd back up reg:\n");
426 memset(dbg_message, 0, sizeof(dbg_message));
427 memset(buf, 0, sizeof(buf));
428 for (i = 0; i <= (0x200 >> 4); i++) {
429 val = sprintf(dbg_message, "0x%04x: ", i * 16);
430 for (j = 0; j < 4; j++) {
431 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
432 strcat(dbg_message, buf);
434 pr_info("%s\n", dbg_message);
435 memset(dbg_message, 0, sizeof(dbg_message));
436 memset(buf, 0, sizeof(buf));
439 pr_info("lcdc reg:\n");
440 for (i = 0; i <= (0x200 >> 4); i++) {
441 val = sprintf(dbg_message, "0x%04x: ", i * 16);
442 for (j = 0; j < 4; j++) {
443 sprintf(buf, "%08x ",
444 readl_relaxed(cbase + i * 4 + j));
445 strcat(dbg_message, buf);
447 pr_info("%s\n", dbg_message);
448 memset(dbg_message, 0, sizeof(dbg_message));
449 memset(buf, 0, sizeof(buf));
456 static int win##id##_enable(struct vop_device *vop_dev, int en) \
458 spin_lock(&vop_dev->reg_lock); \
459 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN((u64)en)); \
460 vop_cfg_done(vop_dev); \
461 spin_unlock(&vop_dev->reg_lock); \
470 /*enable/disable win directly*/
471 static int vop_win_direct_en(struct rk_lcdc_driver *drv,
474 struct vop_device *vop_dev =
475 container_of(drv, struct vop_device, driver);
477 drv->win[win_id]->state = en;
479 win0_enable(vop_dev, en);
480 else if (win_id == 1)
481 win1_enable(vop_dev, en);
482 else if (win_id == 2)
483 win2_enable(vop_dev, en);
484 else if (win_id == 3)
485 win3_enable(vop_dev, en);
487 dev_err(vop_dev->dev, "invalid win number:%d\n", win_id);
491 #define SET_WIN_ADDR(id) \
492 static int set_win##id##_addr(struct vop_device *vop_dev, u32 addr) \
494 spin_lock(&vop_dev->reg_lock); \
495 vop_writel(vop_dev, WIN##id##_YRGB_MST, addr); \
496 vop_msk_reg(vop_dev, WIN##id##_CTRL0, V_WIN##id##_EN(1)); \
497 vop_cfg_done(vop_dev); \
498 spin_unlock(&vop_dev->reg_lock); \
504 int vop_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
505 int win_id, u32 addr)
507 struct vop_device *vop_dev =
508 container_of(dev_drv, struct vop_device, driver);
510 set_win0_addr(vop_dev, addr);
512 set_win1_addr(vop_dev, addr);
517 static void lcdc_read_reg_defalut_cfg(struct vop_device *vop_dev)
521 struct rk_screen *screen = vop_dev->driver.cur_screen;
522 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
523 u32 V_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
525 struct rk_lcdc_win *win0 = vop_dev->driver.win[0];
527 spin_lock(&vop_dev->reg_lock);
528 for (reg = 0; reg < vop_dev->len; reg += 4) {
529 val = vop_readl_backup(vop_dev, reg);
532 win0->area[0].xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
534 ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
537 win0->area[0].xsize = (val & MASK(WIN0_DSP_WIDTH)) + 1;
538 win0->area[0].ysize =
539 ((val & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
542 st_x = val & MASK(WIN0_DSP_XST);
543 st_y = (val & MASK(WIN0_DSP_YST)) >> 16;
544 win0->area[0].xpos = st_x - h_pw_bp;
545 win0->area[0].ypos = st_y - V_pw_bp;
548 win0->state = val & MASK(WIN0_EN);
549 win0->area[0].fmt_cfg =
550 (val & MASK(WIN0_DATA_FMT)) >> 1;
551 win0->fmt_10 = (val & MASK(WIN0_FMT_10)) >> 4;
552 win0->area[0].format = win0->area[0].fmt_cfg;
555 win0->area[0].y_vir_stride =
556 val & MASK(WIN0_VIR_STRIDE);
557 win0->area[0].uv_vir_stride =
558 (val & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
559 if (win0->area[0].format == ARGB888)
560 win0->area[0].xvir = win0->area[0].y_vir_stride;
561 else if (win0->area[0].format == RGB888)
563 win0->area[0].y_vir_stride * 4 / 3;
564 else if (win0->area[0].format == RGB565)
566 2 * win0->area[0].y_vir_stride;
569 4 * win0->area[0].y_vir_stride;
572 win0->area[0].smem_start = val;
575 win0->area[0].cbr_start = val;
581 spin_unlock(&vop_dev->reg_lock);
584 /********do basic init*********/
585 static int vop_pre_init(struct rk_lcdc_driver *dev_drv)
587 struct vop_device *vop_dev =
588 container_of(dev_drv, struct vop_device, driver);
589 if (vop_dev->pre_init)
591 vop_dev->hclk = devm_clk_get(vop_dev->dev, "hclk_lcdc");
592 vop_dev->aclk = devm_clk_get(vop_dev->dev, "aclk_lcdc");
593 vop_dev->dclk = devm_clk_get(vop_dev->dev, "dclk_lcdc");
594 if (IS_ERR(vop_dev->aclk) || IS_ERR(vop_dev->dclk) ||
595 IS_ERR(vop_dev->hclk))
596 dev_err(vop_dev->dev, "failed to get clk source\n");
597 vop_dev->hclk_noc = devm_clk_get(vop_dev->dev, "hclk_vop_noc");
598 if (IS_ERR(vop_dev->hclk_noc)) {
599 vop_dev->hclk_noc = NULL;
600 dev_err(vop_dev->dev, "failed to get clk source\n");
602 vop_dev->aclk_noc = devm_clk_get(vop_dev->dev, "aclk_vop_noc");
603 if (IS_ERR(vop_dev->aclk_noc)) {
604 vop_dev->aclk_noc = NULL;
605 dev_err(vop_dev->dev, "failed to get clk source\n");
607 if (!support_uboot_display())
608 rk_disp_pwr_enable(dev_drv);
609 vop_clk_enable(vop_dev);
611 memcpy(vop_dev->regsbak, vop_dev->regs, vop_dev->len);
612 /*backup reg config at uboot */
613 lcdc_read_reg_defalut_cfg(vop_dev);
614 #ifndef CONFIG_RK_FPGA
618 if (vop_dev->pwr18 == 1) {
620 vop_grf_writel(vop_dev->pmugrf_base,
621 PMUGRF_SOC_CON0_VOP, v);
624 vop_grf_writel(vop_dev->pmugrf_base,
625 PMUGRF_SOC_CON0_VOP, v);
629 vop_writel(vop_dev, FRC_LOWER01_0, 0x12844821);
630 vop_writel(vop_dev, FRC_LOWER01_1, 0x21488412);
631 vop_writel(vop_dev, FRC_LOWER10_0, 0xa55a9696);
632 vop_writel(vop_dev, FRC_LOWER10_1, 0x5aa56969);
633 vop_writel(vop_dev, FRC_LOWER11_0, 0xdeb77deb);
634 vop_writel(vop_dev, FRC_LOWER11_1, 0xed7bb7de);
636 vop_msk_reg(vop_dev, SYS_CTRL, V_AUTO_GATING_EN(1));
637 vop_msk_reg(vop_dev, DSP_CTRL1, V_DITHER_UP_EN(1));
638 vop_cfg_done(vop_dev);
639 vop_dev->pre_init = true;
644 static void vop_deint(struct vop_device *vop_dev)
646 if (vop_dev->clk_on) {
649 vop_disable_irq(vop_dev);
650 spin_lock(&vop_dev->reg_lock);
651 vop_msk_reg(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
652 vop_msk_reg(vop_dev, WIN1_CTRL0, V_WIN0_EN(0));
654 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) | V_WIN2_MST1_EN(0) |
655 V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
656 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
657 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
658 vop_cfg_done(vop_dev);
659 spin_unlock(&vop_dev->reg_lock);
664 static void vop_win_csc_mode(struct vop_device *vop_dev,
665 struct rk_lcdc_win *win,
670 if (win->id == VOP_WIN0) {
671 val = V_WIN0_CSC_MODE(csc_mode);
672 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
673 } else if (win->id == VOP_WIN1) {
674 val = V_WIN1_CSC_MODE(csc_mode);
675 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
677 val = V_HWC_CSC_MODE(csc_mode);
678 vop_msk_reg(vop_dev, HWC_CTRL0, val);
682 static int rk3399_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
684 struct vop_device *vop_dev =
685 container_of(dev_drv, struct vop_device, driver);
686 int output_color = dev_drv->output_color;
689 for (i = 0; i < dev_drv->lcdc_win_num && i <= 4; i++) {
690 struct rk_lcdc_win *win = dev_drv->win[i];
692 u64 val = V_WIN0_YUV2YUV_EN(0) | V_WIN0_YUV2YUV_R2Y_EN(0) |
693 V_WIN0_YUV2YUV_Y2R_EN(0);
697 if (output_color == COLOR_RGB &&
698 !(IS_YUV(win->area[0].fmt_cfg) || win->area[0].yuyv_fmt))
701 if (output_color == COLOR_RGB) {
702 val |= V_WIN0_YUV2YUV_Y2R_EN(1);
703 if (win->colorspace == CSC_BT601) {
705 * Win Y2Y moudle always use 10bit mode.
707 LOAD_CSC(vop_dev, Y2R,
708 csc_y2r_bt601_full_10, i);
709 } else if (win->colorspace == CSC_BT709) {
710 LOAD_CSC(vop_dev, Y2R,
711 csc_y2r_bt709_full_10, i);
712 } else if (win->colorspace == CSC_BT2020) {
713 val |= V_WIN0_YUV2YUV_EN(1);
714 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i);
715 LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i);
717 } else if (output_color == COLOR_YCBCR ||
718 output_color == COLOR_YCBCR_BT709) {
719 if (!(IS_YUV(win->area[0].fmt_cfg) ||
720 win->area[0].yuyv_fmt)) {
721 val |= V_WIN0_YUV2YUV_R2Y_EN(1);
722 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i);
723 } else if (win->colorspace == CSC_BT2020) {
724 val |= V_WIN0_YUV2YUV_EN(1) |
725 V_WIN0_YUV2YUV_Y2R_EN(1) |
726 V_WIN0_YUV2YUV_R2Y_EN(1);
727 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt2020, i);
728 LOAD_CSC(vop_dev, R2R, csc_r2r_bt2020to709, i);
729 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt709_full_10, i);
731 } else if (output_color == COLOR_YCBCR_BT2020) {
732 if (!(IS_YUV(win->area[0].fmt_cfg) ||
733 win->area[0].yuyv_fmt)) {
734 val |= V_WIN0_YUV2YUV_R2Y_EN(1) |
735 V_WIN0_YUV2YUV_EN(1);
736 LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i);
737 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
738 } else if (win->colorspace == CSC_BT601 ||
739 win->colorspace == CSC_BT709) {
740 val |= V_WIN0_YUV2YUV_Y2R_EN(1) |
741 V_WIN0_YUV2YUV_R2Y_EN(1) |
742 V_WIN0_YUV2YUV_EN(1);
743 LOAD_CSC(vop_dev, Y2R, csc_y2r_bt709_full_10, i);
744 LOAD_CSC(vop_dev, R2R, csc_r2r_bt709to2020, i);
745 LOAD_CSC(vop_dev, R2Y, csc_r2y_bt2020, i);
749 vop_msk_reg(vop_dev, YUV2YUV_WIN, val << shift);
757 * Input Win csc Post csc Output
758 * 1. YUV(2020) --> bypass ---+ Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
759 * RGB --> R2Y(709) __/
761 * 2. YUV(2020) --> bypass ---+ bypass --> YUV_OUTPUT(2020)
762 * RGB --> R2Y(709) __/
764 * 3. YUV(2020) --> bypass ---+ Y2R->2020To709 --> RGB_OUTPUT(709)
765 * RGB --> R2Y(709) __/
767 * 4. YUV(601/709)-> bypass ---+ Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
768 * RGB --> R2Y(709) __/
770 * 5. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(709)
771 * RGB --> R2Y(709) __/
773 * 6. YUV(601/709)-> bypass ---+ bypass --> YUV_OUTPUT(601)
774 * RGB --> R2Y(601) __/
776 * 7. YUV(601) --> Y2R(601/mpeg)-+ bypass --> RGB_OUTPUT(709)
777 * RGB --> bypass ____/
779 * 8. YUV(709) --> Y2R(709/hd) --+ bypass --> RGB_OUTPUT(709)
780 * RGB --> bypass ____/
782 * 9. RGB --> bypass ---> 709To2020->R2Y --> YUV_OUTPUT(2020)
784 * 10. RGB --> R2Y(709) ---> bypass --> YUV_OUTPUT(709)
786 * 11. RGB --> R2Y(601) ---> bypass --> YUV_OUTPUT(601)
788 * 12. RGB --> bypass ---> bypass --> RGB_OUTPUT(709)
790 static int rk3228_vop_win_csc_cfg(struct rk_lcdc_driver *dev_drv)
792 struct vop_device *vop_dev =
793 container_of(dev_drv, struct vop_device, driver);
794 struct rk_lcdc_win *win;
795 int output_color = dev_drv->output_color;
796 int win_csc = COLOR_RGB;
797 int r2y_mode = VOP_R2Y_CSC_BT709;
800 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
801 win = dev_drv->win[i];
805 if (IS_YUV(win->area[0].fmt_cfg)) {
806 if (win->colorspace == CSC_BT2020 &&
807 win_csc < COLOR_YCBCR_BT2020) {
808 r2y_mode = VOP_R2Y_CSC_BT709;
809 win_csc = COLOR_YCBCR_BT2020;
812 if (win->colorspace == CSC_BT709 &&
813 win_csc < COLOR_YCBCR_BT709) {
814 r2y_mode = VOP_R2Y_CSC_BT709;
815 win_csc = COLOR_YCBCR_BT709;
818 if (win->colorspace == CSC_BT601 &&
819 win_csc < COLOR_YCBCR) {
820 r2y_mode = VOP_R2Y_CSC_BT709;
821 win_csc = COLOR_YCBCR;
826 if (win_csc == COLOR_RGB) {
827 if (output_color == COLOR_YCBCR_BT709) {
828 r2y_mode = VOP_R2Y_CSC_BT709;
829 win_csc = COLOR_YCBCR_BT709;
830 } else if (output_color == COLOR_YCBCR) {
831 r2y_mode = VOP_R2Y_CSC_BT601;
832 win_csc = COLOR_YCBCR;
836 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
837 win = dev_drv->win[i];
841 if (win_csc != COLOR_RGB && !IS_YUV(win->area[0].fmt_cfg))
842 vop_win_csc_mode(vop_dev, win, r2y_mode);
844 if (IS_YUV(win->area[0].fmt_cfg)) {
845 if (win_csc == COLOR_YCBCR)
846 vop_win_csc_mode(vop_dev, win,
848 else if (win_csc == COLOR_YCBCR_BT709)
849 vop_win_csc_mode(vop_dev, win, VOP_Y2R_CSC_HD);
856 static int vop_post_csc_cfg(struct rk_lcdc_driver *dev_drv)
858 struct vop_device *vop_dev =
859 container_of(dev_drv, struct vop_device, driver);
860 int output_color = dev_drv->output_color;
861 int win_csc = 0, overlay_mode = 0;
864 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
865 win_csc = rk3228_vop_win_csc_cfg(dev_drv);
866 } else if (VOP_CHIP(vop_dev) == VOP_RK3399) {
867 win_csc = rk3399_vop_win_csc_cfg(dev_drv);
870 * RK3399 not support post csc config.
875 val = V_YUV2YUV_POST_Y2R_EN(0) | V_YUV2YUV_POST_EN(0) |
876 V_YUV2YUV_POST_R2Y_EN(0);
878 if (win_csc == COLOR_YCBCR && output_color == COLOR_YCBCR_BT2020) {
879 val |= V_YUV2YUV_POST_Y2R_EN(1);
880 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
883 if (win_csc == COLOR_YCBCR_BT2020 &&
884 output_color != COLOR_YCBCR_BT2020) {
885 val |= V_YUV2YUV_POST_Y2R_EN(1);
886 vop_load_csc_table(vop_dev, POST_YUV2YUV_Y2R_COE,
891 if ((win_csc == COLOR_YCBCR ||
892 win_csc == COLOR_YCBCR_BT709 ||
893 win_csc == COLOR_RGB) && output_color == COLOR_YCBCR_BT2020) {
894 val |= V_YUV2YUV_POST_EN(1);
895 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
896 csc_r2r_bt709to2020);
898 if (win_csc == COLOR_YCBCR_BT2020 &&
899 (output_color == COLOR_YCBCR ||
900 output_color == COLOR_YCBCR_BT709 ||
901 output_color == COLOR_RGB)) {
902 val |= V_YUV2YUV_POST_EN(1);
903 vop_load_csc_table(vop_dev, POST_YUV2YUV_3x3_COE,
904 csc_r2r_bt2020to709);
908 if (output_color != COLOR_RGB) {
909 val |= V_YUV2YUV_POST_R2Y_EN(1);
911 if (output_color == COLOR_YCBCR_BT2020)
912 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
915 vop_load_csc_table(vop_dev, POST_YUV2YUV_R2Y_COE,
919 DBG(1, "win_csc=%d output_color=%d val=%llx\n",
920 win_csc, output_color, val);
921 vop_msk_reg(vop_dev, YUV2YUV_POST, val);
923 overlay_mode = (win_csc != COLOR_RGB) ? VOP_YUV_DOMAIN : VOP_RGB_DOMAIN;
924 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(overlay_mode));
929 static int vop_post_cfg(struct rk_lcdc_driver *dev_drv)
931 struct vop_device *vop_dev =
932 container_of(dev_drv, struct vop_device, driver);
933 struct rk_screen *screen = dev_drv->cur_screen;
934 u16 x_res = screen->mode.xres;
935 u16 y_res = screen->mode.yres;
937 u16 h_total, v_total;
938 u16 post_hsd_en, post_vsd_en;
939 u16 post_dsp_hact_st, post_dsp_hact_end;
940 u16 post_dsp_vact_st, post_dsp_vact_end;
941 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
942 u16 post_h_fac, post_v_fac;
944 screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
945 screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
946 screen->post_xsize = x_res *
947 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
948 screen->post_ysize = y_res *
949 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
951 h_total = screen->mode.hsync_len + screen->mode.left_margin +
952 x_res + screen->mode.right_margin;
953 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
954 y_res + screen->mode.lower_margin;
956 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
957 dev_warn(vop_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
958 screen->post_dsp_stx, screen->post_xsize, x_res);
959 screen->post_dsp_stx = x_res - screen->post_xsize;
961 if (screen->x_mirror == 0) {
962 post_dsp_hact_st = screen->post_dsp_stx +
963 screen->mode.hsync_len + screen->mode.left_margin;
964 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
966 post_dsp_hact_end = h_total - screen->mode.right_margin -
967 screen->post_dsp_stx;
968 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
970 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
973 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
979 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
980 dev_warn(vop_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
981 screen->post_dsp_sty, screen->post_ysize, y_res);
982 screen->post_dsp_sty = y_res - screen->post_ysize;
985 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
987 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
994 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
995 post_dsp_vact_st = screen->post_dsp_sty / 2 +
996 screen->mode.vsync_len +
997 screen->mode.upper_margin;
998 post_dsp_vact_end = post_dsp_vact_st +
999 screen->post_ysize / 2;
1001 post_dsp_vact_st_f1 = screen->mode.vsync_len +
1002 screen->mode.upper_margin +
1004 screen->mode.lower_margin +
1005 screen->mode.vsync_len +
1006 screen->mode.upper_margin +
1007 screen->post_dsp_sty / 2 +
1009 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
1010 screen->post_ysize / 2;
1012 if (screen->y_mirror == 0) {
1013 post_dsp_vact_st = screen->post_dsp_sty +
1014 screen->mode.vsync_len +
1015 screen->mode.upper_margin;
1016 post_dsp_vact_end = post_dsp_vact_st +
1019 post_dsp_vact_end = v_total -
1020 screen->mode.lower_margin -
1021 screen->post_dsp_sty;
1022 post_dsp_vact_st = post_dsp_vact_end -
1025 post_dsp_vact_st_f1 = 0;
1026 post_dsp_vact_end_f1 = 0;
1028 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
1029 screen->post_xsize, screen->post_ysize, screen->xpos);
1030 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
1031 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
1032 val = V_DSP_HACT_END_POST(post_dsp_hact_end) |
1033 V_DSP_HACT_ST_POST(post_dsp_hact_st);
1034 vop_msk_reg(vop_dev, POST_DSP_HACT_INFO, val);
1036 val = V_DSP_VACT_END_POST(post_dsp_vact_end) |
1037 V_DSP_VACT_ST_POST(post_dsp_vact_st);
1038 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO, val);
1040 val = V_POST_HS_FACTOR_YRGB(post_h_fac) |
1041 V_POST_VS_FACTOR_YRGB(post_v_fac);
1042 vop_msk_reg(vop_dev, POST_SCL_FACTOR_YRGB, val);
1043 val = V_DSP_VACT_END_POST(post_dsp_vact_end_f1) |
1044 V_DSP_VACT_ST_POST(post_dsp_vact_st_f1);
1045 vop_msk_reg(vop_dev, POST_DSP_VACT_INFO_F1, val);
1046 val = V_POST_HOR_SD_EN(post_hsd_en) | V_POST_VER_SD_EN(post_vsd_en);
1047 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
1049 vop_post_csc_cfg(dev_drv);
1054 static int vop_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
1056 struct vop_device *vop_dev =
1057 container_of(dev_drv, struct vop_device, driver);
1058 struct rk_lcdc_win *win;
1059 u32 colorkey_r, colorkey_g, colorkey_b;
1062 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1063 win = dev_drv->win[i];
1064 key_val = win->color_key_val;
1065 colorkey_r = (key_val & 0xff) << 2;
1066 colorkey_g = ((key_val >> 8) & 0xff) << 12;
1067 colorkey_b = ((key_val >> 16) & 0xff) << 22;
1068 /* color key dither 565/888->aaa */
1069 key_val = colorkey_r | colorkey_g | colorkey_b;
1072 vop_writel(vop_dev, WIN0_COLOR_KEY, key_val);
1075 vop_writel(vop_dev, WIN1_COLOR_KEY, key_val);
1078 vop_writel(vop_dev, WIN2_COLOR_KEY, key_val);
1081 vop_writel(vop_dev, WIN3_COLOR_KEY, key_val);
1084 pr_info("%s:un support win num:%d\n",
1092 static int vop_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
1094 struct vop_device *vop_dev =
1095 container_of(dev_drv, struct vop_device, driver);
1096 struct rk_lcdc_win *win = dev_drv->win[win_id];
1097 struct alpha_config alpha_config;
1099 int ppixel_alpha = 0, global_alpha = 0, i;
1100 u32 src_alpha_ctl = 0, dst_alpha_ctl = 0;
1103 memset(&alpha_config, 0, sizeof(struct alpha_config));
1104 for (i = 0; i < win->area_num; i++) {
1105 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
1106 (win->area[i].format == FBDC_ARGB_888) ||
1107 (win->area[i].format == FBDC_ABGR_888) ||
1108 (win->area[i].format == ABGR888)) ? 1 : 0;
1111 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
1113 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1114 if (!dev_drv->win[i]->state)
1116 if (win->z_order > dev_drv->win[i]->z_order)
1121 * The bottom layer not support ppixel_alpha mode.
1123 if (i == dev_drv->lcdc_win_num)
1125 alpha_config.src_global_alpha_val = win->g_alpha_val;
1126 win->alpha_mode = AB_SRC_OVER;
1128 switch (win->alpha_mode) {
1129 case AB_USER_DEFINE:
1132 alpha_config.src_factor_mode = AA_ZERO;
1133 alpha_config.dst_factor_mode = AA_ZERO;
1136 alpha_config.src_factor_mode = AA_ONE;
1137 alpha_config.dst_factor_mode = AA_ZERO;
1140 alpha_config.src_factor_mode = AA_ZERO;
1141 alpha_config.dst_factor_mode = AA_ONE;
1144 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1146 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1148 alpha_config.src_factor_mode = AA_ONE;
1149 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1152 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1153 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1154 alpha_config.dst_factor_mode = AA_ONE;
1157 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1158 alpha_config.src_factor_mode = AA_SRC;
1159 alpha_config.dst_factor_mode = AA_ZERO;
1162 alpha_config.src_factor_mode = AA_ZERO;
1163 alpha_config.dst_factor_mode = AA_SRC;
1166 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1167 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1168 alpha_config.dst_factor_mode = AA_ZERO;
1171 alpha_config.src_factor_mode = AA_ZERO;
1172 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1175 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1176 alpha_config.src_factor_mode = AA_SRC;
1177 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1180 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1181 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1182 alpha_config.dst_factor_mode = AA_SRC;
1185 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
1186 alpha_config.src_factor_mode = AA_SRC_INVERSE;
1187 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1189 case AB_SRC_OVER_GLOBAL:
1190 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1191 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
1192 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
1193 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
1196 pr_err("alpha mode error\n");
1199 if ((ppixel_alpha == 1) && (global_alpha == 1))
1200 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
1201 else if (ppixel_alpha == 1)
1202 alpha_config.src_global_alpha_mode = AA_PER_PIX;
1203 else if (global_alpha == 1)
1204 alpha_config.src_global_alpha_mode = AA_GLOBAL;
1207 alpha_config.src_alpha_mode = AA_STRAIGHT;
1208 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
1212 src_alpha_ctl = 0x60;
1213 dst_alpha_ctl = 0x64;
1216 src_alpha_ctl = 0xa0;
1217 dst_alpha_ctl = 0xa4;
1220 src_alpha_ctl = 0xdc;
1221 dst_alpha_ctl = 0xec;
1224 src_alpha_ctl = 0x12c;
1225 dst_alpha_ctl = 0x13c;
1228 src_alpha_ctl = 0x160;
1229 dst_alpha_ctl = 0x164;
1232 val = V_WIN0_DST_FACTOR_MODE(alpha_config.dst_factor_mode);
1233 vop_msk_reg(vop_dev, dst_alpha_ctl, val);
1234 val = V_WIN0_SRC_ALPHA_EN(alpha_en) |
1235 V_WIN0_SRC_COLOR_MODE(alpha_config.src_color_mode) |
1236 V_WIN0_SRC_ALPHA_MODE(alpha_config.src_alpha_mode) |
1237 V_WIN0_SRC_BLEND_MODE(alpha_config.src_global_alpha_mode) |
1238 V_WIN0_SRC_ALPHA_CAL_MODE(alpha_config.src_alpha_cal_m0) |
1239 V_WIN0_SRC_FACTOR_MODE(alpha_config.src_factor_mode) |
1240 V_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
1242 vop_msk_reg(vop_dev, src_alpha_ctl, val);
1247 static int vop_axi_gather_cfg(struct vop_device *vop_dev,
1248 struct rk_lcdc_win *win)
1251 u16 yrgb_gather_num = 3;
1252 u16 cbcr_gather_num = 1;
1254 switch (win->area[0].format) {
1261 yrgb_gather_num = 3;
1266 yrgb_gather_num = 2;
1277 yrgb_gather_num = 1;
1278 cbcr_gather_num = 2;
1282 yrgb_gather_num = 2;
1283 cbcr_gather_num = 2;
1286 dev_err(vop_dev->driver.dev, "%s:un supported format[%d]\n",
1287 __func__, win->area[0].format);
1291 if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1)) {
1292 val = V_WIN0_YRGB_AXI_GATHER_EN(1) |
1293 V_WIN0_CBR_AXI_GATHER_EN(1) |
1294 V_WIN0_YRGB_AXI_GATHER_NUM(yrgb_gather_num) |
1295 V_WIN0_CBR_AXI_GATHER_NUM(cbcr_gather_num);
1296 vop_msk_reg(vop_dev, WIN0_CTRL1 + (win->id * 0x40), val);
1297 } else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3)) {
1298 val = V_WIN2_AXI_GATHER_EN(1) |
1299 V_WIN2_AXI_GATHER_NUM(yrgb_gather_num);
1300 vop_msk_reg(vop_dev, WIN2_CTRL1 + ((win->id - 2) * 0x50), val);
1301 } else if (win->id == VOP_HWC) {
1302 val = V_HWC_AXI_GATHER_EN(1) |
1303 V_HWC_AXI_GATHER_NUM(yrgb_gather_num);
1304 vop_msk_reg(vop_dev, HWC_CTRL1, val);
1309 static int vop_fbdc_reg_update(struct vop_device *vop_dev, int win_id)
1311 struct rk_lcdc_win *win = vop_dev->driver.win[win_id];
1314 val = V_VOP_FBDC_WIN_SEL(win_id) |
1315 V_AFBCD_HREG_PIXEL_PACKING_FMT(win->area[0].fbdc_fmt_cfg) |
1316 V_AFBCD_HREG_BLOCK_SPLIT(win->area[0].fbdc_cor_en);
1317 vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
1319 val = V_AFBCD_HREG_PIC_WIDTH(win->area[0].fbdc_mb_width - 1) |
1320 V_AFBCD_HREG_PIC_HEIGHT(win->area[0].fbdc_mb_height - 1);
1321 vop_msk_reg(vop_dev, AFBCD0_PIC_SIZE, val);
1326 static int vop_init_fbdc_config(struct vop_device *vop_dev, int win_id)
1328 struct rk_lcdc_driver *vop_drv = &vop_dev->driver;
1329 struct rk_lcdc_win *win = vop_drv->win[win_id];
1330 struct rk_screen *screen = vop_drv->cur_screen;
1332 if (screen->mode.flag & FB_VMODE_INTERLACED) {
1333 dev_err(vop_dev->dev, "unsupport fbdc+interlace!\n");
1337 if (VOP_CHIP(vop_dev) != VOP_RK3399) {
1338 pr_err("soc: 0x%08x not support FBDC\n", VOP_CHIP(vop_dev));
1342 win->area[0].fbdc_mb_width = win->area[0].xvir;
1343 win->area[0].fbdc_mb_height = win->area[0].yact;
1344 win->area[0].fbdc_cor_en = 0; /* hreg_block_split */
1345 win->area[0].fbdc_fmt_cfg |= AFBDC_YUV_COLOR_TRANSFORM << 4;
1350 static int vop_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1352 struct vop_device *vop_dev =
1353 container_of(dev_drv, struct vop_device, driver);
1354 struct rk_lcdc_win *win = dev_drv->win[win_id];
1358 struct rk_win_property *win_property =
1359 &dev_drv->win[win_id]->property;
1361 off = win_id * 0x40;
1363 if (win->state == 1) {
1364 if (!(win_property->feature & SUPPORT_HW_EXIST)) {
1365 pr_err("vop[%d] win[%d] hardware unsupport\n",
1366 vop_dev->id, win_id);
1369 vop_axi_gather_cfg(vop_dev, win);
1370 if (win->area[0].fbdc_en)
1371 vop_fbdc_reg_update(vop_dev, win_id);
1373 * rk322x have a bug on windows 0 and 1:
1375 * When switch win format from RGB to YUV, would flash
1376 * some green lines on the top of the windows.
1378 * Use bg_en show one blank frame to skip the error frame.
1380 if (IS_YUV(win->area[0].fmt_cfg)) {
1381 val = vop_readl(vop_dev, WIN0_CTRL0);
1382 format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1384 if (!IS_YUV(format)) {
1385 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1386 val = V_WIN0_DSP_BG_RED(0x200) |
1387 V_WIN0_DSP_BG_GREEN(0x40) |
1388 V_WIN0_DSP_BG_BLUE(0x200) |
1390 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1393 val = V_WIN0_DSP_BG_RED(0) |
1394 V_WIN0_DSP_BG_GREEN(0) |
1395 V_WIN0_DSP_BG_BLUE(0) |
1397 vop_msk_reg(vop_dev, WIN0_DSP_BG + off,
1401 val = V_WIN0_BG_EN(0);
1402 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1405 val = V_WIN0_BG_EN(0);
1406 vop_msk_reg(vop_dev, WIN0_DSP_BG + off, val);
1409 val = V_WIN0_EN(win->state) |
1410 V_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1411 V_WIN0_FMT_10(win->fmt_10) |
1412 V_WIN0_LB_MODE(win->win_lb_mode) |
1413 V_WIN0_RB_SWAP(win->area[0].swap_rb) |
1414 V_WIN0_X_MIR_EN(win->xmirror) |
1415 V_WIN0_Y_MIR_EN(win->ymirror) |
1416 V_WIN0_UV_SWAP(win->area[0].swap_uv);
1417 if (VOP_CHIP(vop_dev) == VOP_RK3399)
1418 val |= V_WIN0_YUYV(win->area[0].yuyv_fmt);
1419 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1420 val = V_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1421 V_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1422 V_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1423 V_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1424 V_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1425 V_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1426 V_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1427 V_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1428 V_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1429 V_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1430 V_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1431 V_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1432 V_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1433 V_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1434 V_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1435 vop_msk_reg(vop_dev, WIN0_CTRL1 + off, val);
1436 val = V_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1437 V_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1438 vop_writel(vop_dev, WIN0_VIR + off, val);
1439 val = V_WIN0_ACT_WIDTH(win->area[0].xact - 1) |
1440 V_WIN0_ACT_HEIGHT(win->area[0].yact - 1);
1441 vop_writel(vop_dev, WIN0_ACT_INFO + off, val);
1443 val = V_WIN0_DSP_WIDTH(win->area[0].xsize - 1) |
1444 V_WIN0_DSP_HEIGHT(win->area[0].ysize - 1);
1445 vop_writel(vop_dev, WIN0_DSP_INFO + off, val);
1447 val = V_WIN0_DSP_XST(win->area[0].dsp_stx) |
1448 V_WIN0_DSP_YST(win->area[0].dsp_sty);
1449 vop_writel(vop_dev, WIN0_DSP_ST + off, val);
1451 val = V_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1452 V_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1453 vop_writel(vop_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1455 val = V_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1456 V_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1457 vop_writel(vop_dev, WIN0_SCL_FACTOR_CBR + off, val);
1459 val = V_WIN0_EN(win->state);
1460 vop_msk_reg(vop_dev, WIN0_CTRL0 + off, val);
1466 static int area_xst(struct rk_lcdc_win *win, int area_num)
1468 struct rk_lcdc_win_area area_temp;
1471 for (i = 0; i < area_num; i++) {
1472 for (j = i + 1; j < area_num; j++) {
1473 if (win->area[i].dsp_stx > win->area[j].dsp_stx) {
1474 memcpy(&area_temp, &win->area[i],
1475 sizeof(struct rk_lcdc_win_area));
1476 memcpy(&win->area[i], &win->area[j],
1477 sizeof(struct rk_lcdc_win_area));
1478 memcpy(&win->area[j], &area_temp,
1479 sizeof(struct rk_lcdc_win_area));
1487 static int vop_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1489 struct vop_device *vop_dev =
1490 container_of(dev_drv, struct vop_device, driver);
1491 struct rk_lcdc_win *win = dev_drv->win[win_id];
1494 struct rk_win_property *win_property =
1495 &dev_drv->win[win_id]->property;
1497 off = (win_id - 2) * 0x50;
1498 area_xst(win, win->area_num);
1500 if (win->state == 1) {
1501 if (!(win_property->feature & SUPPORT_HW_EXIST)) {
1502 pr_err("vop[%d] win[%d] hardware unsupport\n",
1503 vop_dev->id, win_id);
1506 vop_axi_gather_cfg(vop_dev, win);
1507 if (win->area[0].fbdc_en)
1508 vop_fbdc_reg_update(vop_dev, win_id);
1509 val = V_WIN2_EN(1) | V_WIN1_CSC_MODE(win->csc_mode);
1510 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1512 if (win->area[0].state == 1) {
1513 val = V_WIN2_MST0_EN(win->area[0].state) |
1514 V_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1515 V_WIN2_RB_SWAP0(win->area[0].swap_rb);
1516 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1518 val = V_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1519 vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1521 val = V_WIN2_DSP_WIDTH0(win->area[0].xsize - 1) |
1522 V_WIN2_DSP_HEIGHT0(win->area[0].ysize - 1);
1523 vop_writel(vop_dev, WIN2_DSP_INFO0 + off, val);
1524 val = V_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1525 V_WIN2_DSP_YST0(win->area[0].dsp_sty);
1526 vop_writel(vop_dev, WIN2_DSP_ST0 + off, val);
1528 val = V_WIN2_MST0_EN(0);
1529 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1532 if (win->area[1].state == 1) {
1533 val = V_WIN2_MST1_EN(win->area[1].state) |
1534 V_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1535 V_WIN2_RB_SWAP1(win->area[1].swap_rb);
1536 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1538 val = V_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1539 vop_msk_reg(vop_dev, WIN2_VIR0_1 + off, val);
1541 val = V_WIN2_DSP_WIDTH1(win->area[1].xsize - 1) |
1542 V_WIN2_DSP_HEIGHT1(win->area[1].ysize - 1);
1543 vop_writel(vop_dev, WIN2_DSP_INFO1 + off, val);
1544 val = V_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1545 V_WIN2_DSP_YST1(win->area[1].dsp_sty);
1546 vop_writel(vop_dev, WIN2_DSP_ST1 + off, val);
1548 val = V_WIN2_MST1_EN(0);
1549 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1552 if (win->area[2].state == 1) {
1553 val = V_WIN2_MST2_EN(win->area[2].state) |
1554 V_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1555 V_WIN2_RB_SWAP2(win->area[2].swap_rb);
1556 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1558 val = V_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1559 vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1561 val = V_WIN2_DSP_WIDTH2(win->area[2].xsize - 1) |
1562 V_WIN2_DSP_HEIGHT2(win->area[2].ysize - 1);
1563 vop_writel(vop_dev, WIN2_DSP_INFO2 + off, val);
1564 val = V_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1565 V_WIN2_DSP_YST2(win->area[2].dsp_sty);
1566 vop_writel(vop_dev, WIN2_DSP_ST2 + off, val);
1568 val = V_WIN2_MST2_EN(0);
1569 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1572 if (win->area[3].state == 1) {
1573 val = V_WIN2_MST3_EN(win->area[3].state) |
1574 V_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1575 V_WIN2_RB_SWAP3(win->area[3].swap_rb);
1576 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1578 val = V_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1579 vop_msk_reg(vop_dev, WIN2_VIR2_3 + off, val);
1581 val = V_WIN2_DSP_WIDTH3(win->area[3].xsize - 1) |
1582 V_WIN2_DSP_HEIGHT3(win->area[3].ysize - 1);
1583 vop_writel(vop_dev, WIN2_DSP_INFO3 + off, val);
1584 val = V_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1585 V_WIN2_DSP_YST3(win->area[3].dsp_sty);
1586 vop_writel(vop_dev, WIN2_DSP_ST3 + off, val);
1588 val = V_WIN2_MST3_EN(0);
1589 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1592 val = V_WIN2_EN(win->state) | V_WIN2_MST0_EN(0) |
1593 V_WIN2_MST1_EN(0) | V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
1594 vop_msk_reg(vop_dev, WIN2_CTRL0 + off, val);
1600 static int vop_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1602 struct vop_device *vop_dev =
1603 container_of(dev_drv, struct vop_device, driver);
1604 struct rk_lcdc_win *win = dev_drv->win[win_id];
1605 unsigned int hwc_size = 0;
1608 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32)) {
1610 } else if ((win->area[0].xsize == 64) && (win->area[0].ysize == 64)) {
1612 } else if ((win->area[0].xsize == 96) && (win->area[0].ysize == 96)) {
1614 } else if ((win->area[0].xsize == 128) &&
1615 (win->area[0].ysize == 128)) {
1618 dev_err(vop_dev->dev, "un supported hwc size[%dx%d]!\n",
1619 win->area[0].xsize, win->area[0].ysize);
1623 if (win->state == 1) {
1624 vop_axi_gather_cfg(vop_dev, win);
1625 val = V_HWC_EN(1) | V_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1626 V_HWC_RB_SWAP(win->area[0].swap_rb);
1627 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1629 val = V_HWC_SIZE(hwc_size);
1630 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1632 val = V_HWC_DSP_XST(win->area[0].dsp_stx) |
1633 V_HWC_DSP_YST(win->area[0].dsp_sty);
1634 vop_msk_reg(vop_dev, HWC_DSP_ST, val);
1636 val = V_HWC_EN(win->state);
1637 vop_msk_reg(vop_dev, HWC_CTRL0, val);
1643 static int vop_layer_update_regs(struct vop_device *vop_dev,
1644 struct rk_lcdc_win *win)
1646 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
1648 if (likely(vop_dev->clk_on)) {
1649 vop_msk_reg(vop_dev, SYS_CTRL,
1650 V_VOP_STANDBY_EN(vop_dev->standby));
1651 if ((win->id == VOP_WIN0) || (win->id == VOP_WIN1))
1652 vop_win_0_1_reg_update(dev_drv, win->id);
1653 else if ((win->id == VOP_WIN2) || (win->id == VOP_WIN3))
1654 vop_win_2_3_reg_update(dev_drv, win->id);
1655 else if (win->id == VOP_HWC)
1656 vop_hwc_reg_update(dev_drv, win->id);
1657 vop_cfg_done(vop_dev);
1660 DBG(2, "%s for lcdc%d\n", __func__, vop_dev->id);
1664 static int __maybe_unused vop_mmu_en(struct rk_lcdc_driver *dev_drv)
1667 struct vop_device *vop_dev =
1668 container_of(dev_drv, struct vop_device, driver);
1670 if (unlikely(!vop_dev->clk_on)) {
1671 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1674 if (dev_drv->iommu_enabled) {
1675 if (!vop_dev->iommu_status && dev_drv->mmu_dev) {
1676 if (likely(vop_dev->clk_on)) {
1677 val = V_VOP_MMU_EN(1);
1678 vop_msk_reg(vop_dev, SYS_CTRL, val);
1679 val = V_AXI_OUTSTANDING_MAX_NUM(31) |
1680 V_AXI_MAX_OUTSTANDING_EN(1);
1681 vop_msk_reg(vop_dev, SYS_CTRL1, val);
1683 vop_dev->iommu_status = 1;
1684 rockchip_iovmm_activate(dev_drv->dev);
1690 static int vop_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1692 int ret = 0, fps = 0;
1693 struct vop_device *vop_dev =
1694 container_of(dev_drv, struct vop_device, driver);
1695 struct rk_screen *screen = dev_drv->cur_screen;
1696 #ifdef CONFIG_RK_FPGA
1700 ret = clk_set_rate(vop_dev->dclk, screen->mode.pixclock);
1702 dev_err(dev_drv->dev, "set lcdc%d dclk[%d] failed\n",
1703 vop_dev->id, screen->mode.pixclock);
1705 div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
1706 vop_dev->driver.pixclock = vop_dev->pixclock;
1708 fps = rk_fb_calc_fps(screen, vop_dev->pixclock);
1709 screen->ft = 1000 / fps;
1710 dev_info(vop_dev->dev, "%s: dclk:%lu>>fps:%d ",
1711 vop_dev->driver.name, clk_get_rate(vop_dev->dclk), fps);
1715 static int vop_config_timing(struct rk_lcdc_driver *dev_drv)
1717 struct vop_device *vop_dev =
1718 container_of(dev_drv, struct vop_device, driver);
1719 struct rk_screen *screen = dev_drv->cur_screen;
1720 u16 hsync_len = screen->mode.hsync_len;
1721 u16 left_margin = screen->mode.left_margin;
1722 u16 right_margin = screen->mode.right_margin;
1723 u16 vsync_len = screen->mode.vsync_len;
1724 u16 upper_margin = screen->mode.upper_margin;
1725 u16 lower_margin = screen->mode.lower_margin;
1726 u16 x_res = screen->mode.xres;
1727 u16 y_res = screen->mode.yres;
1729 u16 h_total, v_total;
1730 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1732 h_total = hsync_len + left_margin + x_res + right_margin;
1733 v_total = vsync_len + upper_margin + y_res + lower_margin;
1735 val = V_DSP_HS_END(hsync_len) | V_DSP_HTOTAL(h_total);
1736 vop_msk_reg(vop_dev, DSP_HTOTAL_HS_END, val);
1738 val = V_DSP_HACT_END(hsync_len + left_margin + x_res) |
1739 V_DSP_HACT_ST(hsync_len + left_margin);
1740 vop_msk_reg(vop_dev, DSP_HACT_ST_END, val);
1742 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
1743 /* First Field Timing */
1744 val = V_DSP_VS_END(vsync_len) |
1745 V_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1746 lower_margin) + y_res + 1);
1747 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1749 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1750 V_DSP_VACT_ST(vsync_len + upper_margin);
1751 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1753 /* Second Field Timing */
1754 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1755 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1757 val = V_DSP_VS_ST_F1(vs_st_f1) | V_DSP_VS_END_F1(vs_end_f1);
1758 vop_msk_reg(vop_dev, DSP_VS_ST_END_F1, val);
1760 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1762 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1764 val = V_DSP_VACT_END_F1(vact_end_f1) |
1765 V_DSP_VACT_ST_F1(vact_st_f1);
1766 vop_msk_reg(vop_dev, DSP_VACT_ST_END_F1, val);
1767 vop_msk_reg(vop_dev, DSP_CTRL0,
1768 V_DSP_INTERLACE(1) | V_DSP_FIELD_POL(0));
1770 val = V_DSP_LINE_FLAG_NUM_0(lower_margin ?
1771 vact_end_f1 : vact_end_f1 - 1);
1773 val |= V_DSP_LINE_FLAG_NUM_1(lower_margin ?
1774 vact_end_f1 : vact_end_f1 - 1);
1775 vop_msk_reg(vop_dev, LINE_FLAG, val);
1777 val = V_DSP_VS_END(vsync_len) | V_DSP_VTOTAL(v_total);
1778 vop_msk_reg(vop_dev, DSP_VTOTAL_VS_END, val);
1780 val = V_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1781 V_DSP_VACT_ST(vsync_len + upper_margin);
1782 vop_msk_reg(vop_dev, DSP_VACT_ST_END, val);
1784 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_INTERLACE(0) |
1785 V_DSP_FIELD_POL(0));
1787 val = V_DSP_LINE_FLAG_NUM_0(vsync_len + upper_margin + y_res) |
1788 V_DSP_LINE_FLAG_NUM_1(vsync_len + upper_margin + y_res);
1789 vop_msk_reg(vop_dev, LINE_FLAG, val);
1791 vop_post_cfg(dev_drv);
1792 if ((x_res <= VOP_INPUT_MAX_WIDTH / 2) && (vop_dev->id == 0))
1793 vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(1));
1795 vop_msk_reg(vop_dev, SYS_CTRL, V_POST_LB_MODE(0));
1800 static void vop_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1802 struct vop_device *vop_dev =
1803 container_of(dev_drv, struct vop_device, driver);
1806 vop_msk_reg(vop_dev, SYS_CTRL, V_OVERLAY_MODE(dev_drv->overlay_mode));
1807 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1808 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1809 vop_msk_reg(vop_dev, BCSH_CTRL,
1810 V_BCSH_Y2R_EN(0) | V_BCSH_R2Y_EN(0));
1812 vop_msk_reg(vop_dev, BCSH_CTRL, V_BCSH_Y2R_EN(1) |
1813 V_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1816 /* overlay_mode=VOP_RGB_DOMAIN */
1817 /* bypass --need check,if bcsh close? */
1818 if (dev_drv->output_color == COLOR_RGB) {
1819 bcsh_ctrl = vop_readl(vop_dev, BCSH_CTRL);
1820 if (((bcsh_ctrl & MASK(BCSH_EN)) == 1) ||
1821 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1822 vop_msk_reg(vop_dev, BCSH_CTRL,
1826 vop_msk_reg(vop_dev, BCSH_CTRL,
1831 vop_msk_reg(vop_dev, BCSH_CTRL,
1833 V_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1839 static int vop_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1840 u16 *yact, int *format, u32 *dsp_addr,
1843 struct vop_device *vop_dev =
1844 container_of(dev_drv, struct vop_device, driver);
1847 spin_lock(&vop_dev->reg_lock);
1849 val = vop_readl(vop_dev, WIN0_ACT_INFO);
1850 *xact = (val & MASK(WIN0_ACT_WIDTH)) + 1;
1851 *yact = ((val & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
1853 val = vop_readl(vop_dev, WIN0_CTRL0);
1854 *format = (val & MASK(WIN0_DATA_FMT)) >> 1;
1855 *ymirror = (val & MASK(WIN0_Y_MIR_EN)) >> 22;
1856 *dsp_addr = vop_readl(vop_dev, WIN0_YRGB_MST);
1858 spin_unlock(&vop_dev->reg_lock);
1863 static int vop_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1864 int format, u16 xact, u16 yact, u16 xvir,
1867 struct vop_device *vop_dev =
1868 container_of(dev_drv, struct vop_device, driver);
1869 int swap = (format == RGB888) ? 1 : 0;
1870 struct rk_lcdc_win *win = dev_drv->win[0];
1873 val = V_WIN0_DATA_FMT(format) | V_WIN0_RB_SWAP(swap) |
1874 V_WIN0_Y_MIR_EN(ymirror);
1875 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
1877 vop_msk_reg(vop_dev, WIN0_VIR, V_WIN0_VIR_STRIDE(xvir));
1878 vop_writel(vop_dev, WIN0_ACT_INFO, V_WIN0_ACT_WIDTH(xact - 1) |
1879 V_WIN0_ACT_HEIGHT(yact - 1));
1881 vop_writel(vop_dev, WIN0_YRGB_MST, rgb_mst);
1883 vop_cfg_done(vop_dev);
1885 if (format == RGB888)
1886 win->area[0].format = BGR888;
1888 win->area[0].format = format;
1890 win->ymirror = ymirror;
1892 win->last_state = 1;
1897 static int vop_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1901 struct vop_device *vop_dev =
1902 container_of(dev_drv, struct vop_device, driver);
1903 struct rk_screen *screen = dev_drv->cur_screen;
1906 if (unlikely(!vop_dev->clk_on)) {
1907 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
1911 if (!vop_dev->standby && initscreen && (dev_drv->first_frame != 1))
1912 flush_kthread_worker(&dev_drv->update_regs_worker);
1914 spin_lock(&vop_dev->reg_lock);
1915 if (likely(vop_dev->clk_on)) {
1916 switch (screen->face) {
1919 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1920 V_PRE_DITHER_DOWN_EN(1) |
1921 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1925 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1926 V_PRE_DITHER_DOWN_EN(1) |
1927 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1931 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1932 V_PRE_DITHER_DOWN_EN(1) |
1933 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(0);
1937 val = V_DITHER_DOWN_EN(1) | V_DITHER_UP_EN(1) |
1938 V_PRE_DITHER_DOWN_EN(1) |
1939 V_DITHER_DOWN_SEL(1) | V_DITHER_DOWN_MODE(1);
1943 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1)
1944 | V_PRE_DITHER_DOWN_EN(1) |
1945 V_DITHER_DOWN_SEL(0) | V_DITHER_DOWN_MODE(0);
1950 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1951 V_PRE_DITHER_DOWN_EN(1) |
1952 V_DITHER_DOWN_SEL(0) |
1953 V_DITHER_DOWN_MODE(0);
1955 case OUT_YUV_420_10BIT:
1958 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1959 V_PRE_DITHER_DOWN_EN(0) |
1960 V_DITHER_DOWN_SEL(0) |
1961 V_DITHER_DOWN_MODE(0);
1965 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1966 V_PRE_DITHER_DOWN_EN(1) |
1967 V_DITHER_DOWN_SEL(0) |
1968 V_DITHER_DOWN_MODE(0);
1970 case OUT_YUV_422_10BIT:
1972 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1973 V_PRE_DITHER_DOWN_EN(0) |
1974 V_DITHER_DOWN_SEL(0) |
1975 V_DITHER_DOWN_MODE(0);
1979 val = V_DITHER_DOWN_EN(0) | V_DITHER_UP_EN(1) |
1980 V_PRE_DITHER_DOWN_EN(0) |
1981 V_DITHER_DOWN_SEL(0) |
1982 V_DITHER_DOWN_MODE(0);
1985 dev_err(vop_dev->dev, "un supported screen face[%d]!\n",
1990 vop_msk_reg(vop_dev, DSP_CTRL1, val);
1991 switch (screen->type) {
1993 val = V_SW_UV_OFFSET_EN(1) | V_SW_IMD_TVE_DCLK_EN(1) |
1994 V_SW_IMD_TVE_DCLK_EN(1) |
1995 V_SW_IMD_TVE_DCLK_POL(1) |
1996 V_SW_GENLOCK(1) | V_SW_DAC_SEL(1);
1997 if (screen->mode.xres == 720 &&
1998 screen->mode.yres == 576)
1999 val |= V_SW_TVE_MODE(1);
2001 val |= V_SW_TVE_MODE(0);
2002 vop_msk_reg(vop_dev, SYS_CTRL, val);
2005 if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
2006 ((screen->face == OUT_P888) ||
2007 (screen->face == OUT_P101010))) {
2008 if (vop_dev->id == 0)
2009 face = OUT_P101010; /*RGB 10bit output*/
2013 val = V_HDMI_OUT_EN(1) | V_SW_UV_OFFSET_EN(0);
2014 vop_msk_reg(vop_dev, SYS_CTRL, val);
2015 val = V_HDMI_HSYNC_POL(screen->pin_hsync) |
2016 V_HDMI_VSYNC_POL(screen->pin_vsync) |
2017 V_HDMI_DEN_POL(screen->pin_den) |
2018 V_HDMI_DCLK_POL(screen->pin_dclk);
2019 /*hsync vsync den dclk polo,dither */
2020 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2024 val = V_RGB_OUT_EN(1);
2025 vop_msk_reg(vop_dev, SYS_CTRL, val);
2028 val = V_MIPI_OUT_EN(1);
2029 vop_msk_reg(vop_dev, SYS_CTRL, val);
2030 val = V_MIPI_HSYNC_POL(screen->pin_hsync) |
2031 V_MIPI_VSYNC_POL(screen->pin_vsync) |
2032 V_MIPI_DEN_POL(screen->pin_den) |
2033 V_MIPI_DCLK_POL(screen->pin_dclk);
2034 /*hsync vsync den dclk polo,dither */
2035 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2037 case SCREEN_DUAL_MIPI:
2038 val = V_MIPI_OUT_EN(1) | V_MIPI_DUAL_CHANNEL_EN(1);
2039 vop_msk_reg(vop_dev, SYS_CTRL, val);
2040 val = V_MIPI_HSYNC_POL(screen->pin_hsync) |
2041 V_MIPI_VSYNC_POL(screen->pin_vsync) |
2042 V_MIPI_DEN_POL(screen->pin_den) |
2043 V_MIPI_DCLK_POL(screen->pin_dclk);
2044 /*hsync vsync den dclk polo,dither */
2045 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2048 if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
2051 val = V_EDP_OUT_EN(1);
2052 vop_msk_reg(vop_dev, SYS_CTRL, val);
2053 val = V_EDP_HSYNC_POL(screen->pin_hsync) |
2054 V_EDP_VSYNC_POL(screen->pin_vsync) |
2055 V_EDP_DEN_POL(screen->pin_den) |
2056 V_EDP_DCLK_POL(screen->pin_dclk);
2057 /*hsync vsync den dclk polo,dither */
2058 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2062 if ((VOP_CHIP(vop_dev) == VOP_RK3399) &&
2063 ((screen->face == OUT_P888) ||
2064 (screen->face == OUT_P101010))) {
2065 if (vop_dev->id == 0)
2070 val = V_DP_OUT_EN(1);
2071 vop_msk_reg(vop_dev, SYS_CTRL, val);
2072 val = V_DP_HSYNC_POL(screen->pin_hsync) |
2073 V_DP_VSYNC_POL(screen->pin_vsync) |
2074 V_DP_DEN_POL(screen->pin_den) |
2075 V_DP_DCLK_POL(screen->pin_dclk);
2076 /*hsync vsync den dclk polo,dither */
2077 vop_msk_reg(vop_dev, DSP_CTRL1, val);
2080 dev_err(vop_dev->dev, "un supported interface[%d]!\n",
2085 if (screen->color_mode == COLOR_RGB)
2086 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
2088 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
2090 #ifndef CONFIG_RK_FPGA
2093 * writel_relaxed(v, RK_GRF_VIRT + vop_GRF_SOC_CON7);
2094 * move to lvds driver
2096 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
2098 val = V_DSP_OUT_MODE(face) | V_DSP_DCLK_DDR(dclk_ddr) |
2099 V_DSP_BG_SWAP(screen->swap_gb) |
2100 V_DSP_RB_SWAP(screen->swap_rb) |
2101 V_DSP_RG_SWAP(screen->swap_rg) |
2102 V_DSP_DELTA_SWAP(screen->swap_delta) |
2103 V_DSP_DUMMY_SWAP(screen->swap_dumy) | V_DSP_OUT_ZERO(0) |
2104 V_DSP_BLANK_EN(0) | V_DSP_BLACK_EN(0) |
2105 V_DSP_X_MIR_EN(screen->x_mirror) |
2106 V_DSP_Y_MIR_EN(screen->y_mirror);
2107 val |= V_SW_CORE_DCLK_SEL(!!screen->pixelrepeat);
2108 if (screen->mode.vmode & FB_VMODE_INTERLACED)
2109 val |= V_SW_HDMI_CLK_I_SEL(1);
2111 val |= V_SW_HDMI_CLK_I_SEL(0);
2112 vop_msk_reg(vop_dev, DSP_CTRL0, val);
2114 if (screen->mode.vmode & FB_VMODE_INTERLACED)
2115 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(1));
2117 vop_msk_reg(vop_dev, SYS_CTRL1, V_REG_DONE_FRM(0));
2119 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
2120 val = V_DSP_OUT_RGB_YUV(1);
2121 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2122 val = V_DSP_BG_BLUE(0x200) | V_DSP_BG_GREEN(0x40) |
2123 V_DSP_BG_RED(0x200);
2124 vop_msk_reg(vop_dev, DSP_BG, val);
2126 val = V_DSP_OUT_RGB_YUV(0);
2127 vop_msk_reg(vop_dev, POST_SCL_CTRL, val);
2128 val = V_DSP_BG_BLUE(0x55) | V_DSP_BG_GREEN(0x55) |
2130 vop_msk_reg(vop_dev, DSP_BG, val);
2132 dev_drv->output_color = screen->color_mode;
2133 vop_bcsh_path_sel(dev_drv);
2134 vop_config_timing(dev_drv);
2135 vop_cfg_done(vop_dev);
2137 spin_unlock(&vop_dev->reg_lock);
2138 vop_set_dclk(dev_drv, 1);
2139 if (screen->type != SCREEN_HDMI && screen->type != SCREEN_TVOUT &&
2140 dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2141 dev_drv->trsm_ops->enable();
2148 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv);
2149 static int vop_early_resume(struct rk_lcdc_driver *dev_drv);
2150 /*enable layer,open:1,enable;0 disable*/
2151 static void vop_layer_enable(struct vop_device *vop_dev,
2152 unsigned int win_id, bool open)
2154 spin_lock(&vop_dev->reg_lock);
2155 if (likely(vop_dev->clk_on) &&
2156 vop_dev->driver.win[win_id]->state != open) {
2158 if (!vop_dev->atv_layer_cnt) {
2159 dev_info(vop_dev->dev,
2160 "wakeup from standby!\n");
2161 vop_dev->standby = 0;
2163 vop_dev->atv_layer_cnt |= (1 << win_id);
2165 if (vop_dev->atv_layer_cnt & (1 << win_id))
2166 vop_dev->atv_layer_cnt &= ~(1 << win_id);
2168 vop_dev->driver.win[win_id]->state = open;
2170 vop_layer_update_regs(vop_dev,
2171 vop_dev->driver.win[win_id]);
2172 vop_cfg_done(vop_dev);
2175 spin_unlock(&vop_dev->reg_lock);
2176 /* if no layer used,disable lcdc */
2177 if (vop_dev->prop == EXTEND) {
2178 if (!vop_dev->atv_layer_cnt && !open) {
2179 vop_early_suspend(&vop_dev->driver);
2180 dev_info(vop_dev->dev,
2181 "no layer is used,go to standby!\n");
2182 vop_dev->standby = 1;
2184 vop_early_resume(&vop_dev->driver);
2185 dev_info(vop_dev->dev, "wake up from standby!\n");
2191 static int vop_enable_irq(struct rk_lcdc_driver *dev_drv)
2193 struct vop_device *vop_dev = container_of(dev_drv,
2194 struct vop_device, driver);
2196 /* struct rk_screen *screen = dev_drv->cur_screen; */
2198 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
2200 val = INTR_FS | INTR_LINE_FLAG0 | INTR_BUS_ERROR | INTR_LINE_FLAG1 |
2201 INTR_WIN0_EMPTY | INTR_WIN1_EMPTY | INTR_HWC_EMPTY |
2202 INTR_POST_BUF_EMPTY;
2205 vop_msk_reg(vop_dev, INTR_EN0, val);
2210 static int vop_open(struct rk_lcdc_driver *dev_drv, int win_id,
2213 struct vop_device *vop_dev =
2214 container_of(dev_drv, struct vop_device, driver);
2216 /* enable clk,when first layer open */
2217 if ((open) && (!vop_dev->atv_layer_cnt)) {
2218 /* rockchip_set_system_status(sys_status); */
2219 vop_pre_init(dev_drv);
2220 vop_clk_enable(vop_dev);
2221 vop_enable_irq(dev_drv);
2222 if (dev_drv->iommu_enabled) {
2223 if (!dev_drv->mmu_dev) {
2225 rk_fb_get_sysmmu_device_by_compatible
2226 (dev_drv->mmu_dts_name);
2227 if (dev_drv->mmu_dev) {
2228 rk_fb_platform_set_sysmmu
2229 (dev_drv->mmu_dev, dev_drv->dev);
2231 dev_err(dev_drv->dev,
2232 "fail get rk iommu device\n");
2237 if ((support_uboot_display() && (vop_dev->prop == PRMRY)))
2238 vop_set_dclk(dev_drv, 0);
2240 vop_load_screen(dev_drv, 1);
2241 if (dev_drv->bcsh.enable)
2242 vop_set_bcsh(dev_drv, 1);
2243 vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
2244 vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
2247 if (win_id < dev_drv->lcdc_win_num)
2248 vop_layer_enable(vop_dev, win_id, open);
2250 dev_err(vop_dev->dev, "invalid win id:%d\n", win_id);
2252 dev_drv->first_frame = 0;
2256 static int win_0_1_display(struct vop_device *vop_dev,
2257 struct rk_lcdc_win *win)
2263 off = win->id * 0x40;
2264 /*win->smem_start + win->y_offset; */
2265 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2266 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2267 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2268 vop_dev->id, win->id, y_addr, uv_addr);
2269 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2270 win->area[0].y_offset, win->area[0].c_offset);
2271 spin_lock(&vop_dev->reg_lock);
2272 if (likely(vop_dev->clk_on)) {
2273 win->area[0].y_addr = y_addr;
2274 win->area[0].uv_addr = uv_addr;
2275 vop_writel(vop_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2276 vop_writel(vop_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2277 if (win->area[0].fbdc_en == 1)
2278 vop_writel(vop_dev, AFBCD0_HDR_PTR,
2279 win->area[0].y_addr);
2281 spin_unlock(&vop_dev->reg_lock);
2286 static int win_2_3_display(struct vop_device *vop_dev,
2287 struct rk_lcdc_win *win)
2292 off = (win->id - 2) * 0x50;
2293 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2294 DBG(2, "lcdc[%d]:win[%d]:", vop_dev->id, win->id);
2296 if (likely(vop_dev->clk_on)) {
2297 for (i = 0; i < win->area_num; i++) {
2298 DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2299 i, win->area[i].y_addr, win->area[i].y_offset);
2300 win->area[i].y_addr =
2301 win->area[i].smem_start + win->area[i].y_offset;
2303 spin_lock(&vop_dev->reg_lock);
2304 vop_writel(vop_dev, WIN2_MST0 + off, win->area[0].y_addr);
2305 vop_writel(vop_dev, WIN2_MST1 + off, win->area[1].y_addr);
2306 vop_writel(vop_dev, WIN2_MST2 + off, win->area[2].y_addr);
2307 vop_writel(vop_dev, WIN2_MST3 + off, win->area[3].y_addr);
2308 if (win->area[0].fbdc_en == 1)
2309 vop_writel(vop_dev, AFBCD0_HDR_PTR,
2310 win->area[0].y_addr);
2311 spin_unlock(&vop_dev->reg_lock);
2316 static int hwc_display(struct vop_device *vop_dev, struct rk_lcdc_win *win)
2320 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2321 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2322 vop_dev->id, __func__, y_addr);
2323 spin_lock(&vop_dev->reg_lock);
2324 if (likely(vop_dev->clk_on)) {
2325 win->area[0].y_addr = y_addr;
2326 vop_writel(vop_dev, HWC_MST, win->area[0].y_addr);
2328 spin_unlock(&vop_dev->reg_lock);
2333 static int vop_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2335 struct vop_device *vop_dev =
2336 container_of(dev_drv, struct vop_device, driver);
2337 struct rk_lcdc_win *win = NULL;
2338 struct rk_screen *screen = dev_drv->cur_screen;
2340 win = dev_drv->win[win_id];
2342 dev_err(dev_drv->dev, "screen is null!\n");
2345 if (unlikely(!vop_dev->clk_on)) {
2346 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
2350 win_0_1_display(vop_dev, win);
2351 } else if (win_id == 1) {
2352 win_0_1_display(vop_dev, win);
2353 } else if (win_id == 2) {
2354 win_2_3_display(vop_dev, win);
2355 } else if (win_id == 3) {
2356 win_2_3_display(vop_dev, win);
2357 } else if (win_id == 4) {
2358 hwc_display(vop_dev, win);
2360 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2367 static int vop_cal_scl_fac(struct rk_lcdc_win *win, struct rk_screen *screen)
2377 u32 yrgb_vscalednmult = 0;
2378 u32 yrgb_xscl_factor = 0;
2379 u32 yrgb_yscl_factor = 0;
2380 u8 yrgb_vsd_bil_gt2 = 0;
2381 u8 yrgb_vsd_bil_gt4 = 0;
2387 u32 cbcr_vscalednmult = 0;
2388 u32 cbcr_xscl_factor = 0;
2389 u32 cbcr_yscl_factor = 0;
2390 u8 cbcr_vsd_bil_gt2 = 0;
2391 u8 cbcr_vsd_bil_gt4 = 0;
2394 srcW = win->area[0].xact;
2395 if ((screen->mode.vmode & FB_VMODE_INTERLACED) &&
2396 (win->area[0].yact == 2 * win->area[0].ysize)) {
2397 srcH = win->area[0].yact / 2;
2398 yrgb_vsd_bil_gt2 = 1;
2399 cbcr_vsd_bil_gt2 = 1;
2401 srcH = win->area[0].yact;
2403 dstW = win->area[0].xsize;
2404 dstH = win->area[0].ysize;
2411 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2412 pr_err("ERROR: yrgb scale exceed 8,");
2413 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2414 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2416 if (yrgb_srcW < yrgb_dstW)
2417 win->yrgb_hor_scl_mode = SCALE_UP;
2418 else if (yrgb_srcW > yrgb_dstW)
2419 win->yrgb_hor_scl_mode = SCALE_DOWN;
2421 win->yrgb_hor_scl_mode = SCALE_NONE;
2423 if (yrgb_srcH < yrgb_dstH)
2424 win->yrgb_ver_scl_mode = SCALE_UP;
2425 else if (yrgb_srcH > yrgb_dstH)
2426 win->yrgb_ver_scl_mode = SCALE_DOWN;
2428 win->yrgb_ver_scl_mode = SCALE_NONE;
2431 switch (win->area[0].format) {
2436 cbcr_srcW = srcW / 2;
2447 cbcr_srcW = srcW / 2;
2449 cbcr_srcH = srcH / 2;
2470 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2471 (cbcr_dstH * 8 <= cbcr_srcH)) {
2472 pr_err("ERROR: cbcr scale exceed 8,");
2473 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2474 cbcr_srcH, cbcr_dstW, cbcr_dstH);
2478 if (cbcr_srcW < cbcr_dstW)
2479 win->cbr_hor_scl_mode = SCALE_UP;
2480 else if (cbcr_srcW > cbcr_dstW)
2481 win->cbr_hor_scl_mode = SCALE_DOWN;
2483 win->cbr_hor_scl_mode = SCALE_NONE;
2485 if (cbcr_srcH < cbcr_dstH)
2486 win->cbr_ver_scl_mode = SCALE_UP;
2487 else if (cbcr_srcH > cbcr_dstH)
2488 win->cbr_ver_scl_mode = SCALE_DOWN;
2490 win->cbr_ver_scl_mode = SCALE_NONE;
2492 /* line buffer mode */
2493 if ((win->area[0].format == YUV422) ||
2494 (win->area[0].format == YUV420) ||
2495 (win->area[0].format == YUYV422) ||
2496 (win->area[0].format == YUYV420) ||
2497 (win->area[0].format == UYVY422) ||
2498 (win->area[0].format == UYVY420) ||
2499 (win->area[0].format == YUV420_NV21) ||
2500 (win->area[0].format == YUV422_A) ||
2501 (win->area[0].format == YUV420_A)) {
2502 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2503 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2505 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2507 else if (cbcr_dstW > 1280)
2508 win->win_lb_mode = LB_YUV_3840X5;
2510 win->win_lb_mode = LB_YUV_2560X8;
2511 } else { /* SCALE_UP or SCALE_NONE */
2512 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2514 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2516 else if (cbcr_srcW > 1280)
2517 win->win_lb_mode = LB_YUV_3840X5;
2519 win->win_lb_mode = LB_YUV_2560X8;
2522 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2523 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2525 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2526 else if (yrgb_dstW > 2560)
2527 win->win_lb_mode = LB_RGB_3840X2;
2528 else if (yrgb_dstW > 1920)
2529 win->win_lb_mode = LB_RGB_2560X4;
2530 else if (yrgb_dstW > 1280)
2531 win->win_lb_mode = LB_RGB_1920X5;
2533 win->win_lb_mode = LB_RGB_1280X8;
2534 } else { /* SCALE_UP or SCALE_NONE */
2535 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2537 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2538 else if (yrgb_srcW > 2560)
2539 win->win_lb_mode = LB_RGB_3840X2;
2540 else if (yrgb_srcW > 1920)
2541 win->win_lb_mode = LB_RGB_2560X4;
2542 else if (yrgb_srcW > 1280)
2543 win->win_lb_mode = LB_RGB_1920X5;
2545 win->win_lb_mode = LB_RGB_1280X8;
2548 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2550 /* vsd/vsu scale ALGORITHM */
2551 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2552 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2553 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2554 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2556 /* if (VOP_CHIP(vop_dev) == VOP_RK3399) { */
2557 if ((win->area[0].format == YUYV422) ||
2558 (win->area[0].format == YUYV420) ||
2559 (win->area[0].format == UYVY422) ||
2560 (win->area[0].format == UYVY420)) {
2562 vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2563 if (yrgb_vscalednmult == 4) {
2564 yrgb_vsd_bil_gt4 = 1;
2565 yrgb_vsd_bil_gt2 = 0;
2566 } else if (yrgb_vscalednmult == 2) {
2567 yrgb_vsd_bil_gt4 = 0;
2568 yrgb_vsd_bil_gt2 = 1;
2570 yrgb_vsd_bil_gt4 = 0;
2571 yrgb_vsd_bil_gt2 = 0;
2573 if ((win->area[0].format == YUYV420) ||
2574 (win->area[0].format == UYVY420)) {
2575 if ((yrgb_vsd_bil_gt4 == 1) || (yrgb_vsd_bil_gt2 == 1))
2576 win->yrgb_vsd_mode = SCALE_DOWN_AVG;
2580 vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2581 if (cbcr_vscalednmult == 4) {
2582 cbcr_vsd_bil_gt4 = 1;
2583 cbcr_vsd_bil_gt2 = 0;
2584 } else if (cbcr_vscalednmult == 2) {
2585 cbcr_vsd_bil_gt4 = 0;
2586 cbcr_vsd_bil_gt2 = 1;
2588 cbcr_vsd_bil_gt4 = 0;
2589 cbcr_vsd_bil_gt2 = 0;
2591 if ((win->area[0].format == YUYV420) ||
2592 (win->area[0].format == UYVY420)) {
2593 if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1))
2594 win->cbr_vsd_mode = SCALE_DOWN_AVG;
2596 /* CBCR vsd_mode must same to YRGB for YUYV when gt2 or gt4 */
2597 if ((cbcr_vsd_bil_gt4 == 1) || (cbcr_vsd_bil_gt2 == 1)) {
2598 if (win->yrgb_vsd_mode != win->cbr_vsd_mode)
2599 win->cbr_vsd_mode = win->yrgb_vsd_mode;
2602 /* 3399 yuyv support*/
2603 if (win->ymirror == 1) {
2604 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2605 pr_info("y_mirror enable, y-vsd AVG mode unsupprot\n");
2606 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2608 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
2609 if (win->yrgb_vsd_mode == SCALE_DOWN_AVG)
2610 pr_info("interlace mode, y-vsd AVG mode unsupprot\n");
2611 /* interlace mode must bill */
2612 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2613 win->cbr_vsd_mode = SCALE_DOWN_BIL;
2615 switch (win->win_lb_mode) {
2620 win->yrgb_vsu_mode = SCALE_UP_BIC;
2621 win->cbr_vsu_mode = SCALE_UP_BIC;
2624 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2625 pr_err("ERROR : not allow yrgb ver scale\n");
2626 if (win->cbr_ver_scl_mode != SCALE_NONE)
2627 pr_err("ERROR : not allow cbcr ver scale\n");
2630 win->yrgb_vsu_mode = SCALE_UP_BIL;
2631 win->cbr_vsu_mode = SCALE_UP_BIL;
2634 pr_info("%s:un supported win_lb_mode:%d\n",
2635 __func__, win->win_lb_mode);
2639 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2640 (win->area[0].fbdc_en == 1)) {
2641 /* in this pattern,use bil mode,not support souble scd,
2642 * use avg mode, support double scd, but aclk should be
2645 if (yrgb_srcH >= 2 * yrgb_dstH) {
2646 pr_err("ERROR : fbdc mode,not support y scale down:");
2647 pr_err("srcH[%d] > 2 *dstH[%d]\n",
2648 yrgb_srcH, yrgb_dstH);
2651 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2652 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2653 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2657 /* (1.1)YRGB HOR SCALE FACTOR */
2658 switch (win->yrgb_hor_scl_mode) {
2660 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2663 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2666 switch (win->yrgb_hsd_mode) {
2667 case SCALE_DOWN_BIL:
2669 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2671 case SCALE_DOWN_AVG:
2673 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2676 pr_info("%s:un supported yrgb_hsd_mode:%d\n", __func__,
2677 win->yrgb_hsd_mode);
2682 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2683 __func__, win->yrgb_hor_scl_mode);
2687 /* (1.2)YRGB VER SCALE FACTOR */
2688 switch (win->yrgb_ver_scl_mode) {
2690 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2693 switch (win->yrgb_vsu_mode) {
2696 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2699 if (yrgb_srcH < 3) {
2700 pr_err("yrgb_srcH should be");
2701 pr_err(" greater than 3 !!!\n");
2703 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2707 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2708 __func__, win->yrgb_vsu_mode);
2713 switch (win->yrgb_vsd_mode) {
2714 case SCALE_DOWN_BIL:
2716 vop_get_hard_ware_vskiplines(yrgb_srcH, yrgb_dstH);
2718 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2720 if (yrgb_yscl_factor >= 0x2000) {
2721 pr_err("yrgb_yscl_factor should less 0x2000");
2722 pr_err("yrgb_yscl_factor=%4x;\n",
2725 if (yrgb_vscalednmult == 4) {
2726 yrgb_vsd_bil_gt4 = 1;
2727 yrgb_vsd_bil_gt2 = 0;
2728 } else if (yrgb_vscalednmult == 2) {
2729 yrgb_vsd_bil_gt4 = 0;
2730 yrgb_vsd_bil_gt2 = 1;
2732 yrgb_vsd_bil_gt4 = 0;
2733 yrgb_vsd_bil_gt2 = 0;
2736 case SCALE_DOWN_AVG:
2737 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2741 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2742 __func__, win->yrgb_vsd_mode);
2744 } /*win->yrgb_vsd_mode */
2747 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2748 __func__, win->yrgb_ver_scl_mode);
2751 win->scale_yrgb_x = yrgb_xscl_factor;
2752 win->scale_yrgb_y = yrgb_yscl_factor;
2753 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2754 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2755 DBG(1, "yrgb:h_fac=%d, V_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2756 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2758 /*(2.1)CBCR HOR SCALE FACTOR */
2759 switch (win->cbr_hor_scl_mode) {
2761 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2764 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2767 switch (win->cbr_hsd_mode) {
2768 case SCALE_DOWN_BIL:
2770 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2772 case SCALE_DOWN_AVG:
2774 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2777 pr_info("%s:un support cbr_hsd_mode:%d\n",
2778 __func__, win->cbr_hsd_mode);
2783 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2784 __func__, win->cbr_hor_scl_mode);
2786 } /*win->cbr_hor_scl_mode */
2788 /* (2.2)CBCR VER SCALE FACTOR */
2789 switch (win->cbr_ver_scl_mode) {
2791 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2794 switch (win->cbr_vsu_mode) {
2797 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2800 if (cbcr_srcH < 3) {
2801 pr_err("cbcr_srcH should be ");
2802 pr_err("greater than 3 !!!\n");
2804 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2808 pr_info("%s:un support cbr_vsu_mode:%d\n",
2809 __func__, win->cbr_vsu_mode);
2814 switch (win->cbr_vsd_mode) {
2815 case SCALE_DOWN_BIL:
2817 vop_get_hard_ware_vskiplines(cbcr_srcH, cbcr_dstH);
2819 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2821 if (cbcr_yscl_factor >= 0x2000) {
2822 pr_err("cbcr_yscl_factor should be less ");
2823 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2827 if (cbcr_vscalednmult == 4) {
2828 cbcr_vsd_bil_gt4 = 1;
2829 cbcr_vsd_bil_gt2 = 0;
2830 } else if (cbcr_vscalednmult == 2) {
2831 cbcr_vsd_bil_gt4 = 0;
2832 cbcr_vsd_bil_gt2 = 1;
2834 cbcr_vsd_bil_gt4 = 0;
2835 cbcr_vsd_bil_gt2 = 0;
2838 case SCALE_DOWN_AVG:
2839 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2843 pr_info("%s:un support cbr_vsd_mode:%d\n",
2844 __func__, win->cbr_vsd_mode);
2849 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2850 __func__, win->cbr_ver_scl_mode);
2853 win->scale_cbcr_x = cbcr_xscl_factor;
2854 win->scale_cbcr_y = cbcr_yscl_factor;
2855 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2856 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2858 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2859 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2863 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2864 struct rk_lcdc_win_area *area)
2868 if (screen->x_mirror && mirror_en)
2869 pr_err("not support both win and global mirror\n");
2871 if ((!mirror_en) && (!screen->x_mirror))
2872 pos = area->xpos + screen->mode.left_margin +
2873 screen->mode.hsync_len;
2875 pos = screen->mode.xres - area->xpos -
2876 area->xsize + screen->mode.left_margin +
2877 screen->mode.hsync_len;
2882 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2883 struct rk_lcdc_win_area *area)
2887 if (screen->y_mirror && mirror_en)
2888 pr_err("not support both win and global mirror\n");
2890 if ((!mirror_en) && (!screen->y_mirror))
2891 pos = area->ypos + screen->mode.upper_margin +
2892 screen->mode.vsync_len;
2894 pos = screen->mode.yres - area->ypos -
2895 area->ysize + screen->mode.upper_margin +
2896 screen->mode.vsync_len;
2901 static int win_0_1_set_par(struct vop_device *vop_dev,
2902 struct rk_screen *screen, struct rk_lcdc_win *win)
2904 u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
2905 u8 fmt_cfg = 0, swap_rb = 0, swap_uv = 0;
2906 char fmt[9] = "NULL";
2908 xpos = dsp_x_pos(win->xmirror, screen, &win->area[0]);
2909 ypos = dsp_y_pos(win->ymirror, screen, &win->area[0]);
2911 spin_lock(&vop_dev->reg_lock);
2912 if (likely(vop_dev->clk_on)) {
2913 vop_cal_scl_fac(win, screen);
2914 switch (win->area[0].format) {
2919 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_RGB565;
2925 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2931 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
2937 win->area[0].fbdc_fmt_cfg = AFBDC_FMT_U8U8U8U8;
3005 win->area[0].yuyv_fmt = 1;
3011 win->area[0].yuyv_fmt = 1;
3017 win->area[0].yuyv_fmt = 1;
3023 win->area[0].yuyv_fmt = 1;
3026 dev_err(vop_dev->dev, "%s:unsupport format[%d]!\n",
3027 __func__, win->area[0].format);
3030 win->area[0].fmt_cfg = fmt_cfg;
3031 win->area[0].swap_rb = swap_rb;
3032 win->area[0].swap_uv = swap_uv;
3033 win->area[0].dsp_stx = xpos;
3034 win->area[0].dsp_sty = ypos;
3035 xact = win->area[0].xact;
3036 yact = win->area[0].yact;
3037 xvir = win->area[0].xvir;
3038 yvir = win->area[0].yvir;
3040 if (win->area[0].fbdc_en)
3041 vop_init_fbdc_config(vop_dev, win->id);
3042 vop_win_0_1_reg_update(&vop_dev->driver, win->id);
3043 spin_unlock(&vop_dev->reg_lock);
3045 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3046 vop_dev->id, win->id, get_format_string(win->area[0].format, fmt),
3047 xact, yact, win->area[0].xsize);
3048 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3049 win->area[0].ysize, xvir, yvir, xpos, ypos);
3054 static int win_2_3_set_par(struct vop_device *vop_dev,
3055 struct rk_screen *screen, struct rk_lcdc_win *win)
3058 u8 fmt_cfg = 0, swap_rb = 0;
3059 char fmt[9] = "NULL";
3061 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
3062 pr_err("rk3228 not support win2/3 set par\n");
3066 pr_err("win[%d] not support y mirror\n", win->id);
3069 spin_lock(&vop_dev->reg_lock);
3070 if (likely(vop_dev->clk_on)) {
3071 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", vop_dev->id, win->id);
3072 for (i = 0; i < win->area_num; i++) {
3073 switch (win->area[i].format) {
3078 win->area[0].fbdc_fmt_cfg = 0x05;
3084 win->area[0].fbdc_fmt_cfg = 0x0c;
3090 win->area[0].fbdc_fmt_cfg = 0x3a;
3110 dev_err(vop_dev->driver.dev,
3111 "%s:un supported format!\n", __func__);
3112 spin_unlock(&vop_dev->reg_lock);
3115 win->area[i].fmt_cfg = fmt_cfg;
3116 win->area[i].swap_rb = swap_rb;
3117 win->area[i].dsp_stx = dsp_x_pos(win->xmirror, screen,
3119 win->area[i].dsp_sty = dsp_y_pos(win->ymirror, screen,
3121 if (((win->area[i].xact != win->area[i].xsize) ||
3122 (win->area[i].yact != win->area[i].ysize)) &&
3123 (screen->mode.vmode == FB_VMODE_NONINTERLACED)) {
3124 pr_err("win[%d]->area[%d],not support scale\n",
3126 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
3127 win->area[i].xact, win->area[i].yact,
3128 win->area[i].xsize, win->area[i].ysize);
3129 win->area[i].xsize = win->area[i].xact;
3130 win->area[i].ysize = win->area[i].yact;
3132 DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
3133 get_format_string(win->area[i].format, fmt),
3134 win->area[i].xsize, win->area[i].ysize,
3135 win->area[i].xpos, win->area[i].ypos);
3138 if (win->area[0].fbdc_en)
3139 vop_init_fbdc_config(vop_dev, win->id);
3140 vop_win_2_3_reg_update(&vop_dev->driver, win->id);
3141 spin_unlock(&vop_dev->reg_lock);
3145 static int hwc_set_par(struct vop_device *vop_dev,
3146 struct rk_screen *screen, struct rk_lcdc_win *win)
3148 u32 xact = 0, yact = 0, xvir = 0, yvir = 0, xpos = 0, ypos = 0;
3149 u8 fmt_cfg = 0, swap_rb = 0;
3150 char fmt[9] = "NULL";
3152 xpos = win->area[0].xpos + screen->mode.left_margin +
3153 screen->mode.hsync_len;
3154 ypos = win->area[0].ypos + screen->mode.upper_margin +
3155 screen->mode.vsync_len;
3157 spin_lock(&vop_dev->reg_lock);
3158 if (likely(vop_dev->clk_on)) {
3159 switch (win->area[0].format) {
3178 dev_err(vop_dev->dev, "%s:un supported format[%d]!\n",
3179 __func__, win->area[0].format);
3182 win->area[0].fmt_cfg = fmt_cfg;
3183 win->area[0].swap_rb = swap_rb;
3184 win->area[0].dsp_stx = xpos;
3185 win->area[0].dsp_sty = ypos;
3186 xact = win->area[0].xact;
3187 yact = win->area[0].yact;
3188 xvir = win->area[0].xvir;
3189 yvir = win->area[0].yvir;
3191 vop_hwc_reg_update(&vop_dev->driver, 4);
3192 spin_unlock(&vop_dev->reg_lock);
3194 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
3195 vop_dev->id, __func__, get_format_string(win->area[0].format, fmt),
3196 xact, yact, win->area[0].xsize);
3197 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
3198 win->area[0].ysize, xvir, yvir, xpos, ypos);
3202 static int vop_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
3204 struct vop_device *vop_dev =
3205 container_of(dev_drv, struct vop_device, driver);
3206 struct rk_lcdc_win *win = NULL;
3207 struct rk_screen *screen = dev_drv->cur_screen;
3209 if (unlikely(!vop_dev->clk_on)) {
3210 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3213 win = dev_drv->win[win_id];
3217 win_0_1_set_par(vop_dev, screen, win);
3220 win_0_1_set_par(vop_dev, screen, win);
3223 win_2_3_set_par(vop_dev, screen, win);
3226 win_2_3_set_par(vop_dev, screen, win);
3229 hwc_set_par(vop_dev, screen, win);
3232 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
3238 static int vop_set_writeback(struct rk_lcdc_driver *dev_drv)
3240 struct vop_device *vop_dev =
3241 container_of(dev_drv, struct vop_device, driver);
3242 int output_color = dev_drv->output_color;
3243 struct rk_screen *screen = dev_drv->cur_screen;
3244 struct rk_fb_reg_wb_data *wb_data;
3245 int xact = screen->mode.xres;
3246 int yact = screen->mode.yres;
3251 if (unlikely(!vop_dev->clk_on)) {
3252 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
3255 wb_data = &dev_drv->wb_data;
3256 if ((wb_data->xsize == 0) || (wb_data->ysize == 0))
3259 xsize = wb_data->xsize;
3260 ysize = wb_data->ysize;
3263 * RGB overlay mode support ARGB888, RGB888, RGB565, NV12,
3264 * but YUV overlay mode only support NV12, it's hard to judge RGB
3265 * or YUV overlay mode by userspace, so here force only support
3268 if (wb_data->data_format != YUV420 && output_color != COLOR_RGB) {
3269 pr_err("writeback only support NV12 when overlay is not RGB\n");
3273 if (ysize != yact && ysize != (yact / 2)) {
3274 pr_err("WriteBack only support yact=%d, ysize=%d\n",
3279 switch (wb_data->data_format) {
3298 pr_info("unsupport fmt: %d\n", wb_data->data_format);
3302 v = V_WB_EN(wb_data->state) | V_WB_FMT(fmt_cfg) | V_WB_RGB2YUV_MODE(1) |
3303 V_WB_XPSD_BIL_EN(xact != xsize) |
3304 V_WB_YTHROW_EN(ysize == (yact / 2)) |
3305 V_WB_YTHROW_MODE(0);
3307 v |= V_WB_RGB2YUV_EN((output_color == COLOR_RGB) &&
3308 (wb_data->data_format == YUV420));
3310 vop_msk_reg(vop_dev, WB_CTRL0, v);
3312 v = V_WB_WIDTH(xsize) | V_WB_XPSD_BIL_FACTOR((xact << 12) / xsize);
3314 vop_msk_reg(vop_dev, WB_CTRL1, v);
3316 vop_writel(vop_dev, WB_YRGB_MST, wb_data->smem_start);
3317 if (wb_data->data_format == YUV420)
3318 vop_writel(vop_dev, WB_CBR_MST, wb_data->smem_start);
3323 static int vop_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
3324 unsigned long arg, int win_id)
3326 struct vop_device *vop_dev =
3327 container_of(dev_drv, struct vop_device, driver);
3329 void __user *argp = (void __user *)arg;
3330 struct color_key_cfg clr_key_cfg;
3333 case RK_FBIOGET_PANEL_SIZE:
3334 panel_size[0] = vop_dev->screen->mode.xres;
3335 panel_size[1] = vop_dev->screen->mode.yres;
3336 if (copy_to_user(argp, panel_size, 8))
3339 case RK_FBIOPUT_COLOR_KEY_CFG:
3340 if (copy_from_user(&clr_key_cfg, argp, sizeof(clr_key_cfg)))
3342 vop_clr_key_cfg(dev_drv);
3343 vop_writel(vop_dev, WIN0_COLOR_KEY,
3344 clr_key_cfg.win0_color_key_cfg);
3345 vop_writel(vop_dev, WIN1_COLOR_KEY,
3346 clr_key_cfg.win1_color_key_cfg);
3355 static int vop_get_backlight_device(struct rk_lcdc_driver *dev_drv)
3357 struct vop_device *vop_dev = container_of(dev_drv,
3358 struct vop_device, driver);
3359 struct device_node *backlight;
3360 struct property *prop;
3361 u32 *brightness_levels;
3362 u32 length, max, last;
3364 if (vop_dev->backlight)
3366 backlight = of_parse_phandle(vop_dev->dev->of_node, "backlight", 0);
3368 vop_dev->backlight = of_find_backlight_by_node(backlight);
3369 if (!vop_dev->backlight)
3370 dev_info(vop_dev->dev, "No find backlight device\n");
3372 dev_info(vop_dev->dev, "No find backlight device node\n");
3374 prop = of_find_property(backlight, "brightness-levels", &length);
3377 max = length / sizeof(u32);
3379 brightness_levels = kmalloc(256, GFP_KERNEL);
3380 if (brightness_levels)
3383 if (!of_property_read_u32_array(backlight, "brightness-levels",
3384 brightness_levels, max)) {
3385 if (brightness_levels[0] > brightness_levels[last])
3386 dev_drv->cabc_pwm_pol = 1;/*negative*/
3388 dev_drv->cabc_pwm_pol = 0;/*positive*/
3390 dev_info(vop_dev->dev,
3391 "Can not read brightness-levels value\n");
3394 kfree(brightness_levels);
3399 static int vop_early_suspend(struct rk_lcdc_driver *dev_drv)
3401 struct vop_device *vop_dev =
3402 container_of(dev_drv, struct vop_device, driver);
3404 if (dev_drv->suspend_flag)
3407 dev_drv->suspend_flag = 1;
3408 /* ensure suspend_flag take effect on multi process */
3410 flush_kthread_worker(&dev_drv->update_regs_worker);
3412 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3413 dev_drv->trsm_ops->disable();
3415 if (likely(vop_dev->clk_on)) {
3416 spin_lock(&vop_dev->reg_lock);
3417 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(1));
3418 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, INTR_MASK);
3419 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(1));
3420 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(1));
3421 vop_cfg_done(vop_dev);
3423 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3425 rockchip_iovmm_deactivate(dev_drv->dev);
3428 spin_unlock(&vop_dev->reg_lock);
3431 vop_clk_disable(vop_dev);
3432 rk_disp_pwr_disable(dev_drv);
3437 static int vop_early_resume(struct rk_lcdc_driver *dev_drv)
3439 struct vop_device *vop_dev =
3440 container_of(dev_drv, struct vop_device, driver);
3442 if (!dev_drv->suspend_flag)
3444 rk_disp_pwr_enable(dev_drv);
3446 vop_clk_enable(vop_dev);
3447 spin_lock(&vop_dev->reg_lock);
3448 memcpy(vop_dev->regs, vop_dev->regsbak, vop_dev->len);
3449 spin_unlock(&vop_dev->reg_lock);
3451 vop_set_lut(dev_drv, dev_drv->cur_screen->dsp_lut);
3452 vop_set_cabc(dev_drv, dev_drv->cur_screen->cabc_lut);
3453 spin_lock(&vop_dev->reg_lock);
3455 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_OUT_ZERO(0));
3456 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(0));
3457 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLANK_EN(0));
3458 vop_cfg_done(vop_dev);
3459 spin_unlock(&vop_dev->reg_lock);
3461 if (dev_drv->iommu_enabled && dev_drv->mmu_dev) {
3462 /* win address maybe effect after next frame start,
3463 * but mmu maybe effect right now, so we delay 50ms
3466 rockchip_iovmm_activate(dev_drv->dev);
3469 dev_drv->suspend_flag = 0;
3471 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3472 dev_drv->trsm_ops->enable();
3477 static int vop_blank(struct rk_lcdc_driver *dev_drv, int win_id, int blank_mode)
3479 switch (blank_mode) {
3480 case FB_BLANK_UNBLANK:
3481 vop_early_resume(dev_drv);
3483 case FB_BLANK_NORMAL:
3484 vop_early_suspend(dev_drv);
3487 vop_early_suspend(dev_drv);
3491 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3496 static int vop_get_win_state(struct rk_lcdc_driver *dev_drv,
3497 int win_id, int area_id)
3499 struct vop_device *vop_dev =
3500 container_of(dev_drv, struct vop_device, driver);
3501 u32 area_status = 0, state = 0;
3505 area_status = vop_read_bit(vop_dev, WIN0_CTRL0, V_WIN0_EN(0));
3508 area_status = vop_read_bit(vop_dev, WIN1_CTRL0, V_WIN1_EN(0));
3512 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3515 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3518 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3521 area_status = vop_read_bit(vop_dev, WIN2_CTRL0,
3526 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3529 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3532 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3535 area_status = vop_read_bit(vop_dev, WIN3_CTRL0,
3539 area_status = vop_read_bit(vop_dev, HWC_CTRL0, V_HWC_EN(0));
3542 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",
3543 __func__, win_id, area_id);
3547 state = (area_status > 0) ? 1 : 0;
3551 static int vop_get_area_num(struct rk_lcdc_driver *dev_drv,
3552 unsigned int *area_support)
3554 struct vop_device *vop_dev =
3555 container_of(dev_drv, struct vop_device, driver);
3557 area_support[0] = 1;
3558 area_support[1] = 1;
3560 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
3561 area_support[2] = 4;
3562 area_support[3] = 4;
3568 /*overlay will be do at regupdate*/
3569 static int vop_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap, bool set)
3571 struct vop_device *vop_dev =
3572 container_of(dev_drv, struct vop_device, driver);
3573 struct rk_lcdc_win *win = NULL;
3576 int z_order_num = 0;
3577 int layer0_sel = 0, layer1_sel = 1, layer2_sel = 2, layer3_sel = 3;
3580 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3581 win = dev_drv->win[i];
3582 if (win->state == 1)
3585 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
3586 win = dev_drv->win[i];
3587 if (win->state == 0)
3588 win->z_order = z_order_num++;
3589 switch (win->z_order) {
3591 layer0_sel = win->id;
3594 layer1_sel = win->id;
3597 layer2_sel = win->id;
3600 layer3_sel = win->id;
3607 layer0_sel = swap % 10;
3608 layer1_sel = swap / 10 % 10;
3609 layer2_sel = swap / 100 % 10;
3610 layer3_sel = swap / 1000;
3613 spin_lock(&vop_dev->reg_lock);
3614 if (vop_dev->clk_on) {
3616 val = V_DSP_LAYER0_SEL(layer0_sel) |
3617 V_DSP_LAYER1_SEL(layer1_sel) |
3618 V_DSP_LAYER2_SEL(layer2_sel) |
3619 V_DSP_LAYER3_SEL(layer3_sel);
3620 vop_msk_reg(vop_dev, DSP_CTRL1, val);
3622 layer0_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3623 V_DSP_LAYER0_SEL(0));
3624 layer1_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3625 V_DSP_LAYER1_SEL(0));
3626 layer2_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3627 V_DSP_LAYER2_SEL(0));
3628 layer3_sel = vop_read_bit(vop_dev, DSP_CTRL1,
3629 V_DSP_LAYER3_SEL(0));
3630 ovl = layer3_sel * 1000 + layer2_sel * 100 +
3631 layer1_sel * 10 + layer0_sel;
3636 spin_unlock(&vop_dev->reg_lock);
3641 static char *vop_format_to_string(int format, char *fmt)
3648 strcpy(fmt, "ARGB888");
3651 strcpy(fmt, "RGB888");
3654 strcpy(fmt, "RGB565");
3657 strcpy(fmt, "YCbCr420");
3660 strcpy(fmt, "YCbCr422");
3663 strcpy(fmt, "YCbCr444");
3665 strcpy(fmt, "YUYV422");
3668 strcpy(fmt, "YUYV420");
3671 strcpy(fmt, "UYVY422");
3674 strcpy(fmt, "UYVY420");
3677 strcpy(fmt, "invalid\n");
3683 static ssize_t vop_get_disp_info(struct rk_lcdc_driver *dev_drv,
3684 char *buf, int win_id)
3686 struct vop_device *vop_dev =
3687 container_of(dev_drv, struct vop_device, driver);
3688 struct rk_screen *screen = dev_drv->cur_screen;
3689 u16 hsync_len = screen->mode.hsync_len;
3690 u16 left_margin = screen->mode.left_margin;
3691 u16 vsync_len = screen->mode.vsync_len;
3692 u16 upper_margin = screen->mode.upper_margin;
3693 u32 h_pw_bp = hsync_len + left_margin;
3694 u32 v_pw_bp = vsync_len + upper_margin;
3696 char format_w0[9] = "NULL";
3697 char format_w1[9] = "NULL";
3698 char format_w2_0[9] = "NULL";
3699 char format_w2_1[9] = "NULL";
3700 char format_w2_2[9] = "NULL";
3701 char format_w2_3[9] = "NULL";
3702 char format_w3_0[9] = "NULL";
3703 char format_w3_1[9] = "NULL";
3704 char format_w3_2[9] = "NULL";
3705 char format_w3_3[9] = "NULL";
3707 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3708 u32 y_factor, uv_factor;
3709 u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3710 u8 w0_state, w1_state, w2_state, w3_state;
3711 u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3712 u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3714 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3715 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3716 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3717 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3718 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3719 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3721 u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3722 u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3723 u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3724 u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3725 u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3726 u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3727 u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3729 u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3730 u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3731 u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3732 u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3733 u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3734 u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3735 u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3739 dclk_freq = screen->mode.pixclock;
3740 /*vop_reg_dump(dev_drv); */
3742 spin_lock(&vop_dev->reg_lock);
3743 if (vop_dev->clk_on) {
3744 zorder = vop_readl(vop_dev, DSP_CTRL1);
3745 layer0_sel = (zorder & MASK(DSP_LAYER0_SEL)) >> 8;
3746 layer1_sel = (zorder & MASK(DSP_LAYER1_SEL)) >> 10;
3747 layer2_sel = (zorder & MASK(DSP_LAYER2_SEL)) >> 12;
3748 layer3_sel = (zorder & MASK(DSP_LAYER3_SEL)) >> 14;
3750 win_ctrl = vop_readl(vop_dev, WIN0_CTRL0);
3751 w0_state = win_ctrl & MASK(WIN0_EN);
3752 fmt_id = (win_ctrl & MASK(WIN0_DATA_FMT)) >> 1;
3753 fmt_id |= (win_ctrl & MASK(WIN0_YUYV)) >> 14; /* yuyv*/
3754 vop_format_to_string(fmt_id, format_w0);
3755 vir_info = vop_readl(vop_dev, WIN0_VIR);
3756 act_info = vop_readl(vop_dev, WIN0_ACT_INFO);
3757 dsp_info = vop_readl(vop_dev, WIN0_DSP_INFO);
3758 dsp_st = vop_readl(vop_dev, WIN0_DSP_ST);
3759 y_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_YRGB);
3760 uv_factor = vop_readl(vop_dev, WIN0_SCL_FACTOR_CBR);
3761 w0_vir_y = vir_info & MASK(WIN0_VIR_STRIDE);
3762 w0_vir_uv = (vir_info & MASK(WIN0_VIR_STRIDE_UV)) >> 16;
3763 w0_act_x = (act_info & MASK(WIN0_ACT_WIDTH)) + 1;
3764 w0_act_y = ((act_info & MASK(WIN0_ACT_HEIGHT)) >> 16) + 1;
3765 w0_dsp_x = (dsp_info & MASK(WIN0_DSP_WIDTH)) + 1;
3766 w0_dsp_y = ((dsp_info & MASK(WIN0_DSP_HEIGHT)) >> 16) + 1;
3768 w0_st_x = dsp_st & MASK(WIN0_DSP_XST);
3769 w0_st_y = (dsp_st & MASK(WIN0_DSP_YST)) >> 16;
3771 w0_y_h_fac = y_factor & MASK(WIN0_HS_FACTOR_YRGB);
3772 w0_y_v_fac = (y_factor & MASK(WIN0_VS_FACTOR_YRGB)) >> 16;
3773 w0_uv_h_fac = uv_factor & MASK(WIN0_HS_FACTOR_CBR);
3774 w0_uv_v_fac = (uv_factor & MASK(WIN0_VS_FACTOR_CBR)) >> 16;
3777 win_ctrl = vop_readl(vop_dev, WIN1_CTRL0);
3778 w1_state = win_ctrl & MASK(WIN1_EN);
3779 fmt_id = (win_ctrl & MASK(WIN1_DATA_FMT)) >> 1;
3780 fmt_id |= (win_ctrl & MASK(WIN1_YUYV)) >> 14; /* yuyv*/
3781 vop_format_to_string(fmt_id, format_w1);
3782 vir_info = vop_readl(vop_dev, WIN1_VIR);
3783 act_info = vop_readl(vop_dev, WIN1_ACT_INFO);
3784 dsp_info = vop_readl(vop_dev, WIN1_DSP_INFO);
3785 dsp_st = vop_readl(vop_dev, WIN1_DSP_ST);
3786 y_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_YRGB);
3787 uv_factor = vop_readl(vop_dev, WIN1_SCL_FACTOR_CBR);
3788 w1_vir_y = vir_info & MASK(WIN1_VIR_STRIDE);
3789 w1_vir_uv = (vir_info & MASK(WIN1_VIR_STRIDE_UV)) >> 16;
3790 w1_act_x = (act_info & MASK(WIN1_ACT_WIDTH)) + 1;
3791 w1_act_y = ((act_info & MASK(WIN1_ACT_HEIGHT)) >> 16) + 1;
3792 w1_dsp_x = (dsp_info & MASK(WIN1_DSP_WIDTH)) + 1;
3793 w1_dsp_y = ((dsp_info & MASK(WIN1_DSP_HEIGHT)) >> 16) + 1;
3795 w1_st_x = dsp_st & MASK(WIN1_DSP_XST);
3796 w1_st_y = (dsp_st & MASK(WIN1_DSP_YST)) >> 16;
3798 w1_y_h_fac = y_factor & MASK(WIN1_HS_FACTOR_YRGB);
3799 w1_y_v_fac = (y_factor & MASK(WIN1_VS_FACTOR_YRGB)) >> 16;
3800 w1_uv_h_fac = uv_factor & MASK(WIN1_HS_FACTOR_CBR);
3801 w1_uv_v_fac = (uv_factor & MASK(WIN1_VS_FACTOR_CBR)) >> 16;
3804 win_ctrl = vop_readl(vop_dev, WIN2_CTRL0);
3805 w2_state = win_ctrl & MASK(WIN2_EN);
3806 w2_0_state = (win_ctrl & 0x10) >> 4;
3807 w2_1_state = (win_ctrl & 0x100) >> 8;
3808 w2_2_state = (win_ctrl & 0x1000) >> 12;
3809 w2_3_state = (win_ctrl & 0x10000) >> 16;
3810 vir_info = vop_readl(vop_dev, WIN2_VIR0_1);
3811 w2_0_vir_y = vir_info & MASK(WIN2_VIR_STRIDE0);
3812 w2_1_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE1)) >> 16;
3813 vir_info = vop_readl(vop_dev, WIN2_VIR2_3);
3814 w2_2_vir_y = vir_info & MASK(WIN2_VIR_STRIDE2);
3815 w2_3_vir_y = (vir_info & MASK(WIN2_VIR_STRIDE3)) >> 16;
3817 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT0)) >> 5;
3818 vop_format_to_string(fmt_id, format_w2_0);
3819 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT1)) >> 9;
3820 vop_format_to_string(fmt_id, format_w2_1);
3821 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT2)) >> 13;
3822 vop_format_to_string(fmt_id, format_w2_2);
3823 fmt_id = (win_ctrl & MASK(WIN2_DATA_FMT3)) >> 17;
3824 vop_format_to_string(fmt_id, format_w2_3);
3826 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO0);
3827 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST0);
3828 w2_0_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH0)) + 1;
3829 w2_0_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT0)) >> 16) + 1;
3831 w2_0_st_x = dsp_st & MASK(WIN2_DSP_XST0);
3832 w2_0_st_y = (dsp_st & MASK(WIN2_DSP_YST0)) >> 16;
3834 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO1);
3835 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST1);
3836 w2_1_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH1)) + 1;
3837 w2_1_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT1)) >> 16) + 1;
3839 w2_1_st_x = dsp_st & MASK(WIN2_DSP_XST1);
3840 w2_1_st_y = (dsp_st & MASK(WIN2_DSP_YST1)) >> 16;
3842 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO2);
3843 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST2);
3844 w2_2_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH2)) + 1;
3845 w2_2_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT2)) >> 16) + 1;
3847 w2_2_st_x = dsp_st & MASK(WIN2_DSP_XST2);
3848 w2_2_st_y = (dsp_st & MASK(WIN2_DSP_YST2)) >> 16;
3850 dsp_info = vop_readl(vop_dev, WIN2_DSP_INFO3);
3851 dsp_st = vop_readl(vop_dev, WIN2_DSP_ST3);
3852 w2_3_dsp_x = (dsp_info & MASK(WIN2_DSP_WIDTH3)) + 1;
3853 w2_3_dsp_y = ((dsp_info & MASK(WIN2_DSP_HEIGHT3)) >> 16) + 1;
3855 w2_3_st_x = dsp_st & MASK(WIN2_DSP_XST3);
3856 w2_3_st_y = (dsp_st & MASK(WIN2_DSP_YST3)) >> 16;
3860 win_ctrl = vop_readl(vop_dev, WIN3_CTRL0);
3861 w3_state = win_ctrl & MASK(WIN3_EN);
3862 w3_0_state = (win_ctrl & 0x10) >> 4;
3863 w3_1_state = (win_ctrl & 0x100) >> 8;
3864 w3_2_state = (win_ctrl & 0x1000) >> 12;
3865 w3_3_state = (win_ctrl & 0x10000) >> 16;
3866 vir_info = vop_readl(vop_dev, WIN3_VIR0_1);
3867 w3_0_vir_y = vir_info & MASK(WIN3_VIR_STRIDE0);
3868 w3_1_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE1)) >> 16;
3869 vir_info = vop_readl(vop_dev, WIN3_VIR2_3);
3870 w3_2_vir_y = vir_info & MASK(WIN3_VIR_STRIDE2);
3871 w3_3_vir_y = (vir_info & MASK(WIN3_VIR_STRIDE3)) >> 16;
3873 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT0)) >> 5;
3874 vop_format_to_string(fmt_id, format_w3_0);
3875 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT1)) >> 9;
3876 vop_format_to_string(fmt_id, format_w3_1);
3877 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT2)) >> 13;
3878 vop_format_to_string(fmt_id, format_w3_2);
3879 fmt_id = (win_ctrl & MASK(WIN3_DATA_FMT3)) >> 17;
3880 vop_format_to_string(fmt_id, format_w3_3);
3882 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO0);
3883 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST0);
3884 w3_0_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH0)) + 1;
3885 w3_0_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT0)) >> 16) + 1;
3887 w3_0_st_x = dsp_st & MASK(WIN3_DSP_XST0);
3888 w3_0_st_y = (dsp_st & MASK(WIN3_DSP_YST0)) >> 16;
3890 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO1);
3891 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST1);
3892 w3_1_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH1)) + 1;
3893 w3_1_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT1)) >> 16) + 1;
3895 w3_1_st_x = dsp_st & MASK(WIN3_DSP_XST1);
3896 w3_1_st_y = (dsp_st & MASK(WIN3_DSP_YST1)) >> 16;
3898 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO2);
3899 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST2);
3900 w3_2_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH2)) + 1;
3901 w3_2_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT2)) >> 16) + 1;
3903 w3_2_st_x = dsp_st & MASK(WIN3_DSP_XST2);
3904 w3_2_st_y = (dsp_st & MASK(WIN3_DSP_YST2)) >> 16;
3906 dsp_info = vop_readl(vop_dev, WIN3_DSP_INFO3);
3907 dsp_st = vop_readl(vop_dev, WIN3_DSP_ST3);
3908 w3_3_dsp_x = (dsp_info & MASK(WIN3_DSP_WIDTH3)) + 1;
3909 w3_3_dsp_y = ((dsp_info & MASK(WIN3_DSP_HEIGHT3)) >> 16) + 1;
3911 w3_3_st_x = dsp_st & MASK(WIN3_DSP_XST3);
3912 w3_3_st_y = (dsp_st & MASK(WIN3_DSP_YST3)) >> 16;
3915 spin_unlock(&vop_dev->reg_lock);
3918 spin_unlock(&vop_dev->reg_lock);
3919 size += snprintf(dsp_buf, 80,
3920 "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n",
3921 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3922 strcat(buf, dsp_buf);
3923 memset(dsp_buf, 0, sizeof(dsp_buf));
3925 size += snprintf(dsp_buf, 80,
3926 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3927 w0_state, format_w0, w0_vir_y, w0_vir_uv);
3928 strcat(buf, dsp_buf);
3929 memset(dsp_buf, 0, sizeof(dsp_buf));
3931 size += snprintf(dsp_buf, 80,
3932 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3933 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3934 strcat(buf, dsp_buf);
3935 memset(dsp_buf, 0, sizeof(dsp_buf));
3937 size += snprintf(dsp_buf, 80,
3938 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3939 w0_st_x - h_pw_bp, w0_st_y - v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3940 strcat(buf, dsp_buf);
3941 memset(dsp_buf, 0, sizeof(dsp_buf));
3943 size += snprintf(dsp_buf, 80,
3944 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3945 w0_uv_h_fac, w0_uv_v_fac, vop_readl(vop_dev, WIN0_YRGB_MST),
3946 vop_readl(vop_dev, WIN0_CBR_MST));
3947 strcat(buf, dsp_buf);
3948 memset(dsp_buf, 0, sizeof(dsp_buf));
3951 size += snprintf(dsp_buf, 80,
3952 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3953 w1_state, format_w1, w1_vir_y, w1_vir_uv);
3954 strcat(buf, dsp_buf);
3955 memset(dsp_buf, 0, sizeof(dsp_buf));
3957 size += snprintf(dsp_buf, 80,
3958 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3959 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3960 strcat(buf, dsp_buf);
3961 memset(dsp_buf, 0, sizeof(dsp_buf));
3963 size += snprintf(dsp_buf, 80,
3964 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3965 w1_st_x - h_pw_bp, w1_st_y - v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3966 strcat(buf, dsp_buf);
3967 memset(dsp_buf, 0, sizeof(dsp_buf));
3969 size += snprintf(dsp_buf, 80,
3970 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3971 w1_uv_h_fac, w1_uv_v_fac, vop_readl(vop_dev, WIN1_YRGB_MST),
3972 vop_readl(vop_dev, WIN1_CBR_MST));
3973 strcat(buf, dsp_buf);
3974 memset(dsp_buf, 0, sizeof(dsp_buf));
3977 size += snprintf(dsp_buf, 80,
3978 "win2:\n state:%d\n",
3980 strcat(buf, dsp_buf);
3981 memset(dsp_buf, 0, sizeof(dsp_buf));
3983 size += snprintf(dsp_buf, 80,
3984 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3985 w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3986 strcat(buf, dsp_buf);
3987 memset(dsp_buf, 0, sizeof(dsp_buf));
3988 size += snprintf(dsp_buf, 80,
3989 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3990 w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3991 vop_readl(vop_dev, WIN2_MST0));
3992 strcat(buf, dsp_buf);
3993 memset(dsp_buf, 0, sizeof(dsp_buf));
3996 size += snprintf(dsp_buf, 80,
3997 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3998 w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3999 strcat(buf, dsp_buf);
4000 memset(dsp_buf, 0, sizeof(dsp_buf));
4001 size += snprintf(dsp_buf, 80,
4002 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4003 w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
4004 vop_readl(vop_dev, WIN2_MST1));
4005 strcat(buf, dsp_buf);
4006 memset(dsp_buf, 0, sizeof(dsp_buf));
4009 size += snprintf(dsp_buf, 80,
4010 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4011 w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
4012 strcat(buf, dsp_buf);
4013 memset(dsp_buf, 0, sizeof(dsp_buf));
4014 size += snprintf(dsp_buf, 80,
4015 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4016 w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
4017 vop_readl(vop_dev, WIN2_MST2));
4018 strcat(buf, dsp_buf);
4019 memset(dsp_buf, 0, sizeof(dsp_buf));
4022 size += snprintf(dsp_buf, 80,
4023 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4024 w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
4025 strcat(buf, dsp_buf);
4026 memset(dsp_buf, 0, sizeof(dsp_buf));
4027 size += snprintf(dsp_buf, 80,
4028 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4029 w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
4030 vop_readl(vop_dev, WIN2_MST3));
4031 strcat(buf, dsp_buf);
4032 memset(dsp_buf, 0, sizeof(dsp_buf));
4035 size += snprintf(dsp_buf, 80,
4036 "win3:\n state:%d\n",
4038 strcat(buf, dsp_buf);
4039 memset(dsp_buf, 0, sizeof(dsp_buf));
4041 size += snprintf(dsp_buf, 80,
4042 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4043 w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
4044 strcat(buf, dsp_buf);
4045 memset(dsp_buf, 0, sizeof(dsp_buf));
4046 size += snprintf(dsp_buf, 80,
4047 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4048 w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
4049 vop_readl(vop_dev, WIN3_MST0));
4050 strcat(buf, dsp_buf);
4051 memset(dsp_buf, 0, sizeof(dsp_buf));
4054 size += snprintf(dsp_buf, 80,
4055 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4056 w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
4057 strcat(buf, dsp_buf);
4058 memset(dsp_buf, 0, sizeof(dsp_buf));
4059 size += snprintf(dsp_buf, 80,
4060 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4061 w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
4062 vop_readl(vop_dev, WIN3_MST1));
4063 strcat(buf, dsp_buf);
4064 memset(dsp_buf, 0, sizeof(dsp_buf));
4067 size += snprintf(dsp_buf, 80,
4068 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4069 w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
4070 strcat(buf, dsp_buf);
4071 memset(dsp_buf, 0, sizeof(dsp_buf));
4072 size += snprintf(dsp_buf, 80,
4073 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4074 w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
4075 vop_readl(vop_dev, WIN3_MST2));
4076 strcat(buf, dsp_buf);
4077 memset(dsp_buf, 0, sizeof(dsp_buf));
4080 size += snprintf(dsp_buf, 80,
4081 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
4082 w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
4083 strcat(buf, dsp_buf);
4084 memset(dsp_buf, 0, sizeof(dsp_buf));
4085 size += snprintf(dsp_buf, 80,
4086 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
4087 w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
4088 vop_readl(vop_dev, WIN3_MST3));
4089 strcat(buf, dsp_buf);
4090 memset(dsp_buf, 0, sizeof(dsp_buf));
4095 static int vop_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps, bool set)
4097 struct vop_device *vop_dev =
4098 container_of(dev_drv, struct vop_device, driver);
4099 struct rk_screen *screen = dev_drv->cur_screen;
4104 u32 x_total, y_total;
4108 dev_info(dev_drv->dev, "unsupport set fps=0\n");
4111 ft = div_u64(1000000000000llu, fps);
4113 screen->mode.upper_margin + screen->mode.lower_margin +
4114 screen->mode.yres + screen->mode.vsync_len;
4116 screen->mode.left_margin + screen->mode.right_margin +
4117 screen->mode.xres + screen->mode.hsync_len;
4118 dev_drv->pixclock = div_u64(ft, x_total * y_total);
4119 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
4120 ret = clk_set_rate(vop_dev->dclk, dotclk);
4123 pixclock = div_u64(1000000000000llu, clk_get_rate(vop_dev->dclk));
4124 vop_dev->pixclock = pixclock;
4125 dev_drv->pixclock = vop_dev->pixclock;
4126 fps = rk_fb_calc_fps(screen, pixclock);
4127 screen->ft = 1000 / fps; /*one frame time in ms */
4130 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
4131 clk_get_rate(vop_dev->dclk), fps);
4136 static int vop_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
4138 mutex_lock(&dev_drv->fb_win_id_mutex);
4139 if (order == FB_DEFAULT_ORDER)
4140 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
4141 dev_drv->fb4_win_id = order / 10000;
4142 dev_drv->fb3_win_id = (order / 1000) % 10;
4143 dev_drv->fb2_win_id = (order / 100) % 10;
4144 dev_drv->fb1_win_id = (order / 10) % 10;
4145 dev_drv->fb0_win_id = order % 10;
4146 mutex_unlock(&dev_drv->fb_win_id_mutex);
4151 static int vop_get_win_id(struct rk_lcdc_driver *dev_drv, const char *id)
4155 mutex_lock(&dev_drv->fb_win_id_mutex);
4156 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
4157 win_id = dev_drv->fb0_win_id;
4158 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
4159 win_id = dev_drv->fb1_win_id;
4160 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
4161 win_id = dev_drv->fb2_win_id;
4162 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
4163 win_id = dev_drv->fb3_win_id;
4164 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
4165 win_id = dev_drv->fb4_win_id;
4166 mutex_unlock(&dev_drv->fb_win_id_mutex);
4171 static int vop_config_done(struct rk_lcdc_driver *dev_drv)
4173 struct vop_device *vop_dev =
4174 container_of(dev_drv, struct vop_device, driver);
4177 struct rk_lcdc_win *win = NULL;
4179 spin_lock(&vop_dev->reg_lock);
4180 vop_post_cfg(dev_drv);
4181 vop_msk_reg(vop_dev, SYS_CTRL, V_VOP_STANDBY_EN(vop_dev->standby));
4182 for (i = 0; i < dev_drv->lcdc_win_num; i++) {
4183 win = dev_drv->win[i];
4184 vop_alpha_cfg(dev_drv, i);
4185 fbdc_en |= win->area[0].fbdc_en;
4186 vop_dev->atv_layer_cnt &= ~(1 << win->id);
4187 vop_dev->atv_layer_cnt |= (win->state << win->id);
4188 if ((win->state == 0) && (win->last_state == 1)) {
4192 vop_msk_reg(vop_dev, WIN0_CTRL0, val);
4196 vop_msk_reg(vop_dev, WIN1_CTRL0, val);
4199 val = V_WIN2_EN(0) | V_WIN2_MST0_EN(0) |
4201 V_WIN2_MST2_EN(0) | V_WIN2_MST3_EN(0);
4202 vop_msk_reg(vop_dev, WIN2_CTRL0, val);
4205 val = V_WIN3_EN(0) | V_WIN3_MST0_EN(0) |
4207 V_WIN3_MST2_EN(0) | V_WIN3_MST3_EN(0);
4208 vop_msk_reg(vop_dev, WIN3_CTRL0, val);
4212 vop_msk_reg(vop_dev, HWC_CTRL0, val);
4218 win->last_state = win->state;
4220 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
4221 val = V_VOP_FBDC_EN(fbdc_en);
4222 vop_msk_reg(vop_dev, AFBCD0_CTRL, val);
4224 vop_cfg_done(vop_dev);
4225 spin_unlock(&vop_dev->reg_lock);
4229 static int vop_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
4231 struct vop_device *vop_dev =
4232 container_of(dev_drv, struct vop_device, driver);
4233 spin_lock(&vop_dev->reg_lock);
4234 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(open));
4235 vop_cfg_done(vop_dev);
4236 spin_unlock(&vop_dev->reg_lock);
4240 static int vop_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
4242 struct vop_device *vop_dev = container_of(dev_drv,
4243 struct vop_device, driver);
4244 spin_lock(&vop_dev->reg_lock);
4245 vop_msk_reg(vop_dev, SYS_CTRL, V_DIRECT_PATH_LAYER_SEL(win_id));
4246 vop_cfg_done(vop_dev);
4247 spin_unlock(&vop_dev->reg_lock);
4251 static int vop_dpi_status(struct rk_lcdc_driver *dev_drv)
4253 struct vop_device *vop_dev =
4254 container_of(dev_drv, struct vop_device, driver);
4257 spin_lock(&vop_dev->reg_lock);
4258 ovl = vop_read_bit(vop_dev, SYS_CTRL, V_DIRECT_PATH_EN(0));
4259 spin_unlock(&vop_dev->reg_lock);
4263 static int vop_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv, int enable)
4265 struct vop_device *vop_dev =
4266 container_of(dev_drv, struct vop_device, driver);
4268 enable_irq(vop_dev->irq);
4270 disable_irq_nosync(vop_dev->irq);
4274 int vop_poll_vblank(struct rk_lcdc_driver *dev_drv)
4276 struct vop_device *vop_dev =
4277 container_of(dev_drv, struct vop_device, driver);
4281 if (vop_dev->clk_on && (!dev_drv->suspend_flag)) {
4282 int_reg = vop_readl(vop_dev, INTR_STATUS0);
4283 if (int_reg & INTR_LINE_FLAG0) {
4284 vop_dev->driver.frame_time.last_framedone_t =
4285 vop_dev->driver.frame_time.framedone_t;
4286 vop_dev->driver.frame_time.framedone_t = cpu_clock(0);
4287 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_LINE_FLAG0,
4289 ret = RK_LF_STATUS_FC;
4291 ret = RK_LF_STATUS_FR;
4294 ret = RK_LF_STATUS_NC;
4300 static int vop_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
4301 unsigned int dsp_addr[][4])
4303 struct vop_device *vop_dev =
4304 container_of(dev_drv, struct vop_device, driver);
4305 spin_lock(&vop_dev->reg_lock);
4306 if (vop_dev->clk_on) {
4307 dsp_addr[0][0] = vop_readl(vop_dev, WIN0_YRGB_MST);
4308 dsp_addr[1][0] = vop_readl(vop_dev, WIN1_YRGB_MST);
4309 dsp_addr[2][0] = vop_readl(vop_dev, WIN2_MST0);
4310 dsp_addr[2][1] = vop_readl(vop_dev, WIN2_MST1);
4311 dsp_addr[2][2] = vop_readl(vop_dev, WIN2_MST2);
4312 dsp_addr[2][3] = vop_readl(vop_dev, WIN2_MST3);
4313 dsp_addr[3][0] = vop_readl(vop_dev, WIN3_MST0);
4314 dsp_addr[3][1] = vop_readl(vop_dev, WIN3_MST1);
4315 dsp_addr[3][2] = vop_readl(vop_dev, WIN3_MST2);
4316 dsp_addr[3][3] = vop_readl(vop_dev, WIN3_MST3);
4317 dsp_addr[4][0] = vop_readl(vop_dev, HWC_MST);
4319 spin_unlock(&vop_dev->reg_lock);
4324 int vop_update_pwm(int bl_pwm_period, int bl_pwm_duty)
4328 * pwm_period_hpr = bl_pwm_period;
4329 * pwm_duty_lpr = bl_pwm_duty;
4330 * pr_info("bl_pwm_period_hpr = 0x%x, bl_pwm_duty_lpr = 0x%x\n",
4331 * bl_pwm_period, bl_pwm_duty);
4339 * sin_hue = sin(a)*256 +0x100;
4340 * cos_hue = cos(a)*256;
4342 * sin_hue = sin(a)*256;
4343 * cos_hue = cos(a)*256;
4345 static int vop_get_bcsh_hue(struct rk_lcdc_driver *dev_drv, bcsh_hue_mode mode)
4347 struct vop_device *vop_dev =
4348 container_of(dev_drv, struct vop_device, driver);
4351 spin_lock(&vop_dev->reg_lock);
4352 if (vop_dev->clk_on) {
4353 val = vop_readl(vop_dev, BCSH_H);
4356 val &= MASK(SIN_HUE);
4359 val &= MASK(COS_HUE);
4366 spin_unlock(&vop_dev->reg_lock);
4371 static int vop_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode,
4372 int calc, int up, int down, int global)
4374 struct vop_device *vop_dev =
4375 container_of(dev_drv, struct vop_device, driver);
4376 struct rk_screen *screen = dev_drv->cur_screen;
4377 u32 total_pixel, calc_pixel, stage_up, stage_down;
4378 u32 pixel_num, global_dn;
4380 if (!vop_dev->cabc_lut_addr_base) {
4381 pr_err("vop chip[%d] not supoort cabc\n", VOP_CHIP(vop_dev));
4385 if (!screen->cabc_lut) {
4386 pr_err("screen cabc lut not config, so not open cabc\n");
4390 dev_drv->cabc_mode = mode;
4391 if (!dev_drv->cabc_mode) {
4392 spin_lock(&vop_dev->reg_lock);
4393 if (vop_dev->clk_on) {
4394 vop_msk_reg(vop_dev, CABC_CTRL0,
4395 V_CABC_EN(0) | V_CABC_HANDLE_EN(0));
4396 vop_cfg_done(vop_dev);
4398 pr_info("mode = 0, close cabc\n");
4399 spin_unlock(&vop_dev->reg_lock);
4403 total_pixel = screen->mode.xres * screen->mode.yres;
4404 pixel_num = 1000 - calc;
4405 calc_pixel = (total_pixel * pixel_num) / 1000;
4409 pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
4410 mode, calc, stage_up, stage_down, global_dn);
4412 spin_lock(&vop_dev->reg_lock);
4413 if (vop_dev->clk_on) {
4416 val = V_CABC_EN(1) | V_CABC_HANDLE_EN(1) |
4417 V_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
4418 V_CABC_CALC_PIXEL_NUM(calc_pixel);
4419 vop_msk_reg(vop_dev, CABC_CTRL0, val);
4421 val = V_CABC_LUT_EN(1) | V_CABC_TOTAL_NUM(total_pixel);
4422 vop_msk_reg(vop_dev, CABC_CTRL1, val);
4424 val = V_CABC_STAGE_DOWN(stage_down) |
4425 V_CABC_STAGE_UP(stage_up) |
4426 V_CABC_STAGE_UP_MODE(0) | V_MAX_SCALE_CFG_VALUE(1) |
4427 V_MAX_SCALE_CFG_ENABLE(0);
4428 vop_msk_reg(vop_dev, CABC_CTRL2, val);
4430 val = V_CABC_GLOBAL_DN(global_dn) |
4431 V_CABC_GLOBAL_DN_LIMIT_EN(1);
4432 vop_msk_reg(vop_dev, CABC_CTRL3, val);
4433 vop_cfg_done(vop_dev);
4435 spin_unlock(&vop_dev->reg_lock);
4440 static int vop_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
4441 int sin_hue, int cos_hue)
4443 struct vop_device *vop_dev =
4444 container_of(dev_drv, struct vop_device, driver);
4447 spin_lock(&vop_dev->reg_lock);
4448 if (vop_dev->clk_on) {
4449 val = V_SIN_HUE(sin_hue) | V_COS_HUE(cos_hue);
4450 vop_msk_reg(vop_dev, BCSH_H, val);
4451 vop_cfg_done(vop_dev);
4453 spin_unlock(&vop_dev->reg_lock);
4458 static int vop_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4459 bcsh_bcs_mode mode, int value)
4461 struct vop_device *vop_dev =
4462 container_of(dev_drv, struct vop_device, driver);
4465 spin_lock(&vop_dev->reg_lock);
4466 if (vop_dev->clk_on) {
4469 /*from 0 to 255,typical is 128 */
4472 else if (value >= 0x80)
4473 value = value - 0x80;
4474 val = V_BRIGHTNESS(value);
4477 /*from 0 to 510,typical is 256 */
4478 val = V_CONTRAST(value);
4481 /*from 0 to 1015,typical is 256 */
4482 val = V_SAT_CON(value);
4487 vop_msk_reg(vop_dev, BCSH_BCS, val);
4488 vop_cfg_done(vop_dev);
4490 spin_unlock(&vop_dev->reg_lock);
4495 static int vop_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv, bcsh_bcs_mode mode)
4497 struct vop_device *vop_dev =
4498 container_of(dev_drv, struct vop_device, driver);
4501 spin_lock(&vop_dev->reg_lock);
4502 if (vop_dev->clk_on) {
4503 val = vop_readl(vop_dev, BCSH_BCS);
4506 val &= MASK(BRIGHTNESS);
4513 val &= MASK(CONTRAST);
4517 val &= MASK(SAT_CON);
4524 spin_unlock(&vop_dev->reg_lock);
4528 static int vop_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4530 struct vop_device *vop_dev =
4531 container_of(dev_drv, struct vop_device, driver);
4533 spin_lock(&vop_dev->reg_lock);
4534 if (vop_dev->clk_on) {
4536 vop_writel(vop_dev, BCSH_COLOR_BAR, 0x1);
4537 vop_writel(vop_dev, BCSH_BCS, 0xd0010000);
4538 vop_writel(vop_dev, BCSH_H, 0x01000000);
4539 dev_drv->bcsh.enable = 1;
4541 vop_msk_reg(vop_dev, BCSH_COLOR_BAR, V_BCSH_EN(0));
4542 dev_drv->bcsh.enable = 0;
4544 vop_bcsh_path_sel(dev_drv);
4545 vop_cfg_done(vop_dev);
4547 spin_unlock(&vop_dev->reg_lock);
4552 static int vop_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4554 if (!enable || !dev_drv->bcsh.enable) {
4555 vop_open_bcsh(dev_drv, false);
4559 if (dev_drv->bcsh.brightness <= 255 ||
4560 dev_drv->bcsh.contrast <= 510 ||
4561 dev_drv->bcsh.sat_con <= 1015 ||
4562 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4563 vop_open_bcsh(dev_drv, true);
4564 if (dev_drv->bcsh.brightness <= 255)
4565 vop_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4566 dev_drv->bcsh.brightness);
4567 if (dev_drv->bcsh.contrast <= 510)
4568 vop_set_bcsh_bcs(dev_drv, CONTRAST,
4569 dev_drv->bcsh.contrast);
4570 if (dev_drv->bcsh.sat_con <= 1015)
4571 vop_set_bcsh_bcs(dev_drv, SAT_CON,
4572 dev_drv->bcsh.sat_con);
4573 if (dev_drv->bcsh.sin_hue <= 511 &&
4574 dev_drv->bcsh.cos_hue <= 511)
4575 vop_set_bcsh_hue(dev_drv, dev_drv->bcsh.sin_hue,
4576 dev_drv->bcsh.cos_hue);
4582 static int __maybe_unused
4583 vop_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4585 struct vop_device *vop_dev =
4586 container_of(dev_drv, struct vop_device, driver);
4589 spin_lock(&vop_dev->reg_lock);
4590 if (likely(vop_dev->clk_on)) {
4591 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(1));
4592 vop_cfg_done(vop_dev);
4594 spin_unlock(&vop_dev->reg_lock);
4596 spin_lock(&vop_dev->reg_lock);
4597 if (likely(vop_dev->clk_on)) {
4598 vop_msk_reg(vop_dev, DSP_CTRL0, V_DSP_BLACK_EN(0));
4600 vop_cfg_done(vop_dev);
4602 spin_unlock(&vop_dev->reg_lock);
4608 static int vop_backlight_close(struct rk_lcdc_driver *dev_drv, int enable)
4610 struct vop_device *vop_dev =
4611 container_of(dev_drv, struct vop_device, driver);
4613 if (unlikely(!vop_dev->clk_on)) {
4614 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4617 vop_get_backlight_device(dev_drv);
4620 /* close the backlight */
4621 if (vop_dev->backlight) {
4622 vop_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4623 backlight_update_status(vop_dev->backlight);
4625 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4626 dev_drv->trsm_ops->disable();
4628 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4629 dev_drv->trsm_ops->enable();
4631 /* open the backlight */
4632 if (vop_dev->backlight) {
4633 vop_dev->backlight->props.power = FB_BLANK_UNBLANK;
4634 backlight_update_status(vop_dev->backlight);
4641 static int vop_set_overscan(struct rk_lcdc_driver *dev_drv,
4642 struct overscan *overscan)
4644 struct vop_device *vop_dev =
4645 container_of(dev_drv, struct vop_device, driver);
4647 if (unlikely(!vop_dev->clk_on)) {
4648 pr_info("%s,clk_on = %d\n", __func__, vop_dev->clk_on);
4651 /*vop_post_cfg(dev_drv);*/
4656 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4658 .win_direct_en = vop_win_direct_en,
4659 .load_screen = vop_load_screen,
4660 .get_dspbuf_info = vop_get_dspbuf_info,
4661 .post_dspbuf = vop_post_dspbuf,
4662 .set_par = vop_set_par,
4663 .pan_display = vop_pan_display,
4664 .set_wb = vop_set_writeback,
4665 .direct_set_addr = vop_direct_set_win_addr,
4666 /*.lcdc_reg_update = vop_reg_update,*/
4669 .suspend = vop_early_suspend,
4670 .resume = vop_early_resume,
4671 .get_win_state = vop_get_win_state,
4672 .area_support_num = vop_get_area_num,
4673 .ovl_mgr = vop_ovl_mgr,
4674 .get_disp_info = vop_get_disp_info,
4675 .fps_mgr = vop_fps_mgr,
4676 .fb_get_win_id = vop_get_win_id,
4677 .fb_win_remap = vop_fb_win_remap,
4678 .poll_vblank = vop_poll_vblank,
4679 .dpi_open = vop_dpi_open,
4680 .dpi_win_sel = vop_dpi_win_sel,
4681 .dpi_status = vop_dpi_status,
4682 .get_dsp_addr = vop_get_dsp_addr,
4683 .set_dsp_lut = vop_set_lut,
4684 .set_cabc_lut = vop_set_cabc,
4685 .set_dsp_cabc = vop_set_dsp_cabc,
4686 .set_dsp_bcsh_hue = vop_set_bcsh_hue,
4687 .set_dsp_bcsh_bcs = vop_set_bcsh_bcs,
4688 .get_dsp_bcsh_hue = vop_get_bcsh_hue,
4689 .get_dsp_bcsh_bcs = vop_get_bcsh_bcs,
4690 .open_bcsh = vop_open_bcsh,
4691 .dump_reg = vop_reg_dump,
4692 .cfg_done = vop_config_done,
4693 .set_irq_to_cpu = vop_set_irq_to_cpu,
4694 /*.dsp_black = vop_dsp_black,*/
4695 .backlight_close = vop_backlight_close,
4696 .mmu_en = vop_mmu_en,
4697 .set_overscan = vop_set_overscan,
4700 static irqreturn_t vop_isr(int irq, void *dev_id)
4702 struct vop_device *vop_dev = (struct vop_device *)dev_id;
4703 ktime_t timestamp = ktime_get();
4705 unsigned long flags;
4707 spin_lock_irqsave(&vop_dev->irq_lock, flags);
4709 intr_status = vop_readl(vop_dev, INTR_STATUS0);
4710 vop_mask_writel(vop_dev, INTR_CLEAR0, INTR_MASK, intr_status);
4712 spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4713 /* This is expected for vop iommu irqs, since the irq is shared */
4717 if (intr_status & INTR_FS) {
4718 timestamp = ktime_get();
4719 if (vop_dev->driver.wb_data.state) {
4722 spin_lock_irqsave(&vop_dev->irq_lock, flags);
4723 wb_status = vop_read_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4726 vop_clr_bit(vop_dev, WB_CTRL0, V_WB_EN(0));
4728 vop_cfg_done(vop_dev);
4729 vop_dev->driver.wb_data.state = 0;
4730 spin_unlock_irqrestore(&vop_dev->irq_lock, flags);
4732 vop_dev->driver.vsync_info.timestamp = timestamp;
4733 wake_up_interruptible_all(&vop_dev->driver.vsync_info.wait);
4734 intr_status &= ~INTR_FS;
4737 if (intr_status & INTR_LINE_FLAG0)
4738 intr_status &= ~INTR_LINE_FLAG0;
4740 if (intr_status & INTR_LINE_FLAG1)
4741 intr_status &= ~INTR_LINE_FLAG1;
4743 if (intr_status & INTR_FS_NEW)
4744 intr_status &= ~INTR_FS_NEW;
4746 if (intr_status & INTR_BUS_ERROR) {
4747 intr_status &= ~INTR_BUS_ERROR;
4748 dev_warn_ratelimited(vop_dev->dev, "bus error!");
4751 if (intr_status & INTR_WIN0_EMPTY) {
4752 intr_status &= ~INTR_WIN0_EMPTY;
4753 dev_warn_ratelimited(vop_dev->dev, "intr win0 empty!");
4756 if (intr_status & INTR_WIN1_EMPTY) {
4757 intr_status &= ~INTR_WIN1_EMPTY;
4758 dev_warn_ratelimited(vop_dev->dev, "intr win1 empty!");
4761 if (intr_status & INTR_HWC_EMPTY) {
4762 intr_status &= ~INTR_HWC_EMPTY;
4763 dev_warn_ratelimited(vop_dev->dev, "intr hwc empty!");
4766 if (intr_status & INTR_POST_BUF_EMPTY) {
4767 intr_status &= ~INTR_POST_BUF_EMPTY;
4768 dev_warn_ratelimited(vop_dev->dev, "intr post buf empty!");
4772 dev_err(vop_dev->dev, "Unknown VOP IRQs: %#02x\n", intr_status);
4777 #if defined(CONFIG_PM)
4778 static int vop_suspend(struct platform_device *pdev, pm_message_t state)
4783 static int vop_resume(struct platform_device *pdev)
4788 #define vop_suspend NULL
4789 #define vop_resume NULL
4792 static int vop_parse_dt(struct vop_device *vop_dev)
4794 struct device_node *np = vop_dev->dev->of_node;
4795 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4798 if (of_property_read_u32(np, "rockchip,prop", &val))
4799 vop_dev->prop = PRMRY; /*default set it as primary */
4801 vop_dev->prop = val;
4803 if (of_property_read_u32(np, "rockchip,mirror", &val))
4804 dev_drv->rotate_mode = NO_MIRROR;
4806 dev_drv->rotate_mode = val;
4808 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4809 /*default set it as 3.xv power supply */
4810 vop_dev->pwr18 = false;
4812 vop_dev->pwr18 = (val ? true : false);
4814 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4815 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4817 dev_drv->fb_win_map = val;
4819 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4820 dev_drv->bcsh.enable = false;
4822 dev_drv->bcsh.enable = (val ? true : false);
4824 if (of_property_read_u32(np, "rockchip,brightness", &val))
4825 dev_drv->bcsh.brightness = 0xffff;
4827 dev_drv->bcsh.brightness = val;
4829 if (of_property_read_u32(np, "rockchip,contrast", &val))
4830 dev_drv->bcsh.contrast = 0xffff;
4832 dev_drv->bcsh.contrast = val;
4834 if (of_property_read_u32(np, "rockchip,sat-con", &val))
4835 dev_drv->bcsh.sat_con = 0xffff;
4837 dev_drv->bcsh.sat_con = val;
4839 if (of_property_read_u32(np, "rockchip,hue", &val)) {
4840 dev_drv->bcsh.sin_hue = 0xffff;
4841 dev_drv->bcsh.cos_hue = 0xffff;
4843 dev_drv->bcsh.sin_hue = val & 0xff;
4844 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4847 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4848 dev_drv->iommu_enabled = 0;
4850 dev_drv->iommu_enabled = val;
4854 static int vop_probe(struct platform_device *pdev)
4856 struct vop_device *vop_dev = NULL;
4857 struct rk_lcdc_driver *dev_drv;
4858 const struct of_device_id *of_id;
4859 struct device *dev = &pdev->dev;
4860 struct resource *res;
4861 struct device_node *np = pdev->dev.of_node;
4865 /* if the primary lcdc has not registered ,the extend
4866 * lcdc register later
4868 of_property_read_u32(np, "rockchip,prop", &prop);
4869 if (prop == EXTEND) {
4870 if (!is_prmry_rk_lcdc_registered())
4871 return -EPROBE_DEFER;
4873 vop_dev = devm_kzalloc(dev, sizeof(struct vop_device), GFP_KERNEL);
4876 of_id = of_match_device(vop_dt_ids, dev);
4877 vop_dev->data = of_id->data;
4878 if (VOP_CHIP(vop_dev) != VOP_RK322X && VOP_CHIP(vop_dev) != VOP_RK3399)
4880 platform_set_drvdata(pdev, vop_dev);
4882 vop_parse_dt(vop_dev);
4883 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
4884 /* enable power domain */
4885 pm_runtime_enable(dev);
4887 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4888 vop_dev->reg_phy_base = res->start;
4889 vop_dev->len = resource_size(res);
4890 vop_dev->regs = devm_ioremap(&pdev->dev, res->start,
4891 resource_size(res));
4892 if (IS_ERR(vop_dev->regs))
4893 return PTR_ERR(vop_dev->regs);
4895 dev_info(dev, "vop_dev->regs=0x%lx\n", (long)vop_dev->regs);
4897 vop_dev->regsbak = devm_kzalloc(dev, vop_dev->len, GFP_KERNEL);
4898 if (IS_ERR(vop_dev->regsbak))
4899 return PTR_ERR(vop_dev->regsbak);
4900 if (VOP_CHIP(vop_dev) == VOP_RK3399) {
4901 vop_dev->dsp_lut_addr_base = vop_dev->regs + GAMMA_LUT_ADDR;
4902 vop_dev->cabc_lut_addr_base = vop_dev->regs +
4903 CABC_GAMMA_LUT_ADDR;
4906 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4907 if (IS_ERR(vop_dev->grf_base)) {
4908 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4909 vop_dev->grf_base = NULL;
4912 vop_dev->id = vop_get_id(vop_dev, vop_dev->reg_phy_base);
4913 dev_set_name(vop_dev->dev, "vop%d", vop_dev->id);
4914 dev_drv = &vop_dev->driver;
4916 dev_drv->prop = prop;
4917 dev_drv->id = vop_dev->id;
4918 dev_drv->ops = &lcdc_drv_ops;
4919 dev_drv->lcdc_win_num = vop_dev->data->n_wins;
4920 dev_drv->reserved_fb = 0;
4921 spin_lock_init(&vop_dev->reg_lock);
4922 spin_lock_init(&vop_dev->irq_lock);
4923 vop_dev->irq = platform_get_irq(pdev, 0);
4924 if (vop_dev->irq < 0) {
4925 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4930 ret = devm_request_irq(dev, vop_dev->irq, vop_isr,
4931 IRQF_SHARED, dev_name(dev), vop_dev);
4933 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4937 if (dev_drv->iommu_enabled) {
4938 if (VOP_CHIP(vop_dev) == VOP_RK322X) {
4939 strcpy(dev_drv->mmu_dts_name,
4940 VOP_IOMMU_COMPATIBLE_NAME);
4942 if (vop_dev->id == 0)
4943 strcpy(dev_drv->mmu_dts_name,
4944 VOPB_IOMMU_COMPATIBLE_NAME);
4946 strcpy(dev_drv->mmu_dts_name,
4947 VOPL_IOMMU_COMPATIBLE_NAME);
4950 if (VOP_CHIP(vop_dev) == VOP_RK3399)
4951 dev_drv->property.feature |= SUPPORT_WRITE_BACK | SUPPORT_AFBDC;
4952 dev_drv->property.feature |= SUPPORT_VOP_IDENTIFY |
4953 SUPPORT_YUV420_OUTPUT;
4954 dev_drv->property.max_output_x = 4096;
4955 dev_drv->property.max_output_y = 2160;
4957 if ((VOP_CHIP(vop_dev) == VOP_RK3399) && (vop_dev->id == 1)) {
4958 vop_dev->data->win[1].property.feature &= ~SUPPORT_HW_EXIST;
4959 vop_dev->data->win[3].property.feature &= ~SUPPORT_HW_EXIST;
4962 ret = rk_fb_register(dev_drv, vop_dev->data->win, vop_dev->id);
4964 dev_err(dev, "register fb for lcdc%d failed!\n", vop_dev->id);
4967 vop_dev->screen = dev_drv->screen0;
4968 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4969 vop_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4974 static int vop_remove(struct platform_device *pdev)
4979 static void vop_shutdown(struct platform_device *pdev)
4981 struct vop_device *vop_dev = platform_get_drvdata(pdev);
4982 struct rk_lcdc_driver *dev_drv = &vop_dev->driver;
4984 dev_drv->suspend_flag = 1;
4985 /* ensure suspend_flag take effect on multi process */
4987 flush_kthread_worker(&dev_drv->update_regs_worker);
4988 kthread_stop(dev_drv->update_regs_thread);
4991 vop_clk_disable(vop_dev);
4992 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0))
4993 pm_runtime_disable(vop_dev->dev);
4995 rk_disp_pwr_disable(dev_drv);
4998 static struct platform_driver vop_driver = {
5000 .remove = vop_remove,
5002 .name = "rk322x-lcdc",
5003 .owner = THIS_MODULE,
5004 .of_match_table = of_match_ptr(vop_dt_ids),
5006 .suspend = vop_suspend,
5007 .resume = vop_resume,
5008 .shutdown = vop_shutdown,
5011 static int __init vop_module_init(void)
5013 return platform_driver_register(&vop_driver);
5016 static void __exit vop_module_exit(void)
5018 platform_driver_unregister(&vop_driver);
5021 fs_initcall(vop_module_init);
5022 module_exit(vop_module_exit);