2 * drivers/video/rockchip/lcdc/rk3288_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 *Author:hjc<hjc@rock-chips.com>
6 *This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <asm/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk3288_lcdc.h"
40 #if defined(CONFIG_HAS_EARLYSUSPEND)
41 #include <linux/earlysuspend.h>
44 static int dbg_thresd;
45 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
47 #define DBG(level, x...) do { \
48 if (unlikely(dbg_thresd >= level)) \
49 printk(KERN_INFO x); } while (0)
51 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
54 /*#define WAIT_FOR_SYNC 1*/
56 static int rk3288_lcdc_get_id(u32 phy_base)
58 if (cpu_is_rk3288()) {
59 if (phy_base == 0xff930000)/*vop big*/
61 else if (phy_base == 0xff940000)/*vop lit*/
66 pr_err("un supported platform \n");
71 static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
76 struct lcdc_device *lcdc_dev = container_of(dev_drv,
77 struct lcdc_device,driver);
78 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
79 lcdc_cfg_done(lcdc_dev);
81 for (i = 0; i < 256; i++) {
82 v = dev_drv->cur_screen->dsp_lut[i];
83 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
85 g = (v & 0xff00) << 4;
86 r = (v & 0xff0000) << 6;
88 for (j = 0; j < 4; j++) {
90 v += (1 + (1 << 10) + (1 << 20)) ;
94 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
100 static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
102 #ifdef CONFIG_RK_FPGA
103 lcdc_dev->clk_on = 1;
106 if (!lcdc_dev->clk_on) {
107 clk_prepare_enable(lcdc_dev->hclk);
108 clk_prepare_enable(lcdc_dev->dclk);
109 clk_prepare_enable(lcdc_dev->aclk);
110 clk_prepare_enable(lcdc_dev->pd);
111 spin_lock(&lcdc_dev->reg_lock);
112 lcdc_dev->clk_on = 1;
113 spin_unlock(&lcdc_dev->reg_lock);
119 static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
121 #ifdef CONFIG_RK_FPGA
122 lcdc_dev->clk_on = 0;
125 if (lcdc_dev->clk_on) {
126 spin_lock(&lcdc_dev->reg_lock);
127 lcdc_dev->clk_on = 0;
128 spin_unlock(&lcdc_dev->reg_lock);
130 clk_disable_unprepare(lcdc_dev->dclk);
131 clk_disable_unprepare(lcdc_dev->hclk);
132 clk_disable_unprepare(lcdc_dev->aclk);
133 clk_disable_unprepare(lcdc_dev->pd);
139 static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
142 spin_lock(&lcdc_dev->reg_lock);
143 if (likely(lcdc_dev->clk_on)) {
144 mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN |
145 m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN;
146 val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) |
147 v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0);
148 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
150 mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR |
151 m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR;
152 val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) |
153 v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0);
154 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
156 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
157 m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
158 m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
159 m_POST_BUF_EMPTY_INTR_EN;
160 val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) |
161 v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) |
162 v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) |
163 v_PWM_GEN_INTR_EN(0);
164 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
166 mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
167 m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
168 m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
169 m_POST_BUF_EMPTY_INTR_CLR;
170 val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) |
171 v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) |
172 v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) |
173 v_PWM_GEN_INTR_CLR(0);
174 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
175 lcdc_cfg_done(lcdc_dev);
176 spin_unlock(&lcdc_dev->reg_lock);
178 spin_unlock(&lcdc_dev->reg_lock);
183 static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
185 struct lcdc_device *lcdc_dev = container_of(dev_drv,
188 int *cbase = (int *)lcdc_dev->regs;
189 int *regsbak = (int *)lcdc_dev->regsbak;
192 printk("back up reg:\n");
193 for (i = 0; i <= (0x200 >> 4); i++) {
194 printk("0x%04x: ",i*16);
195 for (j = 0; j < 4; j++)
196 printk("%08x ", *(regsbak + i * 4 + j));
200 printk("lcdc reg:\n");
201 for (i = 0; i <= (0x200 >> 4); i++) {
202 printk("0x%04x: ",i*16);
203 for (j = 0; j < 4; j++)
204 printk("%08x ", readl_relaxed(cbase + i * 4 + j));
212 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \
215 spin_lock(&lcdc_dev->reg_lock); \
216 msk = m_WIN##id##_EN; \
217 val = v_WIN##id##_EN(en); \
218 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
219 lcdc_cfg_done(lcdc_dev); \
220 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
221 while (val != (!!en)) { \
222 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
224 spin_unlock(&lcdc_dev->reg_lock); \
232 /*enable/disable win directly*/
233 static int rk3288_lcdc_win_direct_en
234 (struct rk_lcdc_driver *drv, int win_id , int en)
236 struct lcdc_device *lcdc_dev = container_of(drv,
237 struct lcdc_device, driver);
239 win0_enable(lcdc_dev, en);
240 else if (win_id == 1)
241 win1_enable(lcdc_dev, en);
242 else if (win_id == 2)
243 win2_enable(lcdc_dev, en);
244 else if (win_id == 3)
245 win3_enable(lcdc_dev, en);
247 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
252 #define SET_WIN_ADDR(id) \
253 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
256 spin_lock(&lcdc_dev->reg_lock); \
257 lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr); \
258 msk = m_WIN##id##_EN; \
259 val = v_WIN0_EN(1); \
260 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val); \
261 lcdc_cfg_done(lcdc_dev); \
262 spin_unlock(&lcdc_dev->reg_lock); \
268 int rk3288_lcdc_direct_set_win_addr
269 (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr)
271 struct lcdc_device *lcdc_dev = container_of(dev_drv,
272 struct lcdc_device, driver);
274 set_win0_addr(lcdc_dev, addr);
276 set_win1_addr(lcdc_dev, addr);
281 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
285 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
286 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
287 u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
289 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
291 spin_lock(&lcdc_dev->reg_lock);
292 for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
293 val = lcdc_readl(lcdc_dev, reg);
297 (val & m_WIN0_ACT_WIDTH) + 1;
299 ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
302 win0->area[0].xsize =
303 (val & m_WIN0_DSP_WIDTH) + 1;
304 win0->area[0].ysize =
305 ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
308 st_x = val & m_WIN0_DSP_XST;
309 st_y = (val & m_WIN0_DSP_YST) >> 16;
310 win0->area[0].xpos = st_x - h_pw_bp;
311 win0->area[0].ypos = st_y - v_pw_bp;
314 win0->state = val & m_WIN0_EN;
315 win0->area[0].fmt_cfg =
316 (val & m_WIN0_DATA_FMT) >> 1;
317 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
318 win0->area[0].format = win0->area[0].fmt_cfg;
321 win0->area[0].y_vir_stride =
322 val & m_WIN0_VIR_STRIDE;
323 win0->area[0].uv_vir_stride =
324 (val & m_WIN0_VIR_STRIDE_UV) >> 16;
325 if (win0->area[0].format == ARGB888)
327 win0->area[0].y_vir_stride;
328 else if (win0->area[0].format == RGB888)
330 win0->area[0].y_vir_stride * 4 / 3;
331 else if (win0->area[0].format == RGB565)
333 2 * win0->area[0].y_vir_stride;
336 4 * win0->area[0].y_vir_stride;
339 win0->area[0].smem_start = val;
342 win0->area[0].cbr_start = val;
348 spin_unlock(&lcdc_dev->reg_lock);
352 /********do basic init*********/
353 static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
357 struct lcdc_device *lcdc_dev = container_of(dev_drv,
361 if (lcdc_dev->pre_init)
364 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
365 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
366 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
367 lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
369 if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
370 (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
371 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
375 rk_disp_pwr_enable(dev_drv);
376 rk3288_lcdc_clk_enable(lcdc_dev);
378 /*backup reg config at uboot*/
379 lcdc_read_reg_defalut_cfg(lcdc_dev);
381 #ifndef CONFIG_RK_FPGA
382 if (lcdc_dev->pwr18 == true) {
383 v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/
384 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
387 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
390 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
391 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
392 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
393 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
394 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
395 lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
397 lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821);
398 lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412);
399 lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696);
400 lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969);
401 lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb);
402 lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de);
404 mask = m_AUTO_GATING_EN;
405 val = v_AUTO_GATING_EN(0);
406 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val);
407 lcdc_cfg_done(lcdc_dev);
408 if (dev_drv->iommu_enabled) /*disable win0 to workaround iommu pagefault*/
409 win0_enable(lcdc_dev, 0);
410 lcdc_dev->pre_init = true;
416 static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev)
420 rk3288_lcdc_disable_irq(lcdc_dev);
421 spin_lock(&lcdc_dev->reg_lock);
422 if (likely(lcdc_dev->clk_on)) {
423 lcdc_dev->clk_on = 0;
424 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
425 lcdc_cfg_done(lcdc_dev);
426 spin_unlock(&lcdc_dev->reg_lock);
428 spin_unlock(&lcdc_dev->reg_lock);
432 static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
434 struct lcdc_device *lcdc_dev =
435 container_of(dev_drv, struct lcdc_device, driver);
436 struct rk_screen *screen = dev_drv->cur_screen;
437 u16 x_res = screen->mode.xres;
438 u16 y_res = screen->mode.yres;
441 u16 post_hsd_en,post_vsd_en;
442 u16 post_dsp_hact_st,post_dsp_hact_end;
443 u16 post_dsp_vact_st,post_dsp_vact_end;
444 u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1;
445 u16 post_h_fac,post_v_fac;
447 h_total = screen->mode.hsync_len+screen->mode.left_margin +
448 x_res + screen->mode.right_margin;
449 v_total = screen->mode.vsync_len+screen->mode.upper_margin +
450 y_res + screen->mode.lower_margin;
452 if(screen->post_dsp_stx + screen->post_xsize > x_res){
453 dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n",
454 screen->post_dsp_stx,screen->post_xsize,x_res);
455 screen->post_dsp_stx = x_res - screen->post_xsize;
457 if(screen->x_mirror == 0){
458 post_dsp_hact_st=screen->post_dsp_stx +
459 screen->mode.hsync_len+screen->mode.left_margin;
460 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
462 post_dsp_hact_end = h_total - screen->mode.right_margin -
463 screen->post_dsp_stx;
464 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
466 if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){
469 GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize);
476 if(screen->post_dsp_sty + screen->post_ysize > y_res){
477 dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n",
478 screen->post_dsp_sty,screen->post_ysize,y_res);
479 screen->post_dsp_sty = y_res - screen->post_ysize;
482 if(screen->y_mirror == 0){
483 post_dsp_vact_st = screen->post_dsp_sty +
484 screen->mode.vsync_len+screen->mode.upper_margin;
485 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
487 post_dsp_vact_end = v_total - screen->mode.lower_margin -
488 - screen->post_dsp_sty;
489 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
491 if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){
493 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize);
499 if(screen->interlace == 1){
500 post_dsp_vact_st_f1 = v_total + post_dsp_vact_st;
501 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
503 post_dsp_vact_st_f1 = 0;
504 post_dsp_vact_end_f1 = 0;
506 DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d,"
507 "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
508 screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos,
509 post_hsd_en,post_h_fac,post_vsd_en,post_v_fac);
510 mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
511 val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
512 v_DSP_HACT_ST_POST(post_dsp_hact_st);
513 lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
515 mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
516 val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
517 v_DSP_VACT_ST_POST(post_dsp_vact_st);
518 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
520 mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
521 val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
522 v_POST_VS_FACTOR_YRGB(post_v_fac);
523 lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
525 mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
526 val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
527 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
528 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
530 mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
531 val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
532 lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
536 static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
538 struct lcdc_device *lcdc_dev = container_of(dev_drv,
542 struct rk_lcdc_win *win;
543 u32 colorkey_r,colorkey_g,colorkey_b;
546 win = dev_drv->win[i];
547 key_val = win->color_key_val;
548 colorkey_r = (key_val & 0xff)<<2;
549 colorkey_g = ((key_val>>8)&0xff)<<12;
550 colorkey_b = ((key_val>>16)&0xff)<<22;
551 /*color key dither 565/888->aaa*/
552 key_val = colorkey_r | colorkey_g | colorkey_b;
555 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
558 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
561 lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
564 lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
567 printk(KERN_WARNING "%s:un support win num:%d\n",
575 static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id)
577 struct lcdc_device *lcdc_dev =
578 container_of(dev_drv, struct lcdc_device, driver);
579 struct rk_lcdc_win *win = dev_drv->win[win_id];
580 struct alpha_config alpha_config;
583 int ppixel_alpha,global_alpha;
584 u32 src_alpha_ctl,dst_alpha_ctl;
585 ppixel_alpha = ((win->area[0].format == ARGB888) ||
586 (win->area[0].format == ABGR888)) ? 1 : 0;
587 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
588 alpha_config.src_global_alpha_val = win->g_alpha_val;
589 win->alpha_mode = AB_SRC_OVER;
590 /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
591 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/
592 switch(win->alpha_mode){
596 alpha_config.src_factor_mode=AA_ZERO;
597 alpha_config.dst_factor_mode=AA_ZERO;
600 alpha_config.src_factor_mode=AA_ONE;
601 alpha_config.dst_factor_mode=AA_ZERO;
604 alpha_config.src_factor_mode=AA_ZERO;
605 alpha_config.dst_factor_mode=AA_ONE;
608 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
610 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
612 alpha_config.src_factor_mode=AA_ONE;
613 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
616 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
617 alpha_config.src_factor_mode=AA_SRC_INVERSE;
618 alpha_config.dst_factor_mode=AA_ONE;
621 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
622 alpha_config.src_factor_mode=AA_SRC;
623 alpha_config.dst_factor_mode=AA_ZERO;
626 alpha_config.src_factor_mode=AA_ZERO;
627 alpha_config.dst_factor_mode=AA_SRC;
630 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
631 alpha_config.src_factor_mode=AA_SRC_INVERSE;
632 alpha_config.dst_factor_mode=AA_ZERO;
635 alpha_config.src_factor_mode=AA_ZERO;
636 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
639 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
640 alpha_config.src_factor_mode=AA_SRC;
641 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
644 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
645 alpha_config.src_factor_mode=AA_SRC_INVERSE;
646 alpha_config.dst_factor_mode=AA_SRC;
649 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
650 alpha_config.src_factor_mode=AA_SRC_INVERSE;
651 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
653 case AB_SRC_OVER_GLOBAL:
654 alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL;
655 alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL;
656 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
657 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
660 pr_err("alpha mode error\n");
663 if((ppixel_alpha == 1)&&(global_alpha == 1)){
664 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
665 }else if(ppixel_alpha == 1){
666 alpha_config.src_global_alpha_mode = AA_PER_PIX;
667 }else if(global_alpha == 1){
668 alpha_config.src_global_alpha_mode = AA_GLOBAL;
670 dev_warn(lcdc_dev->dev,"alpha_en should be 0\n");
672 alpha_config.src_alpha_mode = AA_STRAIGHT;
673 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
677 src_alpha_ctl = 0x60;
678 dst_alpha_ctl = 0x64;
681 src_alpha_ctl = 0xa0;
682 dst_alpha_ctl = 0xa4;
685 src_alpha_ctl = 0xdc;
686 dst_alpha_ctl = 0xec;
689 src_alpha_ctl = 0x12c;
690 dst_alpha_ctl = 0x13c;
693 mask = m_WIN0_DST_FACTOR_M0;
694 val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
695 lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
696 mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
697 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
698 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0|
699 m_WIN0_SRC_GLOBAL_ALPHA;
700 val = v_WIN0_SRC_ALPHA_EN(1) |
701 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
702 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
703 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
704 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
705 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
706 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
707 lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
711 static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num)
713 struct rk_lcdc_win_area area_temp;
716 area_temp = win->area[0];
717 win->area[0] = win->area[1];
718 win->area[1] = area_temp;
721 area_temp = win->area[0];
722 win->area[0] = win->area[2];
723 win->area[2] = area_temp;
726 area_temp = win->area[0];
727 win->area[0] = win->area[3];
728 win->area[3] = area_temp;
730 area_temp = win->area[1];
731 win->area[1] = win->area[2];
732 win->area[2] = area_temp;
735 printk(KERN_WARNING "un supported area num!\n");
741 static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre,
742 struct rk_lcdc_win_area *area_now)
744 if((area_pre->ypos >= area_now->ypos) ||
745 (area_pre->ypos+area_pre->ysize > area_now->ypos)){
748 "area_pre[%d]:ypos[%d],ysize[%d]\n"
749 "area_now[%d]:ypos[%d],ysize[%d]\n",
751 area_num-1,area_pre->ypos,area_pre->ysize,
752 area_num, area_now->ypos,area_now->ysize);
758 static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
760 struct lcdc_device *lcdc_dev =
761 container_of(dev_drv, struct lcdc_device, driver);
762 struct rk_lcdc_win *win = dev_drv->win[win_id];
763 unsigned int mask, val, off;
765 if(win->win_lb_mode == 5)
766 win->win_lb_mode = 4;
769 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
770 m_WIN0_LB_MODE | m_WIN0_RB_SWAP;
771 val = v_WIN0_EN(win->state) |
772 v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
773 v_WIN0_FMT_10(win->fmt_10) |
774 v_WIN0_LB_MODE(win->win_lb_mode) |
775 v_WIN0_RB_SWAP(win->area[0].swap_rb);
776 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
778 mask = m_WIN0_BIC_COE_SEL |
779 m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
780 m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
781 m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
782 m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
783 m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
784 m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
785 m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
786 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
787 v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
788 v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
789 v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
790 v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
791 v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
792 v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
793 v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
794 v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
795 v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
796 v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
797 v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
798 v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
799 v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
800 v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
801 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val);
803 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
804 v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
805 lcdc_writel(lcdc_dev, WIN0_VIR+off, val);
806 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr);
807 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/
808 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
809 v_WIN0_ACT_HEIGHT(win->area[0].yact);
810 lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val);
812 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
813 v_WIN0_DSP_HEIGHT(win->area[0].ysize);
814 lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val);
816 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
817 v_WIN0_DSP_YST(win->area[0].dsp_sty);
818 lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val);
820 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
821 v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
822 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val);
824 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
825 v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
826 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val);
827 if(win->alpha_en == 1)
828 rk3288_lcdc_alpha_cfg(dev_drv,win_id);
830 mask = m_WIN0_SRC_ALPHA_EN;
831 val = v_WIN0_SRC_ALPHA_EN(0);
832 lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val);
837 val = v_WIN0_EN(win->state);
838 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
843 static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
845 struct lcdc_device *lcdc_dev =
846 container_of(dev_drv, struct lcdc_device, driver);
847 struct rk_lcdc_win *win = dev_drv->win[win_id];
848 struct rk_screen *screen = dev_drv->cur_screen;
849 unsigned int mask, val, off;
850 off = (win_id-2) * 0x50;
851 if((screen->y_mirror == 1)&&(win->area_num > 1)){
852 rk3288_lcdc_area_swap(win,win->area_num);
856 mask = m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP;
858 v_WIN2_DATA_FMT(win->area[0].fmt_cfg) |
859 v_WIN2_RB_SWAP(win->area[0].swap_rb);
860 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
862 if(win->area[0].state == 1){
863 mask = m_WIN2_MST0_EN;
864 val = v_WIN2_MST0_EN(win->area[0].state);
865 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
867 mask = m_WIN2_VIR_STRIDE0;
868 val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
869 lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
871 /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/
872 val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
873 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
874 lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val);
875 val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
876 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
877 lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val);
879 mask = m_WIN2_MST0_EN;
880 val = v_WIN2_MST0_EN(0);
881 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
884 if(win->area[1].state == 1){
885 rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]);
887 mask = m_WIN2_MST1_EN;
888 val = v_WIN2_MST1_EN(win->area[1].state);
889 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
891 mask = m_WIN2_VIR_STRIDE1;
892 val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
893 lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
895 /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/
896 val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
897 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
898 lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val);
899 val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
900 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
901 lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val);
903 mask = m_WIN2_MST1_EN;
904 val = v_WIN2_MST1_EN(0);
905 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
908 if(win->area[2].state == 1){
909 rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]);
911 mask = m_WIN2_MST2_EN;
912 val = v_WIN2_MST2_EN(win->area[2].state);
913 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
915 mask = m_WIN2_VIR_STRIDE2;
916 val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
917 lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
919 /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/
920 val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
921 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
922 lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val);
923 val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
924 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
925 lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val);
927 mask = m_WIN2_MST2_EN;
928 val = v_WIN2_MST2_EN(0);
929 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
932 if(win->area[3].state == 1){
933 rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]);
935 mask = m_WIN2_MST3_EN;
936 val = v_WIN2_MST3_EN(win->area[3].state);
937 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
939 mask = m_WIN2_VIR_STRIDE3;
940 val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
941 lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
943 /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/
944 val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
945 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
946 lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val);
947 val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
948 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
949 lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val);
951 mask = m_WIN2_MST3_EN;
952 val = v_WIN2_MST3_EN(0);
953 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
956 if(win->alpha_en == 1)
957 rk3288_lcdc_alpha_cfg(dev_drv,win_id);
959 mask = m_WIN2_SRC_ALPHA_EN;
960 val = v_WIN2_SRC_ALPHA_EN(0);
961 lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val);
964 mask = m_WIN2_EN | m_WIN2_MST0_EN |
965 m_WIN2_MST0_EN | m_WIN2_MST2_EN |
967 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
968 v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) |
970 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val);
975 static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
977 struct lcdc_device *lcdc_dev =
978 container_of(dev_drv, struct lcdc_device, driver);
982 spin_lock(&lcdc_dev->reg_lock);
983 if(likely(lcdc_dev->clk_on))
985 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
986 v_STANDBY_EN(lcdc_dev->standby));
987 rk3288_win_0_1_reg_update(dev_drv,0);
988 rk3288_win_0_1_reg_update(dev_drv,1);
989 rk3288_win_2_3_reg_update(dev_drv,2);
990 rk3288_win_2_3_reg_update(dev_drv,3);
991 /*rk3288_lcdc_post_cfg(dev_drv);*/
992 lcdc_cfg_done(lcdc_dev);
994 spin_unlock(&lcdc_dev->reg_lock);
996 /*if (dev_drv->wait_fs) {*/
998 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
999 init_completion(&dev_drv->frame_done);
1000 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1001 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1003 (dev_drv->cur_screen->ft +
1005 if (!timeout && (!dev_drv->frame_done.done)) {
1006 dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n");
1010 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1015 static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1017 if (lcdc_dev->driver.iommu_enabled)
1018 memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x330);
1020 memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc);
1023 static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1026 struct lcdc_device *lcdc_dev =
1027 container_of(dev_drv, struct lcdc_device, driver);
1028 spin_lock(&lcdc_dev->reg_lock);
1029 if (likely(lcdc_dev->clk_on)) {
1032 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1033 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1034 val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1);
1035 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1037 spin_unlock(&lcdc_dev->reg_lock);
1041 static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1043 #ifdef CONFIG_RK_FPGA
1047 struct lcdc_device *lcdc_dev =
1048 container_of(dev_drv, struct lcdc_device, driver);
1049 struct rk_screen *screen = dev_drv->cur_screen;
1051 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
1053 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1054 lcdc_dev->pixclock =
1055 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1056 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1058 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1059 screen->ft = 1000 / fps;
1060 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1061 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1066 static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1067 u16 *yact, int *format, u32 *dsp_addr)
1069 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1070 struct lcdc_device, driver);
1073 spin_lock(&lcdc_dev->reg_lock);
1075 val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1076 *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1077 *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1079 val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1080 *format = (val & m_WIN0_DATA_FMT) >> 1;
1081 *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1083 spin_unlock(&lcdc_dev->reg_lock);
1088 static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1089 int format, u16 xact, u16 yact, u16 xvir)
1091 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1092 struct lcdc_device, driver);
1094 int swap = (format == RGB888) ? 1 : 0;
1096 mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1097 val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1098 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1100 lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1101 v_WIN0_VIR_STRIDE(xvir));
1102 lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1103 v_WIN0_ACT_HEIGHT(yact));
1105 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1107 lcdc_cfg_done(lcdc_dev);
1112 static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1116 struct lcdc_device *lcdc_dev =
1117 container_of(dev_drv, struct lcdc_device, driver);
1118 struct rk_screen *screen = dev_drv->cur_screen;
1119 u16 hsync_len = screen->mode.hsync_len;
1120 u16 left_margin = screen->mode.left_margin;
1121 u16 right_margin = screen->mode.right_margin;
1122 u16 vsync_len = screen->mode.vsync_len;
1123 u16 upper_margin = screen->mode.upper_margin;
1124 u16 lower_margin = screen->mode.lower_margin;
1125 u16 x_res = screen->mode.xres;
1126 u16 y_res = screen->mode.yres;
1128 u16 h_total,v_total;
1130 h_total = hsync_len + left_margin + x_res + right_margin;
1131 v_total = vsync_len + upper_margin + y_res + lower_margin;
1133 screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1134 screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1135 screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200;
1136 screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200;
1138 spin_lock(&lcdc_dev->reg_lock);
1139 if (likely(lcdc_dev->clk_on)) {
1140 switch (screen->face) {
1143 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1145 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1146 v_DITHER_DOWN_SEL(1);
1147 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1151 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1153 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1154 v_DITHER_DOWN_SEL(1);
1155 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1159 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1161 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1162 v_DITHER_DOWN_SEL(1);
1163 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1167 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1169 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1170 v_DITHER_DOWN_SEL(1);
1171 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1175 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1176 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1177 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1180 dev_err(lcdc_dev->dev,"un supported interface!\n");
1183 switch(screen->type){
1186 case SCREEN_DUAL_LVDS:
1187 mask = m_RGB_OUT_EN;
1188 val = v_RGB_OUT_EN(1);
1190 v |= (lcdc_dev->id << 3);
1194 mask = m_HDMI_OUT_EN;
1195 val = v_HDMI_OUT_EN(1);
1198 mask = m_MIPI_OUT_EN;
1199 val = v_MIPI_OUT_EN(1);
1201 case SCREEN_DUAL_MIPI:
1202 mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1203 val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1206 face = OUT_RGB_AAA; /*RGB AAA output*/
1207 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1208 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1209 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1210 mask = m_EDP_OUT_EN;
1211 val = v_EDP_OUT_EN(1);
1214 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1215 #ifndef CONFIG_RK_FPGA
1216 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1218 mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL |
1219 m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP |
1220 m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1221 m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1222 m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1223 val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) |
1224 v_DSP_VSYNC_POL(screen->pin_vsync) |
1225 v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) |
1226 v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) |
1227 v_DSP_RG_SWAP(screen->swap_rg) |
1228 v_DSP_DELTA_SWAP(screen->swap_delta) |
1229 v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1230 v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1231 v_DSP_X_MIR_EN(screen->x_mirror) | v_DSP_Y_MIR_EN(screen->y_mirror);
1232 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1234 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1235 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1236 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1238 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1239 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1240 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1242 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1243 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1244 v_DSP_HACT_ST(hsync_len + left_margin);
1245 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1247 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1248 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1249 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1251 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1252 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1253 v_DSP_VACT_ST(vsync_len + upper_margin);
1254 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1256 rk3288_lcdc_post_cfg(dev_drv);
1258 spin_unlock(&lcdc_dev->reg_lock);
1259 rk3288_lcdc_set_dclk(dev_drv);
1260 if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1261 dev_drv->trsm_ops->enable)
1262 dev_drv->trsm_ops->enable();
1269 /*enable layer,open:1,enable;0 disable*/
1270 static int win0_open(struct lcdc_device *lcdc_dev, bool open)
1272 spin_lock(&lcdc_dev->reg_lock);
1273 if (likely(lcdc_dev->clk_on)) {
1275 if (!lcdc_dev->atv_layer_cnt) {
1276 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1277 lcdc_dev->standby = 0;
1279 lcdc_dev->atv_layer_cnt++;
1280 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1281 lcdc_dev->atv_layer_cnt--;
1283 lcdc_dev->driver.win[0]->state = open;
1284 if (!lcdc_dev->atv_layer_cnt) {
1285 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1286 lcdc_dev->standby = 1;
1289 spin_unlock(&lcdc_dev->reg_lock);
1294 static int win1_open(struct lcdc_device *lcdc_dev, bool open)
1296 spin_lock(&lcdc_dev->reg_lock);
1297 if (likely(lcdc_dev->clk_on)) {
1299 if (!lcdc_dev->atv_layer_cnt) {
1300 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1301 lcdc_dev->standby = 0;
1303 lcdc_dev->atv_layer_cnt++;
1304 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1305 lcdc_dev->atv_layer_cnt--;
1307 lcdc_dev->driver.win[1]->state = open;
1309 /*if no layer used,disable lcdc*/
1310 if (!lcdc_dev->atv_layer_cnt) {
1311 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1312 lcdc_dev->standby = 1;
1315 spin_unlock(&lcdc_dev->reg_lock);
1320 static int win2_open(struct lcdc_device *lcdc_dev, bool open)
1322 spin_lock(&lcdc_dev->reg_lock);
1323 if (likely(lcdc_dev->clk_on)) {
1325 if (!lcdc_dev->atv_layer_cnt) {
1326 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1327 lcdc_dev->standby = 0;
1329 lcdc_dev->atv_layer_cnt++;
1330 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1331 lcdc_dev->atv_layer_cnt--;
1333 lcdc_dev->driver.win[2]->state = open;
1335 /*if no layer used,disable lcdc*/
1336 if (!lcdc_dev->atv_layer_cnt) {
1337 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1338 lcdc_dev->standby = 1;
1341 spin_unlock(&lcdc_dev->reg_lock);
1346 static int win3_open(struct lcdc_device *lcdc_dev, bool open)
1348 spin_lock(&lcdc_dev->reg_lock);
1349 if (likely(lcdc_dev->clk_on)) {
1351 if (!lcdc_dev->atv_layer_cnt) {
1352 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1353 lcdc_dev->standby = 0;
1355 lcdc_dev->atv_layer_cnt++;
1356 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1357 lcdc_dev->atv_layer_cnt--;
1359 lcdc_dev->driver.win[3]->state = open;
1361 /*if no layer used,disable lcdc*/
1362 if (!lcdc_dev->atv_layer_cnt) {
1363 dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1364 lcdc_dev->standby = 1;
1367 spin_unlock(&lcdc_dev->reg_lock);
1371 static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1373 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1374 struct lcdc_device, driver);
1376 struct rk_screen *screen = dev_drv->cur_screen;
1378 mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR |
1379 m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR |
1380 m_BUS_ERROR_INTR_EN | m_DSP_LINE_FLAG_NUM;
1381 val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) |
1382 v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0) |
1383 v_DSP_LINE_FLAG_NUM(screen->mode.vsync_len + screen->mode.upper_margin +
1385 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1386 #ifdef LCDC_IRQ_EMPTY_DEBUG
1387 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN |
1388 m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
1390 val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) |
1391 v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) |
1392 v_PWM_GEN_INTR_EN(1);
1393 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
1398 static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1401 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1402 struct lcdc_device, driver);
1403 int sys_status = (dev_drv->id == 0) ?
1404 SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1406 /*enable clk,when first layer open */
1407 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1408 rockchip_set_system_status(sys_status);
1409 rk3288_lcdc_pre_init(dev_drv);
1410 rk3288_lcdc_clk_enable(lcdc_dev);
1411 rk3288_lcdc_enable_irq(dev_drv);
1412 #if defined(CONFIG_ROCKCHIP_IOMMU)
1413 if (dev_drv->iommu_enabled) {
1414 if (!dev_drv->mmu_dev) {
1416 rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1417 if (dev_drv->mmu_dev) {
1418 rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1421 dev_err(dev_drv->dev,
1422 "failed to get rockchip iommu device\n");
1426 if (dev_drv->mmu_dev)
1427 rockchip_iovmm_activate(dev_drv->dev);
1430 rk3288_lcdc_reg_restore(lcdc_dev);
1431 if (dev_drv->iommu_enabled)
1432 rk3288_lcdc_mmu_en(dev_drv);
1433 if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) {
1434 rk3288_lcdc_set_dclk(dev_drv);
1435 rk3288_lcdc_enable_irq(dev_drv);
1437 rk3288_load_screen(dev_drv, 1);
1439 if (dev_drv->bcsh.enable)
1440 rk3288_lcdc_set_bcsh(dev_drv, 1);
1441 spin_lock(&lcdc_dev->reg_lock);
1442 if (dev_drv->cur_screen->dsp_lut)
1443 rk3288_lcdc_set_lut(dev_drv);
1444 spin_unlock(&lcdc_dev->reg_lock);
1448 win0_open(lcdc_dev, open);
1449 else if (win_id == 1)
1450 win1_open(lcdc_dev, open);
1451 else if (win_id == 2)
1452 win2_open(lcdc_dev, open);
1453 else if (win_id == 3)
1454 win3_open(lcdc_dev, open);
1456 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1458 /* when all layer closed,disable clk */
1459 if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1460 rk3288_lcdc_disable_irq(lcdc_dev);
1461 rk3288_lcdc_reg_update(dev_drv);
1462 #if defined(CONFIG_ROCKCHIP_IOMMU)
1463 if (dev_drv->iommu_enabled) {
1464 if (dev_drv->mmu_dev)
1465 rockchip_iovmm_deactivate(dev_drv->dev);
1468 rk3288_lcdc_clk_disable(lcdc_dev);
1469 rockchip_clear_system_status(sys_status);
1475 static int win0_display(struct lcdc_device *lcdc_dev,
1476 struct rk_lcdc_win *win)
1480 y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/
1481 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1482 DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1483 lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset);
1484 spin_lock(&lcdc_dev->reg_lock);
1485 if (likely(lcdc_dev->clk_on)) {
1486 win->area[0].y_addr = y_addr;
1487 win->area[0].uv_addr = uv_addr;
1488 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr);
1489 lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr);
1490 /*lcdc_cfg_done(lcdc_dev);*/
1492 spin_unlock(&lcdc_dev->reg_lock);
1498 static int win1_display(struct lcdc_device *lcdc_dev,
1499 struct rk_lcdc_win *win)
1503 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1504 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1505 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",
1506 lcdc_dev->id, __func__, y_addr, uv_addr);
1508 spin_lock(&lcdc_dev->reg_lock);
1509 if (likely(lcdc_dev->clk_on)) {
1510 win->area[0].y_addr = y_addr;
1511 win->area[0].uv_addr = uv_addr;
1512 lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr);
1513 lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr);
1515 spin_unlock(&lcdc_dev->reg_lock);
1521 static int win2_display(struct lcdc_device *lcdc_dev,
1522 struct rk_lcdc_win *win)
1525 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1526 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1527 lcdc_dev->id, __func__, y_addr);
1529 spin_lock(&lcdc_dev->reg_lock);
1530 if (likely(lcdc_dev->clk_on)){
1531 for(i=0;i<win->area_num;i++)
1532 win->area[i].y_addr =
1533 win->area[i].smem_start + win->area[i].y_offset;
1534 lcdc_writel(lcdc_dev,WIN2_MST0,win->area[0].y_addr);
1535 lcdc_writel(lcdc_dev,WIN2_MST1,win->area[1].y_addr);
1536 lcdc_writel(lcdc_dev,WIN2_MST2,win->area[2].y_addr);
1537 lcdc_writel(lcdc_dev,WIN2_MST3,win->area[3].y_addr);
1539 spin_unlock(&lcdc_dev->reg_lock);
1543 static int win3_display(struct lcdc_device *lcdc_dev,
1544 struct rk_lcdc_win *win)
1547 y_addr = win->area[0].smem_start + win->area[0].y_offset;
1548 DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1549 lcdc_dev->id, __func__, y_addr);
1551 spin_lock(&lcdc_dev->reg_lock);
1552 if (likely(lcdc_dev->clk_on)){
1553 for(i=0;i<win->area_num;i++)
1554 win->area[i].y_addr =
1555 win->area[i].smem_start + win->area[i].y_offset;
1556 lcdc_writel(lcdc_dev,WIN3_MST0,win->area[0].y_addr);
1557 lcdc_writel(lcdc_dev,WIN3_MST1,win->area[1].y_addr);
1558 lcdc_writel(lcdc_dev,WIN3_MST2,win->area[2].y_addr);
1559 lcdc_writel(lcdc_dev,WIN3_MST3,win->area[3].y_addr);
1561 spin_unlock(&lcdc_dev->reg_lock);
1565 static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1567 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1568 struct lcdc_device, driver);
1569 struct rk_lcdc_win *win = NULL;
1570 struct rk_screen *screen = dev_drv->cur_screen;
1572 #if defined(WAIT_FOR_SYNC)
1574 unsigned long flags;
1576 win = dev_drv->win[win_id];
1578 dev_err(dev_drv->dev, "screen is null!\n");
1582 win0_display(lcdc_dev, win);
1583 }else if(win_id == 1){
1584 win1_display(lcdc_dev, win);
1585 }else if(win_id == 2){
1586 win2_display(lcdc_dev, win);
1587 }else if(win_id == 3){
1588 win3_display(lcdc_dev, win);
1590 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1594 /*this is the first frame of the system ,enable frame start interrupt */
1595 if ((dev_drv->first_frame)) {
1596 dev_drv->first_frame = 0;
1597 rk3288_lcdc_enable_irq(dev_drv);
1599 #if defined(WAIT_FOR_SYNC)
1600 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1601 init_completion(&dev_drv->frame_done);
1602 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1603 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1604 msecs_to_jiffies(dev_drv->
1607 if (!timeout && (!dev_drv->frame_done.done)) {
1608 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
1615 static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
1625 u32 yrgb_vScaleDnMult;
1626 u32 yrgb_xscl_factor;
1627 u32 yrgb_yscl_factor;
1628 u8 yrgb_vsd_bil_gt2=0;
1629 u8 yrgb_vsd_bil_gt4=0;
1635 u32 cbcr_vScaleDnMult;
1636 u32 cbcr_xscl_factor;
1637 u32 cbcr_yscl_factor;
1638 u8 cbcr_vsd_bil_gt2=0;
1639 u8 cbcr_vsd_bil_gt4=0;
1643 srcW = win->area[0].xact;
1644 srcH = win->area[0].yact;
1645 dstW = win->area[0].xsize;
1646 dstH = win->area[0].ysize;
1653 if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) {
1654 pr_err("ERROR: yrgb scale exceed 8,"
1655 "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1656 yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH);
1658 if(yrgb_srcW < yrgb_dstW){
1659 win->yrgb_hor_scl_mode = SCALE_UP;
1660 }else if(yrgb_srcW > yrgb_dstW){
1661 win->yrgb_hor_scl_mode = SCALE_DOWN;
1663 win->yrgb_hor_scl_mode = SCALE_NONE;
1666 if(yrgb_srcH < yrgb_dstH){
1667 win->yrgb_ver_scl_mode = SCALE_UP;
1668 }else if (yrgb_srcH > yrgb_dstH){
1669 win->yrgb_ver_scl_mode = SCALE_DOWN;
1671 win->yrgb_ver_scl_mode = SCALE_NONE;
1675 switch (win->area[0].format) {
1709 if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) {
1710 pr_err("ERROR: cbcr scale exceed 8,"
1711 "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1712 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH);
1716 if(cbcr_srcW < cbcr_dstW){
1717 win->cbr_hor_scl_mode = SCALE_UP;
1718 }else if(cbcr_srcW > cbcr_dstW){
1719 win->cbr_hor_scl_mode = SCALE_DOWN;
1721 win->cbr_hor_scl_mode = SCALE_NONE;
1724 if(cbcr_srcH < cbcr_dstH){
1725 win->cbr_ver_scl_mode = SCALE_UP;
1726 }else if(cbcr_srcH > cbcr_dstH){
1727 win->cbr_ver_scl_mode = SCALE_DOWN;
1729 win->cbr_ver_scl_mode = SCALE_NONE;
1731 DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
1732 "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1733 "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1734 ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW,
1735 yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode,
1736 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH,
1737 win->cbr_hor_scl_mode,win->cbr_ver_scl_mode);
1739 /*line buffer mode*/
1740 if ((win->area[0].format == YUV422) ||
1741 (win->area[0].format == YUV420) ||
1742 (win->area[0].format == YUV422_A) ||
1743 (win->area[0].format == YUV420_A)) {
1744 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1745 if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) {
1746 pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW);
1747 } else if (cbcr_dstW > 2560) {
1748 win->win_lb_mode = LB_RGB_3840X2;
1749 } else if (cbcr_dstW > 1920) {
1750 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1751 if(yrgb_dstW > 3840){
1752 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1753 }else if(yrgb_dstW > 2560){
1754 win->win_lb_mode = LB_RGB_3840X2;
1755 }else if(yrgb_dstW > 1920){
1756 win->win_lb_mode = LB_RGB_2560X4;
1758 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1761 } else if (cbcr_dstW > 1280) {
1762 win->win_lb_mode = LB_YUV_3840X5;
1764 win->win_lb_mode = LB_YUV_2560X8;
1766 } else { /*SCALE_UP or SCALE_NONE*/
1767 if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) {
1768 pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW);
1769 }else if(cbcr_srcW > 2560){
1770 win->win_lb_mode = LB_RGB_3840X2;
1771 }else if(cbcr_srcW > 1920){
1772 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1773 if(yrgb_dstW > 3840){
1774 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1775 }else if(yrgb_dstW > 2560){
1776 win->win_lb_mode = LB_RGB_3840X2;
1777 }else if(yrgb_dstW > 1920){
1778 win->win_lb_mode = LB_RGB_2560X4;
1780 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1783 }else if(cbcr_srcW > 1280){
1784 win->win_lb_mode = LB_YUV_3840X5;
1786 win->win_lb_mode = LB_YUV_2560X8;
1790 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1791 if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) {
1792 pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW);
1793 }else if(yrgb_dstW > 2560){
1794 win->win_lb_mode = LB_RGB_3840X2;
1795 }else if(yrgb_dstW > 1920){
1796 win->win_lb_mode = LB_RGB_2560X4;
1797 }else if(yrgb_dstW > 1280){
1798 win->win_lb_mode = LB_RGB_1920X5;
1800 win->win_lb_mode = LB_RGB_1280X8;
1802 }else{ /*SCALE_UP or SCALE_NONE*/
1803 if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) {
1804 pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW);
1805 }else if(yrgb_srcW > 2560){
1806 win->win_lb_mode = LB_RGB_3840X2;
1807 }else if(yrgb_srcW > 1920){
1808 win->win_lb_mode = LB_RGB_2560X4;
1809 }else if(yrgb_srcW > 1280){
1810 win->win_lb_mode = LB_RGB_1920X5;
1812 win->win_lb_mode = LB_RGB_1280X8;
1816 DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode);
1818 /*vsd/vsu scale ALGORITHM*/
1819 win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1820 win->cbr_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1821 win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1822 win->cbr_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1823 switch(win->win_lb_mode){
1828 win->yrgb_vsu_mode = SCALE_UP_BIC;
1829 win->cbr_vsu_mode = SCALE_UP_BIC;
1832 if(win->yrgb_ver_scl_mode != SCALE_NONE) {
1833 pr_err("ERROR : not allow yrgb ver scale\n");
1835 if(win->cbr_ver_scl_mode != SCALE_NONE) {
1836 pr_err("ERROR : not allow cbcr ver scale\n");
1840 win->yrgb_vsu_mode = SCALE_UP_BIL;
1841 win->cbr_vsu_mode = SCALE_UP_BIL;
1844 printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n",
1845 __func__,win->win_lb_mode);
1848 DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
1849 win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode,
1850 win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode);
1854 /*(1.1)YRGB HOR SCALE FACTOR*/
1855 switch(win->yrgb_hor_scl_mode){
1857 yrgb_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1860 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
1863 switch(win->yrgb_hsd_mode)
1865 case SCALE_DOWN_BIL:
1866 yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
1868 case SCALE_DOWN_AVG:
1869 yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
1872 printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n",
1873 __func__,win->yrgb_hsd_mode);
1878 printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n",
1879 __func__,win->yrgb_hor_scl_mode);
1881 } /*win->yrgb_hor_scl_mode*/
1883 /*(1.2)YRGB VER SCALE FACTOR*/
1884 switch(win->yrgb_ver_scl_mode)
1887 yrgb_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1890 switch(win->yrgb_vsu_mode)
1893 yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
1897 pr_err("yrgb_srcH should be greater than 3 !!!\n");
1899 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH);
1902 printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n",
1903 __func__,win->yrgb_vsu_mode);
1908 switch(win->yrgb_vsd_mode)
1910 case SCALE_DOWN_BIL:
1911 yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH);
1912 yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult);
1913 if(yrgb_vScaleDnMult == 4){
1914 yrgb_vsd_bil_gt4 = 1;
1915 yrgb_vsd_bil_gt2 = 0;
1916 }else if(yrgb_vScaleDnMult == 2){
1917 yrgb_vsd_bil_gt4 = 0;
1918 yrgb_vsd_bil_gt2 = 1;
1920 yrgb_vsd_bil_gt4 = 0;
1921 yrgb_vsd_bil_gt2 = 0;
1924 case SCALE_DOWN_AVG:
1925 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH);
1928 printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n",
1929 __func__,win->yrgb_vsd_mode);
1931 } /*win->yrgb_vsd_mode*/
1934 printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n",
1935 __func__,win->yrgb_ver_scl_mode);
1938 win->scale_yrgb_x = yrgb_xscl_factor;
1939 win->scale_yrgb_y = yrgb_yscl_factor;
1940 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
1941 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
1942 DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor,
1943 yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2);
1945 /*(2.1)CBCR HOR SCALE FACTOR*/
1946 switch(win->cbr_hor_scl_mode)
1949 cbcr_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1952 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
1955 switch(win->cbr_hsd_mode)
1957 case SCALE_DOWN_BIL:
1958 cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
1960 case SCALE_DOWN_AVG:
1961 cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
1964 printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n",
1965 __func__,win->cbr_hsd_mode);
1970 printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n",
1971 __func__,win->cbr_hor_scl_mode);
1973 } /*win->cbr_hor_scl_mode*/
1975 /*(2.2)CBCR VER SCALE FACTOR*/
1976 switch(win->cbr_ver_scl_mode)
1979 cbcr_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
1982 switch(win->cbr_vsu_mode)
1985 cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
1989 pr_err("cbcr_srcH should be greater than 3 !!!\n");
1991 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH);
1994 printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n",
1995 __func__,win->cbr_vsu_mode);
2000 switch(win->cbr_vsd_mode)
2002 case SCALE_DOWN_BIL:
2003 cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH);
2004 cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult);
2005 if(cbcr_vScaleDnMult == 4){
2006 cbcr_vsd_bil_gt4 = 1;
2007 cbcr_vsd_bil_gt2 = 0;
2008 }else if(cbcr_vScaleDnMult == 2){
2009 cbcr_vsd_bil_gt4 = 0;
2010 cbcr_vsd_bil_gt2 = 1;
2012 cbcr_vsd_bil_gt4 = 0;
2013 cbcr_vsd_bil_gt2 = 0;
2016 case SCALE_DOWN_AVG:
2017 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH);
2020 printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n",
2021 __func__,win->cbr_vsd_mode);
2026 printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n",
2027 __func__,win->cbr_ver_scl_mode);
2030 win->scale_cbcr_x = cbcr_xscl_factor;
2031 win->scale_cbcr_y = cbcr_yscl_factor;
2032 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2033 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2035 DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor,
2036 cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2);
2042 static int win0_set_par(struct lcdc_device *lcdc_dev,
2043 struct rk_screen *screen, struct rk_lcdc_win *win)
2045 u32 xact,yact,xvir, yvir,xpos, ypos;
2046 u8 fmt_cfg = 0, swap_rb;
2047 char fmt[9] = "NULL";
2049 xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2050 ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2052 spin_lock(&lcdc_dev->reg_lock);
2053 if(likely(lcdc_dev->clk_on)){
2054 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2055 switch (win->area[0].format) {
2107 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2111 win->area[0].fmt_cfg = fmt_cfg;
2112 win->area[0].swap_rb = swap_rb;
2113 win->area[0].dsp_stx = xpos;
2114 win->area[0].dsp_sty = ypos;
2115 xact = win->area[0].xact;
2116 yact = win->area[0].yact;
2117 xvir = win->area[0].xvir;
2118 yvir = win->area[0].yvir;
2120 rk3288_win_0_1_reg_update(&lcdc_dev->driver,0);
2121 spin_unlock(&lcdc_dev->reg_lock);
2123 DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2124 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2125 __func__, get_format_string(win->area[0].format, fmt), xact,
2126 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2131 static int win1_set_par(struct lcdc_device *lcdc_dev,
2132 struct rk_screen *screen, struct rk_lcdc_win *win)
2134 u32 xact, yact, xvir, yvir, xpos, ypos;
2135 u8 fmt_cfg = 0, swap_rb;
2136 char fmt[9] = "NULL";
2138 xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2139 ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2141 spin_lock(&lcdc_dev->reg_lock);
2142 if (likely(lcdc_dev->clk_on)) {
2143 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2144 switch (win->area[0].format) {
2197 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2201 win->area[0].fmt_cfg = fmt_cfg;
2202 win->area[0].swap_rb = swap_rb;
2203 win->area[0].dsp_stx = xpos;
2204 win->area[0].dsp_sty = ypos;
2205 xact = win->area[0].xact;
2206 yact = win->area[0].yact;
2207 xvir = win->area[0].xvir;
2208 yvir = win->area[0].yvir;
2210 rk3288_win_0_1_reg_update(&lcdc_dev->driver,1);
2211 spin_unlock(&lcdc_dev->reg_lock);
2213 DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2214 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2215 __func__, get_format_string(win->area[0].format, fmt), xact,
2216 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2221 static int win2_set_par(struct lcdc_device *lcdc_dev,
2222 struct rk_screen *screen, struct rk_lcdc_win *win)
2225 u8 fmt_cfg, swap_rb;
2227 spin_lock(&lcdc_dev->reg_lock);
2228 if (likely(lcdc_dev->clk_on)) {
2229 for (i = 0; i < win->area_num; i++) {
2230 switch (win->area[i].format) {
2249 dev_err(lcdc_dev->driver.dev,
2250 "%s:un supported format!\n",
2254 win->area[i].fmt_cfg = fmt_cfg;
2255 win->area[i].swap_rb = swap_rb;
2256 win->area[i].dsp_stx = win->area[i].xpos +
2257 screen->mode.left_margin +
2258 screen->mode.hsync_len;
2259 if (screen->y_mirror == 1) {
2260 win->area[i].dsp_sty = screen->mode.yres -
2262 win->area[i].ysize +
2263 screen->mode.upper_margin +
2264 screen->mode.vsync_len;
2266 win->area[i].dsp_sty = win->area[i].ypos +
2267 screen->mode.upper_margin +
2268 screen->mode.vsync_len;
2272 rk3288_win_2_3_reg_update(&lcdc_dev->driver,2);
2273 spin_unlock(&lcdc_dev->reg_lock);
2277 static int win3_set_par(struct lcdc_device *lcdc_dev,
2278 struct rk_screen *screen, struct rk_lcdc_win *win)
2282 u8 fmt_cfg, swap_rb;
2284 spin_lock(&lcdc_dev->reg_lock);
2285 if (likely(lcdc_dev->clk_on)) {
2286 for (i = 0; i < win->area_num; i++) {
2287 switch (win->area[i].format) {
2306 dev_err(lcdc_dev->driver.dev,
2307 "%s:un supported format!\n",
2311 win->area[i].fmt_cfg = fmt_cfg;
2312 win->area[i].swap_rb = swap_rb;
2313 win->area[i].dsp_stx = win->area[i].xpos +
2314 screen->mode.left_margin +
2315 screen->mode.hsync_len;
2316 if (screen->y_mirror == 1) {
2317 win->area[i].dsp_sty = screen->mode.yres -
2319 win->area[i].ysize +
2320 screen->mode.upper_margin +
2321 screen->mode.vsync_len;
2323 win->area[i].dsp_sty = win->area[i].ypos +
2324 screen->mode.upper_margin +
2325 screen->mode.vsync_len;
2329 rk3288_win_2_3_reg_update(&lcdc_dev->driver,3);
2330 spin_unlock(&lcdc_dev->reg_lock);
2334 static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id)
2336 struct lcdc_device *lcdc_dev =
2337 container_of(dev_drv, struct lcdc_device, driver);
2338 struct rk_lcdc_win *win = NULL;
2339 struct rk_screen *screen = dev_drv->cur_screen;
2340 win = dev_drv->win[win_id];
2345 win0_set_par(lcdc_dev, screen, win);
2348 win1_set_par(lcdc_dev, screen, win);
2351 win2_set_par(lcdc_dev, screen, win);
2354 win3_set_par(lcdc_dev, screen, win);
2357 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2363 static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2364 unsigned long arg, int win_id)
2366 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2371 void __user *argp = (void __user *)arg;
2372 struct color_key_cfg clr_key_cfg;
2375 case RK_FBIOGET_PANEL_SIZE:
2376 panel_size[0] = lcdc_dev->screen->mode.xres;
2377 panel_size[1] = lcdc_dev->screen->mode.yres;
2378 if (copy_to_user(argp, panel_size, 8))
2381 case RK_FBIOPUT_COLOR_KEY_CFG:
2382 if (copy_from_user(&clr_key_cfg, argp,
2383 sizeof(struct color_key_cfg)))
2385 rk3288_lcdc_clr_key_cfg(dev_drv);
2386 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2387 clr_key_cfg.win0_color_key_cfg);
2388 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2389 clr_key_cfg.win1_color_key_cfg);
2398 static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2401 struct lcdc_device *lcdc_dev =
2402 container_of(dev_drv, struct lcdc_device, driver);
2403 if (dev_drv->suspend_flag)
2406 dev_drv->suspend_flag = 1;
2407 flush_kthread_worker(&dev_drv->update_regs_worker);
2409 for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4)
2410 lcdc_readl(lcdc_dev, reg);
2411 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2412 dev_drv->trsm_ops->disable();
2414 spin_lock(&lcdc_dev->reg_lock);
2415 if (likely(lcdc_dev->clk_on)) {
2416 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2418 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR,
2419 v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1));
2420 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2422 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2424 lcdc_cfg_done(lcdc_dev);
2426 if (dev_drv->iommu_enabled) {
2427 if (dev_drv->mmu_dev)
2428 rockchip_iovmm_deactivate(dev_drv->dev);
2431 spin_unlock(&lcdc_dev->reg_lock);
2433 spin_unlock(&lcdc_dev->reg_lock);
2436 rk3288_lcdc_clk_disable(lcdc_dev);
2437 rk_disp_pwr_disable(dev_drv);
2441 static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2443 struct lcdc_device *lcdc_dev =
2444 container_of(dev_drv, struct lcdc_device, driver);
2449 if (!dev_drv->suspend_flag)
2451 rk_disp_pwr_enable(dev_drv);
2452 dev_drv->suspend_flag = 0;
2454 if (lcdc_dev->atv_layer_cnt) {
2455 rk3288_lcdc_clk_enable(lcdc_dev);
2456 rk3288_lcdc_reg_restore(lcdc_dev);
2458 spin_lock(&lcdc_dev->reg_lock);
2459 if (dev_drv->cur_screen->dsp_lut) {
2460 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2462 lcdc_cfg_done(lcdc_dev);
2464 for (i = 0; i < 256; i++) {
2465 v = dev_drv->cur_screen->dsp_lut[i];
2466 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
2467 b = (v & 0xff) << 2;
2468 g = (v & 0xff00) << 4;
2469 r = (v & 0xff0000) << 6;
2471 for (j = 0; j < 4; j++) {
2472 writel_relaxed(v, c);
2473 v += (1 + (1 << 10) + (1 << 20)) ;
2477 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
2481 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2483 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2485 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2487 lcdc_cfg_done(lcdc_dev);
2489 if (dev_drv->iommu_enabled) {
2490 if (dev_drv->mmu_dev)
2491 rockchip_iovmm_activate(dev_drv->dev);
2494 spin_unlock(&lcdc_dev->reg_lock);
2497 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2498 dev_drv->trsm_ops->enable();
2503 static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2504 int win_id, int blank_mode)
2506 switch (blank_mode) {
2507 case FB_BLANK_UNBLANK:
2508 rk3288_lcdc_early_resume(dev_drv);
2510 case FB_BLANK_NORMAL:
2511 rk3288_lcdc_early_suspend(dev_drv);
2514 rk3288_lcdc_early_suspend(dev_drv);
2518 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2523 static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2528 /*overlay will be do at regupdate*/
2529 static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2532 struct lcdc_device *lcdc_dev =
2533 container_of(dev_drv, struct lcdc_device, driver);
2534 struct rk_lcdc_win *win = NULL;
2536 unsigned int mask, val;
2538 int layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2541 win = dev_drv->win[i];
2542 if(win->state == 1){
2547 win = dev_drv->win[i];
2549 win->z_order = z_order_num++;
2550 switch(win->z_order){
2552 layer0_sel = win->id;
2555 layer1_sel = win->id;
2558 layer2_sel = win->id;
2561 layer3_sel = win->id;
2568 layer0_sel = swap %10;;
2569 layer1_sel = swap /10 % 10;
2570 layer2_sel = swap / 100 %10;
2571 layer3_sel = swap / 1000;
2574 spin_lock(&lcdc_dev->reg_lock);
2575 if(lcdc_dev->clk_on){
2577 mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
2578 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
2579 val = v_DSP_LAYER0_SEL(layer0_sel) |
2580 v_DSP_LAYER1_SEL(layer1_sel) |
2581 v_DSP_LAYER2_SEL(layer2_sel) |
2582 v_DSP_LAYER3_SEL(layer3_sel);
2583 lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val);
2585 layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL);
2586 layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL);
2587 layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL);
2588 layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL);
2589 ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel;
2594 spin_unlock(&lcdc_dev->reg_lock);
2599 static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2600 char *buf, int win_id)
2602 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2606 struct rk_screen *screen = dev_drv->cur_screen;
2607 u16 hsync_len = screen->mode.hsync_len;
2608 u16 left_margin = screen->mode.left_margin;
2609 u16 vsync_len = screen->mode.vsync_len;
2610 u16 upper_margin = screen->mode.upper_margin;
2611 u32 h_pw_bp = hsync_len + left_margin;
2612 u32 v_pw_bp = vsync_len + upper_margin;
2614 char format_w0[9] = "NULL";
2615 char format_w1[9] = "NULL";
2616 char format_w2[9] = "NULL";
2617 char format_w3[9] = "NULL";
2618 u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor;
2619 u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2620 u8 w0_state,w1_state,w2_state,w3_state;
2621 u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state;
2622 u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state;
2624 u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp;
2625 u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp;
2626 u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac;
2627 u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac;
2629 u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y;
2630 u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x;
2631 u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y;
2632 u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp;
2633 u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp;
2635 u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y;
2636 u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x;
2637 u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y;
2638 u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp;
2639 u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp;
2642 dclk_freq = screen->mode.pixclock;
2643 /*rk3288_lcdc_reg_dump(dev_drv);*/
2645 spin_lock(&lcdc_dev->reg_lock);
2646 if (lcdc_dev->clk_on) {
2647 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
2648 layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8;
2649 layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10;
2650 layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12;
2651 layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14;
2653 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2654 w0_state = win_ctrl & m_WIN0_EN;
2655 fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1;
2658 strcpy(format_w0, "ARGB888");
2661 strcpy(format_w0, "RGB888");
2664 strcpy(format_w0, "RGB565");
2667 strcpy(format_w0, "YCbCr420");
2670 strcpy(format_w0, "YCbCr422");
2673 strcpy(format_w0, "YCbCr444");
2676 strcpy(format_w0, "invalid\n");
2679 vir_info = lcdc_readl(lcdc_dev,WIN0_VIR);
2680 act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
2681 dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
2682 dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
2683 y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
2684 uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR);
2685 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
2686 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16;
2687 w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1;
2688 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1;
2689 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1;
2690 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1;
2692 w0_st_x = dsp_st & m_WIN0_DSP_XST;
2693 w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16;
2695 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
2696 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16;
2697 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
2698 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16;
2701 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2702 w1_state = win_ctrl & m_WIN1_EN;
2703 fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1;
2706 strcpy(format_w1, "ARGB888");
2709 strcpy(format_w1, "RGB888");
2712 strcpy(format_w1, "RGB565");
2715 strcpy(format_w1, "YCbCr420");
2718 strcpy(format_w1, "YCbCr422");
2721 strcpy(format_w1, "YCbCr444");
2724 strcpy(format_w1, "invalid\n");
2727 vir_info = lcdc_readl(lcdc_dev,WIN1_VIR);
2728 act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO);
2729 dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
2730 dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
2731 y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB);
2732 uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR);
2733 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
2734 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16;
2735 w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1;
2736 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1;
2737 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1;
2738 w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1;
2740 w1_st_x = dsp_st & m_WIN1_DSP_XST;
2741 w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16;
2743 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
2744 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16;
2745 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
2746 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16;
2748 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2749 w2_state = win_ctrl & m_WIN2_EN;
2750 w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4;
2751 w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5;
2752 w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6;
2753 w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7;
2754 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1);
2755 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
2756 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16;
2757 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3);
2758 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
2759 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16;
2760 fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1;
2763 strcpy(format_w2, "ARGB888");
2766 strcpy(format_w2, "RGB888");
2769 strcpy(format_w2, "RGB565");
2772 strcpy(format_w2,"8bpp");
2775 strcpy(format_w2,"4bpp");
2778 strcpy(format_w2,"2bpp");
2781 strcpy(format_w2,"1bpp");
2784 strcpy(format_w2, "invalid\n");
2787 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0);
2788 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0);
2789 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1;
2790 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1;
2792 w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
2793 w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16;
2795 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1);
2796 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1);
2797 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1;
2798 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1;
2800 w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
2801 w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16;
2803 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2);
2804 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2);
2805 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1;
2806 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1;
2808 w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
2809 w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16;
2811 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3);
2812 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3);
2813 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1;
2814 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1;
2816 w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
2817 w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16;
2821 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
2822 w3_state = win_ctrl & m_WIN3_EN;
2823 w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4;
2824 w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5;
2825 w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6;
2826 w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7;
2827 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1);
2828 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
2829 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16;
2830 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3);
2831 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
2832 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16;
2833 fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1;
2836 strcpy(format_w3, "ARGB888");
2839 strcpy(format_w3, "RGB888");
2842 strcpy(format_w3, "RGB565");
2845 strcpy(format_w3,"8bpp");
2848 strcpy(format_w3,"4bpp");
2851 strcpy(format_w3,"2bpp");
2854 strcpy(format_w3,"1bpp");
2857 strcpy(format_w3, "invalid");
2860 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0);
2861 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0);
2862 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1;
2863 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1;
2865 w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
2866 w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16;
2869 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1);
2870 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1);
2871 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1;
2872 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1;
2874 w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
2875 w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16;
2878 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2);
2879 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2);
2880 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1;
2881 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1;
2883 w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
2884 w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16;
2887 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3);
2888 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3);
2889 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1;
2890 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1;
2892 w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
2893 w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16;
2897 spin_unlock(&lcdc_dev->reg_lock);
2900 spin_unlock(&lcdc_dev->reg_lock);
2901 return snprintf(buf, PAGE_SIZE,
2903 " layer3_sel_win[%d]\n"
2904 " layer2_sel_win[%d]\n"
2905 " layer1_sel_win[%d]\n"
2906 " layer0_sel_win[%d]\n"
3011 layer3_sel,layer2_sel,layer1_sel,layer0_sel,
3012 w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,
3013 w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,
3014 w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3015 lcdc_readl(lcdc_dev, WIN0_CBR_MST),
3017 w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,
3018 w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,
3019 w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3020 lcdc_readl(lcdc_dev, WIN1_CBR_MST),
3023 w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y,
3024 w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0),
3026 w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y,
3027 w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1),
3029 w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y,
3030 w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2),
3032 w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y,
3033 w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3),
3036 w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y,
3037 w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0),
3039 w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y,
3040 w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1),
3042 w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y,
3043 w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2),
3045 w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y,
3046 w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3)
3051 static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3054 struct lcdc_device *lcdc_dev =
3055 container_of(dev_drv, struct lcdc_device, driver);
3056 struct rk_screen *screen = dev_drv->cur_screen;
3061 u32 x_total, y_total;
3064 dev_info(dev_drv->dev, "unsupport set fps=0\n");
3067 ft = div_u64(1000000000000llu, fps);
3069 screen->mode.upper_margin + screen->mode.lower_margin +
3070 screen->mode.yres + screen->mode.vsync_len;
3072 screen->mode.left_margin + screen->mode.right_margin +
3073 screen->mode.xres + screen->mode.hsync_len;
3074 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3075 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3076 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3079 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3080 dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
3081 fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3082 screen->ft = 1000 / fps; /*one frame time in ms */
3085 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3086 clk_get_rate(lcdc_dev->dclk), fps);
3091 static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3093 mutex_lock(&dev_drv->fb_win_id_mutex);
3094 if (order == FB_DEFAULT_ORDER)
3095 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3;
3096 dev_drv->fb3_win_id = order / 1000;
3097 dev_drv->fb2_win_id = (order / 100) % 10;
3098 dev_drv->fb1_win_id = (order / 10) % 10;
3099 dev_drv->fb0_win_id = order % 10;
3100 mutex_unlock(&dev_drv->fb_win_id_mutex);
3105 static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3109 mutex_lock(&dev_drv->fb_win_id_mutex);
3110 if (!strcmp(id, "fb0") || !strcmp(id, "fb4"))
3111 win_id = dev_drv->fb0_win_id;
3112 else if (!strcmp(id, "fb1") || !strcmp(id, "fb5"))
3113 win_id = dev_drv->fb1_win_id;
3114 else if (!strcmp(id, "fb2") || !strcmp(id, "fb6"))
3115 win_id = dev_drv->fb2_win_id;
3116 else if (!strcmp(id, "fb3") || !strcmp(id, "fb7"))
3117 win_id = dev_drv->fb3_win_id;
3118 mutex_unlock(&dev_drv->fb_win_id_mutex);
3123 static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3130 struct lcdc_device *lcdc_dev =
3131 container_of(dev_drv, struct lcdc_device, driver);
3132 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3133 lcdc_cfg_done(lcdc_dev);
3135 if (dev_drv->cur_screen->dsp_lut) {
3136 for (i = 0; i < 256; i++) {
3137 v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
3138 c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3139 b = (v & 0xff) << 2;
3140 g = (v & 0xff00) << 4;
3141 r = (v & 0xff0000) << 6;
3143 for (j = 0; j < 4; j++) {
3144 writel_relaxed(v, c);
3145 v += (1 + (1 << 10) + (1 << 20)) ;
3150 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3155 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
3156 lcdc_cfg_done(lcdc_dev);
3157 }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN));
3161 static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3163 struct lcdc_device *lcdc_dev =
3164 container_of(dev_drv, struct lcdc_device, driver);
3166 unsigned int mask, val;
3167 struct rk_lcdc_win *win = NULL;
3168 spin_lock(&lcdc_dev->reg_lock);
3169 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3170 v_STANDBY_EN(lcdc_dev->standby));
3172 win = dev_drv->win[i];
3173 if ((win->state == 0)&&(win->last_state == 1)) {
3176 lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3179 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val);
3182 lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3185 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val);
3188 mask = m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN |
3189 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3190 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) |
3191 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3192 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val);
3195 mask = m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN |
3196 m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3197 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) | v_WIN3_MST1_EN(0) |
3198 v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3199 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val);
3205 win->last_state = win->state;
3207 lcdc_cfg_done(lcdc_dev);
3208 spin_unlock(&lcdc_dev->reg_lock);
3213 static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3215 struct lcdc_device *lcdc_dev =
3216 container_of(dev_drv, struct lcdc_device, driver);
3217 spin_lock(&lcdc_dev->reg_lock);
3218 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3219 v_DIRECT_PATH_EN(open));
3220 lcdc_cfg_done(lcdc_dev);
3221 spin_unlock(&lcdc_dev->reg_lock);
3225 static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3227 struct lcdc_device *lcdc_dev = container_of(dev_drv,
3228 struct lcdc_device, driver);
3229 spin_lock(&lcdc_dev->reg_lock);
3230 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3231 v_DIRECT_PATCH_SEL(win_id));
3232 lcdc_cfg_done(lcdc_dev);
3233 spin_unlock(&lcdc_dev->reg_lock);
3238 static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3240 struct lcdc_device *lcdc_dev =
3241 container_of(dev_drv, struct lcdc_device, driver);
3243 spin_lock(&lcdc_dev->reg_lock);
3244 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3245 spin_unlock(&lcdc_dev->reg_lock);
3248 static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable)
3250 struct lcdc_device *lcdc_dev =
3251 container_of(dev_drv,struct lcdc_device,driver);
3253 enable_irq(lcdc_dev->irq);
3255 disable_irq(lcdc_dev->irq);
3259 int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3261 struct lcdc_device *lcdc_dev =
3262 container_of(dev_drv, struct lcdc_device, driver);
3266 if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){
3267 int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3268 if (int_reg & m_LINE_FLAG_INTR_STS) {
3269 lcdc_dev->driver.frame_time.last_framedone_t =
3270 lcdc_dev->driver.frame_time.framedone_t;
3271 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3272 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3273 v_LINE_FLAG_INTR_CLR(1));
3274 ret = RK_LF_STATUS_FC;
3276 ret = RK_LF_STATUS_FR;
3278 ret = RK_LF_STATUS_NC;
3283 static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,unsigned int *dsp_addr)
3285 struct lcdc_device *lcdc_dev =
3286 container_of(dev_drv, struct lcdc_device, driver);
3287 spin_lock(&lcdc_dev->reg_lock);
3288 if(lcdc_dev->clk_on){
3289 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3290 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3291 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3292 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3294 spin_unlock(&lcdc_dev->reg_lock);
3298 static struct lcdc_cabc_mode cabc_mode[4] = {
3299 /* pixel_num, stage_up, stage_down */
3300 {5, 128, 0}, /*mode 1*/
3301 {10, 128, 0}, /*mode 2*/
3302 {15, 128, 0}, /*mode 3*/
3303 {20, 128, 0}, /*mode 4*/
3306 static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3308 struct lcdc_device *lcdc_dev =
3309 container_of(dev_drv, struct lcdc_device, driver);
3310 struct rk_screen *screen = dev_drv->cur_screen;
3311 u32 total_pixel, calc_pixel, stage_up, stage_down, pixel_num;
3312 u32 mask = 0, val = 0, cabc_en = 0;
3313 u32 max_mode_num = sizeof(cabc_mode) / sizeof(struct lcdc_cabc_mode);
3315 dev_drv->cabc_mode = mode;
3317 /* iomux connect to vop or pwm */
3319 DBG(3, "close cabc and select rk pwm\n");
3321 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3323 } else if (mode > 0 && mode <= max_mode_num) {
3324 DBG(3, "open cabc and select vop pwm\n");
3325 val = (dev_drv->id == 0) ? 0x30002 : 0x30003;
3326 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3328 } else if (mode > 0x10 && mode <= (max_mode_num + 0x10)) {
3329 DBG(3, "open cabc and select rk pwm\n");
3331 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3334 } else if (mode == 0xff) {
3335 DBG(3, "close cabc and select vop pwm\n");
3336 val = (dev_drv->id == 0) ? 0x30002 : 0x30003;
3337 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_GPIO7A_IOMUX);
3340 dev_err(lcdc_dev->dev, "invalid cabc mode value:%d", mode);
3345 spin_lock(&lcdc_dev->reg_lock);
3346 if(lcdc_dev->clk_on) {
3347 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN, v_CABC_EN(0));
3348 lcdc_cfg_done(lcdc_dev);
3350 spin_unlock(&lcdc_dev->reg_lock);
3354 total_pixel = screen->mode.xres * screen->mode.yres;
3355 pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3356 calc_pixel = (total_pixel * pixel_num) / 1000;
3357 stage_up = cabc_mode[mode - 1].stage_up;
3358 stage_down = cabc_mode[mode - 1].stage_down;
3360 spin_lock(&lcdc_dev->reg_lock);
3361 if(lcdc_dev->clk_on) {
3362 mask = m_CABC_TOTAL_NUM | m_CABC_STAGE_DOWN;
3363 val = v_CABC_TOTAL_NUM(total_pixel) | v_CABC_STAGE_DOWN(stage_down);
3364 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3366 mask = m_CABC_EN | m_CABC_CALC_PIXEL_NUM |
3368 val = v_CABC_EN(1) | v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3369 v_CABC_STAGE_UP(stage_up);
3370 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3371 lcdc_cfg_done(lcdc_dev);
3373 spin_unlock(&lcdc_dev->reg_lock);
3379 sin_hue = sin(a)*256 +0x100;
3380 cos_hue = cos(a)*256;
3382 sin_hue = sin(a)*256;
3383 cos_hue = cos(a)*256;
3385 static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode)
3388 struct lcdc_device *lcdc_dev =
3389 container_of(dev_drv, struct lcdc_device, driver);
3392 spin_lock(&lcdc_dev->reg_lock);
3393 if (lcdc_dev->clk_on) {
3394 val = lcdc_readl(lcdc_dev, BCSH_H);
3397 val &= m_BCSH_SIN_HUE;
3400 val &= m_BCSH_COS_HUE;
3407 spin_unlock(&lcdc_dev->reg_lock);
3413 static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue)
3416 struct lcdc_device *lcdc_dev =
3417 container_of(dev_drv, struct lcdc_device, driver);
3420 spin_lock(&lcdc_dev->reg_lock);
3421 if (lcdc_dev->clk_on) {
3422 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3423 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3424 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3425 lcdc_cfg_done(lcdc_dev);
3427 spin_unlock(&lcdc_dev->reg_lock);
3432 static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value)
3434 struct lcdc_device *lcdc_dev =
3435 container_of(dev_drv, struct lcdc_device, driver);
3438 spin_lock(&lcdc_dev->reg_lock);
3439 if(lcdc_dev->clk_on) {
3442 /*from 0 to 255,typical is 128*/
3445 else if (value >= 0x80)
3446 value = value - 0x80;
3447 mask = m_BCSH_BRIGHTNESS;
3448 val = v_BCSH_BRIGHTNESS(value);
3451 /*from 0 to 510,typical is 256*/
3452 mask = m_BCSH_CONTRAST;
3453 val = v_BCSH_CONTRAST(value);
3456 /*from 0 to 1015,typical is 256*/
3457 mask = m_BCSH_SAT_CON;
3458 val = v_BCSH_SAT_CON(value);
3463 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3464 lcdc_cfg_done(lcdc_dev);
3466 spin_unlock(&lcdc_dev->reg_lock);
3470 static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode)
3472 struct lcdc_device *lcdc_dev =
3473 container_of(dev_drv, struct lcdc_device, driver);
3476 spin_lock(&lcdc_dev->reg_lock);
3477 if(lcdc_dev->clk_on) {
3478 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3481 val &= m_BCSH_BRIGHTNESS;
3488 val &= m_BCSH_CONTRAST;
3492 val &= m_BCSH_SAT_CON;
3499 spin_unlock(&lcdc_dev->reg_lock);
3504 static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3506 struct lcdc_device *lcdc_dev =
3507 container_of(dev_drv, struct lcdc_device, driver);
3510 spin_lock(&lcdc_dev->reg_lock);
3511 if (lcdc_dev->clk_on) {
3513 lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1);
3514 lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000);
3515 lcdc_writel(lcdc_dev,BCSH_H,0x01000000);
3519 lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3521 lcdc_cfg_done(lcdc_dev);
3523 spin_unlock(&lcdc_dev->reg_lock);
3527 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
3530 if (!enable || !dev_drv->bcsh.enable) {
3531 rk3288_lcdc_open_bcsh(dev_drv, false);
3535 if (dev_drv->bcsh.brightness <= 255 ||
3536 dev_drv->bcsh.contrast <= 510 ||
3537 dev_drv->bcsh.sat_con <= 1015 ||
3538 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3539 rk3288_lcdc_open_bcsh(dev_drv, true);
3540 if (dev_drv->bcsh.brightness <= 255)
3541 rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3542 dev_drv->bcsh.brightness);
3543 if (dev_drv->bcsh.contrast <= 510)
3544 rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3545 dev_drv->bcsh.contrast);
3546 if (dev_drv->bcsh.sat_con <= 1015)
3547 rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3548 dev_drv->bcsh.sat_con);
3549 if (dev_drv->bcsh.sin_hue <= 511 &&
3550 dev_drv->bcsh.cos_hue <= 511)
3551 rk3288_lcdc_set_bcsh_hue(dev_drv,
3552 dev_drv->bcsh.sin_hue,
3553 dev_drv->bcsh.cos_hue);
3558 static struct rk_lcdc_win lcdc_win[] = {
3562 .support_3d = false,
3567 .support_3d = false,
3572 .support_3d = false,
3577 .support_3d = false,
3581 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3582 .open = rk3288_lcdc_open,
3583 .win_direct_en = rk3288_lcdc_win_direct_en,
3584 .load_screen = rk3288_load_screen,
3585 .get_dspbuf_info = rk3288_get_dspbuf_info,
3586 .post_dspbuf = rk3288_post_dspbuf,
3587 .set_par = rk3288_lcdc_set_par,
3588 .pan_display = rk3288_lcdc_pan_display,
3589 .direct_set_addr = rk3288_lcdc_direct_set_win_addr,
3590 .lcdc_reg_update = rk3288_lcdc_reg_update,
3591 .blank = rk3288_lcdc_blank,
3592 .ioctl = rk3288_lcdc_ioctl,
3593 .suspend = rk3288_lcdc_early_suspend,
3594 .resume = rk3288_lcdc_early_resume,
3595 .get_win_state = rk3288_lcdc_get_win_state,
3596 .ovl_mgr = rk3288_lcdc_ovl_mgr,
3597 .get_disp_info = rk3288_lcdc_get_disp_info,
3598 .fps_mgr = rk3288_lcdc_fps_mgr,
3599 .fb_get_win_id = rk3288_lcdc_get_win_id,
3600 .fb_win_remap = rk3288_fb_win_remap,
3601 .set_dsp_lut = rk3288_set_dsp_lut,
3602 .poll_vblank = rk3288_lcdc_poll_vblank,
3603 .dpi_open = rk3288_lcdc_dpi_open,
3604 .dpi_win_sel = rk3288_lcdc_dpi_win_sel,
3605 .dpi_status = rk3288_lcdc_dpi_status,
3606 .get_dsp_addr = rk3288_lcdc_get_dsp_addr,
3607 .set_dsp_cabc = rk3288_lcdc_set_dsp_cabc,
3608 .set_dsp_bcsh_hue = rk3288_lcdc_set_bcsh_hue,
3609 .set_dsp_bcsh_bcs = rk3288_lcdc_set_bcsh_bcs,
3610 .get_dsp_bcsh_hue = rk3288_lcdc_get_bcsh_hue,
3611 .get_dsp_bcsh_bcs = rk3288_lcdc_get_bcsh_bcs,
3612 .open_bcsh = rk3288_lcdc_open_bcsh,
3613 .dump_reg = rk3288_lcdc_reg_dump,
3614 .cfg_done = rk3288_lcdc_config_done,
3615 .set_irq_to_cpu = rk3288_lcdc_set_irq_to_cpu,
3618 #ifdef LCDC_IRQ_DEBUG
3619 static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val)
3621 if (reg_val & m_WIN0_EMPTY_INTR_STS) {
3622 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR,
3623 v_WIN0_EMPTY_INTR_CLR(1));
3624 dev_warn(lcdc_dev->dev,"win0 empty irq!");
3625 }else if (reg_val & m_WIN1_EMPTY_INTR_STS) {
3626 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR,
3627 v_WIN1_EMPTY_INTR_CLR(1));
3628 dev_warn(lcdc_dev->dev,"win1 empty irq!");
3629 }else if (reg_val & m_WIN2_EMPTY_INTR_STS) {
3630 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR,
3631 v_WIN2_EMPTY_INTR_CLR(1));
3632 dev_warn(lcdc_dev->dev,"win2 empty irq!");
3633 }else if (reg_val & m_WIN3_EMPTY_INTR_STS) {
3634 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR,
3635 v_WIN3_EMPTY_INTR_CLR(1));
3636 dev_warn(lcdc_dev->dev,"win3 empty irq!");
3637 }else if (reg_val & m_HWC_EMPTY_INTR_STS) {
3638 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR,
3639 v_HWC_EMPTY_INTR_CLR(1));
3640 dev_warn(lcdc_dev->dev,"HWC empty irq!");
3641 }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) {
3642 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR,
3643 v_POST_BUF_EMPTY_INTR_CLR(1));
3644 dev_warn(lcdc_dev->dev,"post buf empty irq!");
3645 }else if (reg_val & m_PWM_GEN_INTR_STS) {
3646 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR,
3647 v_PWM_GEN_INTR_CLR(1));
3648 dev_warn(lcdc_dev->dev,"PWM gen irq!");
3655 static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id)
3657 struct lcdc_device *lcdc_dev =
3658 (struct lcdc_device *)dev_id;
3659 ktime_t timestamp = ktime_get();
3662 intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3664 if(intr0_reg & m_FS_INTR_STS){
3665 timestamp = ktime_get();
3666 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR,
3668 /*if(lcdc_dev->driver.wait_fs){ */
3670 spin_lock(&(lcdc_dev->driver.cpl_lock));
3671 complete(&(lcdc_dev->driver.frame_done));
3672 spin_unlock(&(lcdc_dev->driver.cpl_lock));
3674 #ifdef CONFIG_DRM_ROCKCHIP
3675 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
3677 lcdc_dev->driver.vsync_info.timestamp = timestamp;
3678 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
3680 }else if(intr0_reg & m_LINE_FLAG_INTR_STS){
3681 lcdc_dev->driver.frame_time.last_framedone_t =
3682 lcdc_dev->driver.frame_time.framedone_t;
3683 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3684 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3685 v_LINE_FLAG_INTR_CLR(1));
3686 }else if(intr0_reg & m_BUS_ERROR_INTR_STS){
3687 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR,
3688 v_BUS_ERROR_INTR_CLR(1));
3689 dev_warn(lcdc_dev->dev,"buf_error_int!");
3692 /* for win empty debug */
3693 #ifdef LCDC_IRQ_EMPTY_DEBUG
3694 intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1);
3695 if (intr1_reg != 0) {
3696 rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg);
3702 #if defined(CONFIG_PM)
3703 static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
3708 static int rk3288_lcdc_resume(struct platform_device *pdev)
3713 #define rk3288_lcdc_suspend NULL
3714 #define rk3288_lcdc_resume NULL
3717 static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
3719 struct device_node *np = lcdc_dev->dev->of_node;
3720 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
3723 if (of_property_read_u32(np, "rockchip,prop", &val))
3724 lcdc_dev->prop = PRMRY; /*default set it as primary */
3726 lcdc_dev->prop = val;
3728 if (of_property_read_u32(np, "rockchip,mirror", &val))
3729 dev_drv->rotate_mode = NO_MIRROR;
3731 dev_drv->rotate_mode = val;
3733 if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
3734 dev_drv->cabc_mode = 0; /* default set close cabc */
3736 dev_drv->cabc_mode = val;
3738 if (of_property_read_u32(np, "rockchip,pwr18", &val))
3739 lcdc_dev->pwr18 = false; /*default set it as 3.xv power supply */
3741 lcdc_dev->pwr18 = (val ? true : false);
3743 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
3744 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
3746 dev_drv->fb_win_map = val;
3748 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
3749 dev_drv->bcsh.enable = false;
3751 dev_drv->bcsh.enable = (val ? true : false);
3753 if (of_property_read_u32(np, "rockchip,brightness", &val))
3754 dev_drv->bcsh.brightness = 0xffff;
3756 dev_drv->bcsh.brightness = val;
3758 if (of_property_read_u32(np, "rockchip,contrast", &val))
3759 dev_drv->bcsh.contrast = 0xffff;
3761 dev_drv->bcsh.contrast = val;
3763 if (of_property_read_u32(np, "rockchip,sat-con", &val))
3764 dev_drv->bcsh.sat_con = 0xffff;
3766 dev_drv->bcsh.sat_con = val;
3768 if (of_property_read_u32(np, "rockchip,hue", &val)) {
3769 dev_drv->bcsh.sin_hue = 0xffff;
3770 dev_drv->bcsh.cos_hue = 0xffff;
3772 dev_drv->bcsh.sin_hue = val & 0xff;
3773 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
3776 #if defined(CONFIG_ROCKCHIP_IOMMU)
3777 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
3778 dev_drv->iommu_enabled = 0;
3780 dev_drv->iommu_enabled = val;
3782 dev_drv->iommu_enabled = 0;
3787 static int rk3288_lcdc_probe(struct platform_device *pdev)
3789 struct lcdc_device *lcdc_dev = NULL;
3790 struct rk_lcdc_driver *dev_drv;
3791 struct device *dev = &pdev->dev;
3792 struct resource *res;
3793 struct device_node *np = pdev->dev.of_node;
3797 /*if the primary lcdc has not registered ,the extend
3798 lcdc register later */
3799 of_property_read_u32(np, "rockchip,prop", &prop);
3800 if (prop == EXTEND) {
3801 if (!is_prmry_rk_lcdc_registered())
3802 return -EPROBE_DEFER;
3804 lcdc_dev = devm_kzalloc(dev,
3805 sizeof(struct lcdc_device), GFP_KERNEL);
3807 dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!");
3810 platform_set_drvdata(pdev, lcdc_dev);
3811 lcdc_dev->dev = dev;
3812 rk3288_lcdc_parse_dt(lcdc_dev);
3813 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3814 lcdc_dev->reg_phy_base = res->start;
3815 lcdc_dev->len = resource_size(res);
3816 lcdc_dev->regs = devm_ioremap_resource(dev, res);
3817 if (IS_ERR(lcdc_dev->regs))
3818 return PTR_ERR(lcdc_dev->regs);
3820 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
3821 if (IS_ERR(lcdc_dev->regsbak))
3822 return PTR_ERR(lcdc_dev->regsbak);
3823 lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
3824 lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base);
3825 if (lcdc_dev->id < 0) {
3826 dev_err(&pdev->dev, "no such lcdc device!\n");
3829 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
3830 dev_drv = &lcdc_dev->driver;
3832 dev_drv->prop = prop;
3833 dev_drv->id = lcdc_dev->id;
3834 dev_drv->ops = &lcdc_drv_ops;
3835 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
3836 spin_lock_init(&lcdc_dev->reg_lock);
3838 lcdc_dev->irq = platform_get_irq(pdev, 0);
3839 if (lcdc_dev->irq < 0) {
3840 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
3845 ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr,
3846 IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
3848 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
3849 lcdc_dev->irq, ret);
3853 if (dev_drv->iommu_enabled) {
3854 if(lcdc_dev->id == 0){
3855 strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME);
3857 strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME);
3861 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
3863 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
3866 lcdc_dev->screen = dev_drv->screen0;
3867 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
3868 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
3873 static int rk3288_lcdc_remove(struct platform_device *pdev)
3879 static void rk3288_lcdc_shutdown(struct platform_device *pdev)
3881 struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
3883 rk3288_lcdc_deint(lcdc_dev);
3884 rk_disp_pwr_disable(&lcdc_dev->driver);
3887 #if defined(CONFIG_OF)
3888 static const struct of_device_id rk3288_lcdc_dt_ids[] = {
3889 {.compatible = "rockchip,rk3288-lcdc",},
3894 static struct platform_driver rk3288_lcdc_driver = {
3895 .probe = rk3288_lcdc_probe,
3896 .remove = rk3288_lcdc_remove,
3898 .name = "rk3288-lcdc",
3899 .owner = THIS_MODULE,
3900 .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids),
3902 .suspend = rk3288_lcdc_suspend,
3903 .resume = rk3288_lcdc_resume,
3904 .shutdown = rk3288_lcdc_shutdown,
3907 static int __init rk3288_lcdc_module_init(void)
3909 return platform_driver_register(&rk3288_lcdc_driver);
3912 static void __exit rk3288_lcdc_module_exit(void)
3914 platform_driver_unregister(&rk3288_lcdc_driver);
3917 fs_initcall(rk3288_lcdc_module_init);
3918 module_exit(rk3288_lcdc_module_exit);