drivers/video/rockchip/lcdc/rk3288_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3288_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3288_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43
  44 static int dbg_thresd;
  45 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  46
  47 #define DBG(level, x...) do {                   \
  48         if (unlikely(dbg_thresd >= level))      \
  49                 printk(KERN_INFO x); } while (0)
  50
  51 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
  52                                      bool enable);
  53
  54 struct fb_info *rk_get_fb(int fb_id);
  55 /*#define WAIT_FOR_SYNC 1*/
  56
  57 static int rk3288_lcdc_get_id(u32 phy_base)
  58 {
  59         if (cpu_is_rk3288()) {
  60                 if (phy_base == 0xff930000)/*vop big*/
  61                         return 0;
  62                 else if (phy_base == 0xff940000)/*vop lit*/
  63                         return 1;
  64                 else
  65                         return -EINVAL;
  66         } else {
  67                 pr_err("un supported platform \n");
  68                 return -EINVAL;
  69         }
  70 }
  71
  72 static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
  73 {
  74         int i,j;
  75         int __iomem *c;
  76         u32 v,r,g,b;
  77         struct lcdc_device *lcdc_dev = container_of(dev_drv,
  78                                         struct lcdc_device,driver);
  79         if (dev_drv->cur_screen->dsp_lut)
  80                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
  81                              v_DSP_LUT_EN(0));
  82         if ((dev_drv->cur_screen->cabc_lut) &&
  83             (dev_drv->version == VOP_FULL_RK3288_V1_1))
  84                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
  85                              v_CABC_LUT_EN(0));
  86         lcdc_cfg_done(lcdc_dev);
  87         mdelay(25);
  88         if (dev_drv->cur_screen->dsp_lut) {
  89                 for (i = 0; i < 256; i++) {
  90                         v = dev_drv->cur_screen->dsp_lut[i];
  91                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
  92                         b = (v & 0xff) << 2;
  93                         g = (v & 0xff00) << 4;
  94                         r = (v & 0xff0000) << 6;
  95                         v = r + g + b;
  96                         for (j = 0; j < 4; j++) {
  97                                 writel_relaxed(v, c);
  98                                 v += (1 + (1 << 10) + (1 << 20));
  99                                 c++;
 100                         }
 101                 }
 102                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 103                              v_DSP_LUT_EN(1));
 104         }
 105         if ((dev_drv->cur_screen->cabc_lut) &&
 106             (dev_drv->version == VOP_FULL_RK3288_V1_1)) {
 107                 for (i = 0; i < 128; i++) {
 108                         v = dev_drv->cur_screen->cabc_lut[i];
 109                         lcdc_writel(lcdc_dev, i * 4 + CABC_LUT_ADDR, v);
 110                 }
 111                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 112                              v_CABC_LUT_EN(1));
 113         }
 114
 115         return 0;
 116
 117 }
 118
 119 static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 120 {
 121 #ifdef CONFIG_RK_FPGA
 122         lcdc_dev->clk_on = 1;
 123         return 0;
 124 #endif
 125         if (!lcdc_dev->clk_on) {
 126                 clk_prepare_enable(lcdc_dev->hclk);
 127                 clk_prepare_enable(lcdc_dev->dclk);
 128                 clk_prepare_enable(lcdc_dev->aclk);
 129                 clk_prepare_enable(lcdc_dev->pd);
 130                 spin_lock(&lcdc_dev->reg_lock);
 131                 lcdc_dev->clk_on = 1;
 132                 spin_unlock(&lcdc_dev->reg_lock);
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 139 {
 140 #ifdef CONFIG_RK_FPGA
 141         lcdc_dev->clk_on = 0;
 142         return 0;
 143 #endif
 144         if (lcdc_dev->clk_on) {
 145                 spin_lock(&lcdc_dev->reg_lock);
 146                 lcdc_dev->clk_on = 0;
 147                 spin_unlock(&lcdc_dev->reg_lock);
 148                 mdelay(25);
 149                 clk_disable_unprepare(lcdc_dev->dclk);
 150                 clk_disable_unprepare(lcdc_dev->hclk);
 151                 clk_disable_unprepare(lcdc_dev->aclk);
 152                 clk_disable_unprepare(lcdc_dev->pd);
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 159 {
 160         u32 mask, val;
 161         spin_lock(&lcdc_dev->reg_lock);
 162         if (likely(lcdc_dev->clk_on)) {
 163                 mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN |
 164                         m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN;
 165                 val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) |
 166                         v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0);
 167                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 168
 169                 mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR |
 170                         m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR;
 171                 val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) |
 172                         v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0);
 173                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 174
 175                 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 176                         m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 177                         m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 178                         m_POST_BUF_EMPTY_INTR_EN;
 179                 val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) |
 180                         v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) |
 181                         v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) |
 182                         v_PWM_GEN_INTR_EN(0);
 183                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 184
 185                 mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 186                         m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 187                         m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 188                         m_POST_BUF_EMPTY_INTR_CLR;
 189                 val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) |
 190                         v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) |
 191                         v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) |
 192                         v_PWM_GEN_INTR_CLR(0);
 193                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 194                 lcdc_cfg_done(lcdc_dev);
 195                 spin_unlock(&lcdc_dev->reg_lock);
 196         } else {
 197                 spin_unlock(&lcdc_dev->reg_lock);
 198         }
 199         mdelay(1);
 200         return 0;
 201 }
 202 static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 203 {
 204         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 205                                                 struct lcdc_device,
 206                                                 driver);
 207         int *cbase = (int *)lcdc_dev->regs;
 208         int *regsbak = (int *)lcdc_dev->regsbak;
 209         int i, j;
 210
 211         printk("back up reg:\n");
 212         for (i = 0; i <= (0x200 >> 4); i++) {
 213                 printk("0x%04x: ",i*16);
 214                 for (j = 0; j < 4; j++)
 215                         printk("%08x  ", *(regsbak + i * 4 + j));
 216                 printk("\n");
 217         }
 218
 219         printk("lcdc reg:\n");
 220         for (i = 0; i <= (0x200 >> 4); i++) {
 221                 printk("0x%04x: ",i*16);
 222                 for (j = 0; j < 4; j++)
 223                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
 224                 printk("\n");
 225         }
 226         return 0;
 227
 228 }
 229
 230 #define WIN_EN(id)              \
 231 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 232 { \
 233         u32 msk, val;                                                   \
 234         spin_lock(&lcdc_dev->reg_lock);                                 \
 235         msk =  m_WIN##id##_EN;                                          \
 236         val  =  v_WIN##id##_EN(en);                                     \
 237         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 238         lcdc_cfg_done(lcdc_dev);                                        \
 239         /*val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);          \
 240         while (val !=  (!!en))  {                                       \
 241                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 242         }*/                                                             \
 243         spin_unlock(&lcdc_dev->reg_lock);                               \
 244         return 0;                                                       \
 245 }
 246
 247 WIN_EN(0);
 248 WIN_EN(1);
 249 WIN_EN(2);
 250 WIN_EN(3);
 251 /*enable/disable win directly*/
 252 static int rk3288_lcdc_win_direct_en
 253                 (struct rk_lcdc_driver *drv, int win_id , int en)
 254 {
 255         struct lcdc_device *lcdc_dev = container_of(drv,
 256                                         struct lcdc_device, driver);
 257         if (win_id == 0)
 258                 win0_enable(lcdc_dev, en);
 259         else if (win_id == 1)
 260                 win1_enable(lcdc_dev, en);
 261         else if (win_id == 2)
 262                 win2_enable(lcdc_dev, en);
 263         else if (win_id == 3)
 264                 win3_enable(lcdc_dev, en);
 265         else
 266                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 267         return 0;
 268
 269 }
 270
 271 #define SET_WIN_ADDR(id) \
 272 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 273 {                                                       \
 274         u32 msk, val;                                   \
 275         spin_lock(&lcdc_dev->reg_lock);                 \
 276         lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr);  \
 277         msk =  m_WIN##id##_EN;                          \
 278         val  =  v_WIN0_EN(1);                           \
 279         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val);       \
 280         lcdc_cfg_done(lcdc_dev);                        \
 281         spin_unlock(&lcdc_dev->reg_lock);               \
 282         return 0;                                       \
 283 }
 284
 285 SET_WIN_ADDR(0);
 286 SET_WIN_ADDR(1);
 287 int rk3288_lcdc_direct_set_win_addr
 288                 (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr)
 289 {
 290         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 291                                 struct lcdc_device, driver);
 292         if (win_id == 0)
 293                 set_win0_addr(lcdc_dev, addr);
 294         else
 295                 set_win1_addr(lcdc_dev, addr);
 296
 297         return 0;
 298 }
 299
 300 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 301 {
 302         int reg = 0;
 303         u32 val = 0;
 304         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 305         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 306         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 307         u32 st_x, st_y;
 308         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 309
 310         spin_lock(&lcdc_dev->reg_lock);
 311         memcpy(lcdc_dev->regsbak, lcdc_dev->regs, FRC_LOWER11_1);
 312         for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
 313                 val = lcdc_readl(lcdc_dev, reg);
 314                 switch (reg) {
 315                 case VERSION_INFO:
 316                         lcdc_dev->driver.version = val;
 317                         break;
 318                         case WIN0_ACT_INFO:
 319                                 win0->area[0].xact =
 320                                         (val & m_WIN0_ACT_WIDTH) + 1;
 321                                 win0->area[0].yact =
 322                                         ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 323                                 break;
 324                         case WIN0_DSP_INFO:
 325                                 win0->area[0].xsize =
 326                                         (val & m_WIN0_DSP_WIDTH) + 1;
 327                                 win0->area[0].ysize =
 328                                         ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 329                                 break;
 330                         case WIN0_DSP_ST:
 331                                 st_x = val & m_WIN0_DSP_XST;
 332                                 st_y = (val & m_WIN0_DSP_YST) >> 16;
 333                                 win0->area[0].xpos = st_x - h_pw_bp;
 334                                 win0->area[0].ypos = st_y - v_pw_bp;
 335                                 break;
 336                         case WIN0_CTRL0:
 337                                 win0->state = val & m_WIN0_EN;
 338                                 win0->area[0].fmt_cfg =
 339                                         (val & m_WIN0_DATA_FMT) >> 1;
 340                                 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 341                                 win0->area[0].format = win0->area[0].fmt_cfg;
 342                                 break;
 343                         case WIN0_VIR:
 344                                 win0->area[0].y_vir_stride =
 345                                         val & m_WIN0_VIR_STRIDE;
 346                                 win0->area[0].uv_vir_stride =
 347                                         (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 348                                 if (win0->area[0].format == ARGB888)
 349                                         win0->area[0].xvir =
 350                                                 win0->area[0].y_vir_stride;
 351                                 else if (win0->area[0].format == RGB888)
 352                                         win0->area[0].xvir =
 353                                                 win0->area[0].y_vir_stride * 4 / 3;
 354                                 else if (win0->area[0].format == RGB565)
 355                                         win0->area[0].xvir =
 356                                                 2 * win0->area[0].y_vir_stride;
 357                                 else /* YUV */
 358                                         win0->area[0].xvir =
 359                                                 4 * win0->area[0].y_vir_stride;
 360                                 break;
 361                         case WIN0_YRGB_MST:
 362                                 win0->area[0].smem_start = val;
 363                                 break;
 364                         case WIN0_CBR_MST:
 365                                 win0->area[0].cbr_start = val;
 366                                 break;
 367                         case DSP_VACT_ST_END:
 368                                 if (support_uboot_display()) {
 369                                         screen->mode.yres =
 370                                         (val & 0x1fff) - ((val >> 16) & 0x1fff);
 371                                         win0->area[0].ypos =
 372                                         st_y - ((val >> 16) & 0x1fff);
 373                                 }
 374                                 break;
 375                         case DSP_HACT_ST_END:
 376                                 if (support_uboot_display()) {
 377                                         screen->mode.xres =
 378                                         (val & 0x1fff) - ((val >> 16) & 0x1fff);
 379                                         win0->area[0].xpos =
 380                                         st_x - ((val >> 16) & 0x1fff);
 381                                 }
 382                                 break;
 383                         default:
 384                                 break;
 385                 }
 386         }
 387         spin_unlock(&lcdc_dev->reg_lock);
 388
 389 }
 390
 391 /********do basic init*********/
 392 static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 393 {
 394         int v;
 395         u32 mask,val;
 396         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 397                                                            struct
 398                                                            lcdc_device,
 399                                                    driver);
 400         if (lcdc_dev->pre_init)
 401                 return 0;
 402
 403         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 404         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 405         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 406         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 407
 408         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 409             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 410                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 411                         lcdc_dev->id);
 412         }
 413         if (!support_uboot_display())
 414                 rk_disp_pwr_enable(dev_drv);
 415         rk3288_lcdc_clk_enable(lcdc_dev);
 416
 417         /*backup reg config at uboot*/
 418         lcdc_read_reg_defalut_cfg(lcdc_dev);
 419         v = 0;
 420 #ifndef CONFIG_RK_FPGA
 421         if (lcdc_dev->pwr18 == true) {
 422                 v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/
 423                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 424         } else {
 425                 v = 0x00010000;
 426                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 427         }
 428 #endif
 429         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
 430         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
 431         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
 432         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
 433         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
 434         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
 435
 436         lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821);
 437         lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412);
 438         lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696);
 439         lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969);
 440         lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb);
 441         lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de);
 442
 443         mask =  m_AUTO_GATING_EN;
 444         val  =  v_AUTO_GATING_EN(0);
 445         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val);
 446         lcdc_cfg_done(lcdc_dev);
 447         /*disable win0 to workaround iommu pagefault */
 448         /*if (dev_drv->iommu_enabled) */
 449         /*      win0_enable(lcdc_dev, 0); */
 450         lcdc_dev->pre_init = true;
 451
 452
 453         return 0;
 454 }
 455
 456 static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev)
 457 {
 458
 459
 460         rk3288_lcdc_disable_irq(lcdc_dev);
 461         spin_lock(&lcdc_dev->reg_lock);
 462         if (likely(lcdc_dev->clk_on)) {
 463                 lcdc_dev->clk_on = 0;
 464                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 465                 lcdc_cfg_done(lcdc_dev);
 466                 spin_unlock(&lcdc_dev->reg_lock);
 467         } else {
 468                 spin_unlock(&lcdc_dev->reg_lock);
 469         }
 470         mdelay(1);
 471 }
 472 static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 473 {
 474         struct lcdc_device *lcdc_dev =
 475             container_of(dev_drv, struct lcdc_device, driver);
 476         struct rk_screen *screen = dev_drv->cur_screen;
 477         u16 x_res = screen->mode.xres;
 478         u16 y_res = screen->mode.yres;
 479         u32 mask, val;
 480         u16 h_total,v_total;
 481         u16 post_hsd_en,post_vsd_en;
 482         u16 post_dsp_hact_st,post_dsp_hact_end;
 483         u16 post_dsp_vact_st,post_dsp_vact_end;
 484         u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1;
 485         u16 post_h_fac,post_v_fac;
 486
 487         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 488         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 489         screen->post_xsize = x_res *
 490                 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 491         screen->post_ysize = y_res *
 492                 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 493         h_total = screen->mode.hsync_len+screen->mode.left_margin +
 494                   x_res + screen->mode.right_margin;
 495         v_total = screen->mode.vsync_len+screen->mode.upper_margin +
 496                   y_res + screen->mode.lower_margin;
 497
 498         if(screen->post_dsp_stx + screen->post_xsize > x_res){
 499                 dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n",
 500                         screen->post_dsp_stx,screen->post_xsize,x_res);
 501                 screen->post_dsp_stx = x_res - screen->post_xsize;
 502         }
 503         if(screen->x_mirror == 0){
 504                 post_dsp_hact_st=screen->post_dsp_stx +
 505                         screen->mode.hsync_len+screen->mode.left_margin;
 506                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 507         }else{
 508                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 509                                         screen->post_dsp_stx;
 510                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 511         }
 512         if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){
 513                 post_hsd_en = 1;
 514                 post_h_fac =
 515                         GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize);
 516         }else{
 517                 post_hsd_en = 0;
 518                 post_h_fac = 0x1000;
 519         }
 520
 521
 522         if(screen->post_dsp_sty + screen->post_ysize > y_res){
 523                 dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n",
 524                         screen->post_dsp_sty,screen->post_ysize,y_res);
 525                 screen->post_dsp_sty = y_res - screen->post_ysize;
 526         }
 527
 528         if(screen->y_mirror == 0){
 529                 post_dsp_vact_st = screen->post_dsp_sty +
 530                         screen->mode.vsync_len+screen->mode.upper_margin;
 531                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 532         }else{
 533                 post_dsp_vact_end = v_total - screen->mode.lower_margin -
 534                                         - screen->post_dsp_sty;
 535                 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
 536         }
 537         if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){
 538                 post_vsd_en = 1;
 539                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize);
 540         }else{
 541                 post_vsd_en = 0;
 542                 post_v_fac = 0x1000;
 543         }
 544
 545         if(screen->interlace == 1){
 546                 post_dsp_vact_st_f1  = v_total + post_dsp_vact_st;
 547                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
 548         }else{
 549                 post_dsp_vact_st_f1  = 0;
 550                 post_dsp_vact_end_f1 = 0;
 551         }
 552         DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d,"
 553               "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 554                 screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos,
 555                 post_hsd_en,post_h_fac,post_vsd_en,post_v_fac);
 556         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 557         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 558               v_DSP_HACT_ST_POST(post_dsp_hact_st);
 559         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 560
 561         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 562         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 563               v_DSP_VACT_ST_POST(post_dsp_vact_st);
 564         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 565
 566         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 567         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 568                 v_POST_VS_FACTOR_YRGB(post_v_fac);
 569         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 570
 571         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 572         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 573                 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 574         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 575
 576         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 577         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 578         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 579         return 0;
 580 }
 581
 582 static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 583 {
 584         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 585                                                            struct
 586                                                            lcdc_device,
 587                                                            driver);
 588         struct rk_lcdc_win *win;
 589         u32  colorkey_r,colorkey_g,colorkey_b;
 590         int i,key_val;
 591         for(i=0;i<4;i++){
 592                 win = dev_drv->win[i];
 593                 key_val = win->color_key_val;
 594                 colorkey_r = (key_val & 0xff)<<2;
 595                 colorkey_g = ((key_val>>8)&0xff)<<12;
 596                 colorkey_b = ((key_val>>16)&0xff)<<22;
 597                 /*color key dither 565/888->aaa*/
 598                 key_val = colorkey_r | colorkey_g | colorkey_b;
 599                 switch(i){
 600                 case 0:
 601                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 602                         break;
 603                 case 1:
 604                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 605                         break;
 606                 case 2:
 607                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 608                         break;
 609                 case 3:
 610                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 611                         break;
 612                 default:
 613                         printk(KERN_WARNING "%s:un support win num:%d\n",
 614                                 __func__,i);
 615                         break;
 616                 }
 617         }
 618         return 0;
 619 }
 620
 621 static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id)
 622 {
 623         struct lcdc_device *lcdc_dev =
 624                 container_of(dev_drv, struct lcdc_device, driver);
 625         struct rk_lcdc_win *win = dev_drv->win[win_id];
 626         struct alpha_config alpha_config;
 627
 628         u32 mask, val;
 629         int ppixel_alpha,global_alpha;
 630         u32 src_alpha_ctl,dst_alpha_ctl;
 631         ppixel_alpha = ((win->area[0].format == ARGB888) ||
 632                         (win->area[0].format == ABGR888)) ? 1 : 0;
 633         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 634         alpha_config.src_global_alpha_val = win->g_alpha_val;
 635         win->alpha_mode = AB_SRC_OVER;
 636         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 637                 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/
 638         switch(win->alpha_mode){
 639         case AB_USER_DEFINE:
 640                 break;
 641         case AB_CLEAR:
 642                 alpha_config.src_factor_mode=AA_ZERO;
 643                 alpha_config.dst_factor_mode=AA_ZERO;
 644                 break;
 645         case AB_SRC:
 646                 alpha_config.src_factor_mode=AA_ONE;
 647                 alpha_config.dst_factor_mode=AA_ZERO;
 648                 break;
 649         case AB_DST:
 650                 alpha_config.src_factor_mode=AA_ZERO;
 651                 alpha_config.dst_factor_mode=AA_ONE;
 652                 break;
 653         case AB_SRC_OVER:
 654                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 655                 if(global_alpha)
 656                         alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 657                 else
 658                         alpha_config.src_factor_mode=AA_ONE;
 659                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 660                 break;
 661         case AB_DST_OVER:
 662                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 663                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 664                 alpha_config.dst_factor_mode=AA_ONE;
 665                 break;
 666         case AB_SRC_IN:
 667                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 668                 alpha_config.src_factor_mode=AA_SRC;
 669                 alpha_config.dst_factor_mode=AA_ZERO;
 670                 break;
 671         case AB_DST_IN:
 672                 alpha_config.src_factor_mode=AA_ZERO;
 673                 alpha_config.dst_factor_mode=AA_SRC;
 674                 break;
 675         case AB_SRC_OUT:
 676                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 677                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 678                 alpha_config.dst_factor_mode=AA_ZERO;
 679                 break;
 680         case AB_DST_OUT:
 681                 alpha_config.src_factor_mode=AA_ZERO;
 682                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 683                 break;
 684         case AB_SRC_ATOP:
 685                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 686                 alpha_config.src_factor_mode=AA_SRC;
 687                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 688                 break;
 689         case AB_DST_ATOP:
 690                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 691                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 692                 alpha_config.dst_factor_mode=AA_SRC;
 693                 break;
 694         case XOR:
 695                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 696                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 697                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 698                 break;
 699         case AB_SRC_OVER_GLOBAL:
 700                 alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL;
 701                 alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL;
 702                 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 703                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 704                 break;
 705         default:
 706                 pr_err("alpha mode error\n");
 707                 break;
 708         }
 709         if((ppixel_alpha == 1)&&(global_alpha == 1)){
 710                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 711         }else if(ppixel_alpha == 1){
 712                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 713         }else if(global_alpha == 1){
 714                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 715         }else{
 716                 dev_warn(lcdc_dev->dev,"alpha_en should be 0\n");
 717         }
 718         alpha_config.src_alpha_mode = AA_STRAIGHT;
 719         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 720
 721         switch(win_id){
 722         case 0:
 723                 src_alpha_ctl = 0x60;
 724                 dst_alpha_ctl = 0x64;
 725                 break;
 726         case 1:
 727                 src_alpha_ctl = 0xa0;
 728                 dst_alpha_ctl = 0xa4;
 729                 break;
 730         case 2:
 731                 src_alpha_ctl = 0xdc;
 732                 dst_alpha_ctl = 0xec;
 733                 break;
 734         case 3:
 735                 src_alpha_ctl = 0x12c;
 736                 dst_alpha_ctl = 0x13c;
 737                 break;
 738         }
 739         mask = m_WIN0_DST_FACTOR_M0;
 740         val  = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 741         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 742         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 743                 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 744                 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0|
 745                 m_WIN0_SRC_GLOBAL_ALPHA;
 746         val = v_WIN0_SRC_ALPHA_EN(1) |
 747                 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 748                 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 749                 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 750                 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 751                 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 752                 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 753         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 754
 755         return 0;
 756 }
 757 static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num)
 758 {
 759         struct rk_lcdc_win_area area_temp;
 760         switch(area_num){
 761         case 2:
 762                 area_temp = win->area[0];
 763                 win->area[0] = win->area[1];
 764                 win->area[1] = area_temp;
 765                 break;
 766         case 3:
 767                 area_temp = win->area[0];
 768                 win->area[0] = win->area[2];
 769                 win->area[2] = area_temp;
 770                 break;
 771         case 4:
 772                 area_temp = win->area[0];
 773                 win->area[0] = win->area[3];
 774                 win->area[3] = area_temp;
 775
 776                 area_temp = win->area[1];
 777                 win->area[1] = win->area[2];
 778                 win->area[2] = area_temp;
 779                 break;
 780         default:
 781                 printk(KERN_WARNING "un supported area num!\n");
 782                 break;
 783         }
 784         return 0;
 785 }
 786
 787 static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre,
 788                         struct rk_lcdc_win_area *area_now)
 789 {
 790         if((area_pre->ypos >= area_now->ypos) ||
 791                 (area_pre->ypos+area_pre->ysize > area_now->ypos)){
 792                 area_now->state = 0;
 793                 pr_err("win[%d]:\n"
 794                         "area_pre[%d]:ypos[%d],ysize[%d]\n"
 795                         "area_now[%d]:ypos[%d],ysize[%d]\n",
 796                         win_id,
 797                         area_num-1,area_pre->ypos,area_pre->ysize,
 798                         area_num,  area_now->ypos,area_now->ysize);
 799                 return -EINVAL;
 800         }
 801         return 0;
 802 }
 803
 804 static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 805 {
 806         struct lcdc_device *lcdc_dev =
 807             container_of(dev_drv, struct lcdc_device, driver);
 808         struct rk_lcdc_win *win = dev_drv->win[win_id];
 809         unsigned int mask, val, off;
 810         off = win_id * 0x40;
 811         if((win->win_lb_mode == 5) &&
 812            (dev_drv->version == VOP_FULL_RK3288_V1_0))
 813                 win->win_lb_mode = 4;
 814
 815         if(win->state == 1){
 816                 mask =  m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
 817                         m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_UV_SWAP;
 818                 val  =  v_WIN0_EN(win->state) |
 819                         v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
 820                         v_WIN0_FMT_10(win->fmt_10) |
 821                         v_WIN0_LB_MODE(win->win_lb_mode) |
 822                         v_WIN0_RB_SWAP(win->area[0].swap_rb) |
 823                         v_WIN0_UV_SWAP(win->area[0].swap_uv);
 824                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 825
 826                 mask =  m_WIN0_BIC_COE_SEL |
 827                         m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
 828                         m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
 829                         m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
 830                         m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
 831                         m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
 832                         m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
 833                         m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
 834                 val =   v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
 835                         v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
 836                         v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
 837                         v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
 838                         v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
 839                         v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
 840                         v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
 841                         v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
 842                         v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
 843                         v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
 844                         v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
 845                         v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
 846                         v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
 847                         v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
 848                         v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
 849                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val);
 850
 851                 val =   v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
 852                         v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
 853                 lcdc_writel(lcdc_dev, WIN0_VIR+off, val);
 854                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr);
 855                 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/
 856                 val =   v_WIN0_ACT_WIDTH(win->area[0].xact) |
 857                         v_WIN0_ACT_HEIGHT(win->area[0].yact);
 858                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val);
 859
 860                 val =   v_WIN0_DSP_WIDTH(win->area[0].xsize) |
 861                         v_WIN0_DSP_HEIGHT(win->area[0].ysize);
 862                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val);
 863
 864                 val =   v_WIN0_DSP_XST(win->area[0].dsp_stx) |
 865                         v_WIN0_DSP_YST(win->area[0].dsp_sty);
 866                 lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val);
 867
 868                 val =   v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
 869                         v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
 870                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val);
 871
 872                 val =   v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
 873                         v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
 874                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val);
 875                 if(win->alpha_en == 1)
 876                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
 877                 else{
 878                         mask = m_WIN0_SRC_ALPHA_EN;
 879                         val = v_WIN0_SRC_ALPHA_EN(0);
 880                         lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val);
 881                 }
 882                 /*offset*/
 883         }else{
 884                 mask = m_WIN0_EN;
 885                 val = v_WIN0_EN(win->state);
 886                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 887         }
 888         return 0;
 889 }
 890
 891 static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 892 {
 893         struct lcdc_device *lcdc_dev =
 894             container_of(dev_drv, struct lcdc_device, driver);
 895         struct rk_lcdc_win *win = dev_drv->win[win_id];
 896         struct rk_screen *screen = dev_drv->cur_screen;
 897         unsigned int mask, val, off;
 898         struct fb_info *fb0 = rk_get_fb(0);
 899
 900         off = (win_id-2) * 0x50;
 901         if((screen->y_mirror == 1)&&(win->area_num > 1)){
 902                 rk3288_lcdc_area_swap(win,win->area_num);
 903         }
 904
 905         if(win->state == 1){
 906                 mask =  m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP;
 907                 val  =  v_WIN2_EN(1) |
 908                         v_WIN2_DATA_FMT(win->area[0].fmt_cfg) |
 909                         v_WIN2_RB_SWAP(win->area[0].swap_rb);
 910                 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 911                 /*area 0*/
 912                 if(win->area[0].state == 1){
 913                         mask = m_WIN2_MST0_EN;
 914                         val  = v_WIN2_MST0_EN(win->area[0].state);
 915                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 916
 917                         mask = m_WIN2_VIR_STRIDE0;
 918                         val  = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
 919                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 920
 921                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/
 922                         val  =  v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
 923                                 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
 924                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val);
 925                         val  =  v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
 926                                 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
 927                         lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val);
 928                 }else{
 929                         mask = m_WIN2_MST0_EN;
 930                         val  = v_WIN2_MST0_EN(0);
 931                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 932                         lcdc_writel(lcdc_dev, WIN2_MST0 + off,
 933                                     fb0->fix.smem_start);
 934                 }
 935                 /*area 1*/
 936                 if(win->area[1].state == 1){
 937                         rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]);
 938
 939                         mask = m_WIN2_MST1_EN;
 940                         val  = v_WIN2_MST1_EN(win->area[1].state);
 941                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 942
 943                         mask = m_WIN2_VIR_STRIDE1;
 944                         val  = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
 945                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 946
 947                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/
 948                         val  =  v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
 949                                 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
 950                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val);
 951                         val  =  v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
 952                                 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
 953                         lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val);
 954                 }else{
 955                         mask = m_WIN2_MST1_EN;
 956                         val  = v_WIN2_MST1_EN(0);
 957                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 958                         lcdc_writel(lcdc_dev, WIN2_MST1 + off,
 959                                     fb0->fix.smem_start);
 960                 }
 961                 /*area 2*/
 962                 if(win->area[2].state == 1){
 963                         rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]);
 964
 965                         mask = m_WIN2_MST2_EN;
 966                         val  = v_WIN2_MST2_EN(win->area[2].state);
 967                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 968
 969                         mask = m_WIN2_VIR_STRIDE2;
 970                         val  = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
 971                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 972
 973                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/
 974                         val  =  v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
 975                                 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
 976                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val);
 977                         val  =  v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
 978                                 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
 979                         lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val);
 980                 }else{
 981                         mask = m_WIN2_MST2_EN;
 982                         val  = v_WIN2_MST2_EN(0);
 983                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 984                         lcdc_writel(lcdc_dev, WIN2_MST2 + off,
 985                                     fb0->fix.smem_start);
 986                 }
 987                 /*area 3*/
 988                 if(win->area[3].state == 1){
 989                         rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]);
 990
 991                         mask = m_WIN2_MST3_EN;
 992                         val  = v_WIN2_MST3_EN(win->area[3].state);
 993                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 994
 995                         mask = m_WIN2_VIR_STRIDE3;
 996                         val  = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
 997                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 998
 999                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/
1000                         val  =  v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1001                                 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1002                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val);
1003                         val  =  v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1004                                 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1005                         lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val);
1006                 }else{
1007                         mask = m_WIN2_MST3_EN;
1008                         val  = v_WIN2_MST3_EN(0);
1009                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
1010                         lcdc_writel(lcdc_dev, WIN2_MST3 + off,
1011                                     fb0->fix.smem_start);
1012                 }
1013
1014                 if(win->alpha_en == 1)
1015                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
1016                 else{
1017                         mask = m_WIN2_SRC_ALPHA_EN;
1018                         val = v_WIN2_SRC_ALPHA_EN(0);
1019                         lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val);
1020                 }
1021         }else{
1022                 mask =  m_WIN2_EN | m_WIN2_MST0_EN |
1023                         m_WIN2_MST0_EN | m_WIN2_MST2_EN |
1024                         m_WIN2_MST3_EN;
1025                 val  =  v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1026                         v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) |
1027                         v_WIN2_MST3_EN(0);
1028                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val);
1029         }
1030         return 0;
1031 }
1032
1033 static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
1034 {
1035         struct lcdc_device *lcdc_dev =
1036             container_of(dev_drv, struct lcdc_device, driver);
1037         int timeout;
1038         unsigned long flags;
1039
1040         spin_lock(&lcdc_dev->reg_lock);
1041         if(likely(lcdc_dev->clk_on))
1042         {
1043                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1044                              v_STANDBY_EN(lcdc_dev->standby));
1045                 rk3288_win_0_1_reg_update(dev_drv,0);
1046                 rk3288_win_0_1_reg_update(dev_drv,1);
1047                 rk3288_win_2_3_reg_update(dev_drv,2);
1048                 rk3288_win_2_3_reg_update(dev_drv,3);
1049                 /*rk3288_lcdc_post_cfg(dev_drv);*/
1050                 lcdc_cfg_done(lcdc_dev);
1051         }
1052         spin_unlock(&lcdc_dev->reg_lock);
1053
1054         /*if (dev_drv->wait_fs) {*/
1055         if (0){
1056                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1057                 init_completion(&dev_drv->frame_done);
1058                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1059                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1060                                                       msecs_to_jiffies
1061                                                       (dev_drv->cur_screen->ft +
1062                                                        5));
1063                 if (!timeout && (!dev_drv->frame_done.done)) {
1064                         dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n");
1065                         return -ETIMEDOUT;
1066                 }
1067         }
1068         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1069         return 0;
1070
1071 }
1072
1073 static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1074 {
1075         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc);
1076         return 0;
1077 }
1078 static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1079 {
1080         u32 mask,val;
1081         struct lcdc_device *lcdc_dev =
1082             container_of(dev_drv, struct lcdc_device, driver);
1083
1084         if (unlikely(!lcdc_dev->clk_on)) {
1085                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1086                 return 0;
1087         }
1088 #if defined(CONFIG_ROCKCHIP_IOMMU)
1089         if (dev_drv->iommu_enabled) {
1090                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1091
1092                 if (likely(lcdc_dev->clk_on)) {
1093                         spin_lock(&lcdc_dev->reg_lock);
1094                         mask = m_MMU_EN;
1095                         val = v_MMU_EN(1);
1096                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1097                         mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1098                         val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1);
1099                         lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1100                         spin_unlock(&lcdc_dev->reg_lock);
1101         }
1102                         lcdc_dev->iommu_status = 1;
1103                         rockchip_iovmm_activate(dev_drv->dev);
1104                 }
1105         }
1106 #endif
1107         return 0;
1108 }
1109
1110 static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1111 {
1112 #ifdef CONFIG_RK_FPGA
1113         return 0;
1114 #endif
1115         int ret = 0,fps;
1116         struct lcdc_device *lcdc_dev =
1117             container_of(dev_drv, struct lcdc_device, driver);
1118         struct rk_screen *screen = dev_drv->cur_screen;
1119
1120         if (reset_rate)
1121                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1122         if (ret)
1123                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1124         lcdc_dev->pixclock =
1125                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1126         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1127
1128         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1129         screen->ft = 1000 / fps;
1130         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1131                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1132         return 0;
1133
1134 }
1135
1136 static void rk3288_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1137 {
1138         struct lcdc_device *lcdc_dev =
1139             container_of(dev_drv, struct lcdc_device, driver);
1140         u32 bcsh_color_bar;
1141
1142         if (dev_drv->output_color == COLOR_RGB) {
1143                 bcsh_color_bar = lcdc_readl(lcdc_dev, BCSH_COLOR_BAR);
1144                 if (((bcsh_color_bar & m_BCSH_EN) == 1) ||
1145                     (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1146                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1147                                      m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1148                                      v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
1149                 else
1150                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1151                                      m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1152                                      v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0));
1153         } else {        /* RGB2YUV */
1154                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1155                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1156                              v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(0));
1157         }
1158 }
1159
1160 static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1161                                   u16 *yact, int *format, u32 *dsp_addr)
1162 {
1163         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1164                                                     struct lcdc_device, driver);
1165         u32 val;
1166
1167         spin_lock(&lcdc_dev->reg_lock);
1168
1169         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1170         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1171         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1172
1173         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1174         *format = (val & m_WIN0_DATA_FMT) >> 1;
1175         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1176
1177         spin_unlock(&lcdc_dev->reg_lock);
1178
1179         return 0;
1180 }
1181
1182 static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1183                               int format, u16 xact, u16 yact, u16 xvir)
1184 {
1185         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1186                                                     struct lcdc_device, driver);
1187         u32 val, mask;
1188         int swap = (format == RGB888) ? 1 : 0;
1189
1190         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1191         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1192         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1193
1194         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1195                         v_WIN0_VIR_STRIDE(xvir));
1196         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1197                     v_WIN0_ACT_HEIGHT(yact));
1198
1199         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1200
1201         lcdc_cfg_done(lcdc_dev);
1202
1203         return 0;
1204 }
1205
1206 static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1207 {
1208         u16 face = 0;
1209         u16 dclk_ddr = 0;
1210         u32 v=0;
1211         struct lcdc_device *lcdc_dev =
1212             container_of(dev_drv, struct lcdc_device, driver);
1213         struct rk_screen *screen = dev_drv->cur_screen;
1214         u16 hsync_len = screen->mode.hsync_len;
1215         u16 left_margin = screen->mode.left_margin;
1216         u16 right_margin = screen->mode.right_margin;
1217         u16 vsync_len = screen->mode.vsync_len;
1218         u16 upper_margin = screen->mode.upper_margin;
1219         u16 lower_margin = screen->mode.lower_margin;
1220         u16 x_res = screen->mode.xres;
1221         u16 y_res = screen->mode.yres;
1222         u32 mask, val;
1223         u16 h_total,v_total;
1224         int ret = 0;
1225         int hdmi_dclk_out_en = 0;
1226
1227         if (unlikely(!lcdc_dev->clk_on)) {
1228                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1229                 return 0;
1230         }
1231
1232         h_total = hsync_len + left_margin  + x_res + right_margin;
1233         v_total = vsync_len + upper_margin + y_res + lower_margin;
1234
1235         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1236         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1237         screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200;
1238         screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200;
1239
1240         spin_lock(&lcdc_dev->reg_lock);
1241         if (likely(lcdc_dev->clk_on)) {
1242                 switch (screen->face) {
1243                 case OUT_P565:
1244                         face = OUT_P565;
1245                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1246                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1247                             m_PRE_DITHER_DOWN_EN;
1248                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1249                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1250                             v_PRE_DITHER_DOWN_EN(1);
1251                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1252                         break;
1253                 case OUT_P666:
1254                         face = OUT_P666;
1255                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1256                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1257                             m_PRE_DITHER_DOWN_EN;
1258                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1259                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1260                             v_PRE_DITHER_DOWN_EN(1);
1261                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1262                         break;
1263                 case OUT_D888_P565:
1264                         face = OUT_P888;
1265                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1266                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1267                             m_PRE_DITHER_DOWN_EN;
1268                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1269                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1270                             v_PRE_DITHER_DOWN_EN(1);
1271                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1272                         break;
1273                 case OUT_D888_P666:
1274                         face = OUT_P888;
1275                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1276                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1277                             m_PRE_DITHER_DOWN_EN;
1278                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1279                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1280                             v_PRE_DITHER_DOWN_EN(1);
1281                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1282                         break;
1283                 case OUT_P888:
1284                         face = OUT_P888;
1285                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1286                                 m_PRE_DITHER_DOWN_EN;
1287                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1288                             v_PRE_DITHER_DOWN_EN(1);
1289                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1290                         break;
1291                 case OUT_YUV_420:
1292                         hdmi_dclk_out_en = 1;
1293                         face = OUT_YUV_420;
1294                         dclk_ddr = 1;
1295                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1296                                 m_PRE_DITHER_DOWN_EN;
1297                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1298                             v_PRE_DITHER_DOWN_EN(1);
1299                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1300                         break;
1301                 case OUT_YUV_420_10BIT:
1302                         hdmi_dclk_out_en = 1;
1303                         face = OUT_YUV_420;
1304                         dclk_ddr = 1;
1305                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1306                                 m_PRE_DITHER_DOWN_EN;
1307                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1308                             v_PRE_DITHER_DOWN_EN(0);
1309                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1310                         break;
1311                 case OUT_P101010:
1312                         face = OUT_P101010;
1313                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1314                                 m_PRE_DITHER_DOWN_EN;
1315                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1316                             v_PRE_DITHER_DOWN_EN(0);
1317                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1318                         break;
1319                 default:
1320                         dev_err(lcdc_dev->dev,"un supported interface!\n");
1321                         break;
1322                 }
1323                 switch(screen->type){
1324                 case SCREEN_RGB:
1325                 case SCREEN_LVDS:
1326                 case SCREEN_DUAL_LVDS:
1327                 case SCREEN_LVDS_10BIT:
1328                 case SCREEN_DUAL_LVDS_10BIT:
1329                         mask = m_RGB_OUT_EN;
1330                         val = v_RGB_OUT_EN(1);
1331                         v = 1 << (3+16);
1332                         v |= (lcdc_dev->id << 3);
1333                         break;
1334                 case SCREEN_HDMI:
1335                         if ((screen->face == OUT_P888) ||
1336                             (screen->face == OUT_P101010))
1337                                 face = OUT_P101010;/*RGB 101010 output*/
1338                         mask = m_HDMI_OUT_EN;
1339                         val = v_HDMI_OUT_EN(1);
1340                         break;
1341                 case SCREEN_MIPI:
1342                         mask = m_MIPI_OUT_EN;
1343                         val = v_MIPI_OUT_EN(1);
1344                         break;
1345                 case SCREEN_DUAL_MIPI:
1346                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1347                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1348                         break;
1349                 case SCREEN_EDP:
1350                         face = OUT_P101010;  /*RGB 101010 output*/
1351                         mask = m_EDP_OUT_EN;
1352                         val = v_EDP_OUT_EN(1);
1353                         break;
1354                 }
1355                 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1356                         mask |= m_HDMI_DCLK_OUT_EN;
1357                         val |= v_HDMI_DCLK_OUT_EN(hdmi_dclk_out_en);
1358                 }
1359                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1360 #ifndef CONFIG_RK_FPGA
1361                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1362 #endif
1363                 mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL |
1364                        m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP |
1365                        m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1366                        m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1367                        m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN |
1368                        m_DSP_DCLK_DDR;
1369                 val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) |
1370                       v_DSP_VSYNC_POL(screen->pin_vsync) |
1371                       v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) |
1372                       v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) |
1373                       v_DSP_RG_SWAP(screen->swap_rg) |
1374                       v_DSP_DELTA_SWAP(screen->swap_delta) |
1375                       v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1376                       v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1377                       v_DSP_X_MIR_EN(screen->x_mirror) |
1378                       v_DSP_Y_MIR_EN(screen->y_mirror) |
1379                       v_DSP_DCLK_DDR(dclk_ddr);
1380                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1381
1382                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1383                 val  = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1384                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1385
1386                 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1387                 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1388                 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1389
1390                 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1391                 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1392                     v_DSP_HACT_ST(hsync_len + left_margin);
1393                 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1394
1395                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1396                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1397                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1398
1399                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1400                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1401                     v_DSP_VACT_ST(vsync_len + upper_margin);
1402                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1403
1404                 rk3288_lcdc_post_cfg(dev_drv);
1405                 mask = m_DSP_LINE_FLAG_NUM;
1406                 val = v_DSP_LINE_FLAG_NUM(vsync_len + upper_margin + y_res);
1407                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1408                 dev_drv->output_color = screen->color_mode;
1409                 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1410                         rk3288_lcdc_bcsh_path_sel(dev_drv);
1411                 } else {
1412                         if (dev_drv->output_color != COLOR_RGB) {
1413                                 pr_err("vop ver:%x,unsupport output color:%d\n",
1414                                        dev_drv->version, dev_drv->output_color);
1415                                 ret = -1;
1416                         }
1417                 }
1418         }
1419         spin_unlock(&lcdc_dev->reg_lock);
1420         rk3288_lcdc_set_dclk(dev_drv, 1);
1421         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1422             dev_drv->trsm_ops->enable)
1423                 dev_drv->trsm_ops->enable();
1424         if (screen->init)
1425                 screen->init();
1426
1427         return ret;
1428 }
1429
1430 /*enable layer,open:1,enable;0 disable*/
1431 static int win0_open(struct lcdc_device *lcdc_dev, bool open)
1432 {
1433         spin_lock(&lcdc_dev->reg_lock);
1434         if (likely(lcdc_dev->clk_on)) {
1435                 if (open) {
1436                         if (!lcdc_dev->atv_layer_cnt) {
1437                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1438                                 lcdc_dev->standby = 0;
1439                         }
1440                         lcdc_dev->atv_layer_cnt++;
1441                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1442                         lcdc_dev->atv_layer_cnt--;
1443                 }
1444                 lcdc_dev->driver.win[0]->state = open;
1445                 if (!lcdc_dev->atv_layer_cnt) {
1446                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1447                         lcdc_dev->standby = 1;
1448                 }
1449         }
1450         spin_unlock(&lcdc_dev->reg_lock);
1451
1452         return 0;
1453 }
1454
1455 static int win1_open(struct lcdc_device *lcdc_dev, bool open)
1456 {
1457         spin_lock(&lcdc_dev->reg_lock);
1458         if (likely(lcdc_dev->clk_on)) {
1459                 if (open) {
1460                         if (!lcdc_dev->atv_layer_cnt) {
1461                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1462                                 lcdc_dev->standby = 0;
1463                         }
1464                         lcdc_dev->atv_layer_cnt++;
1465                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1466                         lcdc_dev->atv_layer_cnt--;
1467                 }
1468                 lcdc_dev->driver.win[1]->state = open;
1469
1470                 /*if no layer used,disable lcdc*/
1471                 if (!lcdc_dev->atv_layer_cnt) {
1472                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1473                         lcdc_dev->standby = 1;
1474                 }
1475         }
1476         spin_unlock(&lcdc_dev->reg_lock);
1477
1478         return 0;
1479 }
1480
1481 static int win2_open(struct lcdc_device *lcdc_dev, bool open)
1482 {
1483         spin_lock(&lcdc_dev->reg_lock);
1484         if (likely(lcdc_dev->clk_on)) {
1485                 if (open) {
1486                         if (!lcdc_dev->atv_layer_cnt) {
1487                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1488                                 lcdc_dev->standby = 0;
1489                         }
1490                         lcdc_dev->atv_layer_cnt++;
1491                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1492                         lcdc_dev->atv_layer_cnt--;
1493                 }
1494                 lcdc_dev->driver.win[2]->state = open;
1495
1496                 /*if no layer used,disable lcdc*/
1497                 if (!lcdc_dev->atv_layer_cnt) {
1498                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1499                         lcdc_dev->standby = 1;
1500                 }
1501         }
1502         spin_unlock(&lcdc_dev->reg_lock);
1503
1504         return 0;
1505 }
1506
1507 static int win3_open(struct lcdc_device *lcdc_dev, bool open)
1508 {
1509         spin_lock(&lcdc_dev->reg_lock);
1510         if (likely(lcdc_dev->clk_on)) {
1511                 if (open) {
1512                         if (!lcdc_dev->atv_layer_cnt) {
1513                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1514                                 lcdc_dev->standby = 0;
1515                         }
1516                         lcdc_dev->atv_layer_cnt++;
1517                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1518                         lcdc_dev->atv_layer_cnt--;
1519                 }
1520                 lcdc_dev->driver.win[3]->state = open;
1521
1522                 /*if no layer used,disable lcdc*/
1523                 if (!lcdc_dev->atv_layer_cnt) {
1524                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1525                         lcdc_dev->standby = 1;
1526                 }
1527         }
1528         spin_unlock(&lcdc_dev->reg_lock);
1529
1530         return 0;
1531 }
1532 static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1533 {
1534         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1535                                         struct lcdc_device, driver);
1536         u32 mask,val;
1537
1538         mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR |
1539                             m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR |
1540                             m_BUS_ERROR_INTR_EN;
1541         val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) |
1542             v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0);
1543         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1544 #ifdef LCDC_IRQ_EMPTY_DEBUG
1545                  mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN |
1546                          m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
1547                          m_PWM_GEN_INTR_EN;
1548                  val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) |
1549                          v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) |
1550                          v_PWM_GEN_INTR_EN(1);
1551                  lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
1552 #endif
1553         return 0;
1554 }
1555
1556 static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1557                             bool open)
1558 {
1559         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1560                                         struct lcdc_device, driver);
1561         int sys_status = (dev_drv->id == 0) ?
1562                         SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1563
1564         /*enable clk,when first layer open */
1565         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1566                 rockchip_set_system_status(sys_status);
1567                 rk3288_lcdc_pre_init(dev_drv);
1568                 rk3288_lcdc_clk_enable(lcdc_dev);
1569                 rk3288_lcdc_enable_irq(dev_drv);
1570 #if defined(CONFIG_ROCKCHIP_IOMMU)
1571                 if (dev_drv->iommu_enabled) {
1572                         if (!dev_drv->mmu_dev) {
1573                                 dev_drv->mmu_dev =
1574                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1575                                 if (dev_drv->mmu_dev) {
1576                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1577                                                                   dev_drv->dev);
1578                                 } else {
1579                                         dev_err(dev_drv->dev,
1580                                                 "failed to get rockchip iommu device\n");
1581                                         return -1;
1582                                 }
1583                         }
1584                 }
1585 #endif
1586                 rk3288_lcdc_reg_restore(lcdc_dev);
1587                 /*if (dev_drv->iommu_enabled)
1588                    rk3368_lcdc_mmu_en(dev_drv); */
1589                 if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) {
1590                         rk3288_lcdc_set_dclk(dev_drv, 0);
1591                         /* rk3288_lcdc_enable_irq(dev_drv); */
1592                 } else {
1593                         rk3288_load_screen(dev_drv, 1);
1594                 }
1595                 if (dev_drv->bcsh.enable)
1596                         rk3288_lcdc_set_bcsh(dev_drv, 1);
1597                 spin_lock(&lcdc_dev->reg_lock);
1598                 rk3288_lcdc_set_lut(dev_drv);
1599                 spin_unlock(&lcdc_dev->reg_lock);
1600         }
1601
1602         if (win_id == 0)
1603                 win0_open(lcdc_dev, open);
1604         else if (win_id == 1)
1605                 win1_open(lcdc_dev, open);
1606         else if (win_id == 2)
1607                 win2_open(lcdc_dev, open);
1608         else if (win_id == 3)
1609                 win3_open(lcdc_dev, open);
1610         else
1611                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1612
1613         /* when all layer closed,disable clk */
1614         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1615                 rk3288_lcdc_disable_irq(lcdc_dev);
1616                 rk3288_lcdc_reg_update(dev_drv);
1617 #if defined(CONFIG_ROCKCHIP_IOMMU)
1618                 if (dev_drv->iommu_enabled) {
1619                         if (dev_drv->mmu_dev) {
1620                                 rockchip_iovmm_deactivate(dev_drv->dev);
1621                                 lcdc_dev->iommu_status = 0;
1622                         }
1623                 }
1624 #endif
1625                 rk3288_lcdc_clk_disable(lcdc_dev);
1626                 rockchip_clear_system_status(sys_status);
1627         }
1628
1629         return 0;
1630 }
1631
1632 static int win0_display(struct lcdc_device *lcdc_dev,
1633                         struct rk_lcdc_win *win)
1634 {
1635         u32 y_addr;
1636         u32 uv_addr;
1637         y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/
1638         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1639         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1640             lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset);
1641         spin_lock(&lcdc_dev->reg_lock);
1642         if (likely(lcdc_dev->clk_on)) {
1643                 win->area[0].y_addr = y_addr;
1644                 win->area[0].uv_addr = uv_addr;
1645                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr);
1646                 lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr);
1647                 /*lcdc_cfg_done(lcdc_dev);*/
1648         }
1649         spin_unlock(&lcdc_dev->reg_lock);
1650
1651         return 0;
1652
1653 }
1654
1655 static int win1_display(struct lcdc_device *lcdc_dev,
1656                         struct rk_lcdc_win *win)
1657 {
1658         u32 y_addr;
1659         u32 uv_addr;
1660         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1661         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1662         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",
1663             lcdc_dev->id, __func__, y_addr, uv_addr);
1664
1665         spin_lock(&lcdc_dev->reg_lock);
1666         if (likely(lcdc_dev->clk_on)) {
1667                 win->area[0].y_addr = y_addr;
1668                 win->area[0].uv_addr = uv_addr;
1669                 lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr);
1670                 lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr);
1671         }
1672         spin_unlock(&lcdc_dev->reg_lock);
1673
1674
1675         return 0;
1676 }
1677
1678 static int win2_display(struct lcdc_device *lcdc_dev,
1679                         struct rk_lcdc_win *win)
1680 {
1681         u32 i,y_addr;
1682         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1683         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1684             lcdc_dev->id, __func__, y_addr);
1685
1686         spin_lock(&lcdc_dev->reg_lock);
1687         if (likely(lcdc_dev->clk_on)){
1688                 for(i=0;i<win->area_num;i++)
1689                         win->area[i].y_addr =
1690                                 win->area[i].smem_start + win->area[i].y_offset;
1691                         if (win->area[0].state)
1692                                 lcdc_writel(lcdc_dev, WIN2_MST0,
1693                                             win->area[0].y_addr);
1694                         if (win->area[1].state)
1695                                 lcdc_writel(lcdc_dev, WIN2_MST1,
1696                                             win->area[1].y_addr);
1697                         if (win->area[2].state)
1698                                 lcdc_writel(lcdc_dev, WIN2_MST2,
1699                                             win->area[2].y_addr);
1700                         if (win->area[3].state)
1701                                 lcdc_writel(lcdc_dev, WIN2_MST3,
1702                                             win->area[3].y_addr);
1703         }
1704         spin_unlock(&lcdc_dev->reg_lock);
1705         return 0;
1706 }
1707
1708 static int win3_display(struct lcdc_device *lcdc_dev,
1709                         struct rk_lcdc_win *win)
1710 {
1711         u32 i,y_addr;
1712         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1713         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1714             lcdc_dev->id, __func__, y_addr);
1715
1716         spin_lock(&lcdc_dev->reg_lock);
1717         if (likely(lcdc_dev->clk_on)){
1718                 for(i=0;i<win->area_num;i++)
1719                         win->area[i].y_addr =
1720                                 win->area[i].smem_start + win->area[i].y_offset;
1721                         if (win->area[0].state)
1722                                 lcdc_writel(lcdc_dev, WIN3_MST0,
1723                                             win->area[0].y_addr);
1724                         if (win->area[1].state)
1725                                 lcdc_writel(lcdc_dev, WIN3_MST1,
1726                                             win->area[1].y_addr);
1727                         if (win->area[2].state)
1728                                 lcdc_writel(lcdc_dev, WIN3_MST2,
1729                                             win->area[2].y_addr);
1730                         if (win->area[3].state)
1731                                 lcdc_writel(lcdc_dev, WIN3_MST3,
1732                                             win->area[3].y_addr);
1733                 }
1734         spin_unlock(&lcdc_dev->reg_lock);
1735         return 0;
1736 }
1737
1738 static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1739 {
1740         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1741                                 struct lcdc_device, driver);
1742         struct rk_lcdc_win *win = NULL;
1743         struct rk_screen *screen = dev_drv->cur_screen;
1744
1745 #if defined(WAIT_FOR_SYNC)
1746         int timeout;
1747         unsigned long flags;
1748 #endif
1749         win = dev_drv->win[win_id];
1750         if (!screen) {
1751                 dev_err(dev_drv->dev, "screen is null!\n");
1752                 return -ENOENT;
1753         }
1754         if(win_id == 0){
1755                 win0_display(lcdc_dev, win);
1756         }else if(win_id == 1){
1757                 win1_display(lcdc_dev, win);
1758         }else if(win_id == 2){
1759                 win2_display(lcdc_dev, win);
1760         }else if(win_id == 3){
1761                 win3_display(lcdc_dev, win);
1762         }else{
1763                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1764                 return -EINVAL;
1765         }
1766
1767         /*this is the first frame of the system ,enable frame start interrupt */
1768         if ((dev_drv->first_frame)) {
1769                 dev_drv->first_frame = 0;
1770                 rk3288_lcdc_enable_irq(dev_drv);
1771         }
1772 #if defined(WAIT_FOR_SYNC)
1773         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1774         init_completion(&dev_drv->frame_done);
1775         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1776         timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1777                                               msecs_to_jiffies(dev_drv->
1778                                                                cur_screen->ft +
1779                                                                5));
1780         if (!timeout && (!dev_drv->frame_done.done)) {
1781                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
1782                 return -ETIMEDOUT;
1783         }
1784 #endif
1785         return 0;
1786 }
1787
1788 static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
1789 {
1790         u16 srcW;
1791         u16 srcH;
1792         u16 dstW;
1793         u16 dstH;
1794         u16 yrgb_srcW;
1795         u16 yrgb_srcH;
1796         u16 yrgb_dstW;
1797         u16 yrgb_dstH;
1798         u32 yrgb_vScaleDnMult;
1799         u32 yrgb_xscl_factor;
1800         u32 yrgb_yscl_factor;
1801         u8  yrgb_vsd_bil_gt2=0;
1802         u8  yrgb_vsd_bil_gt4=0;
1803
1804         u16 cbcr_srcW;
1805         u16 cbcr_srcH;
1806         u16 cbcr_dstW;
1807         u16 cbcr_dstH;
1808         u32 cbcr_vScaleDnMult;
1809         u32 cbcr_xscl_factor;
1810         u32 cbcr_yscl_factor;
1811         u8  cbcr_vsd_bil_gt2=0;
1812         u8  cbcr_vsd_bil_gt4=0;
1813         u8  yuv_fmt=0;
1814
1815
1816         srcW = win->area[0].xact;
1817         srcH = win->area[0].yact;
1818         dstW = win->area[0].xsize;
1819         dstH = win->area[0].ysize;
1820
1821         /*yrgb scl mode*/
1822         yrgb_srcW = srcW;
1823         yrgb_srcH = srcH;
1824         yrgb_dstW = dstW;
1825         yrgb_dstH = dstH;
1826         if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) {
1827                 pr_err("ERROR: yrgb scale exceed 8,"
1828                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1829                        yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH);
1830         }
1831         if(yrgb_srcW < yrgb_dstW){
1832                 win->yrgb_hor_scl_mode = SCALE_UP;
1833         }else if(yrgb_srcW > yrgb_dstW){
1834                 win->yrgb_hor_scl_mode = SCALE_DOWN;
1835         }else{
1836                 win->yrgb_hor_scl_mode = SCALE_NONE;
1837         }
1838
1839         if(yrgb_srcH < yrgb_dstH){
1840                 win->yrgb_ver_scl_mode = SCALE_UP;
1841         }else if (yrgb_srcH  > yrgb_dstH){
1842                 win->yrgb_ver_scl_mode = SCALE_DOWN;
1843         }else{
1844                 win->yrgb_ver_scl_mode = SCALE_NONE;
1845         }
1846
1847         /*cbcr scl mode*/
1848         switch (win->area[0].format) {
1849         case YUV422:
1850         case YUV422_A:
1851                 cbcr_srcW = srcW/2;
1852                 cbcr_dstW = dstW;
1853                 cbcr_srcH = srcH;
1854                 cbcr_dstH = dstH;
1855                 yuv_fmt = 1;
1856                 break;
1857         case YUV420:
1858         case YUV420_A:
1859                 cbcr_srcW = srcW/2;
1860                 cbcr_dstW = dstW;
1861                 cbcr_srcH = srcH/2;
1862                 cbcr_dstH = dstH;
1863                 yuv_fmt = 1;
1864                 break;
1865         case YUV444:
1866         case YUV444_A:
1867                 cbcr_srcW = srcW;
1868                 cbcr_dstW = dstW;
1869                 cbcr_srcH = srcH;
1870                 cbcr_dstH = dstH;
1871                 yuv_fmt = 1;
1872                 break;
1873         default:
1874                 cbcr_srcW = 0;
1875                 cbcr_dstW = 0;
1876                 cbcr_srcH = 0;
1877                 cbcr_dstH = 0;
1878                 yuv_fmt = 0;
1879                 break;
1880         }
1881         if (yuv_fmt) {
1882                 if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) {
1883                         pr_err("ERROR: cbcr scale exceed 8,"
1884                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1885                        cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH);
1886                 }
1887         }
1888
1889         if(cbcr_srcW < cbcr_dstW){
1890                 win->cbr_hor_scl_mode = SCALE_UP;
1891         }else if(cbcr_srcW > cbcr_dstW){
1892                 win->cbr_hor_scl_mode = SCALE_DOWN;
1893         }else{
1894                 win->cbr_hor_scl_mode = SCALE_NONE;
1895         }
1896
1897         if(cbcr_srcH < cbcr_dstH){
1898                 win->cbr_ver_scl_mode = SCALE_UP;
1899         }else if(cbcr_srcH > cbcr_dstH){
1900                 win->cbr_ver_scl_mode = SCALE_DOWN;
1901         }else{
1902                 win->cbr_ver_scl_mode = SCALE_NONE;
1903         }
1904         DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
1905                "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1906                "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1907                 ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW,
1908                 yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode,
1909                 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH,
1910                 win->cbr_hor_scl_mode,win->cbr_ver_scl_mode);
1911
1912     /*line buffer mode*/
1913         if ((win->area[0].format == YUV422) ||
1914             (win->area[0].format == YUV420) ||
1915             (win->area[0].format == YUV422_A) ||
1916             (win->area[0].format == YUV420_A)) {
1917                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1918                         if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) {
1919                                 pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW);
1920                         } else if (cbcr_dstW > 2560) {
1921                                 win->win_lb_mode = LB_RGB_3840X2;
1922                         } else if (cbcr_dstW > 1920) {
1923                                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1924                                         if(yrgb_dstW > 3840){
1925                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1926                                         }else if(yrgb_dstW > 2560){
1927                                                 win->win_lb_mode = LB_RGB_3840X2;
1928                                         }else if(yrgb_dstW > 1920){
1929                                                 win->win_lb_mode = LB_RGB_2560X4;
1930                                         }else{
1931                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1932                                         }
1933                                 }
1934                         } else if (cbcr_dstW > 1280) {
1935                                 win->win_lb_mode = LB_YUV_3840X5;
1936                         } else {
1937                                 win->win_lb_mode = LB_YUV_2560X8;
1938                         }
1939                 } else { /*SCALE_UP or SCALE_NONE*/
1940                         if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) {
1941                                 pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW);
1942                         }else if(cbcr_srcW > 2560){
1943                                 win->win_lb_mode = LB_RGB_3840X2;
1944                         }else if(cbcr_srcW > 1920){
1945                                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1946                                         if(yrgb_dstW > 3840){
1947                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1948                                         }else if(yrgb_dstW > 2560){
1949                                                 win->win_lb_mode = LB_RGB_3840X2;
1950                                         }else if(yrgb_dstW > 1920){
1951                                                 win->win_lb_mode = LB_RGB_2560X4;
1952                                         }else{
1953                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1954                                         }
1955                                 }
1956                         }else if(cbcr_srcW > 1280){
1957                                  win->win_lb_mode = LB_YUV_3840X5;
1958                         }else{
1959                                 win->win_lb_mode = LB_YUV_2560X8;
1960                         }
1961                 }
1962         }else {
1963                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1964                         if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) {
1965                                 pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW);
1966                         }else if(yrgb_dstW > 2560){
1967                                 win->win_lb_mode = LB_RGB_3840X2;
1968                         }else if(yrgb_dstW > 1920){
1969                                 win->win_lb_mode = LB_RGB_2560X4;
1970                         }else if(yrgb_dstW > 1280){
1971                                 win->win_lb_mode = LB_RGB_1920X5;
1972                         }else{
1973                                 win->win_lb_mode = LB_RGB_1280X8;
1974                         }
1975                 }else{ /*SCALE_UP or SCALE_NONE*/
1976                         if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) {
1977                                 pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW);
1978                         }else if(yrgb_srcW > 2560){
1979                                 win->win_lb_mode = LB_RGB_3840X2;
1980                         }else if(yrgb_srcW > 1920){
1981                                 win->win_lb_mode = LB_RGB_2560X4;
1982                         }else if(yrgb_srcW > 1280){
1983                                 win->win_lb_mode = LB_RGB_1920X5;
1984                         }else{
1985                                 win->win_lb_mode = LB_RGB_1280X8;
1986                         }
1987                 }
1988         }
1989         DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode);
1990
1991         /*vsd/vsu scale ALGORITHM*/
1992         win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1993         win->cbr_hsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
1994         win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1995         win->cbr_vsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
1996         switch(win->win_lb_mode){
1997             case LB_YUV_3840X5:
1998             case LB_YUV_2560X8:
1999             case LB_RGB_1920X5:
2000             case LB_RGB_1280X8:
2001                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2002                 win->cbr_vsu_mode  = SCALE_UP_BIC;
2003                 break;
2004             case LB_RGB_3840X2:
2005                 if(win->yrgb_ver_scl_mode != SCALE_NONE) {
2006                     pr_err("ERROR : not allow yrgb ver scale\n");
2007                 }
2008                 if(win->cbr_ver_scl_mode != SCALE_NONE) {
2009                     pr_err("ERROR : not allow cbcr ver scale\n");
2010                 }
2011                 break;
2012             case LB_RGB_2560X4:
2013                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2014                 win->cbr_vsu_mode  = SCALE_UP_BIL;
2015                 break;
2016             default:
2017                 printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n",
2018                         __func__,win->win_lb_mode);
2019                 break;
2020         }
2021         DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2022                win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode,
2023                win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode);
2024
2025         /*SCALE FACTOR*/
2026
2027         /*(1.1)YRGB HOR SCALE FACTOR*/
2028         switch(win->yrgb_hor_scl_mode){
2029         case SCALE_NONE:
2030                 yrgb_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2031                 break;
2032         case SCALE_UP  :
2033                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2034                 break;
2035         case SCALE_DOWN:
2036                 switch(win->yrgb_hsd_mode)
2037                 {
2038                 case SCALE_DOWN_BIL:
2039                         yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2040                         break;
2041                 case SCALE_DOWN_AVG:
2042                         yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2043                         break;
2044                 default :
2045                         printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n",
2046                                 __func__,win->yrgb_hsd_mode);
2047                         break;
2048                 }
2049                 break;
2050         default :
2051                 printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n",
2052                                 __func__,win->yrgb_hor_scl_mode);
2053             break;
2054         } /*win->yrgb_hor_scl_mode*/
2055
2056         /*(1.2)YRGB VER SCALE FACTOR*/
2057         switch(win->yrgb_ver_scl_mode)
2058         {
2059         case SCALE_NONE:
2060                 yrgb_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2061                  break;
2062         case SCALE_UP  :
2063                 switch(win->yrgb_vsu_mode)
2064                 {
2065                 case SCALE_UP_BIL:
2066                         yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2067                         break;
2068                 case SCALE_UP_BIC:
2069                         if(yrgb_srcH < 3){
2070                                 pr_err("yrgb_srcH should be greater than 3 !!!\n");
2071                         }
2072                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH);
2073                         break;
2074                 default :
2075                         printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n",
2076                                 __func__,win->yrgb_vsu_mode);
2077                         break;
2078             }
2079             break;
2080         case SCALE_DOWN:
2081                 switch(win->yrgb_vsd_mode)
2082                 {
2083                 case SCALE_DOWN_BIL:
2084                         yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH);
2085                         yrgb_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult);
2086                         if(yrgb_vScaleDnMult == 4){
2087                                 yrgb_vsd_bil_gt4 = 1;
2088                                 yrgb_vsd_bil_gt2 = 0;
2089                         }else if(yrgb_vScaleDnMult == 2){
2090                                 yrgb_vsd_bil_gt4 = 0;
2091                                 yrgb_vsd_bil_gt2 = 1;
2092                         }else{
2093                                 yrgb_vsd_bil_gt4 = 0;
2094                                 yrgb_vsd_bil_gt2 = 0;
2095                         }
2096                         break;
2097                 case SCALE_DOWN_AVG:
2098                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH);
2099                         break;
2100                 default:
2101                         printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n",
2102                                 __func__,win->yrgb_vsd_mode);
2103                         break;
2104                 } /*win->yrgb_vsd_mode*/
2105                 break;
2106         default :
2107                 printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n",
2108                         __func__,win->yrgb_ver_scl_mode);
2109                 break;
2110         }
2111         win->scale_yrgb_x = yrgb_xscl_factor;
2112         win->scale_yrgb_y = yrgb_yscl_factor;
2113         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2114         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2115         DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor,
2116                 yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2);
2117
2118         /*(2.1)CBCR HOR SCALE FACTOR*/
2119         switch(win->cbr_hor_scl_mode)
2120         {
2121         case SCALE_NONE:
2122                 cbcr_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2123                 break;
2124         case SCALE_UP  :
2125                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2126                 break;
2127         case SCALE_DOWN:
2128                 switch(win->cbr_hsd_mode)
2129                 {
2130                 case SCALE_DOWN_BIL:
2131                         cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2132                         break;
2133                 case SCALE_DOWN_AVG:
2134                         cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2135                         break;
2136                 default :
2137                         printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n",
2138                                 __func__,win->cbr_hsd_mode);
2139                         break;
2140                 }
2141                 break;
2142         default :
2143                 printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n",
2144                         __func__,win->cbr_hor_scl_mode);
2145                 break;
2146         } /*win->cbr_hor_scl_mode*/
2147
2148         /*(2.2)CBCR VER SCALE FACTOR*/
2149         switch(win->cbr_ver_scl_mode)
2150         {
2151         case SCALE_NONE:
2152                 cbcr_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2153                 break;
2154         case SCALE_UP  :
2155                 switch(win->cbr_vsu_mode)
2156                 {
2157                 case SCALE_UP_BIL:
2158                         cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2159                         break;
2160                 case SCALE_UP_BIC:
2161                         if(cbcr_srcH < 3) {
2162                                 pr_err("cbcr_srcH should be greater than 3 !!!\n");
2163                         }
2164                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH);
2165                         break;
2166                 default :
2167                         printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n",
2168                                 __func__,win->cbr_vsu_mode);
2169                         break;
2170                 }
2171                 break;
2172         case SCALE_DOWN:
2173                 switch(win->cbr_vsd_mode)
2174                 {
2175                 case SCALE_DOWN_BIL:
2176                         cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH);
2177                         cbcr_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult);
2178                         if(cbcr_vScaleDnMult == 4){
2179                                 cbcr_vsd_bil_gt4 = 1;
2180                                 cbcr_vsd_bil_gt2 = 0;
2181                         }else if(cbcr_vScaleDnMult == 2){
2182                                 cbcr_vsd_bil_gt4 = 0;
2183                                 cbcr_vsd_bil_gt2 = 1;
2184                         }else{
2185                                 cbcr_vsd_bil_gt4 = 0;
2186                                 cbcr_vsd_bil_gt2 = 0;
2187                         }
2188                         break;
2189                 case SCALE_DOWN_AVG:
2190                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH);
2191                         break;
2192                 default :
2193                         printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n",
2194                                 __func__,win->cbr_vsd_mode);
2195                     break;
2196                 }
2197                 break;
2198         default :
2199                 printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n",
2200                         __func__,win->cbr_ver_scl_mode);
2201                 break;
2202         }
2203         win->scale_cbcr_x = cbcr_xscl_factor;
2204         win->scale_cbcr_y = cbcr_yscl_factor;
2205         win->vsd_cbr_gt4  = cbcr_vsd_bil_gt4;
2206         win->vsd_cbr_gt2  = cbcr_vsd_bil_gt2;
2207
2208         DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor,
2209                 cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2);
2210         return 0;
2211 }
2212
2213
2214
2215 static int win0_set_par(struct lcdc_device *lcdc_dev,
2216                         struct rk_screen *screen, struct rk_lcdc_win *win)
2217 {
2218         u32 xact,yact,xvir, yvir,xpos, ypos;
2219         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2220         char fmt[9] = "NULL";
2221
2222         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2223         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2224
2225         spin_lock(&lcdc_dev->reg_lock);
2226         if(likely(lcdc_dev->clk_on)){
2227                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2228                 switch (win->area[0].format) {
2229                 case ARGB888:
2230                         fmt_cfg = 0;
2231                         swap_rb = 0;
2232                         win->fmt_10 = 0;
2233                         break;
2234                 case XBGR888:
2235                 case ABGR888:
2236                         fmt_cfg = 0;
2237                         swap_rb = 1;
2238                         win->fmt_10 = 0;
2239                         break;
2240                 case RGB888:
2241                         fmt_cfg = 1;
2242                         swap_rb = 0;
2243                         win->fmt_10 = 0;
2244                         break;
2245                 case RGB565:
2246                         fmt_cfg = 2;
2247                         swap_rb = 0;
2248                         win->fmt_10 = 0;
2249                         break;
2250                 case YUV422:
2251                         fmt_cfg = 5;
2252                         swap_rb = 0;
2253                         win->fmt_10 = 0;
2254                         break;
2255                 case YUV420:
2256                         fmt_cfg = 4;
2257                         swap_rb = 0;
2258                         win->fmt_10 = 0;
2259                         break;
2260                 case YUV420_NV21:
2261                         fmt_cfg = 4;
2262                         swap_rb = 0;
2263                         swap_uv = 1;
2264                         win->fmt_10 = 0;
2265                         break;
2266                 case YUV444:
2267                         fmt_cfg = 6;
2268                         swap_rb = 0;
2269                         win->fmt_10 = 0;
2270                 case YUV422_A:
2271                         fmt_cfg = 5;
2272                         swap_rb = 0;
2273                         win->fmt_10 = 1;
2274                         break;
2275                 case YUV420_A:
2276                         fmt_cfg = 4;
2277                         swap_rb = 0;
2278                         win->fmt_10 = 1;
2279                         break;
2280                 case YUV444_A:
2281                         fmt_cfg = 6;
2282                         swap_rb = 0;
2283                         win->fmt_10 = 1;
2284                         break;
2285                 default:
2286                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2287                                 __func__);
2288                         break;
2289                 }
2290                 win->area[0].fmt_cfg = fmt_cfg;
2291                 win->area[0].swap_rb = swap_rb;
2292                 win->area[0].dsp_stx = xpos;
2293                 win->area[0].dsp_sty = ypos;
2294                 win->area[0].swap_uv = swap_uv;
2295                 xact = win->area[0].xact;
2296                 yact = win->area[0].yact;
2297                 xvir = win->area[0].xvir;
2298                 yvir = win->area[0].yvir;
2299         }
2300         rk3288_win_0_1_reg_update(&lcdc_dev->driver,0);
2301         spin_unlock(&lcdc_dev->reg_lock);
2302
2303         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2304                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2305                 __func__, get_format_string(win->area[0].format, fmt), xact,
2306                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2307         return 0;
2308
2309 }
2310
2311 static int win1_set_par(struct lcdc_device *lcdc_dev,
2312                         struct rk_screen *screen, struct rk_lcdc_win *win)
2313 {
2314         u32 xact, yact, xvir, yvir, xpos, ypos;
2315         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2316         char fmt[9] = "NULL";
2317
2318         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2319         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2320
2321         spin_lock(&lcdc_dev->reg_lock);
2322         if (likely(lcdc_dev->clk_on)) {
2323                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2324                 switch (win->area[0].format) {
2325                 case ARGB888:
2326                         fmt_cfg = 0;
2327                         swap_rb = 0;
2328                         win->fmt_10 = 0;
2329                         break;
2330                 case XBGR888:
2331                 case ABGR888:
2332                         fmt_cfg = 0;
2333                         swap_rb = 1;
2334                         win->fmt_10 = 0;
2335                         break;
2336                 case RGB888:
2337                         fmt_cfg = 1;
2338                         swap_rb = 0;
2339                         win->fmt_10 = 0;
2340                         break;
2341                 case RGB565:
2342                         fmt_cfg = 2;
2343                         swap_rb = 0;
2344                         win->fmt_10 = 0;
2345                         break;
2346                 case YUV422:
2347                         fmt_cfg = 5;
2348                         swap_rb = 0;
2349                         win->fmt_10 = 0;
2350                         break;
2351                 case YUV420:
2352                         fmt_cfg = 4;
2353                         swap_rb = 0;
2354                         win->fmt_10 = 0;
2355                         break;
2356                 case YUV420_NV21:
2357                         fmt_cfg = 4;
2358                         swap_rb = 0;
2359                         swap_uv = 1;
2360                         win->fmt_10 = 0;
2361                         break;
2362                 case YUV444:
2363                         fmt_cfg = 6;
2364                         swap_rb = 0;
2365                         win->fmt_10 = 0;
2366                         break;
2367                 case YUV422_A:
2368                         fmt_cfg = 5;
2369                         swap_rb = 0;
2370                         win->fmt_10 = 1;
2371                         break;
2372                 case YUV420_A:
2373                         fmt_cfg = 4;
2374                         swap_rb = 0;
2375                         win->fmt_10 = 1;
2376                         break;
2377                 case YUV444_A:
2378                         fmt_cfg = 6;
2379                         swap_rb = 0;
2380                         win->fmt_10 = 1;
2381                         break;
2382                 default:
2383                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2384                                 __func__);
2385                         break;
2386                 }
2387                 win->area[0].fmt_cfg = fmt_cfg;
2388                 win->area[0].swap_rb = swap_rb;
2389                 win->area[0].dsp_stx = xpos;
2390                 win->area[0].dsp_sty = ypos;
2391                 win->area[0].swap_uv = swap_uv;
2392                 xact = win->area[0].xact;
2393                 yact = win->area[0].yact;
2394                 xvir = win->area[0].xvir;
2395                 yvir = win->area[0].yvir;
2396         }
2397         rk3288_win_0_1_reg_update(&lcdc_dev->driver,1);
2398         spin_unlock(&lcdc_dev->reg_lock);
2399
2400         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2401                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2402                 __func__, get_format_string(win->area[0].format, fmt), xact,
2403                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2404         return 0;
2405
2406 }
2407
2408 static int win2_set_par(struct lcdc_device *lcdc_dev,
2409                         struct rk_screen *screen, struct rk_lcdc_win *win)
2410 {
2411         int i;
2412         u8 fmt_cfg, swap_rb;
2413
2414         spin_lock(&lcdc_dev->reg_lock);
2415         if (likely(lcdc_dev->clk_on)) {
2416                 for (i = 0; i < win->area_num; i++) {
2417                         switch (win->area[i].format) {
2418                         case ARGB888:
2419                                 fmt_cfg = 0;
2420                                 swap_rb = 0;
2421                                 break;
2422                         case XBGR888:
2423                         case ABGR888:
2424                                 fmt_cfg = 0;
2425                                 swap_rb = 1;
2426                                 break;
2427                         case RGB888:
2428                                 fmt_cfg = 1;
2429                                 swap_rb = 0;
2430                                 break;
2431                         case RGB565:
2432                                 fmt_cfg = 2;
2433                                 swap_rb = 0;
2434                                 break;
2435                         default:
2436                                 dev_err(lcdc_dev->driver.dev,
2437                                         "%s:un supported format!\n",
2438                                         __func__);
2439                                 break;
2440                         }
2441                         win->area[i].fmt_cfg = fmt_cfg;
2442                         win->area[i].swap_rb = swap_rb;
2443                         win->area[i].dsp_stx = win->area[i].xpos +
2444                                 screen->mode.left_margin +
2445                                 screen->mode.hsync_len;
2446                         if (screen->y_mirror == 1) {
2447                                 win->area[i].dsp_sty = screen->mode.yres -
2448                                         win->area[i].ypos -
2449                                         win->area[i].ysize +
2450                                         screen->mode.upper_margin +
2451                                         screen->mode.vsync_len;
2452                         } else {
2453                                 win->area[i].dsp_sty = win->area[i].ypos +
2454                                         screen->mode.upper_margin +
2455                                         screen->mode.vsync_len;
2456                         }
2457                         if ((win->area[i].xact != win->area[i].xsize) ||
2458                             (win->area[i].yact != win->area[i].ysize)) {
2459                                 pr_err("win[%d]->area[%d],not support scale\n",
2460                                         win->id, i);
2461                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2462                                         win->area[i].xact,win->area[i].yact,
2463                                         win->area[i].xsize,win->area[i].ysize);
2464                                 win->area[i].xsize = win->area[i].xact;
2465                                 win->area[i].ysize = win->area[i].yact;
2466                         }
2467                 }
2468         }
2469         rk3288_win_2_3_reg_update(&lcdc_dev->driver,2);
2470         spin_unlock(&lcdc_dev->reg_lock);
2471         return 0;
2472 }
2473
2474 static int win3_set_par(struct lcdc_device *lcdc_dev,
2475                         struct rk_screen *screen, struct rk_lcdc_win *win)
2476
2477 {
2478         int i;
2479         u8 fmt_cfg, swap_rb;
2480
2481         spin_lock(&lcdc_dev->reg_lock);
2482         if (likely(lcdc_dev->clk_on)) {
2483                 for (i = 0; i < win->area_num; i++) {
2484                         switch (win->area[i].format) {
2485                         case ARGB888:
2486                                 fmt_cfg = 0;
2487                                 swap_rb = 0;
2488                                 break;
2489                         case XBGR888:
2490                         case ABGR888:
2491                                 fmt_cfg = 0;
2492                                 swap_rb = 1;
2493                                 break;
2494                         case RGB888:
2495                                 fmt_cfg = 1;
2496                                 swap_rb = 0;
2497                                 break;
2498                         case RGB565:
2499                                 fmt_cfg = 2;
2500                                 swap_rb = 0;
2501                                 break;
2502                         default:
2503                                 dev_err(lcdc_dev->driver.dev,
2504                                         "%s:un supported format!\n",
2505                                         __func__);
2506                                 break;
2507                         }
2508                         win->area[i].fmt_cfg = fmt_cfg;
2509                         win->area[i].swap_rb = swap_rb;
2510                         win->area[i].dsp_stx = win->area[i].xpos +
2511                                 screen->mode.left_margin +
2512                                 screen->mode.hsync_len;
2513                         if (screen->y_mirror == 1) {
2514                                 win->area[i].dsp_sty = screen->mode.yres -
2515                                         win->area[i].ypos -
2516                                         win->area[i].ysize +
2517                                         screen->mode.upper_margin +
2518                                         screen->mode.vsync_len;
2519                         } else {
2520                                 win->area[i].dsp_sty = win->area[i].ypos +
2521                                         screen->mode.upper_margin +
2522                                         screen->mode.vsync_len;
2523                         }
2524                         if ((win->area[i].xact != win->area[i].xsize) ||
2525                             (win->area[i].yact != win->area[i].ysize)) {
2526                                 pr_err("win[%d]->area[%d],not support scale\n",
2527                                        win->id, i);
2528                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2529                                        win->area[i].xact, win->area[i].yact,
2530                                        win->area[i].xsize, win->area[i].ysize);
2531                                 win->area[i].xsize = win->area[i].xact;
2532                                 win->area[i].ysize = win->area[i].yact;
2533                         }
2534                 }
2535         }
2536         rk3288_win_2_3_reg_update(&lcdc_dev->driver,3);
2537         spin_unlock(&lcdc_dev->reg_lock);
2538         return 0;
2539 }
2540
2541 static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id)
2542 {
2543         struct lcdc_device *lcdc_dev =
2544             container_of(dev_drv, struct lcdc_device, driver);
2545         struct rk_lcdc_win *win = NULL;
2546         struct rk_screen *screen = dev_drv->cur_screen;
2547         win = dev_drv->win[win_id];
2548
2549         switch(win_id)
2550         {
2551         case 0:
2552                 win0_set_par(lcdc_dev, screen, win);
2553                 break;
2554         case 1:
2555                 win1_set_par(lcdc_dev, screen, win);
2556                 break;
2557         case 2:
2558                 win2_set_par(lcdc_dev, screen, win);
2559                 break;
2560         case 3:
2561                 win3_set_par(lcdc_dev, screen, win);
2562                 break;
2563         default:
2564                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2565                 break;
2566         }
2567         return 0;
2568 }
2569
2570 static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2571                              unsigned long arg, int win_id)
2572 {
2573         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2574                                                            struct
2575                                                            lcdc_device,
2576                                                            driver);
2577         u32 panel_size[2];
2578         void __user *argp = (void __user *)arg;
2579         struct color_key_cfg clr_key_cfg;
2580
2581         switch (cmd) {
2582         case RK_FBIOGET_PANEL_SIZE:
2583                 panel_size[0] = lcdc_dev->screen->mode.xres;
2584                 panel_size[1] = lcdc_dev->screen->mode.yres;
2585                 if (copy_to_user(argp, panel_size, 8))
2586                         return -EFAULT;
2587                 break;
2588         case RK_FBIOPUT_COLOR_KEY_CFG:
2589                 if (copy_from_user(&clr_key_cfg, argp,
2590                                    sizeof(struct color_key_cfg)))
2591                         return -EFAULT;
2592                 rk3288_lcdc_clr_key_cfg(dev_drv);
2593                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2594                             clr_key_cfg.win0_color_key_cfg);
2595                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2596                             clr_key_cfg.win1_color_key_cfg);
2597                 break;
2598
2599         default:
2600                 break;
2601         }
2602         return 0;
2603 }
2604
2605 static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2606 {
2607         u32 reg;
2608         struct lcdc_device *lcdc_dev =
2609             container_of(dev_drv, struct lcdc_device, driver);
2610         if (dev_drv->suspend_flag)
2611                 return 0;
2612
2613         dev_drv->suspend_flag = 1;
2614         flush_kthread_worker(&dev_drv->update_regs_worker);
2615
2616         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4)
2617                         lcdc_readl(lcdc_dev, reg);
2618         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2619                 dev_drv->trsm_ops->disable();
2620
2621         spin_lock(&lcdc_dev->reg_lock);
2622         if (likely(lcdc_dev->clk_on)) {
2623                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2624                                         v_DSP_BLANK_EN(1));
2625                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR,
2626                                         v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1));
2627                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2628                                         v_DSP_OUT_ZERO(1));
2629                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2630                                         v_STANDBY_EN(1));
2631                 lcdc_cfg_done(lcdc_dev);
2632
2633                 if (dev_drv->iommu_enabled) {
2634                         if (dev_drv->mmu_dev)
2635                                 rockchip_iovmm_deactivate(dev_drv->dev);
2636                 }
2637
2638                 spin_unlock(&lcdc_dev->reg_lock);
2639         } else {
2640                 spin_unlock(&lcdc_dev->reg_lock);
2641                 return 0;
2642         }
2643         rk3288_lcdc_clk_disable(lcdc_dev);
2644         rk_disp_pwr_disable(dev_drv);
2645         return 0;
2646 }
2647
2648 static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2649 {
2650         struct lcdc_device *lcdc_dev =
2651             container_of(dev_drv, struct lcdc_device, driver);
2652
2653         if (!dev_drv->suspend_flag)
2654                 return 0;
2655         rk_disp_pwr_enable(dev_drv);
2656         dev_drv->suspend_flag = 0;
2657
2658         if (lcdc_dev->atv_layer_cnt) {
2659                 rk3288_lcdc_clk_enable(lcdc_dev);
2660                 rk3288_lcdc_reg_restore(lcdc_dev);
2661
2662                 spin_lock(&lcdc_dev->reg_lock);
2663                 rk3288_lcdc_set_lut(dev_drv);
2664
2665                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2666                              v_DSP_OUT_ZERO(0));
2667                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2668                              v_STANDBY_EN(0));
2669                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2670                                         v_DSP_BLANK_EN(0));
2671                 lcdc_cfg_done(lcdc_dev);
2672
2673                 if (dev_drv->iommu_enabled) {
2674                         if (dev_drv->mmu_dev)
2675                                 rockchip_iovmm_activate(dev_drv->dev);
2676                 }
2677
2678                 spin_unlock(&lcdc_dev->reg_lock);
2679         }
2680
2681         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2682                 dev_drv->trsm_ops->enable();
2683
2684         return 0;
2685 }
2686
2687 static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2688                              int win_id, int blank_mode)
2689 {
2690         switch (blank_mode) {
2691         case FB_BLANK_UNBLANK:
2692                 rk3288_lcdc_early_resume(dev_drv);
2693                 break;
2694         case FB_BLANK_NORMAL:
2695                 rk3288_lcdc_early_suspend(dev_drv);
2696                 break;
2697         default:
2698                 rk3288_lcdc_early_suspend(dev_drv);
2699                 break;
2700         }
2701
2702         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2703
2704         return 0;
2705 }
2706
2707 static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
2708                                            int win_id, int area_id)
2709 {
2710         struct lcdc_device *lcdc_dev =
2711             container_of(dev_drv, struct lcdc_device, driver);
2712         u32 win_ctrl = 0;
2713         u32 area_status = 0;
2714
2715         switch (win_id) {
2716         case 0:
2717                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2718                 area_status = win_ctrl & m_WIN0_EN;
2719                 break;
2720         case 1:
2721                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2722                 area_status = win_ctrl & m_WIN1_EN;
2723                 break;
2724         case 2:
2725                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2726                 if (area_id == 0)
2727                         area_status = win_ctrl & m_WIN2_MST0_EN;
2728                 if (area_id == 1)
2729                         area_status = win_ctrl & m_WIN2_MST1_EN;
2730                 if (area_id == 2)
2731                         area_status = win_ctrl & m_WIN2_MST2_EN;
2732                 if (area_id == 3)
2733                         area_status = win_ctrl & m_WIN2_MST3_EN;
2734                 break;
2735         case 3:
2736                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
2737                 if (area_id == 0)
2738                         area_status = win_ctrl & m_WIN3_MST0_EN;
2739                 if (area_id == 1)
2740                         area_status = win_ctrl & m_WIN3_MST1_EN;
2741                 if (area_id == 2)
2742                         area_status = win_ctrl & m_WIN3_MST2_EN;
2743                 if (area_id == 3)
2744                         area_status = win_ctrl & m_WIN3_MST3_EN;
2745                 break;
2746         case 4:
2747                 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
2748                 area_status = win_ctrl & m_HWC_EN;
2749                 break;
2750         default:
2751                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id);
2752                 break;
2753         }
2754         return area_status;
2755 }
2756
2757 static int rk3288_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
2758                                            unsigned int *area_support)
2759 {
2760         area_support[0] = 1;
2761         area_support[1] = 1;
2762         area_support[2] = 4;
2763         area_support[3] = 4;
2764
2765         return 0;
2766 }
2767
2768 /*overlay will be do at regupdate*/
2769 static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2770                                bool set)
2771 {
2772         struct lcdc_device *lcdc_dev =
2773             container_of(dev_drv, struct lcdc_device, driver);
2774         struct rk_lcdc_win *win = NULL;
2775         int i,ovl;
2776         unsigned int mask, val;
2777         int z_order_num=0;
2778         int layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2779         if(swap == 0){
2780                 for(i=0;i<4;i++){
2781                         win = dev_drv->win[i];
2782                         if(win->state == 1){
2783                                 z_order_num++;
2784                         }
2785                 }
2786                 for(i=0;i<4;i++){
2787                         win = dev_drv->win[i];
2788                         if(win->state == 0)
2789                                 win->z_order = z_order_num++;
2790                         switch(win->z_order){
2791                         case 0:
2792                                 layer0_sel = win->id;
2793                                 break;
2794                         case 1:
2795                                 layer1_sel = win->id;
2796                                 break;
2797                         case 2:
2798                                 layer2_sel = win->id;
2799                                 break;
2800                         case 3:
2801                                 layer3_sel = win->id;
2802                                 break;
2803                         default:
2804                                 break;
2805                         }
2806                 }
2807         }else{
2808                 layer0_sel = swap %10;;
2809                 layer1_sel = swap /10 % 10;
2810                 layer2_sel = swap / 100 %10;
2811                 layer3_sel = swap / 1000;
2812         }
2813
2814         spin_lock(&lcdc_dev->reg_lock);
2815         if(lcdc_dev->clk_on){
2816                 if(set){
2817                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
2818                                 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
2819                         val  = v_DSP_LAYER0_SEL(layer0_sel) |
2820                                 v_DSP_LAYER1_SEL(layer1_sel) |
2821                                 v_DSP_LAYER2_SEL(layer2_sel) |
2822                                 v_DSP_LAYER3_SEL(layer3_sel);
2823                         lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val);
2824                 }else{
2825                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL);
2826                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL);
2827                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL);
2828                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL);
2829                         ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel;
2830                 }
2831         }else{
2832                 ovl = -EPERM;
2833         }
2834         spin_unlock(&lcdc_dev->reg_lock);
2835
2836         return ovl;
2837 }
2838
2839 static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2840                                          char *buf, int win_id)
2841 {
2842         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2843                                                            struct
2844                                                            lcdc_device,
2845                                                            driver);
2846         struct rk_screen *screen = dev_drv->cur_screen;
2847         u16 hsync_len = screen->mode.hsync_len;
2848         u16 left_margin = screen->mode.left_margin;
2849         u16 vsync_len = screen->mode.vsync_len;
2850         u16 upper_margin = screen->mode.upper_margin;
2851         u32 h_pw_bp = hsync_len + left_margin;
2852         u32 v_pw_bp = vsync_len + upper_margin;
2853         u32 fmt_id;
2854         char format_w0[9] = "NULL";
2855         char format_w1[9] = "NULL";
2856         char format_w2[9] = "NULL";
2857         char format_w3[9] = "NULL";
2858         u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor;
2859         u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2860         u8 w0_state,w1_state,w2_state,w3_state;
2861         u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state;
2862         u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state;
2863
2864         u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp;
2865         u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp;
2866         u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac;
2867         u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac;
2868
2869         u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y;
2870         u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x;
2871         u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y;
2872         u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp;
2873         u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp;
2874
2875         u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y;
2876         u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x;
2877         u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y;
2878         u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp;
2879         u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp;
2880         u32 dclk_freq;
2881
2882         dclk_freq = screen->mode.pixclock;
2883         /*rk3288_lcdc_reg_dump(dev_drv);*/
2884
2885         spin_lock(&lcdc_dev->reg_lock);
2886         if (lcdc_dev->clk_on) {
2887                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
2888                 layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8;
2889                 layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10;
2890                 layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12;
2891                 layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14;
2892                 /*WIN0*/
2893                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2894                 w0_state = win_ctrl & m_WIN0_EN;
2895                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1;
2896                 switch (fmt_id) {
2897                 case 0:
2898                         strcpy(format_w0, "ARGB888");
2899                         break;
2900                 case 1:
2901                         strcpy(format_w0, "RGB888");
2902                         break;
2903                 case 2:
2904                         strcpy(format_w0, "RGB565");
2905                         break;
2906                 case 4:
2907                         strcpy(format_w0, "YCbCr420");
2908                         break;
2909                 case 5:
2910                         strcpy(format_w0, "YCbCr422");
2911                         break;
2912                 case 6:
2913                         strcpy(format_w0, "YCbCr444");
2914                         break;
2915                 default:
2916                         strcpy(format_w0, "invalid\n");
2917                         break;
2918                 }
2919                 vir_info = lcdc_readl(lcdc_dev,WIN0_VIR);
2920                 act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
2921                 dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
2922                 dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
2923                 y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
2924                 uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR);
2925                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
2926                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16;
2927                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1;
2928                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1;
2929                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1;
2930                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1;
2931                 if (w0_state) {
2932                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
2933                         w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16;
2934                 }
2935                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
2936                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16;
2937                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
2938                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16;
2939
2940                 /*WIN1*/
2941                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2942                 w1_state = win_ctrl & m_WIN1_EN;
2943                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1;
2944                 switch (fmt_id) {
2945                 case 0:
2946                         strcpy(format_w1, "ARGB888");
2947                         break;
2948                 case 1:
2949                         strcpy(format_w1, "RGB888");
2950                         break;
2951                 case 2:
2952                         strcpy(format_w1, "RGB565");
2953                         break;
2954                 case 4:
2955                         strcpy(format_w1, "YCbCr420");
2956                         break;
2957                 case 5:
2958                         strcpy(format_w1, "YCbCr422");
2959                         break;
2960                 case 6:
2961                         strcpy(format_w1, "YCbCr444");
2962                         break;
2963                 default:
2964                         strcpy(format_w1, "invalid\n");
2965                         break;
2966                 }
2967                 vir_info = lcdc_readl(lcdc_dev,WIN1_VIR);
2968                 act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO);
2969                 dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
2970                 dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
2971                 y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB);
2972                 uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR);
2973                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
2974                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16;
2975                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1;
2976                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1;
2977                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1;
2978                 w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1;
2979                 if (w1_state) {
2980                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
2981                         w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16;
2982                 }
2983                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
2984                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16;
2985                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
2986                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16;
2987                 /*WIN2*/
2988                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2989                 w2_state = win_ctrl & m_WIN2_EN;
2990                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4;
2991                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5;
2992                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6;
2993                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7;
2994                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1);
2995                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
2996                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16;
2997                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3);
2998                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
2999                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16;
3000                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1;
3001                 switch (fmt_id) {
3002                 case 0:
3003                         strcpy(format_w2, "ARGB888");
3004                         break;
3005                 case 1:
3006                         strcpy(format_w2, "RGB888");
3007                         break;
3008                 case 2:
3009                         strcpy(format_w2, "RGB565");
3010                         break;
3011                 case 4:
3012                         strcpy(format_w2,"8bpp");
3013                         break;
3014                 case 5:
3015                         strcpy(format_w2,"4bpp");
3016                         break;
3017                 case 6:
3018                         strcpy(format_w2,"2bpp");
3019                         break;
3020                 case 7:
3021                         strcpy(format_w2,"1bpp");
3022                         break;
3023                 default:
3024                         strcpy(format_w2, "invalid\n");
3025                         break;
3026                 }
3027                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0);
3028                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0);
3029                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1;
3030                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1;
3031                 if (w2_0_state) {
3032                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3033                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16;
3034                 }
3035                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1);
3036                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1);
3037                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1;
3038                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1;
3039                 if (w2_1_state) {
3040                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3041                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16;
3042                 }
3043                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2);
3044                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2);
3045                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1;
3046                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1;
3047                 if (w2_2_state) {
3048                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3049                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16;
3050                 }
3051                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3);
3052                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3);
3053                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1;
3054                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1;
3055                 if (w2_3_state) {
3056                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3057                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16;
3058                 }
3059
3060                 /*WIN3*/
3061                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3062                 w3_state = win_ctrl & m_WIN3_EN;
3063                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4;
3064                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5;
3065                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6;
3066                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7;
3067                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1);
3068                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3069                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16;
3070                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3);
3071                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3072                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16;
3073                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1;
3074                 switch (fmt_id) {
3075                 case 0:
3076                         strcpy(format_w3, "ARGB888");
3077                         break;
3078                 case 1:
3079                         strcpy(format_w3, "RGB888");
3080                         break;
3081                 case 2:
3082                         strcpy(format_w3, "RGB565");
3083                         break;
3084                 case 4:
3085                         strcpy(format_w3,"8bpp");
3086                         break;
3087                 case 5:
3088                         strcpy(format_w3,"4bpp");
3089                         break;
3090                 case 6:
3091                         strcpy(format_w3,"2bpp");
3092                         break;
3093                 case 7:
3094                         strcpy(format_w3,"1bpp");
3095                         break;
3096                 default:
3097                         strcpy(format_w3, "invalid");
3098                         break;
3099                 }
3100                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0);
3101                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0);
3102                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1;
3103                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1;
3104                 if (w3_0_state) {
3105                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3106                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16;
3107                 }
3108
3109                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1);
3110                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1);
3111                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1;
3112                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1;
3113                 if (w3_1_state) {
3114                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3115                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16;
3116                 }
3117
3118                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2);
3119                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2);
3120                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1;
3121                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1;
3122                 if (w3_2_state) {
3123                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3124                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16;
3125                 }
3126
3127                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3);
3128                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3);
3129                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1;
3130                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1;
3131                 if (w3_3_state) {
3132                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3133                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16;
3134                 }
3135
3136         } else {
3137                 spin_unlock(&lcdc_dev->reg_lock);
3138                 return -EPERM;
3139         }
3140         spin_unlock(&lcdc_dev->reg_lock);
3141         return snprintf(buf, PAGE_SIZE,
3142                         "z-order:\n"
3143                         "  layer3_sel_win[%d]\n"
3144                         "  layer2_sel_win[%d]\n"
3145                         "  layer1_sel_win[%d]\n"
3146                         "  layer0_sel_win[%d]\n"
3147                         "win0:\n"
3148                         "  state:%d, "
3149                         "  fmt:%s, "
3150                         "  y_vir:%d, "
3151                         "  uv_vir:%d\n"
3152                         "  xact:%4d, "
3153                         "  yact:%4d, "
3154                         "  dsp_x:%4d, "
3155                         "  dsp_y:%4d, "
3156                         "  x_st:%4d, "
3157                         "  y_st:%4d\n"
3158                         "  y_h_fac:%8d, "
3159                         "  y_v_fac:%8d, "
3160                         "  uv_h_fac:%8d, "
3161                         "  uv_v_fac:%8d\n"
3162                         "  y_addr: 0x%08x, "
3163                         "  uv_addr:0x%08x\n"
3164                         "win1:\n"
3165                         "  state:%d, "
3166                         "  fmt:%s, "
3167                         "  y_vir:%d, "
3168                         "  uv_vir:%d\n"
3169                         "  xact:%4d, "
3170                         "  yact:%4d, "
3171                         "  dsp_x:%4d, "
3172                         "  dsp_y:%4d, "
3173                         "  x_st:%4d, "
3174                         "  y_st:%4d\n"
3175                         "  y_h_fac:%8d, "
3176                         "  y_v_fac:%8d, "
3177                         "  uv_h_fac:%8d, "
3178                         "  uv_v_fac:%8d\n"
3179                         "  y_addr: 0x%08x, "
3180                         "  uv_addr:0x%08x\n"
3181                         "win2:\n"
3182                         "  state:%d\n"
3183                         "  fmt:%s\n"
3184                         "  area0:"
3185                         "  state:%d,"
3186                         "  y_vir:%4d,"
3187                         "  dsp_x:%4d,"
3188                         "  dsp_y:%4d,"
3189                         "  x_st:%4d,"
3190                         "  y_st:%4d,"
3191                         "  addr:0x%08x\n"
3192                         "  area1:"
3193                         "  state:%d,"
3194                         "  y_vir:%4d,"
3195                         "  dsp_x:%4d,"
3196                         "  dsp_y:%4d,"
3197                         "  x_st:%4d,"
3198                         "  y_st:%4d,"
3199                         "  addr:0x%08x\n"
3200                         "  area2:"
3201                         "  state:%d,"
3202                         "  y_vir:%4d,"
3203                         "  dsp_x:%4d,"
3204                         "  dsp_y:%4d,"
3205                         "  x_st:%4d,"
3206                         "  y_st:%4d,"
3207                         "  addr:0x%08x\n"
3208                         "  area3:"
3209                         "  state:%d,"
3210                         "  y_vir:%4d,"
3211                         "  dsp_x:%4d,"
3212                         "  dsp_y:%4d,"
3213                         "  x_st:%4d,"
3214                         "  y_st:%4d,"
3215                         "  addr:0x%08x\n"
3216                         "win3:\n"
3217                         "  state:%d\n"
3218                         "  fmt:%s\n"
3219                         "  area0:"
3220                         "  state:%d,"
3221                         "  y_vir:%4d,"
3222                         "  dsp_x:%4d,"
3223                         "  dsp_y:%4d,"
3224                         "  x_st:%4d,"
3225                         "  y_st:%4d,"
3226                         "  addr:0x%08x\n"
3227                         "  area1:"
3228                         "  state:%d,"
3229                         "  y_vir:%4d,"
3230                         "  dsp_x:%4d,"
3231                         "  dsp_y:%4d,"
3232                         "  x_st:%4d,"
3233                         "  y_st:%4d "
3234                         "  addr:0x%08x\n"
3235                         "  area2:"
3236                         "  state:%d,"
3237                         "  y_vir:%4d,"
3238                         "  dsp_x:%4d,"
3239                         "  dsp_y:%4d,"
3240                         "  x_st:%4d,"
3241                         "  y_st:%4d,"
3242                         "  addr:0x%08x\n"
3243                         "  area3:"
3244                         "  state:%d,"
3245                         "  y_vir:%4d,"
3246                         "  dsp_x:%4d,"
3247                         "  dsp_y:%4d,"
3248                         "  x_st:%4d,"
3249                         "  y_st:%4d,"
3250                         "  addr:0x%08x\n",
3251                         layer3_sel,layer2_sel,layer1_sel,layer0_sel,
3252                         w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,
3253                         w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,
3254                         w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3255                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
3256
3257                         w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,
3258                         w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,
3259                         w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3260                         lcdc_readl(lcdc_dev, WIN1_CBR_MST),
3261
3262                         w2_state,format_w2,
3263                         w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y,
3264                         w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0),
3265
3266                         w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y,
3267                         w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1),
3268
3269                         w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y,
3270                         w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2),
3271
3272                         w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y,
3273                         w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3),
3274
3275                         w3_state,format_w3,
3276                         w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y,
3277                         w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0),
3278
3279                         w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y,
3280                         w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1),
3281
3282                         w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y,
3283                         w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2),
3284
3285                         w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y,
3286                         w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3)
3287         );
3288
3289 }
3290
3291 static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3292                                bool set)
3293 {
3294         struct lcdc_device *lcdc_dev =
3295             container_of(dev_drv, struct lcdc_device, driver);
3296         struct rk_screen *screen = dev_drv->cur_screen;
3297         u64 ft = 0;
3298         u32 dotclk;
3299         int ret;
3300         u32 pixclock;
3301         u32 x_total, y_total;
3302         if (set) {
3303                 if (fps == 0) {
3304                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3305                         return 0;
3306                 }
3307                 ft = div_u64(1000000000000llu, fps);
3308                 x_total =
3309                     screen->mode.upper_margin + screen->mode.lower_margin +
3310                     screen->mode.yres + screen->mode.vsync_len;
3311                 y_total =
3312                     screen->mode.left_margin + screen->mode.right_margin +
3313                     screen->mode.xres + screen->mode.hsync_len;
3314                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3315                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3316                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3317         }
3318
3319         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3320         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
3321         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3322         screen->ft = 1000 / fps;        /*one frame time in ms */
3323
3324         if (set)
3325                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3326                          clk_get_rate(lcdc_dev->dclk), fps);
3327
3328         return fps;
3329 }
3330
3331 static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3332 {
3333         mutex_lock(&dev_drv->fb_win_id_mutex);
3334         if (order == FB_DEFAULT_ORDER)
3335                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3;
3336         dev_drv->fb3_win_id = order / 1000;
3337         dev_drv->fb2_win_id = (order / 100) % 10;
3338         dev_drv->fb1_win_id = (order / 10) % 10;
3339         dev_drv->fb0_win_id = order % 10;
3340         mutex_unlock(&dev_drv->fb_win_id_mutex);
3341
3342         return 0;
3343 }
3344
3345 static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3346                                   const char *id)
3347 {
3348         int win_id = 0;
3349         mutex_lock(&dev_drv->fb_win_id_mutex);
3350         if (!strcmp(id, "fb0") || !strcmp(id, "fb4"))
3351                 win_id = dev_drv->fb0_win_id;
3352         else if (!strcmp(id, "fb1") || !strcmp(id, "fb5"))
3353                 win_id = dev_drv->fb1_win_id;
3354         else if (!strcmp(id, "fb2") || !strcmp(id, "fb6"))
3355                 win_id = dev_drv->fb2_win_id;
3356         else if (!strcmp(id, "fb3") || !strcmp(id, "fb7"))
3357                 win_id = dev_drv->fb3_win_id;
3358         mutex_unlock(&dev_drv->fb_win_id_mutex);
3359
3360         return win_id;
3361 }
3362
3363 static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3364 {
3365         int i,j;
3366         int __iomem *c;
3367         int v, r, g, b;
3368         int ret = 0;
3369
3370         struct lcdc_device *lcdc_dev =
3371             container_of(dev_drv, struct lcdc_device, driver);
3372         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3373         lcdc_cfg_done(lcdc_dev);
3374         mdelay(25);
3375         if (dev_drv->cur_screen->dsp_lut) {
3376                 for (i = 0; i < 256; i++) {
3377                         v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
3378                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3379                         b = (v & 0xff) << 2;
3380                         g = (v & 0xff00) << 4;
3381                         r = (v & 0xff0000) << 6;
3382                         v = r + g + b;
3383                         for (j = 0; j < 4; j++) {
3384                                 writel_relaxed(v, c);
3385                                 v += (1 + (1 << 10) + (1 << 20)) ;
3386                                 c++;
3387                         }
3388                 }
3389         } else {
3390                 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3391                 ret = -1;
3392         }
3393
3394         do{
3395                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
3396                 lcdc_cfg_done(lcdc_dev);
3397         }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN));
3398         return ret;
3399 }
3400
3401 static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3402 {
3403         struct lcdc_device *lcdc_dev =
3404             container_of(dev_drv, struct lcdc_device, driver);
3405         int i;
3406         unsigned int mask, val;
3407         struct rk_lcdc_win *win = NULL;
3408         struct fb_info *fb0 = rk_get_fb(0);
3409
3410         spin_lock(&lcdc_dev->reg_lock);
3411         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3412                              v_STANDBY_EN(lcdc_dev->standby));
3413         for (i=0;i<4;i++) {
3414                 win = dev_drv->win[i];
3415                 if ((win->state == 0)&&(win->last_state == 1)) {
3416                         switch (win->id) {
3417                         case 0:
3418                                 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3419                                         lcdc_writel(lcdc_dev, WIN0_CTRL1, 0x0);
3420                                 mask =  m_WIN0_EN;
3421                                 val  =  v_WIN0_EN(0);
3422                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val);
3423                                 break;
3424                         case 1:
3425                                 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3426                                         lcdc_writel(lcdc_dev, WIN1_CTRL1, 0x0);
3427                                 mask =  m_WIN1_EN;
3428                                 val  =  v_WIN1_EN(0);
3429                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val);
3430                                 break;
3431                         case 2:
3432                                 mask =  m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN |
3433                                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3434                                 val  =  v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) |
3435                                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3436                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val);
3437                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO0,0);
3438                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO1,0);
3439                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO2,0);
3440                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO3,0);
3441                                 lcdc_writel(lcdc_dev,WIN2_MST0, fb0->fix.smem_start);
3442                                 lcdc_writel(lcdc_dev,WIN2_MST1, fb0->fix.smem_start);
3443                                 lcdc_writel(lcdc_dev,WIN2_MST2, fb0->fix.smem_start);
3444                                 lcdc_writel(lcdc_dev,WIN2_MST3, fb0->fix.smem_start);
3445                                 break;
3446                         case 3:
3447                                 mask =  m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN |
3448                                         m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3449                                 val  =  v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |  v_WIN3_MST1_EN(0) |
3450                                         v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3451                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val);
3452                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO0,0);
3453                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO1,0);
3454                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO2,0);
3455                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO3,0);
3456                                 lcdc_writel(lcdc_dev,WIN3_MST0, fb0->fix.smem_start);
3457                                 lcdc_writel(lcdc_dev,WIN3_MST1, fb0->fix.smem_start);
3458                                 lcdc_writel(lcdc_dev,WIN3_MST2, fb0->fix.smem_start);
3459                                 lcdc_writel(lcdc_dev,WIN3_MST3, fb0->fix.smem_start);
3460                                 break;
3461                         default:
3462                                 break;
3463                         }
3464                 }
3465                 win->last_state = win->state;
3466         }
3467         lcdc_cfg_done(lcdc_dev);
3468         spin_unlock(&lcdc_dev->reg_lock);
3469         return 0;
3470 }
3471
3472
3473 static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3474 {
3475         struct lcdc_device *lcdc_dev =
3476             container_of(dev_drv, struct lcdc_device, driver);
3477         spin_lock(&lcdc_dev->reg_lock);
3478         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3479                      v_DIRECT_PATH_EN(open));
3480         lcdc_cfg_done(lcdc_dev);
3481         spin_unlock(&lcdc_dev->reg_lock);
3482         return 0;
3483 }
3484
3485 static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3486 {
3487         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3488                                         struct lcdc_device, driver);
3489         spin_lock(&lcdc_dev->reg_lock);
3490         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3491                      v_DIRECT_PATCH_SEL(win_id));
3492         lcdc_cfg_done(lcdc_dev);
3493         spin_unlock(&lcdc_dev->reg_lock);
3494         return 0;
3495
3496 }
3497
3498 static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3499 {
3500         struct lcdc_device *lcdc_dev =
3501             container_of(dev_drv, struct lcdc_device, driver);
3502         int ovl;
3503         spin_lock(&lcdc_dev->reg_lock);
3504         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3505         spin_unlock(&lcdc_dev->reg_lock);
3506         return ovl;
3507 }
3508 static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable)
3509 {
3510        struct lcdc_device *lcdc_dev =
3511                                 container_of(dev_drv,struct lcdc_device,driver);
3512        if (enable)
3513                enable_irq(lcdc_dev->irq);
3514        else
3515                disable_irq(lcdc_dev->irq);
3516        return 0;
3517 }
3518
3519 int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3520 {
3521         struct lcdc_device *lcdc_dev =
3522             container_of(dev_drv, struct lcdc_device, driver);
3523         u32 int_reg;
3524         int ret;
3525
3526         if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){
3527                 int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3528                 if (int_reg & m_LINE_FLAG_INTR_STS) {
3529                         lcdc_dev->driver.frame_time.last_framedone_t =
3530                                         lcdc_dev->driver.frame_time.framedone_t;
3531                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3532                         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3533                                      v_LINE_FLAG_INTR_CLR(1));
3534                         ret = RK_LF_STATUS_FC;
3535                 } else
3536                         ret = RK_LF_STATUS_FR;
3537         } else {
3538                 ret = RK_LF_STATUS_NC;
3539         }
3540
3541         return ret;
3542 }
3543
3544 static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3545                                     unsigned int dsp_addr[][4])
3546 {
3547         struct lcdc_device *lcdc_dev =
3548             container_of(dev_drv, struct lcdc_device, driver);
3549         spin_lock(&lcdc_dev->reg_lock);
3550         if (lcdc_dev->clk_on) {
3551                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3552                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3553                 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
3554                 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
3555                 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
3556                 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
3557                 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
3558                 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
3559                 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
3560                 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
3561         }
3562         spin_unlock(&lcdc_dev->reg_lock);
3563         return 0;
3564 }
3565
3566 static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
3567                                     int mode, int calc, int up,
3568                                     int down, int global)
3569 {
3570         struct lcdc_device *lcdc_dev =
3571             container_of(dev_drv, struct lcdc_device, driver);
3572         struct rk_screen *screen = dev_drv->cur_screen;
3573         u32 total_pixel, calc_pixel, stage_up, stage_down;
3574         u32 pixel_num, global_dn;
3575         u32 mask = 0, val = 0;
3576
3577         if (dev_drv->version != VOP_FULL_RK3288_V1_1) {
3578                 pr_err("vop version:%x, not supoort cabc\n", dev_drv->version);
3579                 return 0;
3580         }
3581         if (!screen->cabc_lut) {
3582                 pr_err("screen cabc lut not config, so not open cabc\n");
3583                 return 0;
3584         }
3585         dev_drv->cabc_mode = mode;
3586         if (!dev_drv->cabc_mode) {
3587                 spin_lock(&lcdc_dev->reg_lock);
3588                 if (lcdc_dev->clk_on) {
3589                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3590                                      m_CABC_HANDLE_EN | m_CABC_EN,
3591                                      v_CABC_EN(0) | v_CABC_HANDLE_EN(0));
3592                         lcdc_cfg_done(lcdc_dev);
3593                 }
3594                 pr_info("mode = 0, close cabc\n");
3595                 spin_unlock(&lcdc_dev->reg_lock);
3596                 return 0;
3597         }
3598
3599         total_pixel = screen->mode.xres * screen->mode.yres;
3600         pixel_num = 1000 - calc;
3601         calc_pixel = (total_pixel * pixel_num) / 1000;
3602         stage_up = up;
3603         stage_down = down;
3604         global_dn = global;
3605         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
3606                 mode, calc, stage_up, stage_down, global_dn);
3607
3608         spin_lock(&lcdc_dev->reg_lock);
3609         if (lcdc_dev->clk_on) {
3610                 mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE |
3611                         m_CABC_CALC_PIXEL_NUM;
3612                 val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) |
3613                         v_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
3614                         v_CABC_CALC_PIXEL_NUM(calc_pixel);
3615                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3616
3617                 mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM;
3618                 val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3619                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3620
3621                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP |
3622                         m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE |
3623                         m_MAX_SCALE_CFG_ENABLE;
3624                 val = v_CABC_STAGE_DOWN(stage_down) |
3625                         v_CABC_STAGE_UP(stage_up) |
3626                         v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) |
3627                         v_MAX_SCALE_CFG_ENABLE(0);
3628                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3629
3630                 mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN;
3631                 val = v_CABC_GLOBAL_DN(global_dn) |
3632                         v_CABC_GLOBAL_DN_LIMIT_EN(1);
3633                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3634                 lcdc_cfg_done(lcdc_dev);
3635         }
3636         spin_unlock(&lcdc_dev->reg_lock);
3637
3638         return 0;
3639 }
3640
3641 /*
3642         a:[-30~0]:
3643             sin_hue = sin(a)*256 +0x100;
3644             cos_hue = cos(a)*256;
3645         a:[0~30]
3646             sin_hue = sin(a)*256;
3647             cos_hue = cos(a)*256;
3648 */
3649 static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode)
3650 {
3651
3652         struct lcdc_device *lcdc_dev =
3653             container_of(dev_drv, struct lcdc_device, driver);
3654         u32 val;
3655
3656         spin_lock(&lcdc_dev->reg_lock);
3657         if (lcdc_dev->clk_on) {
3658                 val = lcdc_readl(lcdc_dev, BCSH_H);
3659                 switch(mode){
3660                 case H_SIN:
3661                         val &= m_BCSH_SIN_HUE;
3662                         break;
3663                 case H_COS:
3664                         val &= m_BCSH_COS_HUE;
3665                         val >>= 16;
3666                         break;
3667                 default:
3668                         break;
3669                 }
3670         }
3671         spin_unlock(&lcdc_dev->reg_lock);
3672
3673         return val;
3674 }
3675
3676
3677 static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue)
3678 {
3679
3680         struct lcdc_device *lcdc_dev =
3681             container_of(dev_drv, struct lcdc_device, driver);
3682         u32 mask, val;
3683
3684         spin_lock(&lcdc_dev->reg_lock);
3685         if (lcdc_dev->clk_on) {
3686                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3687                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3688                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3689                 lcdc_cfg_done(lcdc_dev);
3690         }
3691         spin_unlock(&lcdc_dev->reg_lock);
3692
3693         return 0;
3694 }
3695
3696 static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value)
3697 {
3698         struct lcdc_device *lcdc_dev =
3699             container_of(dev_drv, struct lcdc_device, driver);
3700         u32 mask, val;
3701
3702         spin_lock(&lcdc_dev->reg_lock);
3703         if(lcdc_dev->clk_on) {
3704                 switch (mode) {
3705                 case BRIGHTNESS:
3706                 /*from 0 to 255,typical is 128*/
3707                         if (value < 0x80)
3708                                 value += 0x80;
3709                         else if (value >= 0x80)
3710                                 value = value - 0x80;
3711                         mask =  m_BCSH_BRIGHTNESS;
3712                         val = v_BCSH_BRIGHTNESS(value);
3713                         break;
3714                 case CONTRAST:
3715                 /*from 0 to 510,typical is 256*/
3716                         mask =  m_BCSH_CONTRAST;
3717                         val =  v_BCSH_CONTRAST(value);
3718                         break;
3719                 case SAT_CON:
3720                 /*from 0 to 1015,typical is 256*/
3721                         mask = m_BCSH_SAT_CON;
3722                         val = v_BCSH_SAT_CON(value);
3723                         break;
3724                 default:
3725                         break;
3726                 }
3727                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3728                 lcdc_cfg_done(lcdc_dev);
3729         }
3730         spin_unlock(&lcdc_dev->reg_lock);
3731         return val;
3732 }
3733
3734 static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode)
3735 {
3736         struct lcdc_device *lcdc_dev =
3737             container_of(dev_drv, struct lcdc_device, driver);
3738         u32 val;
3739
3740         spin_lock(&lcdc_dev->reg_lock);
3741         if(lcdc_dev->clk_on) {
3742                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3743                 switch (mode) {
3744                 case BRIGHTNESS:
3745                         val &= m_BCSH_BRIGHTNESS;
3746                         if(val > 0x80)
3747                                 val -= 0x80;
3748                         else
3749                                 val += 0x80;
3750                         break;
3751                 case CONTRAST:
3752                         val &= m_BCSH_CONTRAST;
3753                         val >>= 8;
3754                         break;
3755                 case SAT_CON:
3756                         val &= m_BCSH_SAT_CON;
3757                         val >>= 20;
3758                         break;
3759                 default:
3760                         break;
3761                 }
3762         }
3763         spin_unlock(&lcdc_dev->reg_lock);
3764         return val;
3765 }
3766
3767
3768 static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3769 {
3770         struct lcdc_device *lcdc_dev =
3771             container_of(dev_drv, struct lcdc_device, driver);
3772         u32 mask, val;
3773
3774         spin_lock(&lcdc_dev->reg_lock);
3775         if (lcdc_dev->clk_on) {
3776                 if (open) {
3777                         lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1);
3778                         lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000);
3779                         lcdc_writel(lcdc_dev,BCSH_H,0x01000000);
3780                         dev_drv->bcsh.enable = 1;
3781                 } else {
3782                         mask = m_BCSH_EN;
3783                         val = v_BCSH_EN(0);
3784                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3785                         dev_drv->bcsh.enable = 0;
3786                 }
3787                 if (dev_drv->version == VOP_FULL_RK3288_V1_1)
3788                         rk3288_lcdc_bcsh_path_sel(dev_drv);
3789                 lcdc_cfg_done(lcdc_dev);
3790         }
3791         spin_unlock(&lcdc_dev->reg_lock);
3792         return 0;
3793 }
3794
3795 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
3796                                      bool enable)
3797 {
3798         if (!enable || !dev_drv->bcsh.enable) {
3799                 rk3288_lcdc_open_bcsh(dev_drv, false);
3800                 return 0;
3801         }
3802
3803         if (dev_drv->bcsh.brightness <= 255 ||
3804             dev_drv->bcsh.contrast <= 510 ||
3805             dev_drv->bcsh.sat_con <= 1015 ||
3806             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3807                 rk3288_lcdc_open_bcsh(dev_drv, true);
3808                 if (dev_drv->bcsh.brightness <= 255)
3809                         rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3810                                                  dev_drv->bcsh.brightness);
3811                 if (dev_drv->bcsh.contrast <= 510)
3812                         rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3813                                                  dev_drv->bcsh.contrast);
3814                 if (dev_drv->bcsh.sat_con <= 1015)
3815                         rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3816                                                  dev_drv->bcsh.sat_con);
3817                 if (dev_drv->bcsh.sin_hue <= 511 &&
3818                     dev_drv->bcsh.cos_hue <= 511)
3819                         rk3288_lcdc_set_bcsh_hue(dev_drv,
3820                                                  dev_drv->bcsh.sin_hue,
3821                                                  dev_drv->bcsh.cos_hue);
3822         }
3823         return 0;
3824 }
3825
3826 static int rk3288_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
3827                                     struct overscan *overscan)
3828 {
3829         struct lcdc_device *lcdc_dev =
3830                 container_of(dev_drv, struct lcdc_device, driver);
3831
3832         if (unlikely(!lcdc_dev->clk_on)) {
3833                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3834                 return 0;
3835         }
3836         rk3288_lcdc_post_cfg(dev_drv);
3837
3838         return 0;
3839 }
3840
3841 static struct rk_lcdc_win lcdc_win[] = {
3842         [0] = {
3843                .name = "win0",
3844                .id = 0,
3845                .support_3d = false,
3846                },
3847         [1] = {
3848                .name = "win1",
3849                .id = 1,
3850                .support_3d = false,
3851                },
3852         [2] = {
3853                .name = "win2",
3854                .id = 2,
3855                .support_3d = false,
3856                },
3857         [3] = {
3858                .name = "win3",
3859                .id = 3,
3860                .support_3d = false,
3861                },
3862 };
3863
3864 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3865         .open                   = rk3288_lcdc_open,
3866         .win_direct_en          = rk3288_lcdc_win_direct_en,
3867         .load_screen            = rk3288_load_screen,
3868         .get_dspbuf_info        = rk3288_get_dspbuf_info,
3869         .post_dspbuf            = rk3288_post_dspbuf,
3870         .set_par                = rk3288_lcdc_set_par,
3871         .pan_display            = rk3288_lcdc_pan_display,
3872         .direct_set_addr        = rk3288_lcdc_direct_set_win_addr,
3873         .lcdc_reg_update        = rk3288_lcdc_reg_update,
3874         .blank                  = rk3288_lcdc_blank,
3875         .ioctl                  = rk3288_lcdc_ioctl,
3876         .suspend                = rk3288_lcdc_early_suspend,
3877         .resume                 = rk3288_lcdc_early_resume,
3878         .get_win_state          = rk3288_lcdc_get_win_state,
3879         .area_support_num = rk3288_lcdc_get_area_num,
3880         .ovl_mgr                = rk3288_lcdc_ovl_mgr,
3881         .get_disp_info          = rk3288_lcdc_get_disp_info,
3882         .fps_mgr                = rk3288_lcdc_fps_mgr,
3883         .fb_get_win_id          = rk3288_lcdc_get_win_id,
3884         .fb_win_remap           = rk3288_fb_win_remap,
3885         .set_dsp_lut            = rk3288_set_dsp_lut,
3886         .poll_vblank            = rk3288_lcdc_poll_vblank,
3887         .dpi_open               = rk3288_lcdc_dpi_open,
3888         .dpi_win_sel            = rk3288_lcdc_dpi_win_sel,
3889         .dpi_status             = rk3288_lcdc_dpi_status,
3890         .get_dsp_addr           = rk3288_lcdc_get_dsp_addr,
3891         .set_dsp_cabc           = rk3288_lcdc_set_dsp_cabc,
3892         .set_dsp_bcsh_hue       = rk3288_lcdc_set_bcsh_hue,
3893         .set_dsp_bcsh_bcs       = rk3288_lcdc_set_bcsh_bcs,
3894         .get_dsp_bcsh_hue       = rk3288_lcdc_get_bcsh_hue,
3895         .get_dsp_bcsh_bcs       = rk3288_lcdc_get_bcsh_bcs,
3896         .open_bcsh              = rk3288_lcdc_open_bcsh,
3897         .dump_reg               = rk3288_lcdc_reg_dump,
3898         .cfg_done               = rk3288_lcdc_config_done,
3899         .set_irq_to_cpu         = rk3288_lcdc_set_irq_to_cpu,
3900         .mmu_en    = rk3288_lcdc_mmu_en,
3901         .set_overscan           = rk3288_lcdc_set_overscan,
3902
3903 };
3904
3905 #ifdef LCDC_IRQ_DEBUG
3906 static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val)
3907 {
3908         if (reg_val & m_WIN0_EMPTY_INTR_STS) {
3909                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR,
3910                              v_WIN0_EMPTY_INTR_CLR(1));
3911                 dev_warn(lcdc_dev->dev,"win0 empty irq!");
3912         }else if (reg_val & m_WIN1_EMPTY_INTR_STS) {
3913                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR,
3914                              v_WIN1_EMPTY_INTR_CLR(1));
3915                 dev_warn(lcdc_dev->dev,"win1 empty irq!");
3916         }else if (reg_val & m_WIN2_EMPTY_INTR_STS) {
3917                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR,
3918                              v_WIN2_EMPTY_INTR_CLR(1));
3919                 dev_warn(lcdc_dev->dev,"win2 empty irq!");
3920         }else if (reg_val & m_WIN3_EMPTY_INTR_STS) {
3921                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR,
3922                              v_WIN3_EMPTY_INTR_CLR(1));
3923                 dev_warn(lcdc_dev->dev,"win3 empty irq!");
3924         }else if (reg_val & m_HWC_EMPTY_INTR_STS) {
3925                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR,
3926                              v_HWC_EMPTY_INTR_CLR(1));
3927                 dev_warn(lcdc_dev->dev,"HWC empty irq!");
3928         }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) {
3929                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR,
3930                              v_POST_BUF_EMPTY_INTR_CLR(1));
3931                 dev_warn(lcdc_dev->dev,"post buf empty irq!");
3932         }else if (reg_val & m_PWM_GEN_INTR_STS) {
3933                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR,
3934                              v_PWM_GEN_INTR_CLR(1));
3935                 dev_warn(lcdc_dev->dev,"PWM gen irq!");
3936         }
3937
3938         return 0;
3939 }
3940 #endif
3941
3942 static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id)
3943 {
3944         struct lcdc_device *lcdc_dev =
3945             (struct lcdc_device *)dev_id;
3946         ktime_t timestamp = ktime_get();
3947         u32 intr0_reg;
3948
3949         intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3950
3951         if(intr0_reg & m_FS_INTR_STS){
3952                 timestamp = ktime_get();
3953                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR,
3954                              v_FS_INTR_CLR(1));
3955                 /*if(lcdc_dev->driver.wait_fs){ */
3956                 if (0) {
3957                         spin_lock(&(lcdc_dev->driver.cpl_lock));
3958                         complete(&(lcdc_dev->driver.frame_done));
3959                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
3960                 }
3961 #ifdef CONFIG_DRM_ROCKCHIP
3962                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
3963 #endif
3964                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
3965                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
3966
3967         }else if(intr0_reg & m_LINE_FLAG_INTR_STS){
3968                 lcdc_dev->driver.frame_time.last_framedone_t =
3969                                 lcdc_dev->driver.frame_time.framedone_t;
3970                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3971                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3972                              v_LINE_FLAG_INTR_CLR(1));
3973         }else if(intr0_reg & m_BUS_ERROR_INTR_STS){
3974                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR,
3975                              v_BUS_ERROR_INTR_CLR(1));
3976                 dev_warn(lcdc_dev->dev,"buf_error_int!");
3977         }
3978
3979         /* for win empty debug */
3980 #ifdef LCDC_IRQ_EMPTY_DEBUG
3981         intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1);
3982         if (intr1_reg != 0) {
3983                 rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg);
3984         }
3985 #endif
3986         return IRQ_HANDLED;
3987 }
3988
3989 #if defined(CONFIG_PM)
3990 static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
3991 {
3992         return 0;
3993 }
3994
3995 static int rk3288_lcdc_resume(struct platform_device *pdev)
3996 {
3997         return 0;
3998 }
3999 #else
4000 #define rk3288_lcdc_suspend NULL
4001 #define rk3288_lcdc_resume  NULL
4002 #endif
4003
4004 static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4005 {
4006         struct device_node *np = lcdc_dev->dev->of_node;
4007         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4008         int val;
4009
4010         if (of_property_read_u32(np, "rockchip,prop", &val))
4011                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4012         else
4013                 lcdc_dev->prop = val;
4014
4015         if (of_property_read_u32(np, "rockchip,mirror", &val))
4016                 dev_drv->rotate_mode = NO_MIRROR;
4017         else
4018                 dev_drv->rotate_mode = val;
4019
4020         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4021                 dev_drv->cabc_mode = 0; /* default set close cabc */
4022         else
4023                 dev_drv->cabc_mode = val;
4024
4025         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4026                 lcdc_dev->pwr18 = false;        /*default set it as 3.xv power supply */
4027         else
4028                 lcdc_dev->pwr18 = (val ? true : false);
4029
4030         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4031                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4032         else
4033                 dev_drv->fb_win_map = val;
4034
4035         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4036                 dev_drv->bcsh.enable = false;
4037         else
4038                 dev_drv->bcsh.enable = (val ? true : false);
4039
4040         if (of_property_read_u32(np, "rockchip,brightness", &val))
4041                 dev_drv->bcsh.brightness = 0xffff;
4042         else
4043                 dev_drv->bcsh.brightness = val;
4044
4045         if (of_property_read_u32(np, "rockchip,contrast", &val))
4046                 dev_drv->bcsh.contrast = 0xffff;
4047         else
4048                 dev_drv->bcsh.contrast = val;
4049
4050         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4051                 dev_drv->bcsh.sat_con = 0xffff;
4052         else
4053                 dev_drv->bcsh.sat_con = val;
4054
4055         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4056                 dev_drv->bcsh.sin_hue = 0xffff;
4057                 dev_drv->bcsh.cos_hue = 0xffff;
4058         } else {
4059                 dev_drv->bcsh.sin_hue = val & 0xff;
4060                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4061         }
4062
4063 #if defined(CONFIG_ROCKCHIP_IOMMU)
4064         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4065                 dev_drv->iommu_enabled = 0;
4066         else
4067                 dev_drv->iommu_enabled = val;
4068 #else
4069         dev_drv->iommu_enabled = 0;
4070 #endif
4071         return 0;
4072 }
4073
4074 static int rk3288_lcdc_probe(struct platform_device *pdev)
4075 {
4076         struct lcdc_device *lcdc_dev = NULL;
4077         struct rk_lcdc_driver *dev_drv;
4078         struct device *dev = &pdev->dev;
4079         struct resource *res;
4080         struct device_node *np = pdev->dev.of_node;
4081         int prop;
4082         int ret = 0;
4083
4084         /*if the primary lcdc has not registered ,the extend
4085            lcdc register later */
4086         of_property_read_u32(np, "rockchip,prop", &prop);
4087         if (prop == EXTEND) {
4088                 if (!is_prmry_rk_lcdc_registered())
4089                         return -EPROBE_DEFER;
4090         }
4091         lcdc_dev = devm_kzalloc(dev,
4092                                 sizeof(struct lcdc_device), GFP_KERNEL);
4093         if (!lcdc_dev) {
4094                 dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!");
4095                 return -ENOMEM;
4096         }
4097         platform_set_drvdata(pdev, lcdc_dev);
4098         lcdc_dev->dev = dev;
4099         rk3288_lcdc_parse_dt(lcdc_dev);
4100         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4101         lcdc_dev->reg_phy_base = res->start;
4102         lcdc_dev->len = resource_size(res);
4103         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4104         if (IS_ERR(lcdc_dev->regs))
4105                 return PTR_ERR(lcdc_dev->regs);
4106
4107         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4108         if (IS_ERR(lcdc_dev->regsbak))
4109                 return PTR_ERR(lcdc_dev->regsbak);
4110         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4111         lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base);
4112         if (lcdc_dev->id < 0) {
4113                 dev_err(&pdev->dev, "no such lcdc device!\n");
4114                 return -ENXIO;
4115         }
4116         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4117         dev_drv = &lcdc_dev->driver;
4118         dev_drv->dev = dev;
4119         dev_drv->prop = prop;
4120         dev_drv->id = lcdc_dev->id;
4121         dev_drv->ops = &lcdc_drv_ops;
4122         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4123         spin_lock_init(&lcdc_dev->reg_lock);
4124
4125         lcdc_dev->irq = platform_get_irq(pdev, 0);
4126         if (lcdc_dev->irq < 0) {
4127                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4128                         lcdc_dev->id);
4129                 return -ENXIO;
4130         }
4131
4132         ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr,
4133                                IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
4134         if (ret) {
4135                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4136                         lcdc_dev->irq, ret);
4137                 return ret;
4138         }
4139
4140         if (dev_drv->iommu_enabled) {
4141                 if(lcdc_dev->id == 0){
4142                         strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME);
4143                 }else{
4144                         strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME);
4145                 }
4146         }
4147
4148         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4149         if (ret < 0) {
4150                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4151                 return ret;
4152         }
4153         lcdc_dev->screen = dev_drv->screen0;
4154         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4155                 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4156
4157         return 0;
4158 }
4159
4160 static int rk3288_lcdc_remove(struct platform_device *pdev)
4161 {
4162
4163         return 0;
4164 }
4165
4166 static void rk3288_lcdc_shutdown(struct platform_device *pdev)
4167 {
4168         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4169
4170         rk3288_lcdc_deint(lcdc_dev);
4171         rk_disp_pwr_disable(&lcdc_dev->driver);
4172 }
4173
4174 #if defined(CONFIG_OF)
4175 static const struct of_device_id rk3288_lcdc_dt_ids[] = {
4176         {.compatible = "rockchip,rk3288-lcdc",},
4177         {}
4178 };
4179 #endif
4180
4181 static struct platform_driver rk3288_lcdc_driver = {
4182         .probe = rk3288_lcdc_probe,
4183         .remove = rk3288_lcdc_remove,
4184         .driver = {
4185                    .name = "rk3288-lcdc",
4186                    .owner = THIS_MODULE,
4187                    .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids),
4188                    },
4189         .suspend = rk3288_lcdc_suspend,
4190         .resume = rk3288_lcdc_resume,
4191         .shutdown = rk3288_lcdc_shutdown,
4192 };
4193
4194 static int __init rk3288_lcdc_module_init(void)
4195 {
4196         return platform_driver_register(&rk3288_lcdc_driver);
4197 }
4198
4199 static void __exit rk3288_lcdc_module_exit(void)
4200 {
4201         platform_driver_unregister(&rk3288_lcdc_driver);
4202 }
4203
4204 fs_initcall(rk3288_lcdc_module_init);
4205 module_exit(rk3288_lcdc_module_exit);
4206
4207