drivers/video/rockchip/lcdc/rk3288_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3288_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <asm/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3288_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43
  44 static int dbg_thresd;
  45 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  46
  47 #define DBG(level, x...) do {                   \
  48         if (unlikely(dbg_thresd >= level))      \
  49                 printk(KERN_INFO x); } while (0)
  50
  51 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
  52                                      bool enable);
  53
  54 struct fb_info *rk_get_fb(int fb_id);
  55 /*#define WAIT_FOR_SYNC 1*/
  56
  57 static int rk3288_lcdc_get_id(u32 phy_base)
  58 {
  59         if (cpu_is_rk3288()) {
  60                 if (phy_base == 0xff930000)/*vop big*/
  61                         return 0;
  62                 else if (phy_base == 0xff940000)/*vop lit*/
  63                         return 1;
  64                 else
  65                         return -EINVAL;
  66         } else {
  67                 pr_err("un supported platform \n");
  68                 return -EINVAL;
  69         }
  70 }
  71
  72 static int rk3288_lcdc_set_lut(struct rk_lcdc_driver *dev_drv)
  73 {
  74         int i,j;
  75         int __iomem *c;
  76         u32 v,r,g,b;
  77         struct lcdc_device *lcdc_dev = container_of(dev_drv,
  78                                         struct lcdc_device,driver);
  79         if (dev_drv->cur_screen->dsp_lut)
  80                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
  81                              v_DSP_LUT_EN(0));
  82         if ((dev_drv->cur_screen->cabc_lut) &&
  83             (dev_drv->version == VOP_FULL_RK3288_V1_1))
  84                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
  85                              v_CABC_LUT_EN(0));
  86         lcdc_cfg_done(lcdc_dev);
  87         mdelay(25);
  88         if (dev_drv->cur_screen->dsp_lut) {
  89                 for (i = 0; i < 256; i++) {
  90                         v = dev_drv->cur_screen->dsp_lut[i];
  91                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
  92                         b = (v & 0xff) << 2;
  93                         g = (v & 0xff00) << 4;
  94                         r = (v & 0xff0000) << 6;
  95                         v = r + g + b;
  96                         for (j = 0; j < 4; j++) {
  97                                 writel_relaxed(v, c);
  98                                 v += (1 + (1 << 10) + (1 << 20));
  99                                 c++;
 100                         }
 101                 }
 102                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 103                              v_DSP_LUT_EN(1));
 104         }
 105         if ((dev_drv->cur_screen->cabc_lut) &&
 106             (dev_drv->version == VOP_FULL_RK3288_V1_1)) {
 107                 for (i = 0; i < 128; i++) {
 108                         v = dev_drv->cur_screen->cabc_lut[i];
 109                         lcdc_writel(lcdc_dev, i * 4 + CABC_LUT_ADDR, v);
 110                 }
 111                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 112                              v_CABC_LUT_EN(1));
 113         }
 114
 115         return 0;
 116
 117 }
 118
 119 static int rk3288_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 120 {
 121 #ifdef CONFIG_RK_FPGA
 122         lcdc_dev->clk_on = 1;
 123         return 0;
 124 #endif
 125         if (!lcdc_dev->clk_on) {
 126                 clk_prepare_enable(lcdc_dev->hclk);
 127                 clk_prepare_enable(lcdc_dev->dclk);
 128                 clk_prepare_enable(lcdc_dev->aclk);
 129                 clk_prepare_enable(lcdc_dev->pd);
 130                 spin_lock(&lcdc_dev->reg_lock);
 131                 lcdc_dev->clk_on = 1;
 132                 spin_unlock(&lcdc_dev->reg_lock);
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk3288_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 139 {
 140 #ifdef CONFIG_RK_FPGA
 141         lcdc_dev->clk_on = 0;
 142         return 0;
 143 #endif
 144         if (lcdc_dev->clk_on) {
 145                 spin_lock(&lcdc_dev->reg_lock);
 146                 lcdc_dev->clk_on = 0;
 147                 spin_unlock(&lcdc_dev->reg_lock);
 148                 mdelay(25);
 149                 clk_disable_unprepare(lcdc_dev->dclk);
 150                 clk_disable_unprepare(lcdc_dev->hclk);
 151                 clk_disable_unprepare(lcdc_dev->aclk);
 152                 clk_disable_unprepare(lcdc_dev->pd);
 153         }
 154
 155         return 0;
 156 }
 157
 158 static int rk3288_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 159 {
 160         u32 mask, val;
 161         spin_lock(&lcdc_dev->reg_lock);
 162         if (likely(lcdc_dev->clk_on)) {
 163                 mask = m_DSP_HOLD_VALID_INTR_EN | m_FS_INTR_EN |
 164                         m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_EN;
 165                 val = v_DSP_HOLD_VALID_INTR_EN(0) | v_FS_INTR_EN(0) |
 166                         v_LINE_FLAG_INTR_EN(0) | v_BUS_ERROR_INTR_EN(0);
 167                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 168
 169                 mask = m_DSP_HOLD_VALID_INTR_CLR | m_FS_INTR_CLR |
 170                         m_LINE_FLAG_INTR_CLR | m_LINE_FLAG_INTR_CLR;
 171                 val = v_DSP_HOLD_VALID_INTR_CLR(0) | v_FS_INTR_CLR(0) |
 172                         v_LINE_FLAG_INTR_CLR(0) | v_BUS_ERROR_INTR_CLR(0);
 173                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
 174
 175                 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 176                         m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 177                         m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 178                         m_POST_BUF_EMPTY_INTR_EN;
 179                 val = v_WIN0_EMPTY_INTR_EN(0) | v_WIN1_EMPTY_INTR_EN(0) |
 180                         v_WIN2_EMPTY_INTR_EN(0) | v_WIN3_EMPTY_INTR_EN(0) |
 181                         v_HWC_EMPTY_INTR_EN(0) | v_POST_BUF_EMPTY_INTR_EN(0) |
 182                         v_PWM_GEN_INTR_EN(0);
 183                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 184
 185                 mask = m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 186                         m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 187                         m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 188                         m_POST_BUF_EMPTY_INTR_CLR;
 189                 val = v_WIN0_EMPTY_INTR_CLR(0) | v_WIN1_EMPTY_INTR_CLR(0) |
 190                         v_WIN2_EMPTY_INTR_CLR(0) | v_WIN3_EMPTY_INTR_CLR(0) |
 191                         v_HWC_EMPTY_INTR_CLR(0) | v_POST_BUF_EMPTY_INTR_CLR(0) |
 192                         v_PWM_GEN_INTR_CLR(0);
 193                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
 194                 lcdc_cfg_done(lcdc_dev);
 195                 spin_unlock(&lcdc_dev->reg_lock);
 196         } else {
 197                 spin_unlock(&lcdc_dev->reg_lock);
 198         }
 199         mdelay(1);
 200         return 0;
 201 }
 202 static int rk3288_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 203 {
 204         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 205                                                 struct lcdc_device,
 206                                                 driver);
 207         int *cbase = (int *)lcdc_dev->regs;
 208         int *regsbak = (int *)lcdc_dev->regsbak;
 209         int i, j;
 210
 211         printk("back up reg:\n");
 212         for (i = 0; i <= (0x200 >> 4); i++) {
 213                 printk("0x%04x: ",i*16);
 214                 for (j = 0; j < 4; j++)
 215                         printk("%08x  ", *(regsbak + i * 4 + j));
 216                 printk("\n");
 217         }
 218
 219         printk("lcdc reg:\n");
 220         for (i = 0; i <= (0x200 >> 4); i++) {
 221                 printk("0x%04x: ",i*16);
 222                 for (j = 0; j < 4; j++)
 223                         printk("%08x  ", readl_relaxed(cbase + i * 4 + j));
 224                 printk("\n");
 225         }
 226         return 0;
 227
 228 }
 229
 230 #define WIN_EN(id)              \
 231 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 232 { \
 233         u32 msk, val;                                                   \
 234         spin_lock(&lcdc_dev->reg_lock);                                 \
 235         msk =  m_WIN##id##_EN;                                          \
 236         val  =  v_WIN##id##_EN(en);                                     \
 237         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 238         lcdc_cfg_done(lcdc_dev);                                        \
 239         /*val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);          \
 240         while (val !=  (!!en))  {                                       \
 241                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 242         }*/                                                             \
 243         spin_unlock(&lcdc_dev->reg_lock);                               \
 244         return 0;                                                       \
 245 }
 246
 247 WIN_EN(0);
 248 WIN_EN(1);
 249 WIN_EN(2);
 250 WIN_EN(3);
 251 /*enable/disable win directly*/
 252 static int rk3288_lcdc_win_direct_en
 253                 (struct rk_lcdc_driver *drv, int win_id , int en)
 254 {
 255         struct lcdc_device *lcdc_dev = container_of(drv,
 256                                         struct lcdc_device, driver);
 257         if (win_id == 0)
 258                 win0_enable(lcdc_dev, en);
 259         else if (win_id == 1)
 260                 win1_enable(lcdc_dev, en);
 261         else if (win_id == 2)
 262                 win2_enable(lcdc_dev, en);
 263         else if (win_id == 3)
 264                 win3_enable(lcdc_dev, en);
 265         else
 266                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 267         return 0;
 268
 269 }
 270
 271 #define SET_WIN_ADDR(id) \
 272 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 273 {                                                       \
 274         u32 msk, val;                                   \
 275         spin_lock(&lcdc_dev->reg_lock);                 \
 276         lcdc_writel(lcdc_dev,WIN##id##_YRGB_MST,addr);  \
 277         msk =  m_WIN##id##_EN;                          \
 278         val  =  v_WIN0_EN(1);                           \
 279         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk,val);       \
 280         lcdc_cfg_done(lcdc_dev);                        \
 281         spin_unlock(&lcdc_dev->reg_lock);               \
 282         return 0;                                       \
 283 }
 284
 285 SET_WIN_ADDR(0);
 286 SET_WIN_ADDR(1);
 287 int rk3288_lcdc_direct_set_win_addr
 288                 (struct rk_lcdc_driver *dev_drv, int win_id, u32 addr)
 289 {
 290         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 291                                 struct lcdc_device, driver);
 292         if (win_id == 0)
 293                 set_win0_addr(lcdc_dev, addr);
 294         else
 295                 set_win1_addr(lcdc_dev, addr);
 296
 297         return 0;
 298 }
 299
 300 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 301 {
 302         int reg = 0;
 303         u32 val = 0;
 304         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 305         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 306         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 307         u32 st_x, st_y;
 308         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 309
 310         spin_lock(&lcdc_dev->reg_lock);
 311         memcpy(lcdc_dev->regsbak, lcdc_dev->regs, FRC_LOWER11_1);
 312         for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
 313                 val = lcdc_readl(lcdc_dev, reg);
 314                 switch (reg) {
 315                 case VERSION_INFO:
 316                         lcdc_dev->driver.version = val;
 317                         break;
 318                         case WIN0_ACT_INFO:
 319                                 win0->area[0].xact =
 320                                         (val & m_WIN0_ACT_WIDTH) + 1;
 321                                 win0->area[0].yact =
 322                                         ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 323                                 break;
 324                         case WIN0_DSP_INFO:
 325                                 win0->area[0].xsize =
 326                                         (val & m_WIN0_DSP_WIDTH) + 1;
 327                                 win0->area[0].ysize =
 328                                         ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 329                                 break;
 330                         case WIN0_DSP_ST:
 331                                 st_x = val & m_WIN0_DSP_XST;
 332                                 st_y = (val & m_WIN0_DSP_YST) >> 16;
 333                                 win0->area[0].xpos = st_x - h_pw_bp;
 334                                 win0->area[0].ypos = st_y - v_pw_bp;
 335                                 break;
 336                         case WIN0_CTRL0:
 337                                 win0->state = val & m_WIN0_EN;
 338                                 win0->area[0].fmt_cfg =
 339                                         (val & m_WIN0_DATA_FMT) >> 1;
 340                                 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 341                                 win0->area[0].format = win0->area[0].fmt_cfg;
 342                                 break;
 343                         case WIN0_VIR:
 344                                 win0->area[0].y_vir_stride =
 345                                         val & m_WIN0_VIR_STRIDE;
 346                                 win0->area[0].uv_vir_stride =
 347                                         (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 348                                 if (win0->area[0].format == ARGB888)
 349                                         win0->area[0].xvir =
 350                                                 win0->area[0].y_vir_stride;
 351                                 else if (win0->area[0].format == RGB888)
 352                                         win0->area[0].xvir =
 353                                                 win0->area[0].y_vir_stride * 4 / 3;
 354                                 else if (win0->area[0].format == RGB565)
 355                                         win0->area[0].xvir =
 356                                                 2 * win0->area[0].y_vir_stride;
 357                                 else /* YUV */
 358                                         win0->area[0].xvir =
 359                                                 4 * win0->area[0].y_vir_stride;
 360                                 break;
 361                         case WIN0_YRGB_MST:
 362                                 win0->area[0].smem_start = val;
 363                                 break;
 364                         case WIN0_CBR_MST:
 365                                 win0->area[0].cbr_start = val;
 366                                 break;
 367                         case DSP_VACT_ST_END:
 368                                 if (support_uboot_display()) {
 369                                         screen->mode.yres =
 370                                         (val & 0x1fff) - ((val >> 16) & 0x1fff);
 371                                         win0->area[0].ypos =
 372                                         st_y - ((val >> 16) & 0x1fff);
 373                                 }
 374                                 break;
 375                         case DSP_HACT_ST_END:
 376                                 if (support_uboot_display()) {
 377                                         screen->mode.xres =
 378                                         (val & 0x1fff) - ((val >> 16) & 0x1fff);
 379                                         win0->area[0].xpos =
 380                                         st_x - ((val >> 16) & 0x1fff);
 381                                 }
 382                                 break;
 383                         default:
 384                                 break;
 385                 }
 386         }
 387         spin_unlock(&lcdc_dev->reg_lock);
 388
 389 }
 390
 391 /********do basic init*********/
 392 static int rk3288_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 393 {
 394         int v;
 395         u32 mask,val;
 396         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 397                                                            struct
 398                                                            lcdc_device,
 399                                                    driver);
 400         if (lcdc_dev->pre_init)
 401                 return 0;
 402
 403         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 404         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 405         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 406         lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc");
 407
 408         if (IS_ERR(lcdc_dev->pd) || (IS_ERR(lcdc_dev->aclk)) ||
 409             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 410                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 411                         lcdc_dev->id);
 412         }
 413         if (!support_uboot_display())
 414                 rk_disp_pwr_enable(dev_drv);
 415         rk3288_lcdc_clk_enable(lcdc_dev);
 416
 417         /*backup reg config at uboot*/
 418         lcdc_read_reg_defalut_cfg(lcdc_dev);
 419         v = 0;
 420 #ifndef CONFIG_RK_FPGA
 421         if (lcdc_dev->pwr18 == true) {
 422                 v = 0x00010001; /*bit14: 1,1.8v;0,3.3v*/
 423                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 424         } else {
 425                 v = 0x00010000;
 426                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_IO_VSEL);
 427         }
 428 #endif
 429         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_0,0x15110903);
 430         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE0_1,0x00030911);
 431         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_0,0x1a150b04);
 432         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE1_1,0x00040b15);
 433         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_0,0x15110903);
 434         lcdc_writel(lcdc_dev,CABC_GAUSS_LINE2_1,0x00030911);
 435
 436         lcdc_writel(lcdc_dev,FRC_LOWER01_0,0x12844821);
 437         lcdc_writel(lcdc_dev,FRC_LOWER01_1,0x21488412);
 438         lcdc_writel(lcdc_dev,FRC_LOWER10_0,0xa55a9696);
 439         lcdc_writel(lcdc_dev,FRC_LOWER10_1,0x5aa56969);
 440         lcdc_writel(lcdc_dev,FRC_LOWER11_0,0xdeb77deb);
 441         lcdc_writel(lcdc_dev,FRC_LOWER11_1,0xed7bb7de);
 442
 443         mask =  m_AUTO_GATING_EN;
 444         val  =  v_AUTO_GATING_EN(0);
 445         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask,val);
 446         lcdc_cfg_done(lcdc_dev);
 447         /*disable win0 to workaround iommu pagefault */
 448         /*if (dev_drv->iommu_enabled) */
 449         /*      win0_enable(lcdc_dev, 0); */
 450         lcdc_dev->pre_init = true;
 451
 452
 453         return 0;
 454 }
 455
 456 static void rk3288_lcdc_deint(struct lcdc_device *lcdc_dev)
 457 {
 458
 459
 460         rk3288_lcdc_disable_irq(lcdc_dev);
 461         spin_lock(&lcdc_dev->reg_lock);
 462         if (likely(lcdc_dev->clk_on)) {
 463                 lcdc_dev->clk_on = 0;
 464                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 465                 lcdc_cfg_done(lcdc_dev);
 466                 spin_unlock(&lcdc_dev->reg_lock);
 467         } else {
 468                 spin_unlock(&lcdc_dev->reg_lock);
 469         }
 470         mdelay(1);
 471 }
 472 static int rk3288_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 473 {
 474         struct lcdc_device *lcdc_dev =
 475             container_of(dev_drv, struct lcdc_device, driver);
 476         struct rk_screen *screen = dev_drv->cur_screen;
 477         u16 x_res = screen->mode.xres;
 478         u16 y_res = screen->mode.yres;
 479         u32 mask, val;
 480         u16 h_total,v_total;
 481         u16 post_hsd_en,post_vsd_en;
 482         u16 post_dsp_hact_st,post_dsp_hact_end;
 483         u16 post_dsp_vact_st,post_dsp_vact_end;
 484         u16 post_dsp_vact_st_f1,post_dsp_vact_end_f1;
 485         u16 post_h_fac,post_v_fac;
 486
 487         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 488         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 489         screen->post_xsize = x_res *
 490                 (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 491         screen->post_ysize = y_res *
 492                 (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 493         h_total = screen->mode.hsync_len+screen->mode.left_margin +
 494                   x_res + screen->mode.right_margin;
 495         v_total = screen->mode.vsync_len+screen->mode.upper_margin +
 496                   y_res + screen->mode.lower_margin;
 497
 498         if(screen->post_dsp_stx + screen->post_xsize > x_res){
 499                 dev_warn(lcdc_dev->dev, "post:stx[%d] + xsize[%d] > x_res[%d]\n",
 500                         screen->post_dsp_stx,screen->post_xsize,x_res);
 501                 screen->post_dsp_stx = x_res - screen->post_xsize;
 502         }
 503         if(screen->x_mirror == 0){
 504                 post_dsp_hact_st=screen->post_dsp_stx +
 505                         screen->mode.hsync_len+screen->mode.left_margin;
 506                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 507         }else{
 508                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 509                                         screen->post_dsp_stx;
 510                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 511         }
 512         if((screen->post_xsize < x_res)&&(screen->post_xsize != 0)){
 513                 post_hsd_en = 1;
 514                 post_h_fac =
 515                         GET_SCALE_FACTOR_BILI_DN(x_res , screen->post_xsize);
 516         }else{
 517                 post_hsd_en = 0;
 518                 post_h_fac = 0x1000;
 519         }
 520
 521
 522         if(screen->post_dsp_sty + screen->post_ysize > y_res){
 523                 dev_warn(lcdc_dev->dev, "post:sty[%d] + ysize[%d] > y_res[%d]\n",
 524                         screen->post_dsp_sty,screen->post_ysize,y_res);
 525                 screen->post_dsp_sty = y_res - screen->post_ysize;
 526         }
 527
 528         if(screen->y_mirror == 0){
 529                 post_dsp_vact_st = screen->post_dsp_sty +
 530                         screen->mode.vsync_len+screen->mode.upper_margin;
 531                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 532         }else{
 533                 post_dsp_vact_end = v_total - screen->mode.lower_margin -
 534                                         - screen->post_dsp_sty;
 535                 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
 536         }
 537         if((screen->post_ysize < y_res)&&(screen->post_ysize != 0)){
 538                 post_vsd_en = 1;
 539                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res, screen->post_ysize);
 540         }else{
 541                 post_vsd_en = 0;
 542                 post_v_fac = 0x1000;
 543         }
 544
 545         if(screen->interlace == 1){
 546                 post_dsp_vact_st_f1  = v_total + post_dsp_vact_st;
 547                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
 548         }else{
 549                 post_dsp_vact_st_f1  = 0;
 550                 post_dsp_vact_end_f1 = 0;
 551         }
 552         DBG(1,"post:xsize=%d,ysize=%d,xpos=%d,ypos=%d,"
 553               "hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 554                 screen->post_xsize,screen->post_ysize,screen->xpos,screen->ypos,
 555                 post_hsd_en,post_h_fac,post_vsd_en,post_v_fac);
 556         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 557         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 558               v_DSP_HACT_ST_POST(post_dsp_hact_st);
 559         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 560
 561         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 562         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 563               v_DSP_VACT_ST_POST(post_dsp_vact_st);
 564         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 565
 566         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 567         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 568                 v_POST_VS_FACTOR_YRGB(post_v_fac);
 569         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 570
 571         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 572         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 573                 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 574         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 575
 576         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 577         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 578         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 579         return 0;
 580 }
 581
 582 static int rk3288_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 583 {
 584         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 585                                                            struct
 586                                                            lcdc_device,
 587                                                            driver);
 588         struct rk_lcdc_win *win;
 589         u32  colorkey_r,colorkey_g,colorkey_b;
 590         int i,key_val;
 591         for(i=0;i<4;i++){
 592                 win = dev_drv->win[i];
 593                 key_val = win->color_key_val;
 594                 colorkey_r = (key_val & 0xff)<<2;
 595                 colorkey_g = ((key_val>>8)&0xff)<<12;
 596                 colorkey_b = ((key_val>>16)&0xff)<<22;
 597                 /*color key dither 565/888->aaa*/
 598                 key_val = colorkey_r | colorkey_g | colorkey_b;
 599                 switch(i){
 600                 case 0:
 601                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 602                         break;
 603                 case 1:
 604                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 605                         break;
 606                 case 2:
 607                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 608                         break;
 609                 case 3:
 610                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 611                         break;
 612                 default:
 613                         printk(KERN_WARNING "%s:un support win num:%d\n",
 614                                 __func__,i);
 615                         break;
 616                 }
 617         }
 618         return 0;
 619 }
 620
 621 static int rk3288_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv,int win_id)
 622 {
 623         struct lcdc_device *lcdc_dev =
 624                 container_of(dev_drv, struct lcdc_device, driver);
 625         struct rk_lcdc_win *win = dev_drv->win[win_id];
 626         struct alpha_config alpha_config;
 627
 628         u32 mask, val;
 629         int ppixel_alpha,global_alpha;
 630         u32 src_alpha_ctl,dst_alpha_ctl;
 631         ppixel_alpha = ((win->area[0].format == ARGB888) ||
 632                         (win->area[0].format == ABGR888)) ? 1 : 0;
 633         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 634         alpha_config.src_global_alpha_val = win->g_alpha_val;
 635         win->alpha_mode = AB_SRC_OVER;
 636         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 637                 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,global_alpha);*/
 638         switch(win->alpha_mode){
 639         case AB_USER_DEFINE:
 640                 break;
 641         case AB_CLEAR:
 642                 alpha_config.src_factor_mode=AA_ZERO;
 643                 alpha_config.dst_factor_mode=AA_ZERO;
 644                 break;
 645         case AB_SRC:
 646                 alpha_config.src_factor_mode=AA_ONE;
 647                 alpha_config.dst_factor_mode=AA_ZERO;
 648                 break;
 649         case AB_DST:
 650                 alpha_config.src_factor_mode=AA_ZERO;
 651                 alpha_config.dst_factor_mode=AA_ONE;
 652                 break;
 653         case AB_SRC_OVER:
 654                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 655                 if(global_alpha)
 656                         alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 657                 else
 658                         alpha_config.src_factor_mode=AA_ONE;
 659                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 660                 break;
 661         case AB_DST_OVER:
 662                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 663                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 664                 alpha_config.dst_factor_mode=AA_ONE;
 665                 break;
 666         case AB_SRC_IN:
 667                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 668                 alpha_config.src_factor_mode=AA_SRC;
 669                 alpha_config.dst_factor_mode=AA_ZERO;
 670                 break;
 671         case AB_DST_IN:
 672                 alpha_config.src_factor_mode=AA_ZERO;
 673                 alpha_config.dst_factor_mode=AA_SRC;
 674                 break;
 675         case AB_SRC_OUT:
 676                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 677                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 678                 alpha_config.dst_factor_mode=AA_ZERO;
 679                 break;
 680         case AB_DST_OUT:
 681                 alpha_config.src_factor_mode=AA_ZERO;
 682                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 683                 break;
 684         case AB_SRC_ATOP:
 685                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 686                 alpha_config.src_factor_mode=AA_SRC;
 687                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 688                 break;
 689         case AB_DST_ATOP:
 690                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 691                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 692                 alpha_config.dst_factor_mode=AA_SRC;
 693                 break;
 694         case XOR:
 695                 alpha_config.src_color_mode=AA_SRC_PRE_MUL;
 696                 alpha_config.src_factor_mode=AA_SRC_INVERSE;
 697                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 698                 break;
 699         case AB_SRC_OVER_GLOBAL:
 700                 alpha_config.src_global_alpha_mode=AA_PER_PIX_GLOBAL;
 701                 alpha_config.src_color_mode=AA_SRC_NO_PRE_MUL;
 702                 alpha_config.src_factor_mode=AA_SRC_GLOBAL;
 703                 alpha_config.dst_factor_mode=AA_SRC_INVERSE;
 704                 break;
 705         default:
 706                 pr_err("alpha mode error\n");
 707                 break;
 708         }
 709         if((ppixel_alpha == 1)&&(global_alpha == 1)){
 710                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 711         }else if(ppixel_alpha == 1){
 712                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 713         }else if(global_alpha == 1){
 714                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 715         }else{
 716                 dev_warn(lcdc_dev->dev,"alpha_en should be 0\n");
 717         }
 718         alpha_config.src_alpha_mode = AA_STRAIGHT;
 719         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 720
 721         switch(win_id){
 722         case 0:
 723                 src_alpha_ctl = 0x60;
 724                 dst_alpha_ctl = 0x64;
 725                 break;
 726         case 1:
 727                 src_alpha_ctl = 0xa0;
 728                 dst_alpha_ctl = 0xa4;
 729                 break;
 730         case 2:
 731                 src_alpha_ctl = 0xdc;
 732                 dst_alpha_ctl = 0xec;
 733                 break;
 734         case 3:
 735                 src_alpha_ctl = 0x12c;
 736                 dst_alpha_ctl = 0x13c;
 737                 break;
 738         }
 739         mask = m_WIN0_DST_FACTOR_M0;
 740         val  = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 741         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 742         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 743                 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 744                 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0|
 745                 m_WIN0_SRC_GLOBAL_ALPHA;
 746         val = v_WIN0_SRC_ALPHA_EN(1) |
 747                 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 748                 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 749                 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 750                 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 751                 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 752                 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 753         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 754
 755         return 0;
 756 }
 757 static int rk3288_lcdc_area_swap(struct rk_lcdc_win *win,int area_num)
 758 {
 759         struct rk_lcdc_win_area area_temp;
 760         switch(area_num){
 761         case 2:
 762                 area_temp = win->area[0];
 763                 win->area[0] = win->area[1];
 764                 win->area[1] = area_temp;
 765                 break;
 766         case 3:
 767                 area_temp = win->area[0];
 768                 win->area[0] = win->area[2];
 769                 win->area[2] = area_temp;
 770                 break;
 771         case 4:
 772                 area_temp = win->area[0];
 773                 win->area[0] = win->area[3];
 774                 win->area[3] = area_temp;
 775
 776                 area_temp = win->area[1];
 777                 win->area[1] = win->area[2];
 778                 win->area[2] = area_temp;
 779                 break;
 780         default:
 781                 printk(KERN_WARNING "un supported area num!\n");
 782                 break;
 783         }
 784         return 0;
 785 }
 786
 787 static int rk3288_win_area_check_var(int win_id,int area_num,struct rk_lcdc_win_area *area_pre,
 788                         struct rk_lcdc_win_area *area_now)
 789 {
 790         if((area_pre->ypos >= area_now->ypos) ||
 791                 (area_pre->ypos+area_pre->ysize > area_now->ypos)){
 792                 area_now->state = 0;
 793                 pr_err("win[%d]:\n"
 794                         "area_pre[%d]:ypos[%d],ysize[%d]\n"
 795                         "area_now[%d]:ypos[%d],ysize[%d]\n",
 796                         win_id,
 797                         area_num-1,area_pre->ypos,area_pre->ysize,
 798                         area_num,  area_now->ypos,area_now->ysize);
 799                 return -EINVAL;
 800         }
 801         return 0;
 802 }
 803
 804 static int rk3288_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 805 {
 806         struct lcdc_device *lcdc_dev =
 807             container_of(dev_drv, struct lcdc_device, driver);
 808         struct rk_lcdc_win *win = dev_drv->win[win_id];
 809         unsigned int mask, val, off;
 810         off = win_id * 0x40;
 811         if((win->win_lb_mode == 5) &&
 812            (dev_drv->version == VOP_FULL_RK3288_V1_0))
 813                 win->win_lb_mode = 4;
 814
 815         if(win->state == 1){
 816                 mask =  m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
 817                         m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_UV_SWAP;
 818                 val  =  v_WIN0_EN(win->state) |
 819                         v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
 820                         v_WIN0_FMT_10(win->fmt_10) |
 821                         v_WIN0_LB_MODE(win->win_lb_mode) |
 822                         v_WIN0_RB_SWAP(win->area[0].swap_rb) |
 823                         v_WIN0_UV_SWAP(win->area[0].swap_uv);
 824                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 825
 826                 mask =  m_WIN0_BIC_COE_SEL |
 827                         m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
 828                         m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
 829                         m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
 830                         m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
 831                         m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
 832                         m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
 833                         m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
 834                 val =   v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
 835                         v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
 836                         v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
 837                         v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
 838                         v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
 839                         v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
 840                         v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
 841                         v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
 842                         v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
 843                         v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
 844                         v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
 845                         v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
 846                         v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
 847                         v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
 848                         v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
 849                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1+off, mask,val);
 850
 851                 val =   v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
 852                         v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
 853                 lcdc_writel(lcdc_dev, WIN0_VIR+off, val);
 854                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off, win->area[0].y_addr);
 855                 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off, win->area[0].uv_addr);*/
 856                 val =   v_WIN0_ACT_WIDTH(win->area[0].xact) |
 857                         v_WIN0_ACT_HEIGHT(win->area[0].yact);
 858                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO+off, val);
 859
 860                 val =   v_WIN0_DSP_WIDTH(win->area[0].xsize) |
 861                         v_WIN0_DSP_HEIGHT(win->area[0].ysize);
 862                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO+off, val);
 863
 864                 val =   v_WIN0_DSP_XST(win->area[0].dsp_stx) |
 865                         v_WIN0_DSP_YST(win->area[0].dsp_sty);
 866                 lcdc_writel(lcdc_dev, WIN0_DSP_ST+off, val);
 867
 868                 val =   v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
 869                         v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
 870                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB+off, val);
 871
 872                 val =   v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
 873                         v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
 874                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR+off, val);
 875                 if(win->alpha_en == 1)
 876                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
 877                 else{
 878                         mask = m_WIN0_SRC_ALPHA_EN;
 879                         val = v_WIN0_SRC_ALPHA_EN(0);
 880                         lcdc_msk_reg(lcdc_dev,WIN0_SRC_ALPHA_CTRL+off,mask,val);
 881                 }
 882                 /*offset*/
 883         }else{
 884                 mask = m_WIN0_EN;
 885                 val = v_WIN0_EN(win->state);
 886                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0+off, mask,val);
 887         }
 888         return 0;
 889 }
 890
 891 static int rk3288_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv,int win_id)
 892 {
 893         struct lcdc_device *lcdc_dev =
 894             container_of(dev_drv, struct lcdc_device, driver);
 895         struct rk_lcdc_win *win = dev_drv->win[win_id];
 896         struct rk_screen *screen = dev_drv->cur_screen;
 897         unsigned int mask, val, off;
 898         struct fb_info *fb0 = rk_get_fb(0);
 899
 900         off = (win_id-2) * 0x50;
 901         if((screen->y_mirror == 1)&&(win->area_num > 1)){
 902                 rk3288_lcdc_area_swap(win,win->area_num);
 903         }
 904
 905         if(win->state == 1){
 906                 mask =  m_WIN2_EN | m_WIN2_DATA_FMT | m_WIN2_RB_SWAP;
 907                 val  =  v_WIN2_EN(1) |
 908                         v_WIN2_DATA_FMT(win->area[0].fmt_cfg) |
 909                         v_WIN2_RB_SWAP(win->area[0].swap_rb);
 910                 lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 911                 /*area 0*/
 912                 if(win->area[0].state == 1){
 913                         mask = m_WIN2_MST0_EN;
 914                         val  = v_WIN2_MST0_EN(win->area[0].state);
 915                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 916
 917                         mask = m_WIN2_VIR_STRIDE0;
 918                         val  = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
 919                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 920
 921                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,win->area[0].y_addr);*/
 922                         val  =  v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
 923                                 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
 924                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO0+off,val);
 925                         val  =  v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
 926                                 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
 927                         lcdc_writel(lcdc_dev,WIN2_DSP_ST0+off,val);
 928                 }else{
 929                         mask = m_WIN2_MST0_EN;
 930                         val  = v_WIN2_MST0_EN(0);
 931                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 932                         lcdc_writel(lcdc_dev, WIN2_MST0 + off,
 933                                     fb0->fix.smem_start);
 934                 }
 935                 /*area 1*/
 936                 if(win->area[1].state == 1){
 937                         rk3288_win_area_check_var(win_id,1,&win->area[0],&win->area[1]);
 938
 939                         mask = m_WIN2_MST1_EN;
 940                         val  = v_WIN2_MST1_EN(win->area[1].state);
 941                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 942
 943                         mask = m_WIN2_VIR_STRIDE1;
 944                         val  = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
 945                         lcdc_msk_reg(lcdc_dev,WIN2_VIR0_1+off,mask,val);
 946
 947                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,win->area[1].y_addr);*/
 948                         val  =  v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
 949                                 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
 950                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO1+off,val);
 951                         val  =  v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
 952                                 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
 953                         lcdc_writel(lcdc_dev,WIN2_DSP_ST1+off,val);
 954                 }else{
 955                         mask = m_WIN2_MST1_EN;
 956                         val  = v_WIN2_MST1_EN(0);
 957                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 958                         lcdc_writel(lcdc_dev, WIN2_MST1 + off,
 959                                     fb0->fix.smem_start);
 960                 }
 961                 /*area 2*/
 962                 if(win->area[2].state == 1){
 963                         rk3288_win_area_check_var(win_id,2,&win->area[1],&win->area[2]);
 964
 965                         mask = m_WIN2_MST2_EN;
 966                         val  = v_WIN2_MST2_EN(win->area[2].state);
 967                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 968
 969                         mask = m_WIN2_VIR_STRIDE2;
 970                         val  = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
 971                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 972
 973                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,win->area[2].y_addr);*/
 974                         val  =  v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
 975                                 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
 976                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO2+off,val);
 977                         val  =  v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
 978                                 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
 979                         lcdc_writel(lcdc_dev,WIN2_DSP_ST2+off,val);
 980                 }else{
 981                         mask = m_WIN2_MST2_EN;
 982                         val  = v_WIN2_MST2_EN(0);
 983                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 984                         lcdc_writel(lcdc_dev, WIN2_MST2 + off,
 985                                     fb0->fix.smem_start);
 986                 }
 987                 /*area 3*/
 988                 if(win->area[3].state == 1){
 989                         rk3288_win_area_check_var(win_id,3,&win->area[2],&win->area[3]);
 990
 991                         mask = m_WIN2_MST3_EN;
 992                         val  = v_WIN2_MST3_EN(win->area[3].state);
 993                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
 994
 995                         mask = m_WIN2_VIR_STRIDE3;
 996                         val  = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
 997                         lcdc_msk_reg(lcdc_dev,WIN2_VIR2_3+off,mask,val);
 998
 999                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,win->area[3].y_addr);*/
1000                         val  =  v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1001                                 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1002                         lcdc_writel(lcdc_dev,WIN2_DSP_INFO3+off,val);
1003                         val  =  v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1004                                 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1005                         lcdc_writel(lcdc_dev,WIN2_DSP_ST3+off,val);
1006                 }else{
1007                         mask = m_WIN2_MST3_EN;
1008                         val  = v_WIN2_MST3_EN(0);
1009                         lcdc_msk_reg(lcdc_dev,WIN2_CTRL0+off,mask,val);
1010                         lcdc_writel(lcdc_dev, WIN2_MST3 + off,
1011                                     fb0->fix.smem_start);
1012                 }
1013
1014                 if(win->alpha_en == 1)
1015                         rk3288_lcdc_alpha_cfg(dev_drv,win_id);
1016                 else{
1017                         mask = m_WIN2_SRC_ALPHA_EN;
1018                         val = v_WIN2_SRC_ALPHA_EN(0);
1019                         lcdc_msk_reg(lcdc_dev,WIN2_SRC_ALPHA_CTRL+off,mask,val);
1020                 }
1021         }else{
1022                 mask =  m_WIN2_EN | m_WIN2_MST0_EN |
1023                         m_WIN2_MST0_EN | m_WIN2_MST2_EN |
1024                         m_WIN2_MST3_EN;
1025                 val  =  v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1026                         v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) |
1027                         v_WIN2_MST3_EN(0);
1028                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0+off, mask,val);
1029         }
1030         return 0;
1031 }
1032
1033 static int rk3288_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
1034 {
1035         struct lcdc_device *lcdc_dev =
1036             container_of(dev_drv, struct lcdc_device, driver);
1037         int timeout;
1038         unsigned long flags;
1039
1040         spin_lock(&lcdc_dev->reg_lock);
1041         if(likely(lcdc_dev->clk_on))
1042         {
1043                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1044                              v_STANDBY_EN(lcdc_dev->standby));
1045                 rk3288_win_0_1_reg_update(dev_drv,0);
1046                 rk3288_win_0_1_reg_update(dev_drv,1);
1047                 rk3288_win_2_3_reg_update(dev_drv,2);
1048                 rk3288_win_2_3_reg_update(dev_drv,3);
1049                 /*rk3288_lcdc_post_cfg(dev_drv);*/
1050                 lcdc_cfg_done(lcdc_dev);
1051         }
1052         spin_unlock(&lcdc_dev->reg_lock);
1053
1054         /*if (dev_drv->wait_fs) {*/
1055         if (0){
1056                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1057                 init_completion(&dev_drv->frame_done);
1058                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1059                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1060                                                       msecs_to_jiffies
1061                                                       (dev_drv->cur_screen->ft +
1062                                                        5));
1063                 if (!timeout && (!dev_drv->frame_done.done)) {
1064                         dev_warn(lcdc_dev->dev, "wait for new frame start time out!\n");
1065                         return -ETIMEDOUT;
1066                 }
1067         }
1068         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1069         return 0;
1070
1071 }
1072
1073 static int rk3288_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1074 {
1075         memcpy((u8 *) lcdc_dev->regs, (u8 *) lcdc_dev->regsbak, 0x1fc);
1076         return 0;
1077 }
1078 static int rk3288_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1079 {
1080         u32 mask,val;
1081         struct lcdc_device *lcdc_dev =
1082             container_of(dev_drv, struct lcdc_device, driver);
1083
1084         if (unlikely(!lcdc_dev->clk_on)) {
1085                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1086                 return 0;
1087         }
1088 #if defined(CONFIG_ROCKCHIP_IOMMU)
1089         if (dev_drv->iommu_enabled) {
1090                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1091
1092                 if (likely(lcdc_dev->clk_on)) {
1093                         spin_lock(&lcdc_dev->reg_lock);
1094                         mask = m_MMU_EN;
1095                         val = v_MMU_EN(1);
1096                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1097                         mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1098                         val = v_AXI_OUTSTANDING_MAX_NUM(31) | v_AXI_MAX_OUTSTANDING_EN(1);
1099                         lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1100                         spin_unlock(&lcdc_dev->reg_lock);
1101         }
1102                         lcdc_dev->iommu_status = 1;
1103                         rockchip_iovmm_activate(dev_drv->dev);
1104                 }
1105         }
1106 #endif
1107         return 0;
1108 }
1109
1110 static int rk3288_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1111 {
1112 #ifdef CONFIG_RK_FPGA
1113         return 0;
1114 #endif
1115         int ret = 0,fps;
1116         struct lcdc_device *lcdc_dev =
1117             container_of(dev_drv, struct lcdc_device, driver);
1118         struct rk_screen *screen = dev_drv->cur_screen;
1119
1120         if (reset_rate)
1121                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1122         if (ret)
1123                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1124         lcdc_dev->pixclock =
1125                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1126         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1127
1128         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1129         screen->ft = 1000 / fps;
1130         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1131                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1132         return 0;
1133
1134 }
1135
1136 static void rk3288_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1137 {
1138         struct lcdc_device *lcdc_dev =
1139             container_of(dev_drv, struct lcdc_device, driver);
1140         u32 bcsh_color_bar;
1141
1142         if (dev_drv->output_color == COLOR_RGB) {
1143                 bcsh_color_bar = lcdc_readl(lcdc_dev, BCSH_COLOR_BAR);
1144                 if (((bcsh_color_bar & m_BCSH_EN) == 1) ||
1145                     (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1146                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1147                                      m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1148                                      v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(1));
1149                 else
1150                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1151                                      m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1152                                      v_BCSH_R2Y_EN(0) | v_BCSH_Y2R_EN(0));
1153         } else {        /* RGB2YUV */
1154                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1155                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1156                              v_BCSH_R2Y_EN(1) | v_BCSH_Y2R_EN(0));
1157         }
1158 }
1159
1160 static int rk3288_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1161                                   u16 *yact, int *format, u32 *dsp_addr,
1162                                   int *ymirror)
1163 {
1164         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1165                                                     struct lcdc_device, driver);
1166         u32 val;
1167
1168         spin_lock(&lcdc_dev->reg_lock);
1169
1170         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1171         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1172         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1173
1174         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1175         *format = (val & m_WIN0_DATA_FMT) >> 1;
1176         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1177
1178         spin_unlock(&lcdc_dev->reg_lock);
1179
1180         return 0;
1181 }
1182
1183 static int rk3288_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1184                               int format, u16 xact, u16 yact, u16 xvir,
1185                               int ymirror)
1186 {
1187         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1188                                                     struct lcdc_device, driver);
1189         u32 val, mask;
1190         struct rk_lcdc_win *win = dev_drv->win[0];
1191         int swap = (format == RGB888) ? 1 : 0;
1192
1193         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1194         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1195         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1196
1197         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1198                         v_WIN0_VIR_STRIDE(xvir));
1199         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1200                     v_WIN0_ACT_HEIGHT(yact));
1201
1202         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1203
1204         lcdc_cfg_done(lcdc_dev);
1205         win->state = 1;
1206         win->last_state = 1;
1207
1208         return 0;
1209 }
1210
1211 static int rk3288_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1212 {
1213         u16 face = 0;
1214         u16 dclk_ddr = 0;
1215         u32 v=0;
1216         struct lcdc_device *lcdc_dev =
1217             container_of(dev_drv, struct lcdc_device, driver);
1218         struct rk_screen *screen = dev_drv->cur_screen;
1219         u16 hsync_len = screen->mode.hsync_len;
1220         u16 left_margin = screen->mode.left_margin;
1221         u16 right_margin = screen->mode.right_margin;
1222         u16 vsync_len = screen->mode.vsync_len;
1223         u16 upper_margin = screen->mode.upper_margin;
1224         u16 lower_margin = screen->mode.lower_margin;
1225         u16 x_res = screen->mode.xres;
1226         u16 y_res = screen->mode.yres;
1227         u32 mask, val;
1228         u16 h_total,v_total;
1229         int ret = 0;
1230         int hdmi_dclk_out_en = 0;
1231
1232         if (unlikely(!lcdc_dev->clk_on)) {
1233                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
1234                 return 0;
1235         }
1236
1237         h_total = hsync_len + left_margin  + x_res + right_margin;
1238         v_total = vsync_len + upper_margin + y_res + lower_margin;
1239
1240         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1241         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1242         screen->post_xsize = x_res * (screen->overscan.left + screen->overscan.right) / 200;
1243         screen->post_ysize = y_res * (screen->overscan.top + screen->overscan.bottom) / 200;
1244
1245         spin_lock(&lcdc_dev->reg_lock);
1246         if (likely(lcdc_dev->clk_on)) {
1247                 switch (screen->face) {
1248                 case OUT_P565:
1249                         face = OUT_P565;
1250                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1251                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1252                             m_PRE_DITHER_DOWN_EN;
1253                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1254                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1255                             v_PRE_DITHER_DOWN_EN(1);
1256                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1257                         break;
1258                 case OUT_P666:
1259                         face = OUT_P666;
1260                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1261                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1262                             m_PRE_DITHER_DOWN_EN;
1263                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1264                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1265                             v_PRE_DITHER_DOWN_EN(1);
1266                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1267                         break;
1268                 case OUT_D888_P565:
1269                         face = OUT_P888;
1270                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1271                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1272                             m_PRE_DITHER_DOWN_EN;
1273                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1274                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1275                             v_PRE_DITHER_DOWN_EN(1);
1276                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1277                         break;
1278                 case OUT_D888_P666:
1279                         face = OUT_P888;
1280                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1281                             m_DITHER_DOWN_SEL | m_DITHER_UP_EN |
1282                             m_PRE_DITHER_DOWN_EN;
1283                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1284                             v_DITHER_DOWN_SEL(1) | v_DITHER_UP_EN(1) |
1285                             v_PRE_DITHER_DOWN_EN(1);
1286                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1287                         break;
1288                 case OUT_P888:
1289                         face = OUT_P888;
1290                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1291                                 m_PRE_DITHER_DOWN_EN;
1292                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1293                             v_PRE_DITHER_DOWN_EN(1);
1294                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1295                         break;
1296                 case OUT_YUV_420:
1297                         hdmi_dclk_out_en = 1;
1298                         face = OUT_YUV_420;
1299                         dclk_ddr = 1;
1300                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1301                                 m_PRE_DITHER_DOWN_EN;
1302                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1303                             v_PRE_DITHER_DOWN_EN(1);
1304                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1305                         break;
1306                 case OUT_YUV_420_10BIT:
1307                         hdmi_dclk_out_en = 1;
1308                         face = OUT_YUV_420;
1309                         dclk_ddr = 1;
1310                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1311                                 m_PRE_DITHER_DOWN_EN;
1312                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1313                             v_PRE_DITHER_DOWN_EN(0);
1314                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1315                         break;
1316                 case OUT_P101010:
1317                         face = OUT_P101010;
1318                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN |
1319                                 m_PRE_DITHER_DOWN_EN;
1320                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(1) |
1321                             v_PRE_DITHER_DOWN_EN(0);
1322                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1323                         break;
1324                 default:
1325                         dev_err(lcdc_dev->dev,"un supported interface!\n");
1326                         break;
1327                 }
1328                 switch(screen->type){
1329                 case SCREEN_RGB:
1330                 case SCREEN_LVDS:
1331                 case SCREEN_DUAL_LVDS:
1332                 case SCREEN_LVDS_10BIT:
1333                 case SCREEN_DUAL_LVDS_10BIT:
1334                         mask = m_RGB_OUT_EN;
1335                         val = v_RGB_OUT_EN(1);
1336                         v = 1 << (3+16);
1337                         v |= (lcdc_dev->id << 3);
1338                         break;
1339                 case SCREEN_HDMI:
1340                         if ((screen->face == OUT_P888) ||
1341                             (screen->face == OUT_P101010))
1342                                 face = OUT_P101010;/*RGB 101010 output*/
1343                         mask = m_HDMI_OUT_EN;
1344                         val = v_HDMI_OUT_EN(1);
1345                         break;
1346                 case SCREEN_MIPI:
1347                         mask = m_MIPI_OUT_EN;
1348                         val = v_MIPI_OUT_EN(1);
1349                         break;
1350                 case SCREEN_DUAL_MIPI:
1351                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN;
1352                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1);
1353                         break;
1354                 case SCREEN_EDP:
1355                         face = OUT_P101010;  /*RGB 101010 output*/
1356                         mask = m_EDP_OUT_EN;
1357                         val = v_EDP_OUT_EN(1);
1358                         break;
1359                 }
1360                 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1361                         mask |= m_HDMI_DCLK_OUT_EN;
1362                         val |= v_HDMI_DCLK_OUT_EN(hdmi_dclk_out_en);
1363                 }
1364                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1365 #ifndef CONFIG_RK_FPGA
1366                 writel_relaxed(v, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
1367 #endif
1368                 mask = m_DSP_OUT_MODE | m_DSP_HSYNC_POL | m_DSP_VSYNC_POL |
1369                        m_DSP_DEN_POL | m_DSP_DCLK_POL | m_DSP_BG_SWAP |
1370                        m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1371                        m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1372                        m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN |
1373                        m_DSP_DCLK_DDR;
1374                 val = v_DSP_OUT_MODE(face) | v_DSP_HSYNC_POL(screen->pin_hsync) |
1375                       v_DSP_VSYNC_POL(screen->pin_vsync) |
1376                       v_DSP_DEN_POL(screen->pin_den) | v_DSP_DCLK_POL(screen->pin_dclk) |
1377                       v_DSP_BG_SWAP(screen->swap_gb) | v_DSP_RB_SWAP(screen->swap_rb) |
1378                       v_DSP_RG_SWAP(screen->swap_rg) |
1379                       v_DSP_DELTA_SWAP(screen->swap_delta) |
1380                       v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1381                       v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1382                       v_DSP_X_MIR_EN(screen->x_mirror) |
1383                       v_DSP_Y_MIR_EN(screen->y_mirror) |
1384                       v_DSP_DCLK_DDR(dclk_ddr);
1385                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1386
1387                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1388                 val  = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1389                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1390
1391                 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1392                 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1393                 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1394
1395                 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1396                 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1397                     v_DSP_HACT_ST(hsync_len + left_margin);
1398                 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1399
1400                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1401                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1402                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1403
1404                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1405                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1406                     v_DSP_VACT_ST(vsync_len + upper_margin);
1407                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1408
1409                 rk3288_lcdc_post_cfg(dev_drv);
1410                 mask = m_DSP_LINE_FLAG_NUM;
1411                 val = v_DSP_LINE_FLAG_NUM(vsync_len + upper_margin + y_res);
1412                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1413                 dev_drv->output_color = screen->color_mode;
1414                 if (dev_drv->version == VOP_FULL_RK3288_V1_1) {
1415                         rk3288_lcdc_bcsh_path_sel(dev_drv);
1416                 } else {
1417                         if (dev_drv->output_color != COLOR_RGB) {
1418                                 pr_err("vop ver:%x,unsupport output color:%d\n",
1419                                        dev_drv->version, dev_drv->output_color);
1420                                 ret = -1;
1421                         }
1422                 }
1423         }
1424         spin_unlock(&lcdc_dev->reg_lock);
1425         rk3288_lcdc_set_dclk(dev_drv, 1);
1426         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1427             dev_drv->trsm_ops->enable)
1428                 dev_drv->trsm_ops->enable();
1429         if (screen->init)
1430                 screen->init();
1431
1432         return ret;
1433 }
1434
1435 /*enable layer,open:1,enable;0 disable*/
1436 static int win0_open(struct lcdc_device *lcdc_dev, bool open)
1437 {
1438         spin_lock(&lcdc_dev->reg_lock);
1439         if (likely(lcdc_dev->clk_on)) {
1440                 if (open) {
1441                         if (!lcdc_dev->atv_layer_cnt) {
1442                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1443                                 lcdc_dev->standby = 0;
1444                         }
1445                         lcdc_dev->atv_layer_cnt++;
1446                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1447                         lcdc_dev->atv_layer_cnt--;
1448                 }
1449                 lcdc_dev->driver.win[0]->state = open;
1450                 if (!lcdc_dev->atv_layer_cnt) {
1451                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1452                         lcdc_dev->standby = 1;
1453                 }
1454         }
1455         spin_unlock(&lcdc_dev->reg_lock);
1456
1457         return 0;
1458 }
1459
1460 static int win1_open(struct lcdc_device *lcdc_dev, bool open)
1461 {
1462         spin_lock(&lcdc_dev->reg_lock);
1463         if (likely(lcdc_dev->clk_on)) {
1464                 if (open) {
1465                         if (!lcdc_dev->atv_layer_cnt) {
1466                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1467                                 lcdc_dev->standby = 0;
1468                         }
1469                         lcdc_dev->atv_layer_cnt++;
1470                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1471                         lcdc_dev->atv_layer_cnt--;
1472                 }
1473                 lcdc_dev->driver.win[1]->state = open;
1474
1475                 /*if no layer used,disable lcdc*/
1476                 if (!lcdc_dev->atv_layer_cnt) {
1477                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1478                         lcdc_dev->standby = 1;
1479                 }
1480         }
1481         spin_unlock(&lcdc_dev->reg_lock);
1482
1483         return 0;
1484 }
1485
1486 static int win2_open(struct lcdc_device *lcdc_dev, bool open)
1487 {
1488         spin_lock(&lcdc_dev->reg_lock);
1489         if (likely(lcdc_dev->clk_on)) {
1490                 if (open) {
1491                         if (!lcdc_dev->atv_layer_cnt) {
1492                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1493                                 lcdc_dev->standby = 0;
1494                         }
1495                         lcdc_dev->atv_layer_cnt++;
1496                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1497                         lcdc_dev->atv_layer_cnt--;
1498                 }
1499                 lcdc_dev->driver.win[2]->state = open;
1500
1501                 /*if no layer used,disable lcdc*/
1502                 if (!lcdc_dev->atv_layer_cnt) {
1503                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1504                         lcdc_dev->standby = 1;
1505                 }
1506         }
1507         spin_unlock(&lcdc_dev->reg_lock);
1508
1509         return 0;
1510 }
1511
1512 static int win3_open(struct lcdc_device *lcdc_dev, bool open)
1513 {
1514         spin_lock(&lcdc_dev->reg_lock);
1515         if (likely(lcdc_dev->clk_on)) {
1516                 if (open) {
1517                         if (!lcdc_dev->atv_layer_cnt) {
1518                                 dev_info(lcdc_dev->dev, "wakeup from standby!\n");
1519                                 lcdc_dev->standby = 0;
1520                         }
1521                         lcdc_dev->atv_layer_cnt++;
1522                 } else if ((lcdc_dev->atv_layer_cnt > 0) && (!open)) {
1523                         lcdc_dev->atv_layer_cnt--;
1524                 }
1525                 lcdc_dev->driver.win[3]->state = open;
1526
1527                 /*if no layer used,disable lcdc*/
1528                 if (!lcdc_dev->atv_layer_cnt) {
1529                         dev_info(lcdc_dev->dev, "no layer is used,go to standby!\n");
1530                         lcdc_dev->standby = 1;
1531                 }
1532         }
1533         spin_unlock(&lcdc_dev->reg_lock);
1534
1535         return 0;
1536 }
1537 static int rk3288_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1538 {
1539         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1540                                         struct lcdc_device, driver);
1541         u32 mask,val;
1542
1543         mask = m_FS_INTR_CLR | m_FS_INTR_EN | m_LINE_FLAG_INTR_CLR |
1544                             m_LINE_FLAG_INTR_EN | m_BUS_ERROR_INTR_CLR |
1545                             m_BUS_ERROR_INTR_EN;
1546         val = v_FS_INTR_CLR(1) | v_FS_INTR_EN(1) | v_LINE_FLAG_INTR_CLR(1) |
1547             v_LINE_FLAG_INTR_EN(1) | v_BUS_ERROR_INTR_CLR(1) | v_BUS_ERROR_INTR_EN(0);
1548         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, mask, val);
1549 #ifdef LCDC_IRQ_EMPTY_DEBUG
1550                  mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN | m_WIN2_EMPTY_INTR_EN |
1551                          m_WIN3_EMPTY_INTR_EN |m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
1552                          m_PWM_GEN_INTR_EN;
1553                  val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) | v_WIN2_EMPTY_INTR_EN(1) |
1554                          v_WIN3_EMPTY_INTR_EN(1)| v_HWC_EMPTY_INTR_EN(1) | v_POST_BUF_EMPTY_INTR_EN(1) |
1555                          v_PWM_GEN_INTR_EN(1);
1556                  lcdc_msk_reg(lcdc_dev, INTR_CTRL1, mask, val);
1557 #endif
1558         return 0;
1559 }
1560
1561 static int rk3288_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1562                             bool open)
1563 {
1564         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1565                                         struct lcdc_device, driver);
1566         int sys_status = (dev_drv->id == 0) ?
1567                         SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1568
1569         /*enable clk,when first layer open */
1570         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1571                 rockchip_set_system_status(sys_status);
1572                 rk3288_lcdc_pre_init(dev_drv);
1573                 rk3288_lcdc_clk_enable(lcdc_dev);
1574                 rk3288_lcdc_enable_irq(dev_drv);
1575 #if defined(CONFIG_ROCKCHIP_IOMMU)
1576                 if (dev_drv->iommu_enabled) {
1577                         if (!dev_drv->mmu_dev) {
1578                                 dev_drv->mmu_dev =
1579                                         rk_fb_get_sysmmu_device_by_compatible(dev_drv->mmu_dts_name);
1580                                 if (dev_drv->mmu_dev) {
1581                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
1582                                                                   dev_drv->dev);
1583                                 } else {
1584                                         dev_err(dev_drv->dev,
1585                                                 "failed to get rockchip iommu device\n");
1586                                         return -1;
1587                                 }
1588                         }
1589                 }
1590 #endif
1591                 rk3288_lcdc_reg_restore(lcdc_dev);
1592                 /*if (dev_drv->iommu_enabled)
1593                    rk3368_lcdc_mmu_en(dev_drv); */
1594                 if ((support_uboot_display()&&(lcdc_dev->prop == PRMRY))) {
1595                         rk3288_lcdc_set_dclk(dev_drv, 0);
1596                         /* rk3288_lcdc_enable_irq(dev_drv); */
1597                 } else {
1598                         rk3288_load_screen(dev_drv, 1);
1599                 }
1600                 if (dev_drv->bcsh.enable)
1601                         rk3288_lcdc_set_bcsh(dev_drv, 1);
1602                 spin_lock(&lcdc_dev->reg_lock);
1603                 rk3288_lcdc_set_lut(dev_drv);
1604                 spin_unlock(&lcdc_dev->reg_lock);
1605         }
1606
1607         if (win_id == 0)
1608                 win0_open(lcdc_dev, open);
1609         else if (win_id == 1)
1610                 win1_open(lcdc_dev, open);
1611         else if (win_id == 2)
1612                 win2_open(lcdc_dev, open);
1613         else if (win_id == 3)
1614                 win3_open(lcdc_dev, open);
1615         else
1616                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1617
1618         /* when all layer closed,disable clk */
1619         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1620                 rk3288_lcdc_disable_irq(lcdc_dev);
1621                 rk3288_lcdc_reg_update(dev_drv);
1622 #if defined(CONFIG_ROCKCHIP_IOMMU)
1623                 if (dev_drv->iommu_enabled) {
1624                         if (dev_drv->mmu_dev) {
1625                                 rockchip_iovmm_deactivate(dev_drv->dev);
1626                                 lcdc_dev->iommu_status = 0;
1627                         }
1628                 }
1629 #endif
1630                 rk3288_lcdc_clk_disable(lcdc_dev);
1631                 rockchip_clear_system_status(sys_status);
1632         }
1633
1634         return 0;
1635 }
1636
1637 static int win0_display(struct lcdc_device *lcdc_dev,
1638                         struct rk_lcdc_win *win)
1639 {
1640         u32 y_addr;
1641         u32 uv_addr;
1642         y_addr = win->area[0].smem_start+win->area[0].y_offset;/*win->smem_start + win->y_offset;*/
1643         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1644         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
1645             lcdc_dev->id, __func__, y_addr, uv_addr,win->area[0].y_offset);
1646         spin_lock(&lcdc_dev->reg_lock);
1647         if (likely(lcdc_dev->clk_on)) {
1648                 win->area[0].y_addr = y_addr;
1649                 win->area[0].uv_addr = uv_addr;
1650                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, win->area[0].y_addr);
1651                 lcdc_writel(lcdc_dev, WIN0_CBR_MST, win->area[0].uv_addr);
1652                 /*lcdc_cfg_done(lcdc_dev);*/
1653         }
1654         spin_unlock(&lcdc_dev->reg_lock);
1655
1656         return 0;
1657
1658 }
1659
1660 static int win1_display(struct lcdc_device *lcdc_dev,
1661                         struct rk_lcdc_win *win)
1662 {
1663         u32 y_addr;
1664         u32 uv_addr;
1665         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1666         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1667         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>uv_addr:0x%x\n",
1668             lcdc_dev->id, __func__, y_addr, uv_addr);
1669
1670         spin_lock(&lcdc_dev->reg_lock);
1671         if (likely(lcdc_dev->clk_on)) {
1672                 win->area[0].y_addr = y_addr;
1673                 win->area[0].uv_addr = uv_addr;
1674                 lcdc_writel(lcdc_dev, WIN1_YRGB_MST, win->area[0].y_addr);
1675                 lcdc_writel(lcdc_dev, WIN1_CBR_MST, win->area[0].uv_addr);
1676         }
1677         spin_unlock(&lcdc_dev->reg_lock);
1678
1679
1680         return 0;
1681 }
1682
1683 static int win2_display(struct lcdc_device *lcdc_dev,
1684                         struct rk_lcdc_win *win)
1685 {
1686         u32 i,y_addr;
1687         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1688         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1689             lcdc_dev->id, __func__, y_addr);
1690
1691         spin_lock(&lcdc_dev->reg_lock);
1692         if (likely(lcdc_dev->clk_on)){
1693                 for(i=0;i<win->area_num;i++)
1694                         win->area[i].y_addr =
1695                                 win->area[i].smem_start + win->area[i].y_offset;
1696                         if (win->area[0].state)
1697                                 lcdc_writel(lcdc_dev, WIN2_MST0,
1698                                             win->area[0].y_addr);
1699                         if (win->area[1].state)
1700                                 lcdc_writel(lcdc_dev, WIN2_MST1,
1701                                             win->area[1].y_addr);
1702                         if (win->area[2].state)
1703                                 lcdc_writel(lcdc_dev, WIN2_MST2,
1704                                             win->area[2].y_addr);
1705                         if (win->area[3].state)
1706                                 lcdc_writel(lcdc_dev, WIN2_MST3,
1707                                             win->area[3].y_addr);
1708         }
1709         spin_unlock(&lcdc_dev->reg_lock);
1710         return 0;
1711 }
1712
1713 static int win3_display(struct lcdc_device *lcdc_dev,
1714                         struct rk_lcdc_win *win)
1715 {
1716         u32 i,y_addr;
1717         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1718         DBG(2, "lcdc%d>>%s>>y_addr:0x%x>>\n",
1719             lcdc_dev->id, __func__, y_addr);
1720
1721         spin_lock(&lcdc_dev->reg_lock);
1722         if (likely(lcdc_dev->clk_on)){
1723                 for(i=0;i<win->area_num;i++)
1724                         win->area[i].y_addr =
1725                                 win->area[i].smem_start + win->area[i].y_offset;
1726                         if (win->area[0].state)
1727                                 lcdc_writel(lcdc_dev, WIN3_MST0,
1728                                             win->area[0].y_addr);
1729                         if (win->area[1].state)
1730                                 lcdc_writel(lcdc_dev, WIN3_MST1,
1731                                             win->area[1].y_addr);
1732                         if (win->area[2].state)
1733                                 lcdc_writel(lcdc_dev, WIN3_MST2,
1734                                             win->area[2].y_addr);
1735                         if (win->area[3].state)
1736                                 lcdc_writel(lcdc_dev, WIN3_MST3,
1737                                             win->area[3].y_addr);
1738                 }
1739         spin_unlock(&lcdc_dev->reg_lock);
1740         return 0;
1741 }
1742
1743 static int rk3288_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
1744 {
1745         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1746                                 struct lcdc_device, driver);
1747         struct rk_lcdc_win *win = NULL;
1748         struct rk_screen *screen = dev_drv->cur_screen;
1749
1750 #if defined(WAIT_FOR_SYNC)
1751         int timeout;
1752         unsigned long flags;
1753 #endif
1754         win = dev_drv->win[win_id];
1755         if (!screen) {
1756                 dev_err(dev_drv->dev, "screen is null!\n");
1757                 return -ENOENT;
1758         }
1759         if(win_id == 0){
1760                 win0_display(lcdc_dev, win);
1761         }else if(win_id == 1){
1762                 win1_display(lcdc_dev, win);
1763         }else if(win_id == 2){
1764                 win2_display(lcdc_dev, win);
1765         }else if(win_id == 3){
1766                 win3_display(lcdc_dev, win);
1767         }else{
1768                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1769                 return -EINVAL;
1770         }
1771
1772         /*this is the first frame of the system ,enable frame start interrupt */
1773         if ((dev_drv->first_frame)) {
1774                 dev_drv->first_frame = 0;
1775                 rk3288_lcdc_enable_irq(dev_drv);
1776         }
1777 #if defined(WAIT_FOR_SYNC)
1778         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1779         init_completion(&dev_drv->frame_done);
1780         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1781         timeout = wait_for_completion_timeout(&dev_drv->frame_done,
1782                                               msecs_to_jiffies(dev_drv->
1783                                                                cur_screen->ft +
1784                                                                5));
1785         if (!timeout && (!dev_drv->frame_done.done)) {
1786                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
1787                 return -ETIMEDOUT;
1788         }
1789 #endif
1790         return 0;
1791 }
1792
1793 static int rk3288_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
1794 {
1795         u16 srcW;
1796         u16 srcH;
1797         u16 dstW;
1798         u16 dstH;
1799         u16 yrgb_srcW;
1800         u16 yrgb_srcH;
1801         u16 yrgb_dstW;
1802         u16 yrgb_dstH;
1803         u32 yrgb_vScaleDnMult;
1804         u32 yrgb_xscl_factor;
1805         u32 yrgb_yscl_factor;
1806         u8  yrgb_vsd_bil_gt2=0;
1807         u8  yrgb_vsd_bil_gt4=0;
1808
1809         u16 cbcr_srcW;
1810         u16 cbcr_srcH;
1811         u16 cbcr_dstW;
1812         u16 cbcr_dstH;
1813         u32 cbcr_vScaleDnMult;
1814         u32 cbcr_xscl_factor;
1815         u32 cbcr_yscl_factor;
1816         u8  cbcr_vsd_bil_gt2=0;
1817         u8  cbcr_vsd_bil_gt4=0;
1818         u8  yuv_fmt=0;
1819
1820
1821         srcW = win->area[0].xact;
1822         srcH = win->area[0].yact;
1823         dstW = win->area[0].xsize;
1824         dstH = win->area[0].ysize;
1825
1826         /*yrgb scl mode*/
1827         yrgb_srcW = srcW;
1828         yrgb_srcH = srcH;
1829         yrgb_dstW = dstW;
1830         yrgb_dstH = dstH;
1831         if ((yrgb_dstW*8 <= yrgb_srcW) || (yrgb_dstH*8 <= yrgb_srcH)) {
1832                 pr_err("ERROR: yrgb scale exceed 8,"
1833                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1834                        yrgb_srcW,yrgb_srcH,yrgb_dstW,yrgb_dstH);
1835         }
1836         if(yrgb_srcW < yrgb_dstW){
1837                 win->yrgb_hor_scl_mode = SCALE_UP;
1838         }else if(yrgb_srcW > yrgb_dstW){
1839                 win->yrgb_hor_scl_mode = SCALE_DOWN;
1840         }else{
1841                 win->yrgb_hor_scl_mode = SCALE_NONE;
1842         }
1843
1844         if(yrgb_srcH < yrgb_dstH){
1845                 win->yrgb_ver_scl_mode = SCALE_UP;
1846         }else if (yrgb_srcH  > yrgb_dstH){
1847                 win->yrgb_ver_scl_mode = SCALE_DOWN;
1848         }else{
1849                 win->yrgb_ver_scl_mode = SCALE_NONE;
1850         }
1851
1852         /*cbcr scl mode*/
1853         switch (win->area[0].format) {
1854         case YUV422:
1855         case YUV422_A:
1856                 cbcr_srcW = srcW/2;
1857                 cbcr_dstW = dstW;
1858                 cbcr_srcH = srcH;
1859                 cbcr_dstH = dstH;
1860                 yuv_fmt = 1;
1861                 break;
1862         case YUV420:
1863         case YUV420_A:
1864                 cbcr_srcW = srcW/2;
1865                 cbcr_dstW = dstW;
1866                 cbcr_srcH = srcH/2;
1867                 cbcr_dstH = dstH;
1868                 yuv_fmt = 1;
1869                 break;
1870         case YUV444:
1871         case YUV444_A:
1872                 cbcr_srcW = srcW;
1873                 cbcr_dstW = dstW;
1874                 cbcr_srcH = srcH;
1875                 cbcr_dstH = dstH;
1876                 yuv_fmt = 1;
1877                 break;
1878         default:
1879                 cbcr_srcW = 0;
1880                 cbcr_dstW = 0;
1881                 cbcr_srcH = 0;
1882                 cbcr_dstH = 0;
1883                 yuv_fmt = 0;
1884                 break;
1885         }
1886         if (yuv_fmt) {
1887                 if ((cbcr_dstW*8 <= cbcr_srcW) || (cbcr_dstH*8 <= cbcr_srcH)) {
1888                         pr_err("ERROR: cbcr scale exceed 8,"
1889                        "srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
1890                        cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH);
1891                 }
1892         }
1893
1894         if(cbcr_srcW < cbcr_dstW){
1895                 win->cbr_hor_scl_mode = SCALE_UP;
1896         }else if(cbcr_srcW > cbcr_dstW){
1897                 win->cbr_hor_scl_mode = SCALE_DOWN;
1898         }else{
1899                 win->cbr_hor_scl_mode = SCALE_NONE;
1900         }
1901
1902         if(cbcr_srcH < cbcr_dstH){
1903                 win->cbr_ver_scl_mode = SCALE_UP;
1904         }else if(cbcr_srcH > cbcr_dstH){
1905                 win->cbr_ver_scl_mode = SCALE_DOWN;
1906         }else{
1907                 win->cbr_ver_scl_mode = SCALE_NONE;
1908         }
1909         DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
1910                "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1911                "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
1912                 ,srcW,srcH,dstW,dstH,yrgb_srcW,yrgb_srcH,yrgb_dstW,
1913                 yrgb_dstH,win->yrgb_hor_scl_mode,win->yrgb_ver_scl_mode,
1914                 cbcr_srcW,cbcr_srcH,cbcr_dstW,cbcr_dstH,
1915                 win->cbr_hor_scl_mode,win->cbr_ver_scl_mode);
1916
1917     /*line buffer mode*/
1918         if ((win->area[0].format == YUV422) ||
1919             (win->area[0].format == YUV420) ||
1920             (win->area[0].format == YUV422_A) ||
1921             (win->area[0].format == YUV420_A)) {
1922                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
1923                         if ((cbcr_dstW > 3840) || (cbcr_dstW == 0)) {
1924                                 pr_err("ERROR cbcr_dstW = %d\n",cbcr_dstW);
1925                         } else if (cbcr_dstW > 2560) {
1926                                 win->win_lb_mode = LB_RGB_3840X2;
1927                         } else if (cbcr_dstW > 1920) {
1928                                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
1929                                         if(yrgb_dstW > 3840){
1930                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1931                                         }else if(yrgb_dstW > 2560){
1932                                                 win->win_lb_mode = LB_RGB_3840X2;
1933                                         }else if(yrgb_dstW > 1920){
1934                                                 win->win_lb_mode = LB_RGB_2560X4;
1935                                         }else{
1936                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1937                                         }
1938                                 }
1939                         } else if (cbcr_dstW > 1280) {
1940                                 win->win_lb_mode = LB_YUV_3840X5;
1941                         } else {
1942                                 win->win_lb_mode = LB_YUV_2560X8;
1943                         }
1944                 } else { /*SCALE_UP or SCALE_NONE*/
1945                         if ((cbcr_srcW > 3840) || (cbcr_srcW == 0)) {
1946                                 pr_err("ERROR cbcr_srcW = %d\n",cbcr_srcW);
1947                         }else if(cbcr_srcW > 2560){
1948                                 win->win_lb_mode = LB_RGB_3840X2;
1949                         }else if(cbcr_srcW > 1920){
1950                                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1951                                         if(yrgb_dstW > 3840){
1952                                                 pr_err("ERROR yrgb_dst_width exceeds 3840\n");
1953                                         }else if(yrgb_dstW > 2560){
1954                                                 win->win_lb_mode = LB_RGB_3840X2;
1955                                         }else if(yrgb_dstW > 1920){
1956                                                 win->win_lb_mode = LB_RGB_2560X4;
1957                                         }else{
1958                                                 pr_err("ERROR never run here!yrgb_dstW<1920 ==> cbcr_dstW>1920\n");
1959                                         }
1960                                 }
1961                         }else if(cbcr_srcW > 1280){
1962                                  win->win_lb_mode = LB_YUV_3840X5;
1963                         }else{
1964                                 win->win_lb_mode = LB_YUV_2560X8;
1965                         }
1966                 }
1967         }else {
1968                 if(win->yrgb_hor_scl_mode == SCALE_DOWN){
1969                         if ((yrgb_dstW > 3840) || (yrgb_dstW == 0)) {
1970                                 pr_err("ERROR yrgb_dstW = %d\n",yrgb_dstW);
1971                         }else if(yrgb_dstW > 2560){
1972                                 win->win_lb_mode = LB_RGB_3840X2;
1973                         }else if(yrgb_dstW > 1920){
1974                                 win->win_lb_mode = LB_RGB_2560X4;
1975                         }else if(yrgb_dstW > 1280){
1976                                 win->win_lb_mode = LB_RGB_1920X5;
1977                         }else{
1978                                 win->win_lb_mode = LB_RGB_1280X8;
1979                         }
1980                 }else{ /*SCALE_UP or SCALE_NONE*/
1981                         if ((yrgb_srcW > 3840) || (yrgb_srcW == 0)) {
1982                                 pr_err("ERROR yrgb_srcW = %d\n",yrgb_srcW);
1983                         }else if(yrgb_srcW > 2560){
1984                                 win->win_lb_mode = LB_RGB_3840X2;
1985                         }else if(yrgb_srcW > 1920){
1986                                 win->win_lb_mode = LB_RGB_2560X4;
1987                         }else if(yrgb_srcW > 1280){
1988                                 win->win_lb_mode = LB_RGB_1920X5;
1989                         }else{
1990                                 win->win_lb_mode = LB_RGB_1280X8;
1991                         }
1992                 }
1993         }
1994         DBG(1,"win->win_lb_mode = %d;\n",win->win_lb_mode);
1995
1996         /*vsd/vsu scale ALGORITHM*/
1997         win->yrgb_hsd_mode = SCALE_DOWN_BIL;/*not to specify*/
1998         win->cbr_hsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
1999         win->yrgb_vsd_mode = SCALE_DOWN_BIL;/*not to specify*/
2000         win->cbr_vsd_mode  = SCALE_DOWN_BIL;/*not to specify*/
2001         switch(win->win_lb_mode){
2002             case LB_YUV_3840X5:
2003             case LB_YUV_2560X8:
2004             case LB_RGB_1920X5:
2005             case LB_RGB_1280X8:
2006                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2007                 win->cbr_vsu_mode  = SCALE_UP_BIC;
2008                 break;
2009             case LB_RGB_3840X2:
2010                 if(win->yrgb_ver_scl_mode != SCALE_NONE) {
2011                     pr_err("ERROR : not allow yrgb ver scale\n");
2012                 }
2013                 if(win->cbr_ver_scl_mode != SCALE_NONE) {
2014                     pr_err("ERROR : not allow cbcr ver scale\n");
2015                 }
2016                 break;
2017             case LB_RGB_2560X4:
2018                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2019                 win->cbr_vsu_mode  = SCALE_UP_BIL;
2020                 break;
2021             default:
2022                 printk(KERN_WARNING "%s:un supported win_lb_mode:%d\n",
2023                         __func__,win->win_lb_mode);
2024                 break;
2025         }
2026         DBG(1,"yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2027                win->yrgb_hsd_mode,win->yrgb_vsd_mode,win->yrgb_vsu_mode,
2028                win->cbr_hsd_mode,win->cbr_vsd_mode,win->cbr_vsu_mode);
2029
2030         /*SCALE FACTOR*/
2031
2032         /*(1.1)YRGB HOR SCALE FACTOR*/
2033         switch(win->yrgb_hor_scl_mode){
2034         case SCALE_NONE:
2035                 yrgb_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2036                 break;
2037         case SCALE_UP  :
2038                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2039                 break;
2040         case SCALE_DOWN:
2041                 switch(win->yrgb_hsd_mode)
2042                 {
2043                 case SCALE_DOWN_BIL:
2044                         yrgb_xscl_factor = GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2045                         break;
2046                 case SCALE_DOWN_AVG:
2047                         yrgb_xscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2048                         break;
2049                 default :
2050                         printk(KERN_WARNING "%s:un supported yrgb_hsd_mode:%d\n",
2051                                 __func__,win->yrgb_hsd_mode);
2052                         break;
2053                 }
2054                 break;
2055         default :
2056                 printk(KERN_WARNING "%s:un supported yrgb_hor_scl_mode:%d\n",
2057                                 __func__,win->yrgb_hor_scl_mode);
2058             break;
2059         } /*win->yrgb_hor_scl_mode*/
2060
2061         /*(1.2)YRGB VER SCALE FACTOR*/
2062         switch(win->yrgb_ver_scl_mode)
2063         {
2064         case SCALE_NONE:
2065                 yrgb_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2066                  break;
2067         case SCALE_UP  :
2068                 switch(win->yrgb_vsu_mode)
2069                 {
2070                 case SCALE_UP_BIL:
2071                         yrgb_yscl_factor = GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2072                         break;
2073                 case SCALE_UP_BIC:
2074                         if(yrgb_srcH < 3){
2075                                 pr_err("yrgb_srcH should be greater than 3 !!!\n");
2076                         }
2077                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH, yrgb_dstH);
2078                         break;
2079                 default :
2080                         printk(KERN_WARNING "%s:un supported yrgb_vsu_mode:%d\n",
2081                                 __func__,win->yrgb_vsu_mode);
2082                         break;
2083             }
2084             break;
2085         case SCALE_DOWN:
2086                 switch(win->yrgb_vsd_mode)
2087                 {
2088                 case SCALE_DOWN_BIL:
2089                         yrgb_vScaleDnMult = getHardWareVSkipLines(yrgb_srcH, yrgb_dstH);
2090                         yrgb_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH, yrgb_vScaleDnMult);
2091                         if(yrgb_vScaleDnMult == 4){
2092                                 yrgb_vsd_bil_gt4 = 1;
2093                                 yrgb_vsd_bil_gt2 = 0;
2094                         }else if(yrgb_vScaleDnMult == 2){
2095                                 yrgb_vsd_bil_gt4 = 0;
2096                                 yrgb_vsd_bil_gt2 = 1;
2097                         }else{
2098                                 yrgb_vsd_bil_gt4 = 0;
2099                                 yrgb_vsd_bil_gt2 = 0;
2100                         }
2101                         break;
2102                 case SCALE_DOWN_AVG:
2103                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH, yrgb_dstH);
2104                         break;
2105                 default:
2106                         printk(KERN_WARNING "%s:un supported yrgb_vsd_mode:%d\n",
2107                                 __func__,win->yrgb_vsd_mode);
2108                         break;
2109                 } /*win->yrgb_vsd_mode*/
2110                 break;
2111         default :
2112                 printk(KERN_WARNING "%s:un supported yrgb_ver_scl_mode:%d\n",
2113                         __func__,win->yrgb_ver_scl_mode);
2114                 break;
2115         }
2116         win->scale_yrgb_x = yrgb_xscl_factor;
2117         win->scale_yrgb_y = yrgb_yscl_factor;
2118         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2119         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2120         DBG(1,"yrgb:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",yrgb_xscl_factor,
2121                 yrgb_yscl_factor,yrgb_vsd_bil_gt4,yrgb_vsd_bil_gt2);
2122
2123         /*(2.1)CBCR HOR SCALE FACTOR*/
2124         switch(win->cbr_hor_scl_mode)
2125         {
2126         case SCALE_NONE:
2127                 cbcr_xscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2128                 break;
2129         case SCALE_UP  :
2130                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2131                 break;
2132         case SCALE_DOWN:
2133                 switch(win->cbr_hsd_mode)
2134                 {
2135                 case SCALE_DOWN_BIL:
2136                         cbcr_xscl_factor = GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2137                         break;
2138                 case SCALE_DOWN_AVG:
2139                         cbcr_xscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2140                         break;
2141                 default :
2142                         printk(KERN_WARNING "%s:un supported cbr_hsd_mode:%d\n",
2143                                 __func__,win->cbr_hsd_mode);
2144                         break;
2145                 }
2146                 break;
2147         default :
2148                 printk(KERN_WARNING "%s:un supported cbr_hor_scl_mode:%d\n",
2149                         __func__,win->cbr_hor_scl_mode);
2150                 break;
2151         } /*win->cbr_hor_scl_mode*/
2152
2153         /*(2.2)CBCR VER SCALE FACTOR*/
2154         switch(win->cbr_ver_scl_mode)
2155         {
2156         case SCALE_NONE:
2157                 cbcr_yscl_factor = (1<<SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2158                 break;
2159         case SCALE_UP  :
2160                 switch(win->cbr_vsu_mode)
2161                 {
2162                 case SCALE_UP_BIL:
2163                         cbcr_yscl_factor = GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2164                         break;
2165                 case SCALE_UP_BIC:
2166                         if(cbcr_srcH < 3) {
2167                                 pr_err("cbcr_srcH should be greater than 3 !!!\n");
2168                         }
2169                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH, cbcr_dstH);
2170                         break;
2171                 default :
2172                         printk(KERN_WARNING "%s:un supported cbr_vsu_mode:%d\n",
2173                                 __func__,win->cbr_vsu_mode);
2174                         break;
2175                 }
2176                 break;
2177         case SCALE_DOWN:
2178                 switch(win->cbr_vsd_mode)
2179                 {
2180                 case SCALE_DOWN_BIL:
2181                         cbcr_vScaleDnMult = getHardWareVSkipLines(cbcr_srcH, cbcr_dstH);
2182                         cbcr_yscl_factor  = GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH, cbcr_vScaleDnMult);
2183                         if(cbcr_vScaleDnMult == 4){
2184                                 cbcr_vsd_bil_gt4 = 1;
2185                                 cbcr_vsd_bil_gt2 = 0;
2186                         }else if(cbcr_vScaleDnMult == 2){
2187                                 cbcr_vsd_bil_gt4 = 0;
2188                                 cbcr_vsd_bil_gt2 = 1;
2189                         }else{
2190                                 cbcr_vsd_bil_gt4 = 0;
2191                                 cbcr_vsd_bil_gt2 = 0;
2192                         }
2193                         break;
2194                 case SCALE_DOWN_AVG:
2195                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH, cbcr_dstH);
2196                         break;
2197                 default :
2198                         printk(KERN_WARNING "%s:un supported cbr_vsd_mode:%d\n",
2199                                 __func__,win->cbr_vsd_mode);
2200                     break;
2201                 }
2202                 break;
2203         default :
2204                 printk(KERN_WARNING "%s:un supported cbr_ver_scl_mode:%d\n",
2205                         __func__,win->cbr_ver_scl_mode);
2206                 break;
2207         }
2208         win->scale_cbcr_x = cbcr_xscl_factor;
2209         win->scale_cbcr_y = cbcr_yscl_factor;
2210         win->vsd_cbr_gt4  = cbcr_vsd_bil_gt4;
2211         win->vsd_cbr_gt2  = cbcr_vsd_bil_gt2;
2212
2213         DBG(1,"cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n",cbcr_xscl_factor,
2214                 cbcr_yscl_factor,cbcr_vsd_bil_gt4,cbcr_vsd_bil_gt2);
2215         return 0;
2216 }
2217
2218
2219
2220 static int win0_set_par(struct lcdc_device *lcdc_dev,
2221                         struct rk_screen *screen, struct rk_lcdc_win *win)
2222 {
2223         u32 xact,yact,xvir, yvir,xpos, ypos;
2224         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2225         char fmt[9] = "NULL";
2226
2227         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2228         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2229
2230         spin_lock(&lcdc_dev->reg_lock);
2231         if(likely(lcdc_dev->clk_on)){
2232                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2233                 switch (win->area[0].format) {
2234                 case ARGB888:
2235                         fmt_cfg = 0;
2236                         swap_rb = 0;
2237                         win->fmt_10 = 0;
2238                         break;
2239                 case XBGR888:
2240                 case ABGR888:
2241                         fmt_cfg = 0;
2242                         swap_rb = 1;
2243                         win->fmt_10 = 0;
2244                         break;
2245                 case RGB888:
2246                         fmt_cfg = 1;
2247                         swap_rb = 0;
2248                         win->fmt_10 = 0;
2249                         break;
2250                 case RGB565:
2251                         fmt_cfg = 2;
2252                         swap_rb = 0;
2253                         win->fmt_10 = 0;
2254                         break;
2255                 case YUV422:
2256                         fmt_cfg = 5;
2257                         swap_rb = 0;
2258                         win->fmt_10 = 0;
2259                         break;
2260                 case YUV420:
2261                         fmt_cfg = 4;
2262                         swap_rb = 0;
2263                         win->fmt_10 = 0;
2264                         break;
2265                 case YUV420_NV21:
2266                         fmt_cfg = 4;
2267                         swap_rb = 0;
2268                         swap_uv = 1;
2269                         win->fmt_10 = 0;
2270                         break;
2271                 case YUV444:
2272                         fmt_cfg = 6;
2273                         swap_rb = 0;
2274                         win->fmt_10 = 0;
2275                 case YUV422_A:
2276                         fmt_cfg = 5;
2277                         swap_rb = 0;
2278                         win->fmt_10 = 1;
2279                         break;
2280                 case YUV420_A:
2281                         fmt_cfg = 4;
2282                         swap_rb = 0;
2283                         win->fmt_10 = 1;
2284                         break;
2285                 case YUV444_A:
2286                         fmt_cfg = 6;
2287                         swap_rb = 0;
2288                         win->fmt_10 = 1;
2289                         break;
2290                 default:
2291                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2292                                 __func__);
2293                         break;
2294                 }
2295                 win->area[0].fmt_cfg = fmt_cfg;
2296                 win->area[0].swap_rb = swap_rb;
2297                 win->area[0].dsp_stx = xpos;
2298                 win->area[0].dsp_sty = ypos;
2299                 win->area[0].swap_uv = swap_uv;
2300                 xact = win->area[0].xact;
2301                 yact = win->area[0].yact;
2302                 xvir = win->area[0].xvir;
2303                 yvir = win->area[0].yvir;
2304         }
2305         rk3288_win_0_1_reg_update(&lcdc_dev->driver,0);
2306         spin_unlock(&lcdc_dev->reg_lock);
2307
2308         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2309                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2310                 __func__, get_format_string(win->area[0].format, fmt), xact,
2311                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2312         return 0;
2313
2314 }
2315
2316 static int win1_set_par(struct lcdc_device *lcdc_dev,
2317                         struct rk_screen *screen, struct rk_lcdc_win *win)
2318 {
2319         u32 xact, yact, xvir, yvir, xpos, ypos;
2320         u8 fmt_cfg = 0, swap_rb, swap_uv = 0;
2321         char fmt[9] = "NULL";
2322
2323         xpos = win->area[0].xpos + screen->mode.left_margin + screen->mode.hsync_len;
2324         ypos = win->area[0].ypos + screen->mode.upper_margin + screen->mode.vsync_len;
2325
2326         spin_lock(&lcdc_dev->reg_lock);
2327         if (likely(lcdc_dev->clk_on)) {
2328                 rk3288_lcdc_cal_scl_fac(win);/*fac,lb,gt2,gt4*/
2329                 switch (win->area[0].format) {
2330                 case ARGB888:
2331                         fmt_cfg = 0;
2332                         swap_rb = 0;
2333                         win->fmt_10 = 0;
2334                         break;
2335                 case XBGR888:
2336                 case ABGR888:
2337                         fmt_cfg = 0;
2338                         swap_rb = 1;
2339                         win->fmt_10 = 0;
2340                         break;
2341                 case RGB888:
2342                         fmt_cfg = 1;
2343                         swap_rb = 0;
2344                         win->fmt_10 = 0;
2345                         break;
2346                 case RGB565:
2347                         fmt_cfg = 2;
2348                         swap_rb = 0;
2349                         win->fmt_10 = 0;
2350                         break;
2351                 case YUV422:
2352                         fmt_cfg = 5;
2353                         swap_rb = 0;
2354                         win->fmt_10 = 0;
2355                         break;
2356                 case YUV420:
2357                         fmt_cfg = 4;
2358                         swap_rb = 0;
2359                         win->fmt_10 = 0;
2360                         break;
2361                 case YUV420_NV21:
2362                         fmt_cfg = 4;
2363                         swap_rb = 0;
2364                         swap_uv = 1;
2365                         win->fmt_10 = 0;
2366                         break;
2367                 case YUV444:
2368                         fmt_cfg = 6;
2369                         swap_rb = 0;
2370                         win->fmt_10 = 0;
2371                         break;
2372                 case YUV422_A:
2373                         fmt_cfg = 5;
2374                         swap_rb = 0;
2375                         win->fmt_10 = 1;
2376                         break;
2377                 case YUV420_A:
2378                         fmt_cfg = 4;
2379                         swap_rb = 0;
2380                         win->fmt_10 = 1;
2381                         break;
2382                 case YUV444_A:
2383                         fmt_cfg = 6;
2384                         swap_rb = 0;
2385                         win->fmt_10 = 1;
2386                         break;
2387                 default:
2388                         dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
2389                                 __func__);
2390                         break;
2391                 }
2392                 win->area[0].fmt_cfg = fmt_cfg;
2393                 win->area[0].swap_rb = swap_rb;
2394                 win->area[0].dsp_stx = xpos;
2395                 win->area[0].dsp_sty = ypos;
2396                 win->area[0].swap_uv = swap_uv;
2397                 xact = win->area[0].xact;
2398                 yact = win->area[0].yact;
2399                 xvir = win->area[0].xvir;
2400                 yvir = win->area[0].yvir;
2401         }
2402         rk3288_win_0_1_reg_update(&lcdc_dev->driver,1);
2403         spin_unlock(&lcdc_dev->reg_lock);
2404
2405         DBG(1, "lcdc%d>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
2406                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
2407                 __func__, get_format_string(win->area[0].format, fmt), xact,
2408                 yact, win->area[0].xsize, win->area[0].ysize, xvir, yvir, xpos, ypos);
2409         return 0;
2410
2411 }
2412
2413 static int win2_set_par(struct lcdc_device *lcdc_dev,
2414                         struct rk_screen *screen, struct rk_lcdc_win *win)
2415 {
2416         int i;
2417         u8 fmt_cfg, swap_rb;
2418
2419         spin_lock(&lcdc_dev->reg_lock);
2420         if (likely(lcdc_dev->clk_on)) {
2421                 for (i = 0; i < win->area_num; i++) {
2422                         switch (win->area[i].format) {
2423                         case ARGB888:
2424                                 fmt_cfg = 0;
2425                                 swap_rb = 0;
2426                                 break;
2427                         case XBGR888:
2428                         case ABGR888:
2429                                 fmt_cfg = 0;
2430                                 swap_rb = 1;
2431                                 break;
2432                         case RGB888:
2433                                 fmt_cfg = 1;
2434                                 swap_rb = 0;
2435                                 break;
2436                         case RGB565:
2437                                 fmt_cfg = 2;
2438                                 swap_rb = 0;
2439                                 break;
2440                         default:
2441                                 dev_err(lcdc_dev->driver.dev,
2442                                         "%s:un supported format!\n",
2443                                         __func__);
2444                                 break;
2445                         }
2446                         win->area[i].fmt_cfg = fmt_cfg;
2447                         win->area[i].swap_rb = swap_rb;
2448                         win->area[i].dsp_stx = win->area[i].xpos +
2449                                 screen->mode.left_margin +
2450                                 screen->mode.hsync_len;
2451                         if (screen->y_mirror == 1) {
2452                                 win->area[i].dsp_sty = screen->mode.yres -
2453                                         win->area[i].ypos -
2454                                         win->area[i].ysize +
2455                                         screen->mode.upper_margin +
2456                                         screen->mode.vsync_len;
2457                         } else {
2458                                 win->area[i].dsp_sty = win->area[i].ypos +
2459                                         screen->mode.upper_margin +
2460                                         screen->mode.vsync_len;
2461                         }
2462                         if ((win->area[i].xact != win->area[i].xsize) ||
2463                             (win->area[i].yact != win->area[i].ysize)) {
2464                                 pr_err("win[%d]->area[%d],not support scale\n",
2465                                         win->id, i);
2466                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2467                                         win->area[i].xact,win->area[i].yact,
2468                                         win->area[i].xsize,win->area[i].ysize);
2469                                 win->area[i].xsize = win->area[i].xact;
2470                                 win->area[i].ysize = win->area[i].yact;
2471                         }
2472                 }
2473         }
2474         rk3288_win_2_3_reg_update(&lcdc_dev->driver,2);
2475         spin_unlock(&lcdc_dev->reg_lock);
2476         return 0;
2477 }
2478
2479 static int win3_set_par(struct lcdc_device *lcdc_dev,
2480                         struct rk_screen *screen, struct rk_lcdc_win *win)
2481
2482 {
2483         int i;
2484         u8 fmt_cfg, swap_rb;
2485
2486         spin_lock(&lcdc_dev->reg_lock);
2487         if (likely(lcdc_dev->clk_on)) {
2488                 for (i = 0; i < win->area_num; i++) {
2489                         switch (win->area[i].format) {
2490                         case ARGB888:
2491                                 fmt_cfg = 0;
2492                                 swap_rb = 0;
2493                                 break;
2494                         case XBGR888:
2495                         case ABGR888:
2496                                 fmt_cfg = 0;
2497                                 swap_rb = 1;
2498                                 break;
2499                         case RGB888:
2500                                 fmt_cfg = 1;
2501                                 swap_rb = 0;
2502                                 break;
2503                         case RGB565:
2504                                 fmt_cfg = 2;
2505                                 swap_rb = 0;
2506                                 break;
2507                         default:
2508                                 dev_err(lcdc_dev->driver.dev,
2509                                         "%s:un supported format!\n",
2510                                         __func__);
2511                                 break;
2512                         }
2513                         win->area[i].fmt_cfg = fmt_cfg;
2514                         win->area[i].swap_rb = swap_rb;
2515                         win->area[i].dsp_stx = win->area[i].xpos +
2516                                 screen->mode.left_margin +
2517                                 screen->mode.hsync_len;
2518                         if (screen->y_mirror == 1) {
2519                                 win->area[i].dsp_sty = screen->mode.yres -
2520                                         win->area[i].ypos -
2521                                         win->area[i].ysize +
2522                                         screen->mode.upper_margin +
2523                                         screen->mode.vsync_len;
2524                         } else {
2525                                 win->area[i].dsp_sty = win->area[i].ypos +
2526                                         screen->mode.upper_margin +
2527                                         screen->mode.vsync_len;
2528                         }
2529                         if ((win->area[i].xact != win->area[i].xsize) ||
2530                             (win->area[i].yact != win->area[i].ysize)) {
2531                                 pr_err("win[%d]->area[%d],not support scale\n",
2532                                        win->id, i);
2533                                 pr_err("xact=%d,yact=%d,xsize=%d,ysize=%d\n",
2534                                        win->area[i].xact, win->area[i].yact,
2535                                        win->area[i].xsize, win->area[i].ysize);
2536                                 win->area[i].xsize = win->area[i].xact;
2537                                 win->area[i].ysize = win->area[i].yact;
2538                         }
2539                 }
2540         }
2541         rk3288_win_2_3_reg_update(&lcdc_dev->driver,3);
2542         spin_unlock(&lcdc_dev->reg_lock);
2543         return 0;
2544 }
2545
2546 static int rk3288_lcdc_set_par(struct rk_lcdc_driver *dev_drv,int win_id)
2547 {
2548         struct lcdc_device *lcdc_dev =
2549             container_of(dev_drv, struct lcdc_device, driver);
2550         struct rk_lcdc_win *win = NULL;
2551         struct rk_screen *screen = dev_drv->cur_screen;
2552         win = dev_drv->win[win_id];
2553
2554         switch(win_id)
2555         {
2556         case 0:
2557                 win0_set_par(lcdc_dev, screen, win);
2558                 break;
2559         case 1:
2560                 win1_set_par(lcdc_dev, screen, win);
2561                 break;
2562         case 2:
2563                 win2_set_par(lcdc_dev, screen, win);
2564                 break;
2565         case 3:
2566                 win3_set_par(lcdc_dev, screen, win);
2567                 break;
2568         default:
2569                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2570                 break;
2571         }
2572         return 0;
2573 }
2574
2575 static int rk3288_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2576                              unsigned long arg, int win_id)
2577 {
2578         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2579                                                            struct
2580                                                            lcdc_device,
2581                                                            driver);
2582         u32 panel_size[2];
2583         void __user *argp = (void __user *)arg;
2584         struct color_key_cfg clr_key_cfg;
2585
2586         switch (cmd) {
2587         case RK_FBIOGET_PANEL_SIZE:
2588                 panel_size[0] = lcdc_dev->screen->mode.xres;
2589                 panel_size[1] = lcdc_dev->screen->mode.yres;
2590                 if (copy_to_user(argp, panel_size, 8))
2591                         return -EFAULT;
2592                 break;
2593         case RK_FBIOPUT_COLOR_KEY_CFG:
2594                 if (copy_from_user(&clr_key_cfg, argp,
2595                                    sizeof(struct color_key_cfg)))
2596                         return -EFAULT;
2597                 rk3288_lcdc_clr_key_cfg(dev_drv);
2598                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2599                             clr_key_cfg.win0_color_key_cfg);
2600                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2601                             clr_key_cfg.win1_color_key_cfg);
2602                 break;
2603
2604         default:
2605                 break;
2606         }
2607         return 0;
2608 }
2609
2610 static int rk3288_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2611 {
2612         u32 reg;
2613         struct lcdc_device *lcdc_dev =
2614             container_of(dev_drv, struct lcdc_device, driver);
2615         if (dev_drv->suspend_flag)
2616                 return 0;
2617
2618         dev_drv->suspend_flag = 1;
2619         flush_kthread_worker(&dev_drv->update_regs_worker);
2620
2621         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg +=4)
2622                         lcdc_readl(lcdc_dev, reg);
2623         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2624                 dev_drv->trsm_ops->disable();
2625
2626         spin_lock(&lcdc_dev->reg_lock);
2627         if (likely(lcdc_dev->clk_on)) {
2628                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2629                                         v_DSP_BLANK_EN(1));
2630                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR | m_LINE_FLAG_INTR_CLR,
2631                                         v_FS_INTR_CLR(1) | v_LINE_FLAG_INTR_CLR(1));
2632                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2633                                         v_DSP_OUT_ZERO(1));
2634                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2635                                         v_STANDBY_EN(1));
2636                 lcdc_cfg_done(lcdc_dev);
2637
2638                 if (dev_drv->iommu_enabled) {
2639                         if (dev_drv->mmu_dev)
2640                                 rockchip_iovmm_deactivate(dev_drv->dev);
2641                 }
2642
2643                 spin_unlock(&lcdc_dev->reg_lock);
2644         } else {
2645                 spin_unlock(&lcdc_dev->reg_lock);
2646                 return 0;
2647         }
2648         rk3288_lcdc_clk_disable(lcdc_dev);
2649         rk_disp_pwr_disable(dev_drv);
2650         return 0;
2651 }
2652
2653 static int rk3288_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2654 {
2655         struct lcdc_device *lcdc_dev =
2656             container_of(dev_drv, struct lcdc_device, driver);
2657
2658         if (!dev_drv->suspend_flag)
2659                 return 0;
2660         rk_disp_pwr_enable(dev_drv);
2661         dev_drv->suspend_flag = 0;
2662
2663         if (lcdc_dev->atv_layer_cnt) {
2664                 rk3288_lcdc_clk_enable(lcdc_dev);
2665                 rk3288_lcdc_reg_restore(lcdc_dev);
2666
2667                 spin_lock(&lcdc_dev->reg_lock);
2668                 rk3288_lcdc_set_lut(dev_drv);
2669
2670                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2671                              v_DSP_OUT_ZERO(0));
2672                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
2673                              v_STANDBY_EN(0));
2674                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2675                                         v_DSP_BLANK_EN(0));
2676                 lcdc_cfg_done(lcdc_dev);
2677
2678                 if (dev_drv->iommu_enabled) {
2679                         if (dev_drv->mmu_dev)
2680                                 rockchip_iovmm_activate(dev_drv->dev);
2681                 }
2682
2683                 spin_unlock(&lcdc_dev->reg_lock);
2684         }
2685
2686         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2687                 dev_drv->trsm_ops->enable();
2688
2689         return 0;
2690 }
2691
2692 static int rk3288_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2693                              int win_id, int blank_mode)
2694 {
2695         switch (blank_mode) {
2696         case FB_BLANK_UNBLANK:
2697                 rk3288_lcdc_early_resume(dev_drv);
2698                 break;
2699         case FB_BLANK_NORMAL:
2700                 rk3288_lcdc_early_suspend(dev_drv);
2701                 break;
2702         default:
2703                 rk3288_lcdc_early_suspend(dev_drv);
2704                 break;
2705         }
2706
2707         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2708
2709         return 0;
2710 }
2711
2712 static int rk3288_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
2713                                            int win_id, int area_id)
2714 {
2715         struct lcdc_device *lcdc_dev =
2716             container_of(dev_drv, struct lcdc_device, driver);
2717         u32 win_ctrl = 0;
2718         u32 area_status = 0;
2719
2720         switch (win_id) {
2721         case 0:
2722                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2723                 area_status = win_ctrl & m_WIN0_EN;
2724                 break;
2725         case 1:
2726                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2727                 area_status = win_ctrl & m_WIN1_EN;
2728                 break;
2729         case 2:
2730                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2731                 if (area_id == 0)
2732                         area_status = win_ctrl & m_WIN2_MST0_EN;
2733                 if (area_id == 1)
2734                         area_status = win_ctrl & m_WIN2_MST1_EN;
2735                 if (area_id == 2)
2736                         area_status = win_ctrl & m_WIN2_MST2_EN;
2737                 if (area_id == 3)
2738                         area_status = win_ctrl & m_WIN2_MST3_EN;
2739                 break;
2740         case 3:
2741                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
2742                 if (area_id == 0)
2743                         area_status = win_ctrl & m_WIN3_MST0_EN;
2744                 if (area_id == 1)
2745                         area_status = win_ctrl & m_WIN3_MST1_EN;
2746                 if (area_id == 2)
2747                         area_status = win_ctrl & m_WIN3_MST2_EN;
2748                 if (area_id == 3)
2749                         area_status = win_ctrl & m_WIN3_MST3_EN;
2750                 break;
2751         case 4:
2752                 win_ctrl = lcdc_readl(lcdc_dev, HWC_CTRL0);
2753                 area_status = win_ctrl & m_HWC_EN;
2754                 break;
2755         default:
2756                 pr_err("!!!%s,win[%d]area[%d],unsupport!!!\n",__func__,win_id,area_id);
2757                 break;
2758         }
2759         return area_status;
2760 }
2761
2762 static int rk3288_lcdc_get_area_num(struct rk_lcdc_driver *dev_drv,
2763                                            unsigned int *area_support)
2764 {
2765         area_support[0] = 1;
2766         area_support[1] = 1;
2767         area_support[2] = 4;
2768         area_support[3] = 4;
2769
2770         return 0;
2771 }
2772
2773 /*overlay will be do at regupdate*/
2774 static int rk3288_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2775                                bool set)
2776 {
2777         struct lcdc_device *lcdc_dev =
2778             container_of(dev_drv, struct lcdc_device, driver);
2779         struct rk_lcdc_win *win = NULL;
2780         int i,ovl;
2781         unsigned int mask, val;
2782         int z_order_num=0;
2783         int layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2784         if(swap == 0){
2785                 for(i=0;i<4;i++){
2786                         win = dev_drv->win[i];
2787                         if(win->state == 1){
2788                                 z_order_num++;
2789                         }
2790                 }
2791                 for(i=0;i<4;i++){
2792                         win = dev_drv->win[i];
2793                         if(win->state == 0)
2794                                 win->z_order = z_order_num++;
2795                         switch(win->z_order){
2796                         case 0:
2797                                 layer0_sel = win->id;
2798                                 break;
2799                         case 1:
2800                                 layer1_sel = win->id;
2801                                 break;
2802                         case 2:
2803                                 layer2_sel = win->id;
2804                                 break;
2805                         case 3:
2806                                 layer3_sel = win->id;
2807                                 break;
2808                         default:
2809                                 break;
2810                         }
2811                 }
2812         }else{
2813                 layer0_sel = swap %10;;
2814                 layer1_sel = swap /10 % 10;
2815                 layer2_sel = swap / 100 %10;
2816                 layer3_sel = swap / 1000;
2817         }
2818
2819         spin_lock(&lcdc_dev->reg_lock);
2820         if(lcdc_dev->clk_on){
2821                 if(set){
2822                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
2823                                 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
2824                         val  = v_DSP_LAYER0_SEL(layer0_sel) |
2825                                 v_DSP_LAYER1_SEL(layer1_sel) |
2826                                 v_DSP_LAYER2_SEL(layer2_sel) |
2827                                 v_DSP_LAYER3_SEL(layer3_sel);
2828                         lcdc_msk_reg(lcdc_dev,DSP_CTRL1,mask,val);
2829                 }else{
2830                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER0_SEL);
2831                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER1_SEL);
2832                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER2_SEL);
2833                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1, m_DSP_LAYER3_SEL);
2834                         ovl = layer3_sel*1000 + layer2_sel*100 + layer1_sel *10 + layer0_sel;
2835                 }
2836         }else{
2837                 ovl = -EPERM;
2838         }
2839         spin_unlock(&lcdc_dev->reg_lock);
2840
2841         return ovl;
2842 }
2843
2844 static ssize_t rk3288_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
2845                                          char *buf, int win_id)
2846 {
2847         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2848                                                            struct
2849                                                            lcdc_device,
2850                                                            driver);
2851         struct rk_screen *screen = dev_drv->cur_screen;
2852         u16 hsync_len = screen->mode.hsync_len;
2853         u16 left_margin = screen->mode.left_margin;
2854         u16 vsync_len = screen->mode.vsync_len;
2855         u16 upper_margin = screen->mode.upper_margin;
2856         u32 h_pw_bp = hsync_len + left_margin;
2857         u32 v_pw_bp = vsync_len + upper_margin;
2858         u32 fmt_id;
2859         char format_w0[9] = "NULL";
2860         char format_w1[9] = "NULL";
2861         char format_w2[9] = "NULL";
2862         char format_w3[9] = "NULL";
2863         u32 win_ctrl,zorder,vir_info,act_info,dsp_info,dsp_st,y_factor,uv_factor;
2864         u8 layer0_sel,layer1_sel,layer2_sel,layer3_sel;
2865         u8 w0_state,w1_state,w2_state,w3_state;
2866         u8 w2_0_state,w2_1_state,w2_2_state,w2_3_state;
2867         u8 w3_0_state,w3_1_state,w3_2_state,w3_3_state;
2868
2869         u32 w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,w0_dsp_x,w0_dsp_y,w0_st_x=h_pw_bp,w0_st_y=v_pw_bp;
2870         u32 w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,w1_dsp_x,w1_dsp_y,w1_st_x=h_pw_bp,w1_st_y=v_pw_bp;
2871         u32 w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,w0_uv_v_fac;
2872         u32 w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,w1_uv_v_fac;
2873
2874         u32 w2_0_vir_y,w2_1_vir_y,w2_2_vir_y,w2_3_vir_y;
2875         u32 w2_0_dsp_x,w2_1_dsp_x,w2_2_dsp_x,w2_3_dsp_x;
2876         u32 w2_0_dsp_y,w2_1_dsp_y,w2_2_dsp_y,w2_3_dsp_y;
2877         u32 w2_0_st_x=h_pw_bp,w2_1_st_x=h_pw_bp,w2_2_st_x=h_pw_bp,w2_3_st_x=h_pw_bp;
2878         u32 w2_0_st_y=v_pw_bp,w2_1_st_y=v_pw_bp,w2_2_st_y=v_pw_bp,w2_3_st_y=v_pw_bp;
2879
2880         u32 w3_0_vir_y,w3_1_vir_y,w3_2_vir_y,w3_3_vir_y;
2881         u32 w3_0_dsp_x,w3_1_dsp_x,w3_2_dsp_x,w3_3_dsp_x;
2882         u32 w3_0_dsp_y,w3_1_dsp_y,w3_2_dsp_y,w3_3_dsp_y;
2883         u32 w3_0_st_x=h_pw_bp,w3_1_st_x=h_pw_bp,w3_2_st_x=h_pw_bp,w3_3_st_x=h_pw_bp;
2884         u32 w3_0_st_y=v_pw_bp,w3_1_st_y=v_pw_bp,w3_2_st_y=v_pw_bp,w3_3_st_y=v_pw_bp;
2885         u32 dclk_freq;
2886
2887         dclk_freq = screen->mode.pixclock;
2888         /*rk3288_lcdc_reg_dump(dev_drv);*/
2889
2890         spin_lock(&lcdc_dev->reg_lock);
2891         if (lcdc_dev->clk_on) {
2892                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
2893                 layer0_sel = (zorder & m_DSP_LAYER0_SEL)>>8;
2894                 layer1_sel = (zorder & m_DSP_LAYER1_SEL)>>10;
2895                 layer2_sel = (zorder & m_DSP_LAYER2_SEL)>>12;
2896                 layer3_sel = (zorder & m_DSP_LAYER3_SEL)>>14;
2897                 /*WIN0*/
2898                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
2899                 w0_state = win_ctrl & m_WIN0_EN;
2900                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT)>>1;
2901                 switch (fmt_id) {
2902                 case 0:
2903                         strcpy(format_w0, "ARGB888");
2904                         break;
2905                 case 1:
2906                         strcpy(format_w0, "RGB888");
2907                         break;
2908                 case 2:
2909                         strcpy(format_w0, "RGB565");
2910                         break;
2911                 case 4:
2912                         strcpy(format_w0, "YCbCr420");
2913                         break;
2914                 case 5:
2915                         strcpy(format_w0, "YCbCr422");
2916                         break;
2917                 case 6:
2918                         strcpy(format_w0, "YCbCr444");
2919                         break;
2920                 default:
2921                         strcpy(format_w0, "invalid\n");
2922                         break;
2923                 }
2924                 vir_info = lcdc_readl(lcdc_dev,WIN0_VIR);
2925                 act_info = lcdc_readl(lcdc_dev,WIN0_ACT_INFO);
2926                 dsp_info = lcdc_readl(lcdc_dev,WIN0_DSP_INFO);
2927                 dsp_st = lcdc_readl(lcdc_dev,WIN0_DSP_ST);
2928                 y_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_YRGB);
2929                 uv_factor = lcdc_readl(lcdc_dev,WIN0_SCL_FACTOR_CBR);
2930                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
2931                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV)>>16;
2932                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH)+1;
2933                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT)>>16)+1;
2934                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH)+1;
2935                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT)>>16)+1;
2936                 if (w0_state) {
2937                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
2938                         w0_st_y = (dsp_st & m_WIN0_DSP_YST)>>16;
2939                 }
2940                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
2941                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB)>>16;
2942                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
2943                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR)>>16;
2944
2945                 /*WIN1*/
2946                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
2947                 w1_state = win_ctrl & m_WIN1_EN;
2948                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT)>>1;
2949                 switch (fmt_id) {
2950                 case 0:
2951                         strcpy(format_w1, "ARGB888");
2952                         break;
2953                 case 1:
2954                         strcpy(format_w1, "RGB888");
2955                         break;
2956                 case 2:
2957                         strcpy(format_w1, "RGB565");
2958                         break;
2959                 case 4:
2960                         strcpy(format_w1, "YCbCr420");
2961                         break;
2962                 case 5:
2963                         strcpy(format_w1, "YCbCr422");
2964                         break;
2965                 case 6:
2966                         strcpy(format_w1, "YCbCr444");
2967                         break;
2968                 default:
2969                         strcpy(format_w1, "invalid\n");
2970                         break;
2971                 }
2972                 vir_info = lcdc_readl(lcdc_dev,WIN1_VIR);
2973                 act_info = lcdc_readl(lcdc_dev,WIN1_ACT_INFO);
2974                 dsp_info = lcdc_readl(lcdc_dev,WIN1_DSP_INFO);
2975                 dsp_st = lcdc_readl(lcdc_dev,WIN1_DSP_ST);
2976                 y_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_YRGB);
2977                 uv_factor = lcdc_readl(lcdc_dev,WIN1_SCL_FACTOR_CBR);
2978                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
2979                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV)>>16;
2980                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH)+1;
2981                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT)>>16)+1;
2982                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH)+1;
2983                 w1_dsp_y =((dsp_info & m_WIN1_DSP_HEIGHT)>>16)+1;
2984                 if (w1_state) {
2985                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
2986                         w1_st_y = (dsp_st & m_WIN1_DSP_YST)>>16;
2987                 }
2988                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
2989                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB)>>16;
2990                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
2991                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR)>>16;
2992                 /*WIN2*/
2993                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
2994                 w2_state = win_ctrl & m_WIN2_EN;
2995                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN)>>4;
2996                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN)>>5;
2997                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN)>>6;
2998                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN)>>7;
2999                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR0_1);
3000                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3001                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1)>>16;
3002                 vir_info = lcdc_readl(lcdc_dev,WIN2_VIR2_3);
3003                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3004                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3)>>16;
3005                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT)>>1;
3006                 switch (fmt_id) {
3007                 case 0:
3008                         strcpy(format_w2, "ARGB888");
3009                         break;
3010                 case 1:
3011                         strcpy(format_w2, "RGB888");
3012                         break;
3013                 case 2:
3014                         strcpy(format_w2, "RGB565");
3015                         break;
3016                 case 4:
3017                         strcpy(format_w2,"8bpp");
3018                         break;
3019                 case 5:
3020                         strcpy(format_w2,"4bpp");
3021                         break;
3022                 case 6:
3023                         strcpy(format_w2,"2bpp");
3024                         break;
3025                 case 7:
3026                         strcpy(format_w2,"1bpp");
3027                         break;
3028                 default:
3029                         strcpy(format_w2, "invalid\n");
3030                         break;
3031                 }
3032                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO0);
3033                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST0);
3034                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0)+1;
3035                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0)>>16)+1;
3036                 if (w2_0_state) {
3037                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3038                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0)>>16;
3039                 }
3040                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO1);
3041                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST1);
3042                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1)+1;
3043                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1)>>16)+1;
3044                 if (w2_1_state) {
3045                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3046                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1)>>16;
3047                 }
3048                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO2);
3049                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST2);
3050                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2)+1;
3051                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2)>>16)+1;
3052                 if (w2_2_state) {
3053                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3054                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2)>>16;
3055                 }
3056                 dsp_info = lcdc_readl(lcdc_dev,WIN2_DSP_INFO3);
3057                 dsp_st = lcdc_readl(lcdc_dev,WIN2_DSP_ST3);
3058                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3)+1;
3059                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3)>>16)+1;
3060                 if (w2_3_state) {
3061                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3062                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3)>>16;
3063                 }
3064
3065                 /*WIN3*/
3066                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3067                 w3_state = win_ctrl & m_WIN3_EN;
3068                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN)>>4;
3069                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN)>>5;
3070                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN)>>6;
3071                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN)>>7;
3072                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR0_1);
3073                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3074                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1)>>16;
3075                 vir_info = lcdc_readl(lcdc_dev,WIN3_VIR2_3);
3076                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3077                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3)>>16;
3078                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT)>>1;
3079                 switch (fmt_id) {
3080                 case 0:
3081                         strcpy(format_w3, "ARGB888");
3082                         break;
3083                 case 1:
3084                         strcpy(format_w3, "RGB888");
3085                         break;
3086                 case 2:
3087                         strcpy(format_w3, "RGB565");
3088                         break;
3089                 case 4:
3090                         strcpy(format_w3,"8bpp");
3091                         break;
3092                 case 5:
3093                         strcpy(format_w3,"4bpp");
3094                         break;
3095                 case 6:
3096                         strcpy(format_w3,"2bpp");
3097                         break;
3098                 case 7:
3099                         strcpy(format_w3,"1bpp");
3100                         break;
3101                 default:
3102                         strcpy(format_w3, "invalid");
3103                         break;
3104                 }
3105                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO0);
3106                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST0);
3107                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0)+1;
3108                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0)>>16)+1;
3109                 if (w3_0_state) {
3110                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3111                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0)>>16;
3112                 }
3113
3114                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO1);
3115                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST1);
3116                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1)+1;
3117                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1)>>16)+1;
3118                 if (w3_1_state) {
3119                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3120                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1)>>16;
3121                 }
3122
3123                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO2);
3124                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST2);
3125                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2)+1;
3126                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2)>>16)+1;
3127                 if (w3_2_state) {
3128                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3129                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2)>>16;
3130                 }
3131
3132                 dsp_info = lcdc_readl(lcdc_dev,WIN3_DSP_INFO3);
3133                 dsp_st = lcdc_readl(lcdc_dev,WIN3_DSP_ST3);
3134                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3)+1;
3135                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3)>>16)+1;
3136                 if (w3_3_state) {
3137                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3138                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3)>>16;
3139                 }
3140
3141         } else {
3142                 spin_unlock(&lcdc_dev->reg_lock);
3143                 return -EPERM;
3144         }
3145         spin_unlock(&lcdc_dev->reg_lock);
3146         return snprintf(buf, PAGE_SIZE,
3147                         "z-order:\n"
3148                         "  layer3_sel_win[%d]\n"
3149                         "  layer2_sel_win[%d]\n"
3150                         "  layer1_sel_win[%d]\n"
3151                         "  layer0_sel_win[%d]\n"
3152                         "win0:\n"
3153                         "  state:%d, "
3154                         "  fmt:%s, "
3155                         "  y_vir:%d, "
3156                         "  uv_vir:%d\n"
3157                         "  xact:%4d, "
3158                         "  yact:%4d, "
3159                         "  dsp_x:%4d, "
3160                         "  dsp_y:%4d, "
3161                         "  x_st:%4d, "
3162                         "  y_st:%4d\n"
3163                         "  y_h_fac:%8d, "
3164                         "  y_v_fac:%8d, "
3165                         "  uv_h_fac:%8d, "
3166                         "  uv_v_fac:%8d\n"
3167                         "  y_addr: 0x%08x, "
3168                         "  uv_addr:0x%08x\n"
3169                         "win1:\n"
3170                         "  state:%d, "
3171                         "  fmt:%s, "
3172                         "  y_vir:%d, "
3173                         "  uv_vir:%d\n"
3174                         "  xact:%4d, "
3175                         "  yact:%4d, "
3176                         "  dsp_x:%4d, "
3177                         "  dsp_y:%4d, "
3178                         "  x_st:%4d, "
3179                         "  y_st:%4d\n"
3180                         "  y_h_fac:%8d, "
3181                         "  y_v_fac:%8d, "
3182                         "  uv_h_fac:%8d, "
3183                         "  uv_v_fac:%8d\n"
3184                         "  y_addr: 0x%08x, "
3185                         "  uv_addr:0x%08x\n"
3186                         "win2:\n"
3187                         "  state:%d\n"
3188                         "  fmt:%s\n"
3189                         "  area0:"
3190                         "  state:%d,"
3191                         "  y_vir:%4d,"
3192                         "  dsp_x:%4d,"
3193                         "  dsp_y:%4d,"
3194                         "  x_st:%4d,"
3195                         "  y_st:%4d,"
3196                         "  addr:0x%08x\n"
3197                         "  area1:"
3198                         "  state:%d,"
3199                         "  y_vir:%4d,"
3200                         "  dsp_x:%4d,"
3201                         "  dsp_y:%4d,"
3202                         "  x_st:%4d,"
3203                         "  y_st:%4d,"
3204                         "  addr:0x%08x\n"
3205                         "  area2:"
3206                         "  state:%d,"
3207                         "  y_vir:%4d,"
3208                         "  dsp_x:%4d,"
3209                         "  dsp_y:%4d,"
3210                         "  x_st:%4d,"
3211                         "  y_st:%4d,"
3212                         "  addr:0x%08x\n"
3213                         "  area3:"
3214                         "  state:%d,"
3215                         "  y_vir:%4d,"
3216                         "  dsp_x:%4d,"
3217                         "  dsp_y:%4d,"
3218                         "  x_st:%4d,"
3219                         "  y_st:%4d,"
3220                         "  addr:0x%08x\n"
3221                         "win3:\n"
3222                         "  state:%d\n"
3223                         "  fmt:%s\n"
3224                         "  area0:"
3225                         "  state:%d,"
3226                         "  y_vir:%4d,"
3227                         "  dsp_x:%4d,"
3228                         "  dsp_y:%4d,"
3229                         "  x_st:%4d,"
3230                         "  y_st:%4d,"
3231                         "  addr:0x%08x\n"
3232                         "  area1:"
3233                         "  state:%d,"
3234                         "  y_vir:%4d,"
3235                         "  dsp_x:%4d,"
3236                         "  dsp_y:%4d,"
3237                         "  x_st:%4d,"
3238                         "  y_st:%4d "
3239                         "  addr:0x%08x\n"
3240                         "  area2:"
3241                         "  state:%d,"
3242                         "  y_vir:%4d,"
3243                         "  dsp_x:%4d,"
3244                         "  dsp_y:%4d,"
3245                         "  x_st:%4d,"
3246                         "  y_st:%4d,"
3247                         "  addr:0x%08x\n"
3248                         "  area3:"
3249                         "  state:%d,"
3250                         "  y_vir:%4d,"
3251                         "  dsp_x:%4d,"
3252                         "  dsp_y:%4d,"
3253                         "  x_st:%4d,"
3254                         "  y_st:%4d,"
3255                         "  addr:0x%08x\n",
3256                         layer3_sel,layer2_sel,layer1_sel,layer0_sel,
3257                         w0_state,format_w0,w0_vir_y,w0_vir_uv,w0_act_x,w0_act_y,
3258                         w0_dsp_x,w0_dsp_y,w0_st_x-h_pw_bp,w0_st_y-v_pw_bp,w0_y_h_fac,w0_y_v_fac,w0_uv_h_fac,
3259                         w0_uv_v_fac,lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3260                         lcdc_readl(lcdc_dev, WIN0_CBR_MST),
3261
3262                         w1_state,format_w1,w1_vir_y,w1_vir_uv,w1_act_x,w1_act_y,
3263                         w1_dsp_x,w1_dsp_y,w1_st_x-h_pw_bp,w1_st_y-v_pw_bp,w1_y_h_fac,w1_y_v_fac,w1_uv_h_fac,
3264                         w1_uv_v_fac,lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3265                         lcdc_readl(lcdc_dev, WIN1_CBR_MST),
3266
3267                         w2_state,format_w2,
3268                         w2_0_state,w2_0_vir_y,w2_0_dsp_x,w2_0_dsp_y,
3269                         w2_0_st_x-h_pw_bp,w2_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST0),
3270
3271                         w2_1_state,w2_1_vir_y,w2_1_dsp_x,w2_1_dsp_y,
3272                         w2_1_st_x-h_pw_bp,w2_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST1),
3273
3274                         w2_2_state,w2_2_vir_y,w2_2_dsp_x,w2_2_dsp_y,
3275                         w2_2_st_x-h_pw_bp,w2_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST2),
3276
3277                         w2_3_state,w2_3_vir_y,w2_3_dsp_x,w2_3_dsp_y,
3278                         w2_3_st_x-h_pw_bp,w2_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN2_MST3),
3279
3280                         w3_state,format_w3,
3281                         w3_0_state,w3_0_vir_y,w3_0_dsp_x,w3_0_dsp_y,
3282                         w3_0_st_x-h_pw_bp,w3_0_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST0),
3283
3284                         w3_1_state,w3_1_vir_y,w3_1_dsp_x,w3_1_dsp_y,
3285                         w3_1_st_x-h_pw_bp,w3_1_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST1),
3286
3287                         w3_2_state,w3_2_vir_y,w3_2_dsp_x,w3_2_dsp_y,
3288                         w3_2_st_x-h_pw_bp,w3_2_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST2),
3289
3290                         w3_3_state,w3_3_vir_y,w3_3_dsp_x,w3_3_dsp_y,
3291                         w3_3_st_x-h_pw_bp,w3_3_st_y-v_pw_bp,lcdc_readl(lcdc_dev, WIN3_MST3)
3292         );
3293
3294 }
3295
3296 static int rk3288_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3297                                bool set)
3298 {
3299         struct lcdc_device *lcdc_dev =
3300             container_of(dev_drv, struct lcdc_device, driver);
3301         struct rk_screen *screen = dev_drv->cur_screen;
3302         u64 ft = 0;
3303         u32 dotclk;
3304         int ret;
3305         u32 pixclock;
3306         u32 x_total, y_total;
3307         if (set) {
3308                 if (fps == 0) {
3309                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3310                         return 0;
3311                 }
3312                 ft = div_u64(1000000000000llu, fps);
3313                 x_total =
3314                     screen->mode.upper_margin + screen->mode.lower_margin +
3315                     screen->mode.yres + screen->mode.vsync_len;
3316                 y_total =
3317                     screen->mode.left_margin + screen->mode.right_margin +
3318                     screen->mode.xres + screen->mode.hsync_len;
3319                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3320                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3321                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3322         }
3323
3324         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3325         dev_drv->pixclock = lcdc_dev->pixclock = pixclock;
3326         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3327         screen->ft = 1000 / fps;        /*one frame time in ms */
3328
3329         if (set)
3330                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3331                          clk_get_rate(lcdc_dev->dclk), fps);
3332
3333         return fps;
3334 }
3335
3336 static int rk3288_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3337 {
3338         mutex_lock(&dev_drv->fb_win_id_mutex);
3339         if (order == FB_DEFAULT_ORDER)
3340                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3;
3341         dev_drv->fb3_win_id = order / 1000;
3342         dev_drv->fb2_win_id = (order / 100) % 10;
3343         dev_drv->fb1_win_id = (order / 10) % 10;
3344         dev_drv->fb0_win_id = order % 10;
3345         mutex_unlock(&dev_drv->fb_win_id_mutex);
3346
3347         return 0;
3348 }
3349
3350 static int rk3288_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3351                                   const char *id)
3352 {
3353         int win_id = 0;
3354         mutex_lock(&dev_drv->fb_win_id_mutex);
3355         if (!strcmp(id, "fb0") || !strcmp(id, "fb4"))
3356                 win_id = dev_drv->fb0_win_id;
3357         else if (!strcmp(id, "fb1") || !strcmp(id, "fb5"))
3358                 win_id = dev_drv->fb1_win_id;
3359         else if (!strcmp(id, "fb2") || !strcmp(id, "fb6"))
3360                 win_id = dev_drv->fb2_win_id;
3361         else if (!strcmp(id, "fb3") || !strcmp(id, "fb7"))
3362                 win_id = dev_drv->fb3_win_id;
3363         mutex_unlock(&dev_drv->fb_win_id_mutex);
3364
3365         return win_id;
3366 }
3367
3368 static int rk3288_set_dsp_lut(struct rk_lcdc_driver *dev_drv, int *lut)
3369 {
3370         int i,j;
3371         int __iomem *c;
3372         int v, r, g, b;
3373         int ret = 0;
3374
3375         struct lcdc_device *lcdc_dev =
3376             container_of(dev_drv, struct lcdc_device, driver);
3377         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
3378         lcdc_cfg_done(lcdc_dev);
3379         mdelay(25);
3380         if (dev_drv->cur_screen->dsp_lut) {
3381                 for (i = 0; i < 256; i++) {
3382                         v = dev_drv->cur_screen->dsp_lut[i] = lut[i];
3383                         c = lcdc_dev->dsp_lut_addr_base + (i << 2);
3384                         b = (v & 0xff) << 2;
3385                         g = (v & 0xff00) << 4;
3386                         r = (v & 0xff0000) << 6;
3387                         v = r + g + b;
3388                         for (j = 0; j < 4; j++) {
3389                                 writel_relaxed(v, c);
3390                                 v += (1 + (1 << 10) + (1 << 20)) ;
3391                                 c++;
3392                         }
3393                 }
3394         } else {
3395                 dev_err(dev_drv->dev, "no buffer to backup lut data!\n");
3396                 ret = -1;
3397         }
3398
3399         do{
3400                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
3401                 lcdc_cfg_done(lcdc_dev);
3402         }while(!lcdc_read_bit(lcdc_dev,DSP_CTRL1,m_DSP_LUT_EN));
3403         return ret;
3404 }
3405
3406 static int rk3288_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3407 {
3408         struct lcdc_device *lcdc_dev =
3409             container_of(dev_drv, struct lcdc_device, driver);
3410         int i;
3411         unsigned int mask, val;
3412         struct rk_lcdc_win *win = NULL;
3413         struct fb_info *fb0 = rk_get_fb(0);
3414
3415         spin_lock(&lcdc_dev->reg_lock);
3416         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3417                              v_STANDBY_EN(lcdc_dev->standby));
3418         for (i=0;i<4;i++) {
3419                 win = dev_drv->win[i];
3420                 if ((win->state == 0)&&(win->last_state == 1)) {
3421                         switch (win->id) {
3422                         case 0:
3423                                 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3424                                         lcdc_writel(lcdc_dev, WIN0_CTRL1, 0x0);
3425                                 mask =  m_WIN0_EN;
3426                                 val  =  v_WIN0_EN(0);
3427                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask,val);
3428                                 break;
3429                         case 1:
3430                                 if (dev_drv->version == VOP_FULL_RK3288_V1_0)
3431                                         lcdc_writel(lcdc_dev, WIN1_CTRL1, 0x0);
3432                                 mask =  m_WIN1_EN;
3433                                 val  =  v_WIN1_EN(0);
3434                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask,val);
3435                                 break;
3436                         case 2:
3437                                 mask =  m_WIN2_EN | m_WIN2_MST0_EN | m_WIN2_MST1_EN |
3438                                         m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3439                                 val  =  v_WIN2_EN(0) | v_WIN2_MST0_EN(0) | v_WIN2_MST1_EN(0) |
3440                                         v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3441                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask,val);
3442                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO0,0);
3443                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO1,0);
3444                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO2,0);
3445                                 lcdc_writel(lcdc_dev,WIN2_DSP_INFO3,0);
3446                                 lcdc_writel(lcdc_dev,WIN2_MST0, fb0->fix.smem_start);
3447                                 lcdc_writel(lcdc_dev,WIN2_MST1, fb0->fix.smem_start);
3448                                 lcdc_writel(lcdc_dev,WIN2_MST2, fb0->fix.smem_start);
3449                                 lcdc_writel(lcdc_dev,WIN2_MST3, fb0->fix.smem_start);
3450                                 break;
3451                         case 3:
3452                                 mask =  m_WIN3_EN | m_WIN3_MST0_EN | m_WIN3_MST1_EN |
3453                                         m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3454                                 val  =  v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |  v_WIN3_MST1_EN(0) |
3455                                         v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3456                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask,val);
3457                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO0,0);
3458                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO1,0);
3459                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO2,0);
3460                                 lcdc_writel(lcdc_dev,WIN3_DSP_INFO3,0);
3461                                 lcdc_writel(lcdc_dev,WIN3_MST0, fb0->fix.smem_start);
3462                                 lcdc_writel(lcdc_dev,WIN3_MST1, fb0->fix.smem_start);
3463                                 lcdc_writel(lcdc_dev,WIN3_MST2, fb0->fix.smem_start);
3464                                 lcdc_writel(lcdc_dev,WIN3_MST3, fb0->fix.smem_start);
3465                                 break;
3466                         default:
3467                                 break;
3468                         }
3469                 }
3470                 win->last_state = win->state;
3471         }
3472         lcdc_cfg_done(lcdc_dev);
3473         spin_unlock(&lcdc_dev->reg_lock);
3474         return 0;
3475 }
3476
3477
3478 static int rk3288_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3479 {
3480         struct lcdc_device *lcdc_dev =
3481             container_of(dev_drv, struct lcdc_device, driver);
3482         spin_lock(&lcdc_dev->reg_lock);
3483         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3484                      v_DIRECT_PATH_EN(open));
3485         lcdc_cfg_done(lcdc_dev);
3486         spin_unlock(&lcdc_dev->reg_lock);
3487         return 0;
3488 }
3489
3490 static int rk3288_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3491 {
3492         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3493                                         struct lcdc_device, driver);
3494         spin_lock(&lcdc_dev->reg_lock);
3495         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3496                      v_DIRECT_PATCH_SEL(win_id));
3497         lcdc_cfg_done(lcdc_dev);
3498         spin_unlock(&lcdc_dev->reg_lock);
3499         return 0;
3500
3501 }
3502
3503 static int rk3288_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3504 {
3505         struct lcdc_device *lcdc_dev =
3506             container_of(dev_drv, struct lcdc_device, driver);
3507         int ovl;
3508         spin_lock(&lcdc_dev->reg_lock);
3509         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3510         spin_unlock(&lcdc_dev->reg_lock);
3511         return ovl;
3512 }
3513 static int rk3288_lcdc_set_irq_to_cpu(struct rk_lcdc_driver * dev_drv,int enable)
3514 {
3515        struct lcdc_device *lcdc_dev =
3516                                 container_of(dev_drv,struct lcdc_device,driver);
3517        if (enable)
3518                enable_irq(lcdc_dev->irq);
3519        else
3520                disable_irq(lcdc_dev->irq);
3521        return 0;
3522 }
3523
3524 int rk3288_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3525 {
3526         struct lcdc_device *lcdc_dev =
3527             container_of(dev_drv, struct lcdc_device, driver);
3528         u32 int_reg;
3529         int ret;
3530
3531         if (lcdc_dev->clk_on &&(!dev_drv->suspend_flag)){
3532                 int_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3533                 if (int_reg & m_LINE_FLAG_INTR_STS) {
3534                         lcdc_dev->driver.frame_time.last_framedone_t =
3535                                         lcdc_dev->driver.frame_time.framedone_t;
3536                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3537                         lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3538                                      v_LINE_FLAG_INTR_CLR(1));
3539                         ret = RK_LF_STATUS_FC;
3540                 } else
3541                         ret = RK_LF_STATUS_FR;
3542         } else {
3543                 ret = RK_LF_STATUS_NC;
3544         }
3545
3546         return ret;
3547 }
3548
3549 static int rk3288_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3550                                     unsigned int dsp_addr[][4])
3551 {
3552         struct lcdc_device *lcdc_dev =
3553             container_of(dev_drv, struct lcdc_device, driver);
3554         spin_lock(&lcdc_dev->reg_lock);
3555         if (lcdc_dev->clk_on) {
3556                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3557                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3558                 dsp_addr[2][0] = lcdc_readl(lcdc_dev, WIN2_MST0);
3559                 dsp_addr[2][1] = lcdc_readl(lcdc_dev, WIN2_MST1);
3560                 dsp_addr[2][2] = lcdc_readl(lcdc_dev, WIN2_MST2);
3561                 dsp_addr[2][3] = lcdc_readl(lcdc_dev, WIN2_MST3);
3562                 dsp_addr[3][0] = lcdc_readl(lcdc_dev, WIN3_MST0);
3563                 dsp_addr[3][1] = lcdc_readl(lcdc_dev, WIN3_MST1);
3564                 dsp_addr[3][2] = lcdc_readl(lcdc_dev, WIN3_MST2);
3565                 dsp_addr[3][3] = lcdc_readl(lcdc_dev, WIN3_MST3);
3566         }
3567         spin_unlock(&lcdc_dev->reg_lock);
3568         return 0;
3569 }
3570
3571 static int rk3288_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv,
3572                                     int mode, int calc, int up,
3573                                     int down, int global)
3574 {
3575         struct lcdc_device *lcdc_dev =
3576             container_of(dev_drv, struct lcdc_device, driver);
3577         struct rk_screen *screen = dev_drv->cur_screen;
3578         u32 total_pixel, calc_pixel, stage_up, stage_down;
3579         u32 pixel_num, global_dn;
3580         u32 mask = 0, val = 0;
3581
3582         if (dev_drv->version != VOP_FULL_RK3288_V1_1) {
3583                 pr_err("vop version:%x, not supoort cabc\n", dev_drv->version);
3584                 return 0;
3585         }
3586         if (!screen->cabc_lut) {
3587                 pr_err("screen cabc lut not config, so not open cabc\n");
3588                 return 0;
3589         }
3590         dev_drv->cabc_mode = mode;
3591         if (!dev_drv->cabc_mode) {
3592                 spin_lock(&lcdc_dev->reg_lock);
3593                 if (lcdc_dev->clk_on) {
3594                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3595                                      m_CABC_HANDLE_EN | m_CABC_EN,
3596                                      v_CABC_EN(0) | v_CABC_HANDLE_EN(0));
3597                         lcdc_cfg_done(lcdc_dev);
3598                 }
3599                 pr_info("mode = 0, close cabc\n");
3600                 spin_unlock(&lcdc_dev->reg_lock);
3601                 return 0;
3602         }
3603
3604         total_pixel = screen->mode.xres * screen->mode.yres;
3605         pixel_num = 1000 - calc;
3606         calc_pixel = (total_pixel * pixel_num) / 1000;
3607         stage_up = up;
3608         stage_down = down;
3609         global_dn = global;
3610         pr_info("enable cabc:mode=%d, calc=%d, up=%d, down=%d, global=%d\n",
3611                 mode, calc, stage_up, stage_down, global_dn);
3612
3613         spin_lock(&lcdc_dev->reg_lock);
3614         if (lcdc_dev->clk_on) {
3615                 mask = m_CABC_EN | m_CABC_HANDLE_EN | m_PWM_CONFIG_MODE |
3616                         m_CABC_CALC_PIXEL_NUM;
3617                 val = v_CABC_EN(1) | v_CABC_HANDLE_EN(1) |
3618                         v_PWM_CONFIG_MODE(STAGE_BY_STAGE) |
3619                         v_CABC_CALC_PIXEL_NUM(calc_pixel);
3620                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3621
3622                 mask = m_CABC_LUT_EN | m_CABC_TOTAL_PIXEL_NUM;
3623                 val = v_CABC_LUT_EN(1) | v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3624                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3625
3626                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_UP |
3627                         m_CABC_STAGE_MODE | m_MAX_SCALE_CFG_VALUE |
3628                         m_MAX_SCALE_CFG_ENABLE;
3629                 val = v_CABC_STAGE_DOWN(stage_down) |
3630                         v_CABC_STAGE_UP(stage_up) |
3631                         v_CABC_STAGE_MODE(0) | v_MAX_SCALE_CFG_VALUE(1) |
3632                         v_MAX_SCALE_CFG_ENABLE(0);
3633                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3634
3635                 mask = m_CABC_GLOBAL_DN | m_CABC_GLOBAL_DN_LIMIT_EN;
3636                 val = v_CABC_GLOBAL_DN(global_dn) |
3637                         v_CABC_GLOBAL_DN_LIMIT_EN(1);
3638                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3639                 lcdc_cfg_done(lcdc_dev);
3640         }
3641         spin_unlock(&lcdc_dev->reg_lock);
3642
3643         return 0;
3644 }
3645
3646 /*
3647         a:[-30~0]:
3648             sin_hue = sin(a)*256 +0x100;
3649             cos_hue = cos(a)*256;
3650         a:[0~30]
3651             sin_hue = sin(a)*256;
3652             cos_hue = cos(a)*256;
3653 */
3654 static int rk3288_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode)
3655 {
3656
3657         struct lcdc_device *lcdc_dev =
3658             container_of(dev_drv, struct lcdc_device, driver);
3659         u32 val;
3660
3661         spin_lock(&lcdc_dev->reg_lock);
3662         if (lcdc_dev->clk_on) {
3663                 val = lcdc_readl(lcdc_dev, BCSH_H);
3664                 switch(mode){
3665                 case H_SIN:
3666                         val &= m_BCSH_SIN_HUE;
3667                         break;
3668                 case H_COS:
3669                         val &= m_BCSH_COS_HUE;
3670                         val >>= 16;
3671                         break;
3672                 default:
3673                         break;
3674                 }
3675         }
3676         spin_unlock(&lcdc_dev->reg_lock);
3677
3678         return val;
3679 }
3680
3681
3682 static int rk3288_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue)
3683 {
3684
3685         struct lcdc_device *lcdc_dev =
3686             container_of(dev_drv, struct lcdc_device, driver);
3687         u32 mask, val;
3688
3689         spin_lock(&lcdc_dev->reg_lock);
3690         if (lcdc_dev->clk_on) {
3691                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3692                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3693                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3694                 lcdc_cfg_done(lcdc_dev);
3695         }
3696         spin_unlock(&lcdc_dev->reg_lock);
3697
3698         return 0;
3699 }
3700
3701 static int rk3288_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value)
3702 {
3703         struct lcdc_device *lcdc_dev =
3704             container_of(dev_drv, struct lcdc_device, driver);
3705         u32 mask, val;
3706
3707         spin_lock(&lcdc_dev->reg_lock);
3708         if(lcdc_dev->clk_on) {
3709                 switch (mode) {
3710                 case BRIGHTNESS:
3711                 /*from 0 to 255,typical is 128*/
3712                         if (value < 0x80)
3713                                 value += 0x80;
3714                         else if (value >= 0x80)
3715                                 value = value - 0x80;
3716                         mask =  m_BCSH_BRIGHTNESS;
3717                         val = v_BCSH_BRIGHTNESS(value);
3718                         break;
3719                 case CONTRAST:
3720                 /*from 0 to 510,typical is 256*/
3721                         mask =  m_BCSH_CONTRAST;
3722                         val =  v_BCSH_CONTRAST(value);
3723                         break;
3724                 case SAT_CON:
3725                 /*from 0 to 1015,typical is 256*/
3726                         mask = m_BCSH_SAT_CON;
3727                         val = v_BCSH_SAT_CON(value);
3728                         break;
3729                 default:
3730                         break;
3731                 }
3732                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3733                 lcdc_cfg_done(lcdc_dev);
3734         }
3735         spin_unlock(&lcdc_dev->reg_lock);
3736         return val;
3737 }
3738
3739 static int rk3288_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode)
3740 {
3741         struct lcdc_device *lcdc_dev =
3742             container_of(dev_drv, struct lcdc_device, driver);
3743         u32 val;
3744
3745         spin_lock(&lcdc_dev->reg_lock);
3746         if(lcdc_dev->clk_on) {
3747                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3748                 switch (mode) {
3749                 case BRIGHTNESS:
3750                         val &= m_BCSH_BRIGHTNESS;
3751                         if(val > 0x80)
3752                                 val -= 0x80;
3753                         else
3754                                 val += 0x80;
3755                         break;
3756                 case CONTRAST:
3757                         val &= m_BCSH_CONTRAST;
3758                         val >>= 8;
3759                         break;
3760                 case SAT_CON:
3761                         val &= m_BCSH_SAT_CON;
3762                         val >>= 20;
3763                         break;
3764                 default:
3765                         break;
3766                 }
3767         }
3768         spin_unlock(&lcdc_dev->reg_lock);
3769         return val;
3770 }
3771
3772
3773 static int rk3288_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3774 {
3775         struct lcdc_device *lcdc_dev =
3776             container_of(dev_drv, struct lcdc_device, driver);
3777         u32 mask, val;
3778
3779         spin_lock(&lcdc_dev->reg_lock);
3780         if (lcdc_dev->clk_on) {
3781                 if (open) {
3782                         lcdc_writel(lcdc_dev,BCSH_COLOR_BAR,0x1);
3783                         lcdc_writel(lcdc_dev,BCSH_BCS,0xd0010000);
3784                         lcdc_writel(lcdc_dev,BCSH_H,0x01000000);
3785                         dev_drv->bcsh.enable = 1;
3786                 } else {
3787                         mask = m_BCSH_EN;
3788                         val = v_BCSH_EN(0);
3789                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3790                         dev_drv->bcsh.enable = 0;
3791                 }
3792                 if (dev_drv->version == VOP_FULL_RK3288_V1_1)
3793                         rk3288_lcdc_bcsh_path_sel(dev_drv);
3794                 lcdc_cfg_done(lcdc_dev);
3795         }
3796         spin_unlock(&lcdc_dev->reg_lock);
3797         return 0;
3798 }
3799
3800 static int rk3288_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv,
3801                                      bool enable)
3802 {
3803         if (!enable || !dev_drv->bcsh.enable) {
3804                 rk3288_lcdc_open_bcsh(dev_drv, false);
3805                 return 0;
3806         }
3807
3808         if (dev_drv->bcsh.brightness <= 255 ||
3809             dev_drv->bcsh.contrast <= 510 ||
3810             dev_drv->bcsh.sat_con <= 1015 ||
3811             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3812                 rk3288_lcdc_open_bcsh(dev_drv, true);
3813                 if (dev_drv->bcsh.brightness <= 255)
3814                         rk3288_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3815                                                  dev_drv->bcsh.brightness);
3816                 if (dev_drv->bcsh.contrast <= 510)
3817                         rk3288_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3818                                                  dev_drv->bcsh.contrast);
3819                 if (dev_drv->bcsh.sat_con <= 1015)
3820                         rk3288_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3821                                                  dev_drv->bcsh.sat_con);
3822                 if (dev_drv->bcsh.sin_hue <= 511 &&
3823                     dev_drv->bcsh.cos_hue <= 511)
3824                         rk3288_lcdc_set_bcsh_hue(dev_drv,
3825                                                  dev_drv->bcsh.sin_hue,
3826                                                  dev_drv->bcsh.cos_hue);
3827         }
3828         return 0;
3829 }
3830
3831 static int rk3288_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
3832                                     struct overscan *overscan)
3833 {
3834         struct lcdc_device *lcdc_dev =
3835                 container_of(dev_drv, struct lcdc_device, driver);
3836
3837         if (unlikely(!lcdc_dev->clk_on)) {
3838                 pr_info("%s,clk_on = %d\n", __func__, lcdc_dev->clk_on);
3839                 return 0;
3840         }
3841         rk3288_lcdc_post_cfg(dev_drv);
3842
3843         return 0;
3844 }
3845
3846 static struct rk_lcdc_win lcdc_win[] = {
3847         [0] = {
3848                .name = "win0",
3849                .id = 0,
3850                .support_3d = false,
3851                },
3852         [1] = {
3853                .name = "win1",
3854                .id = 1,
3855                .support_3d = false,
3856                },
3857         [2] = {
3858                .name = "win2",
3859                .id = 2,
3860                .support_3d = false,
3861                },
3862         [3] = {
3863                .name = "win3",
3864                .id = 3,
3865                .support_3d = false,
3866                },
3867 };
3868
3869 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
3870         .open                   = rk3288_lcdc_open,
3871         .win_direct_en          = rk3288_lcdc_win_direct_en,
3872         .load_screen            = rk3288_load_screen,
3873         .get_dspbuf_info        = rk3288_get_dspbuf_info,
3874         .post_dspbuf            = rk3288_post_dspbuf,
3875         .set_par                = rk3288_lcdc_set_par,
3876         .pan_display            = rk3288_lcdc_pan_display,
3877         .direct_set_addr        = rk3288_lcdc_direct_set_win_addr,
3878         .lcdc_reg_update        = rk3288_lcdc_reg_update,
3879         .blank                  = rk3288_lcdc_blank,
3880         .ioctl                  = rk3288_lcdc_ioctl,
3881         .suspend                = rk3288_lcdc_early_suspend,
3882         .resume                 = rk3288_lcdc_early_resume,
3883         .get_win_state          = rk3288_lcdc_get_win_state,
3884         .area_support_num = rk3288_lcdc_get_area_num,
3885         .ovl_mgr                = rk3288_lcdc_ovl_mgr,
3886         .get_disp_info          = rk3288_lcdc_get_disp_info,
3887         .fps_mgr                = rk3288_lcdc_fps_mgr,
3888         .fb_get_win_id          = rk3288_lcdc_get_win_id,
3889         .fb_win_remap           = rk3288_fb_win_remap,
3890         .set_dsp_lut            = rk3288_set_dsp_lut,
3891         .poll_vblank            = rk3288_lcdc_poll_vblank,
3892         .dpi_open               = rk3288_lcdc_dpi_open,
3893         .dpi_win_sel            = rk3288_lcdc_dpi_win_sel,
3894         .dpi_status             = rk3288_lcdc_dpi_status,
3895         .get_dsp_addr           = rk3288_lcdc_get_dsp_addr,
3896         .set_dsp_cabc           = rk3288_lcdc_set_dsp_cabc,
3897         .set_dsp_bcsh_hue       = rk3288_lcdc_set_bcsh_hue,
3898         .set_dsp_bcsh_bcs       = rk3288_lcdc_set_bcsh_bcs,
3899         .get_dsp_bcsh_hue       = rk3288_lcdc_get_bcsh_hue,
3900         .get_dsp_bcsh_bcs       = rk3288_lcdc_get_bcsh_bcs,
3901         .open_bcsh              = rk3288_lcdc_open_bcsh,
3902         .dump_reg               = rk3288_lcdc_reg_dump,
3903         .cfg_done               = rk3288_lcdc_config_done,
3904         .set_irq_to_cpu         = rk3288_lcdc_set_irq_to_cpu,
3905         .mmu_en    = rk3288_lcdc_mmu_en,
3906         .set_overscan           = rk3288_lcdc_set_overscan,
3907
3908 };
3909
3910 #ifdef LCDC_IRQ_DEBUG
3911 static int rk3288_lcdc_parse_irq(struct lcdc_device *lcdc_dev,unsigned int reg_val)
3912 {
3913         if (reg_val & m_WIN0_EMPTY_INTR_STS) {
3914                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN0_EMPTY_INTR_CLR,
3915                              v_WIN0_EMPTY_INTR_CLR(1));
3916                 dev_warn(lcdc_dev->dev,"win0 empty irq!");
3917         }else if (reg_val & m_WIN1_EMPTY_INTR_STS) {
3918                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN1_EMPTY_INTR_CLR,
3919                              v_WIN1_EMPTY_INTR_CLR(1));
3920                 dev_warn(lcdc_dev->dev,"win1 empty irq!");
3921         }else if (reg_val & m_WIN2_EMPTY_INTR_STS) {
3922                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN2_EMPTY_INTR_CLR,
3923                              v_WIN2_EMPTY_INTR_CLR(1));
3924                 dev_warn(lcdc_dev->dev,"win2 empty irq!");
3925         }else if (reg_val & m_WIN3_EMPTY_INTR_STS) {
3926                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_WIN3_EMPTY_INTR_CLR,
3927                              v_WIN3_EMPTY_INTR_CLR(1));
3928                 dev_warn(lcdc_dev->dev,"win3 empty irq!");
3929         }else if (reg_val & m_HWC_EMPTY_INTR_STS) {
3930                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_HWC_EMPTY_INTR_CLR,
3931                              v_HWC_EMPTY_INTR_CLR(1));
3932                 dev_warn(lcdc_dev->dev,"HWC empty irq!");
3933         }else if (reg_val & m_POST_BUF_EMPTY_INTR_STS) {
3934                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_POST_BUF_EMPTY_INTR_CLR,
3935                              v_POST_BUF_EMPTY_INTR_CLR(1));
3936                 dev_warn(lcdc_dev->dev,"post buf empty irq!");
3937         }else if (reg_val & m_PWM_GEN_INTR_STS) {
3938                 lcdc_msk_reg(lcdc_dev, INTR_CTRL1, m_PWM_GEN_INTR_CLR,
3939                              v_PWM_GEN_INTR_CLR(1));
3940                 dev_warn(lcdc_dev->dev,"PWM gen irq!");
3941         }
3942
3943         return 0;
3944 }
3945 #endif
3946
3947 static irqreturn_t rk3288_lcdc_isr(int irq, void *dev_id)
3948 {
3949         struct lcdc_device *lcdc_dev =
3950             (struct lcdc_device *)dev_id;
3951         ktime_t timestamp = ktime_get();
3952         u32 intr0_reg;
3953
3954         intr0_reg = lcdc_readl(lcdc_dev, INTR_CTRL0);
3955
3956         if(intr0_reg & m_FS_INTR_STS){
3957                 timestamp = ktime_get();
3958                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_FS_INTR_CLR,
3959                              v_FS_INTR_CLR(1));
3960                 /*if(lcdc_dev->driver.wait_fs){ */
3961                 if (0) {
3962                         spin_lock(&(lcdc_dev->driver.cpl_lock));
3963                         complete(&(lcdc_dev->driver.frame_done));
3964                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
3965                 }
3966                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
3967                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
3968
3969         }else if(intr0_reg & m_LINE_FLAG_INTR_STS){
3970                 lcdc_dev->driver.frame_time.last_framedone_t =
3971                                 lcdc_dev->driver.frame_time.framedone_t;
3972                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3973                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_LINE_FLAG_INTR_CLR,
3974                              v_LINE_FLAG_INTR_CLR(1));
3975         }else if(intr0_reg & m_BUS_ERROR_INTR_STS){
3976                 lcdc_msk_reg(lcdc_dev, INTR_CTRL0, m_BUS_ERROR_INTR_CLR,
3977                              v_BUS_ERROR_INTR_CLR(1));
3978                 dev_warn(lcdc_dev->dev,"buf_error_int!");
3979         }
3980
3981         /* for win empty debug */
3982 #ifdef LCDC_IRQ_EMPTY_DEBUG
3983         intr1_reg = lcdc_readl(lcdc_dev, INTR_CTRL1);
3984         if (intr1_reg != 0) {
3985                 rk3288_lcdc_parse_irq(lcdc_dev,intr1_reg);
3986         }
3987 #endif
3988         return IRQ_HANDLED;
3989 }
3990
3991 #if defined(CONFIG_PM)
3992 static int rk3288_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
3993 {
3994         return 0;
3995 }
3996
3997 static int rk3288_lcdc_resume(struct platform_device *pdev)
3998 {
3999         return 0;
4000 }
4001 #else
4002 #define rk3288_lcdc_suspend NULL
4003 #define rk3288_lcdc_resume  NULL
4004 #endif
4005
4006 static int rk3288_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4007 {
4008         struct device_node *np = lcdc_dev->dev->of_node;
4009         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4010         int val;
4011
4012         if (of_property_read_u32(np, "rockchip,prop", &val))
4013                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4014         else
4015                 lcdc_dev->prop = val;
4016
4017         if (of_property_read_u32(np, "rockchip,mirror", &val))
4018                 dev_drv->rotate_mode = NO_MIRROR;
4019         else
4020                 dev_drv->rotate_mode = val;
4021
4022         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4023                 dev_drv->cabc_mode = 0; /* default set close cabc */
4024         else
4025                 dev_drv->cabc_mode = val;
4026
4027         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4028                 lcdc_dev->pwr18 = false;        /*default set it as 3.xv power supply */
4029         else
4030                 lcdc_dev->pwr18 = (val ? true : false);
4031
4032         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4033                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4034         else
4035                 dev_drv->fb_win_map = val;
4036
4037         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4038                 dev_drv->bcsh.enable = false;
4039         else
4040                 dev_drv->bcsh.enable = (val ? true : false);
4041
4042         if (of_property_read_u32(np, "rockchip,brightness", &val))
4043                 dev_drv->bcsh.brightness = 0xffff;
4044         else
4045                 dev_drv->bcsh.brightness = val;
4046
4047         if (of_property_read_u32(np, "rockchip,contrast", &val))
4048                 dev_drv->bcsh.contrast = 0xffff;
4049         else
4050                 dev_drv->bcsh.contrast = val;
4051
4052         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4053                 dev_drv->bcsh.sat_con = 0xffff;
4054         else
4055                 dev_drv->bcsh.sat_con = val;
4056
4057         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4058                 dev_drv->bcsh.sin_hue = 0xffff;
4059                 dev_drv->bcsh.cos_hue = 0xffff;
4060         } else {
4061                 dev_drv->bcsh.sin_hue = val & 0xff;
4062                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4063         }
4064
4065 #if defined(CONFIG_ROCKCHIP_IOMMU)
4066         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4067                 dev_drv->iommu_enabled = 0;
4068         else
4069                 dev_drv->iommu_enabled = val;
4070 #else
4071         dev_drv->iommu_enabled = 0;
4072 #endif
4073         return 0;
4074 }
4075
4076 static int rk3288_lcdc_probe(struct platform_device *pdev)
4077 {
4078         struct lcdc_device *lcdc_dev = NULL;
4079         struct rk_lcdc_driver *dev_drv;
4080         struct device *dev = &pdev->dev;
4081         struct resource *res;
4082         struct device_node *np = pdev->dev.of_node;
4083         int prop;
4084         int ret = 0;
4085
4086         /*if the primary lcdc has not registered ,the extend
4087            lcdc register later */
4088         of_property_read_u32(np, "rockchip,prop", &prop);
4089         if (prop == EXTEND) {
4090                 if (!is_prmry_rk_lcdc_registered())
4091                         return -EPROBE_DEFER;
4092         }
4093         lcdc_dev = devm_kzalloc(dev,
4094                                 sizeof(struct lcdc_device), GFP_KERNEL);
4095         if (!lcdc_dev) {
4096                 dev_err(&pdev->dev, "rk3288 lcdc device kmalloc fail!");
4097                 return -ENOMEM;
4098         }
4099         platform_set_drvdata(pdev, lcdc_dev);
4100         lcdc_dev->dev = dev;
4101         rk3288_lcdc_parse_dt(lcdc_dev);
4102         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4103         lcdc_dev->reg_phy_base = res->start;
4104         lcdc_dev->len = resource_size(res);
4105         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4106         if (IS_ERR(lcdc_dev->regs))
4107                 return PTR_ERR(lcdc_dev->regs);
4108
4109         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4110         if (IS_ERR(lcdc_dev->regsbak))
4111                 return PTR_ERR(lcdc_dev->regsbak);
4112         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4113         lcdc_dev->id = rk3288_lcdc_get_id(lcdc_dev->reg_phy_base);
4114         if (lcdc_dev->id < 0) {
4115                 dev_err(&pdev->dev, "no such lcdc device!\n");
4116                 return -ENXIO;
4117         }
4118         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4119         dev_drv = &lcdc_dev->driver;
4120         dev_drv->dev = dev;
4121         dev_drv->prop = prop;
4122         dev_drv->id = lcdc_dev->id;
4123         dev_drv->ops = &lcdc_drv_ops;
4124         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4125         spin_lock_init(&lcdc_dev->reg_lock);
4126
4127         lcdc_dev->irq = platform_get_irq(pdev, 0);
4128         if (lcdc_dev->irq < 0) {
4129                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4130                         lcdc_dev->id);
4131                 return -ENXIO;
4132         }
4133
4134         ret = devm_request_irq(dev, lcdc_dev->irq, rk3288_lcdc_isr,
4135                                IRQF_DISABLED | IRQF_SHARED, dev_name(dev), lcdc_dev);
4136         if (ret) {
4137                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4138                         lcdc_dev->irq, ret);
4139                 return ret;
4140         }
4141
4142         if (dev_drv->iommu_enabled) {
4143                 if(lcdc_dev->id == 0){
4144                         strcpy(dev_drv->mmu_dts_name, VOPB_IOMMU_COMPATIBLE_NAME);
4145                 }else{
4146                         strcpy(dev_drv->mmu_dts_name, VOPL_IOMMU_COMPATIBLE_NAME);
4147                 }
4148         }
4149
4150         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4151         if (ret < 0) {
4152                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4153                 return ret;
4154         }
4155         lcdc_dev->screen = dev_drv->screen0;
4156         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4157                 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4158
4159         return 0;
4160 }
4161
4162 static int rk3288_lcdc_remove(struct platform_device *pdev)
4163 {
4164
4165         return 0;
4166 }
4167
4168 static void rk3288_lcdc_shutdown(struct platform_device *pdev)
4169 {
4170         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4171
4172         rk3288_lcdc_deint(lcdc_dev);
4173         rk_disp_pwr_disable(&lcdc_dev->driver);
4174 }
4175
4176 #if defined(CONFIG_OF)
4177 static const struct of_device_id rk3288_lcdc_dt_ids[] = {
4178         {.compatible = "rockchip,rk3288-lcdc",},
4179         {}
4180 };
4181 #endif
4182
4183 static struct platform_driver rk3288_lcdc_driver = {
4184         .probe = rk3288_lcdc_probe,
4185         .remove = rk3288_lcdc_remove,
4186         .driver = {
4187                    .name = "rk3288-lcdc",
4188                    .owner = THIS_MODULE,
4189                    .of_match_table = of_match_ptr(rk3288_lcdc_dt_ids),
4190                    },
4191         .suspend = rk3288_lcdc_suspend,
4192         .resume = rk3288_lcdc_resume,
4193         .shutdown = rk3288_lcdc_shutdown,
4194 };
4195
4196 static int __init rk3288_lcdc_module_init(void)
4197 {
4198         return platform_driver_register(&rk3288_lcdc_driver);
4199 }
4200
4201 static void __exit rk3288_lcdc_module_exit(void)
4202 {
4203         platform_driver_unregister(&rk3288_lcdc_driver);
4204 }
4205
4206 fs_initcall(rk3288_lcdc_module_init);
4207 module_exit(rk3288_lcdc_module_exit);
4208
4209