2 * drivers/video/rockchip/lcdc/rk3368_lcdc.c
4 * Copyright (C) 2014 ROCKCHIP, Inc.
5 *Author:hjc<hjc@rock-chips.com>
6 *This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/errno.h>
20 #include <linux/string.h>
22 #include <linux/slab.h>
23 #include <linux/device.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/rockchip-iovmm.h>
30 #include <asm/div64.h>
31 #include <linux/uaccess.h>
32 #include <linux/rockchip/cpu.h>
33 #include <linux/rockchip/iomap.h>
34 #include <linux/rockchip/grf.h>
35 #include <linux/rockchip/common.h>
36 #include <dt-bindings/clock/rk_system_status.h>
38 #include "rk3368_lcdc.h"
40 #if defined(CONFIG_HAS_EARLYSUSPEND)
41 #include <linux/earlysuspend.h>
43 /*#define CONFIG_RK_FPGA 1*/
45 static int dbg_thresd;
46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
48 #define DBG(level, x...) do { \
49 if (unlikely(dbg_thresd >= level)) \
53 static struct rk_lcdc_win lcdc_win[] = {
81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
83 /*#define WAIT_FOR_SYNC 1*/
84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
88 if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
90 else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
104 struct lcdc_device *lcdc_dev =
105 container_of(dev_drv, struct lcdc_device, driver);
107 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
109 lcdc_cfg_done(lcdc_dev);
111 for (i = 0; i < 256; i++) {
113 c = lcdc_dev->cabc_lut_addr_base + i;
114 writel_relaxed(v, c);
116 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
127 struct lcdc_device *lcdc_dev =
128 container_of(dev_drv, struct lcdc_device, driver);
130 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
132 lcdc_cfg_done(lcdc_dev);
134 for (i = 0; i < 256; i++) {
136 c = lcdc_dev->dsp_lut_addr_base + i;
137 writel_relaxed(v, c);
139 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
147 #ifdef CONFIG_RK_FPGA
148 lcdc_dev->clk_on = 1;
151 if (!lcdc_dev->clk_on) {
152 clk_prepare_enable(lcdc_dev->hclk);
153 clk_prepare_enable(lcdc_dev->dclk);
154 clk_prepare_enable(lcdc_dev->aclk);
155 /*clk_prepare_enable(lcdc_dev->pd);*/
156 spin_lock(&lcdc_dev->reg_lock);
157 lcdc_dev->clk_on = 1;
158 spin_unlock(&lcdc_dev->reg_lock);
164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
166 #ifdef CONFIG_RK_FPGA
167 lcdc_dev->clk_on = 0;
170 if (lcdc_dev->clk_on) {
171 spin_lock(&lcdc_dev->reg_lock);
172 lcdc_dev->clk_on = 0;
173 spin_unlock(&lcdc_dev->reg_lock);
175 clk_disable_unprepare(lcdc_dev->dclk);
176 clk_disable_unprepare(lcdc_dev->hclk);
177 clk_disable_unprepare(lcdc_dev->aclk);
178 /*clk_disable_unprepare(lcdc_dev->pd);*/
184 static int __maybe_unused
185 rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
189 spin_lock(&lcdc_dev->reg_lock);
190 if (likely(lcdc_dev->clk_on)) {
191 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
192 m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
193 m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
194 m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
195 m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
196 m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
197 m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
198 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
199 v_ADDR_SAME_INTR_EN(0) |
200 v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
201 v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
202 v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
203 v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
204 v_POST_BUF_EMPTY_INTR_EN(0) |
205 v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
206 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
208 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
209 m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
210 m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
211 m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
212 m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
213 m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
214 m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
215 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
216 v_ADDR_SAME_INTR_CLR(1) |
217 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
218 v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
219 v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
220 v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
221 v_POST_BUF_EMPTY_INTR_CLR(1) |
222 v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
223 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
224 lcdc_cfg_done(lcdc_dev);
225 spin_unlock(&lcdc_dev->reg_lock);
227 spin_unlock(&lcdc_dev->reg_lock);
233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
235 struct lcdc_device *lcdc_dev =
236 container_of(dev_drv, struct lcdc_device, driver);
237 int *cbase = (int *)lcdc_dev->regs;
238 int *regsbak = (int *)lcdc_dev->regsbak;
240 char dbg_message[30];
243 pr_info("lcd back up reg:\n");
244 memset(dbg_message, 0, sizeof(dbg_message));
245 memset(buf, 0, sizeof(buf));
246 for (i = 0; i <= (0x200 >> 4); i++) {
247 val = sprintf(dbg_message, "0x%04x: ", i * 16);
248 for (j = 0; j < 4; j++) {
249 val = sprintf(buf, "%08x ", *(regsbak + i * 4 + j));
250 strcat(dbg_message, buf);
252 pr_info("%s\n", dbg_message);
253 memset(dbg_message, 0, sizeof(dbg_message));
254 memset(buf, 0, sizeof(buf));
257 pr_info("lcdc reg:\n");
258 for (i = 0; i <= (0x200 >> 4); i++) {
259 val = sprintf(dbg_message, "0x%04x: ", i * 16);
260 for (j = 0; j < 4; j++) {
261 sprintf(buf, "%08x ",
262 readl_relaxed(cbase + i * 4 + j));
263 strcat(dbg_message, buf);
265 pr_info("%s\n", dbg_message);
266 memset(dbg_message, 0, sizeof(dbg_message));
267 memset(buf, 0, sizeof(buf));
274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en) \
277 spin_lock(&lcdc_dev->reg_lock); \
278 msk = m_WIN##id##_EN; \
279 val = v_WIN##id##_EN(en); \
280 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
281 lcdc_cfg_done(lcdc_dev); \
282 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
283 while (val != (!!en)) { \
284 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk); \
286 spin_unlock(&lcdc_dev->reg_lock); \
294 /*enable/disable win directly*/
295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
298 struct lcdc_device *lcdc_dev =
299 container_of(drv, struct lcdc_device, driver);
301 win0_enable(lcdc_dev, en);
302 else if (win_id == 1)
303 win1_enable(lcdc_dev, en);
304 else if (win_id == 2)
305 win2_enable(lcdc_dev, en);
306 else if (win_id == 3)
307 win3_enable(lcdc_dev, en);
309 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
313 #define SET_WIN_ADDR(id) \
314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
317 spin_lock(&lcdc_dev->reg_lock); \
318 lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr); \
319 msk = m_WIN##id##_EN; \
320 val = v_WIN0_EN(1); \
321 lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val); \
322 lcdc_cfg_done(lcdc_dev); \
323 spin_unlock(&lcdc_dev->reg_lock); \
329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
330 int win_id, u32 addr)
332 struct lcdc_device *lcdc_dev =
333 container_of(dev_drv, struct lcdc_device, driver);
335 set_win0_addr(lcdc_dev, addr);
337 set_win1_addr(lcdc_dev, addr);
342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
346 struct rk_screen *screen = lcdc_dev->driver.cur_screen;
347 u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
348 u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
350 struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
352 spin_lock(&lcdc_dev->reg_lock);
353 for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
354 val = lcdc_readl_backup(lcdc_dev, reg);
357 win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
359 ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
362 win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
363 win0->area[0].ysize =
364 ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
367 st_x = val & m_WIN0_DSP_XST;
368 st_y = (val & m_WIN0_DSP_YST) >> 16;
369 win0->area[0].xpos = st_x - h_pw_bp;
370 win0->area[0].ypos = st_y - v_pw_bp;
373 win0->state = val & m_WIN0_EN;
374 win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
375 win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
376 win0->area[0].format = win0->area[0].fmt_cfg;
379 win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
380 win0->area[0].uv_vir_stride =
381 (val & m_WIN0_VIR_STRIDE_UV) >> 16;
382 if (win0->area[0].format == ARGB888)
383 win0->area[0].xvir = win0->area[0].y_vir_stride;
384 else if (win0->area[0].format == RGB888)
386 win0->area[0].y_vir_stride * 4 / 3;
387 else if (win0->area[0].format == RGB565)
389 2 * win0->area[0].y_vir_stride;
392 4 * win0->area[0].y_vir_stride;
395 win0->area[0].smem_start = val;
398 win0->area[0].cbr_start = val;
404 spin_unlock(&lcdc_dev->reg_lock);
407 /********do basic init*********/
408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
411 struct lcdc_device *lcdc_dev =
412 container_of(dev_drv, struct lcdc_device, driver);
413 if (lcdc_dev->pre_init)
416 lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
417 lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
418 lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
419 /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
421 if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
422 (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
423 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
427 rk_disp_pwr_enable(dev_drv);
428 rk3368_lcdc_clk_enable(lcdc_dev);
430 /*backup reg config at uboot */
431 lcdc_read_reg_defalut_cfg(lcdc_dev);
432 if (lcdc_dev->pwr18 == 1) {
433 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
434 lcdc_grf_writel(lcdc_dev->pmugrf_base,
435 PMUGRF_SOC_CON0_VOP, v);
437 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
438 lcdc_grf_writel(lcdc_dev->pmugrf_base,
439 PMUGRF_SOC_CON0_VOP, v);
441 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
442 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
443 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
444 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
445 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
446 lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
448 lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
449 lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
450 lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
451 lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
452 lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
453 lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
455 mask = m_AUTO_GATING_EN;
456 val = v_AUTO_GATING_EN(0);
457 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
458 lcdc_cfg_done(lcdc_dev);
459 /*disable win0 to workaround iommu pagefault */
460 /*if (dev_drv->iommu_enabled) */
461 /* win0_enable(lcdc_dev, 0); */
462 lcdc_dev->pre_init = true;
467 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
471 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
473 struct lcdc_device *lcdc_dev =
474 container_of(dev_drv, struct lcdc_device, driver);
475 struct rk_screen *screen = dev_drv->cur_screen;
476 u16 x_res = screen->mode.xres;
477 u16 y_res = screen->mode.yres;
479 u16 h_total, v_total;
480 u16 post_hsd_en, post_vsd_en;
481 u16 post_dsp_hact_st, post_dsp_hact_end;
482 u16 post_dsp_vact_st, post_dsp_vact_end;
483 u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
484 u16 post_h_fac, post_v_fac;
486 h_total = screen->mode.hsync_len + screen->mode.left_margin +
487 x_res + screen->mode.right_margin;
488 v_total = screen->mode.vsync_len + screen->mode.upper_margin +
489 y_res + screen->mode.lower_margin;
491 if (screen->post_dsp_stx + screen->post_xsize > x_res) {
492 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
493 screen->post_dsp_stx, screen->post_xsize, x_res);
494 screen->post_dsp_stx = x_res - screen->post_xsize;
496 if (screen->x_mirror == 0) {
497 post_dsp_hact_st = screen->post_dsp_stx +
498 screen->mode.hsync_len + screen->mode.left_margin;
499 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
501 post_dsp_hact_end = h_total - screen->mode.right_margin -
502 screen->post_dsp_stx;
503 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
505 if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
508 GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
514 if (screen->post_dsp_sty + screen->post_ysize > y_res) {
515 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
516 screen->post_dsp_sty, screen->post_ysize, y_res);
517 screen->post_dsp_sty = y_res - screen->post_ysize;
520 if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
522 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
529 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
530 post_dsp_vact_st = screen->post_dsp_sty / 2 +
531 screen->mode.vsync_len +
532 screen->mode.upper_margin;
533 post_dsp_vact_end = post_dsp_vact_st +
534 screen->post_ysize / 2;
536 post_dsp_vact_st_f1 = screen->mode.vsync_len +
537 screen->mode.upper_margin +
539 screen->mode.lower_margin +
540 screen->mode.vsync_len +
541 screen->mode.upper_margin +
542 screen->post_dsp_sty / 2 +
544 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
545 screen->post_ysize/2;
547 if (screen->y_mirror == 0) {
548 post_dsp_vact_st = screen->post_dsp_sty +
549 screen->mode.vsync_len +
550 screen->mode.upper_margin;
551 post_dsp_vact_end = post_dsp_vact_st +
554 post_dsp_vact_end = v_total -
555 screen->mode.lower_margin -
556 screen->post_dsp_sty;
557 post_dsp_vact_st = post_dsp_vact_end -
560 post_dsp_vact_st_f1 = 0;
561 post_dsp_vact_end_f1 = 0;
563 DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
564 screen->post_xsize, screen->post_ysize, screen->xpos);
565 DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
566 screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
567 mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
568 val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
569 v_DSP_HACT_ST_POST(post_dsp_hact_st);
570 lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
572 mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
573 val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
574 v_DSP_VACT_ST_POST(post_dsp_vact_st);
575 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
577 mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
578 val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
579 v_POST_VS_FACTOR_YRGB(post_v_fac);
580 lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
582 mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
583 val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
584 v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
585 lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
587 mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
588 val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
589 lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
593 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
595 struct lcdc_device *lcdc_dev =
596 container_of(dev_drv, struct lcdc_device, driver);
597 struct rk_lcdc_win *win;
598 u32 colorkey_r, colorkey_g, colorkey_b;
601 for (i = 0; i < 4; i++) {
602 win = dev_drv->win[i];
603 key_val = win->color_key_val;
604 colorkey_r = (key_val & 0xff) << 2;
605 colorkey_g = ((key_val >> 8) & 0xff) << 12;
606 colorkey_b = ((key_val >> 16) & 0xff) << 22;
607 /*color key dither 565/888->aaa */
608 key_val = colorkey_r | colorkey_g | colorkey_b;
611 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
614 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
617 lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
620 lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
623 pr_info("%s:un support win num:%d\n",
631 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
633 struct lcdc_device *lcdc_dev =
634 container_of(dev_drv, struct lcdc_device, driver);
635 struct rk_lcdc_win *win = dev_drv->win[win_id];
636 struct alpha_config alpha_config;
638 int ppixel_alpha = 0, global_alpha = 0, i;
639 u32 src_alpha_ctl, dst_alpha_ctl;
641 for (i = 0; i < win->area_num; i++) {
642 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
643 (win->area[i].format == FBDC_ARGB_888) ||
644 (win->area[i].format == ABGR888)) ? 1 : 0;
646 global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
647 alpha_config.src_global_alpha_val = win->g_alpha_val;
648 win->alpha_mode = AB_SRC_OVER;
649 /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
650 __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
652 switch (win->alpha_mode) {
656 alpha_config.src_factor_mode = AA_ZERO;
657 alpha_config.dst_factor_mode = AA_ZERO;
660 alpha_config.src_factor_mode = AA_ONE;
661 alpha_config.dst_factor_mode = AA_ZERO;
664 alpha_config.src_factor_mode = AA_ZERO;
665 alpha_config.dst_factor_mode = AA_ONE;
668 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
670 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
672 alpha_config.src_factor_mode = AA_ONE;
673 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
676 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
677 alpha_config.src_factor_mode = AA_SRC_INVERSE;
678 alpha_config.dst_factor_mode = AA_ONE;
681 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
682 alpha_config.src_factor_mode = AA_SRC;
683 alpha_config.dst_factor_mode = AA_ZERO;
686 alpha_config.src_factor_mode = AA_ZERO;
687 alpha_config.dst_factor_mode = AA_SRC;
690 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
691 alpha_config.src_factor_mode = AA_SRC_INVERSE;
692 alpha_config.dst_factor_mode = AA_ZERO;
695 alpha_config.src_factor_mode = AA_ZERO;
696 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
699 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
700 alpha_config.src_factor_mode = AA_SRC;
701 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
704 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
705 alpha_config.src_factor_mode = AA_SRC_INVERSE;
706 alpha_config.dst_factor_mode = AA_SRC;
709 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
710 alpha_config.src_factor_mode = AA_SRC_INVERSE;
711 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
713 case AB_SRC_OVER_GLOBAL:
714 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
715 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
716 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
717 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
720 pr_err("alpha mode error\n");
723 if ((ppixel_alpha == 1) && (global_alpha == 1))
724 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
725 else if (ppixel_alpha == 1)
726 alpha_config.src_global_alpha_mode = AA_PER_PIX;
727 else if (global_alpha == 1)
728 alpha_config.src_global_alpha_mode = AA_GLOBAL;
730 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
731 alpha_config.src_alpha_mode = AA_STRAIGHT;
732 alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
736 src_alpha_ctl = 0x60;
737 dst_alpha_ctl = 0x64;
740 src_alpha_ctl = 0xa0;
741 dst_alpha_ctl = 0xa4;
744 src_alpha_ctl = 0xdc;
745 dst_alpha_ctl = 0xec;
748 src_alpha_ctl = 0x12c;
749 dst_alpha_ctl = 0x13c;
752 src_alpha_ctl = 0x160;
753 dst_alpha_ctl = 0x164;
756 mask = m_WIN0_DST_FACTOR_M0;
757 val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
758 lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
759 mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
760 m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
761 m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
762 m_WIN0_SRC_GLOBAL_ALPHA;
763 val = v_WIN0_SRC_ALPHA_EN(1) |
764 v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
765 v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
766 v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
767 v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
768 v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
769 v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
770 lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
775 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
777 struct rk_lcdc_win_area area_temp;
780 for (i = 0; i < area_num; i++) {
781 for (j = i + 1; j < area_num; j++) {
782 if (win->area[i].dsp_stx > win->area[j].dsp_stx) {
783 memcpy(&area_temp, &win->area[i],
784 sizeof(struct rk_lcdc_win_area));
785 memcpy(&win->area[i], &win->area[j],
786 sizeof(struct rk_lcdc_win_area));
787 memcpy(&win->area[j], &area_temp,
788 sizeof(struct rk_lcdc_win_area));
796 static int __maybe_unused
797 rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
799 struct rk_lcdc_win_area area_temp;
803 area_temp = win->area[0];
804 win->area[0] = win->area[1];
805 win->area[1] = area_temp;
808 area_temp = win->area[0];
809 win->area[0] = win->area[2];
810 win->area[2] = area_temp;
813 area_temp = win->area[0];
814 win->area[0] = win->area[3];
815 win->area[3] = area_temp;
817 area_temp = win->area[1];
818 win->area[1] = win->area[2];
819 win->area[2] = area_temp;
822 pr_info("un supported area num!\n");
828 static int __maybe_unused
829 rk3368_win_area_check_var(int win_id, int area_num,
830 struct rk_lcdc_win_area *area_pre,
831 struct rk_lcdc_win_area *area_now)
833 if ((area_pre->xpos > area_now->xpos) ||
834 ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
835 (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
838 "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
839 "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
841 area_num - 1, area_pre->xpos, area_pre->xsize,
842 area_pre->ypos, area_pre->ysize,
843 area_num, area_now->xpos, area_now->xsize,
844 area_now->ypos, area_now->ysize);
850 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
852 struct lcdc_device *lcdc_dev =
853 container_of(dev_drv, struct lcdc_device, driver);
856 for (i = 0; i < 100; i++) {
857 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
858 val &= m_DBG_IFBDC_IDLE;
867 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
869 struct lcdc_device *lcdc_dev =
870 container_of(dev_drv, struct lcdc_device, driver);
871 struct rk_lcdc_win *win = dev_drv->win[win_id];
874 mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
875 m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
876 m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
877 val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
878 v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
879 v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
880 v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
881 v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
882 v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
883 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
885 mask = m_IFBDC_TILES_NUM;
886 val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
887 lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
889 mask = m_IFBDC_BASE_ADDR;
890 val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
891 lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
893 mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
894 val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
895 v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
896 lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
898 mask = m_IFBDC_CMP_INDEX_INIT;
899 val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
900 lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
902 mask = m_IFBDC_MB_VIR_WIDTH;
903 val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
904 lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
909 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
911 struct lcdc_device *lcdc_dev =
912 container_of(dev_drv, struct lcdc_device, driver);
913 struct rk_lcdc_win *win = dev_drv->win[win_id];
914 u8 fbdc_dsp_width_ratio;
915 u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
916 u16 fbdc_mb_width, fbdc_mb_height;
917 u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
918 u16 fbdc_cmp_index_init;
919 u8 mb_w_size, mb_h_size;
920 struct rk_screen *screen = dev_drv->cur_screen;
922 if (screen->mode.flag == FB_VMODE_INTERLACED) {
923 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
927 switch (win->area[0].fmt_cfg) {
928 case VOP_FORMAT_ARGB888:
929 fbdc_dsp_width_ratio = 0;
932 case VOP_FORMAT_RGB888:
933 fbdc_dsp_width_ratio = 0;
936 case VOP_FORMAT_RGB565:
937 fbdc_dsp_width_ratio = 1;
941 dev_err(lcdc_dev->dev,
942 "in fbdc mode,unsupport fmt:%d!\n",
943 win->area[0].fmt_cfg);
948 /*macro block xvir and yvir */
949 if ((win->area[0].xvir % mb_w_size == 0) &&
950 (win->area[0].yvir % mb_h_size == 0)) {
951 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
952 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
954 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
955 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
956 win->area[0].xvir, win->area[0].yvir,
957 mb_w_size, mb_h_size);
959 /*macro block xact and yact */
960 if ((win->area[0].xact % mb_w_size == 0) &&
961 (win->area[0].yact % mb_h_size == 0)) {
962 fbdc_mb_width = win->area[0].xact / mb_w_size;
963 fbdc_mb_height = win->area[0].yact / mb_h_size;
965 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
966 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
967 win->area[0].xact, win->area[0].yact,
968 mb_w_size, mb_h_size);
970 /*macro block xoff and yoff */
971 if ((win->area[0].xoff % mb_w_size == 0) &&
972 (win->area[0].yoff % mb_h_size == 0)) {
973 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
974 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
976 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
977 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
978 win->area[0].xoff, win->area[0].yoff,
979 mb_w_size, mb_h_size);
983 fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
986 switch (fbdc_rotation_mode) {
988 fbdc_cmp_index_init =
989 (fbdc_mb_yst*fbdc_mb_vir_width) + fbdc_mb_xst;
992 fbdc_cmp_index_init =
993 (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
997 fbdc_cmp_index_init =
998 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1002 fbdc_cmp_index_init =
1003 ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1004 (fbdc_mb_xst+(fbdc_mb_width-1));
1008 if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1009 fbdc_cmp_index_init =
1010 ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1011 (fbdc_mb_xst + (fbdc_mb_width - 1));
1013 fbdc_cmp_index_init =
1014 (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1016 /*fbdc fmt maybe need to change*/
1017 win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1018 win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1019 win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1020 win->area[0].fbdc_mb_width = fbdc_mb_width;
1021 win->area[0].fbdc_mb_height = fbdc_mb_height;
1022 win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1023 win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1024 win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1025 win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1030 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1031 struct rk_lcdc_win *win)
1033 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1034 struct rk_screen *screen = dev_drv->cur_screen;
1036 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1037 switch (win->area[0].fmt_cfg) {
1038 case VOP_FORMAT_ARGB888:
1039 case VOP_FORMAT_RGB888:
1040 case VOP_FORMAT_RGB565:
1041 if ((screen->mode.xres < 1280) &&
1042 (screen->mode.yres < 720)) {
1043 win->csc_mode = VOP_R2Y_CSC_BT601;
1045 win->csc_mode = VOP_R2Y_CSC_BT709;
1051 } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1052 switch (win->area[0].fmt_cfg) {
1053 case VOP_FORMAT_YCBCR420:
1054 if ((win->id == 0) || (win->id == 1))
1055 win->csc_mode = VOP_Y2R_CSC_MPEG;
1063 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1065 struct lcdc_device *lcdc_dev =
1066 container_of(dev_drv, struct lcdc_device, driver);
1067 struct rk_lcdc_win *win = dev_drv->win[win_id];
1068 unsigned int mask, val, off;
1070 off = win_id * 0x40;
1071 /*if(win->win_lb_mode == 5)
1072 win->win_lb_mode = 4;
1073 for rk3288 to fix hw bug? */
1075 if (win->state == 1) {
1076 rk3368_lcdc_csc_mode(lcdc_dev, win);
1077 if (win->area[0].fbdc_en) {
1078 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1080 mask = m_IFBDC_CTRL_FBDC_EN;
1081 val = v_IFBDC_CTRL_FBDC_EN(0);
1082 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1084 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1085 m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1086 m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1087 val = v_WIN0_EN(win->state) |
1088 v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1089 v_WIN0_FMT_10(win->fmt_10) |
1090 v_WIN0_LB_MODE(win->win_lb_mode) |
1091 v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1092 v_WIN0_X_MIRROR(win->mirror_en) |
1093 v_WIN0_Y_MIRROR(win->mirror_en) |
1094 v_WIN0_CSC_MODE(win->csc_mode);
1095 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1097 mask = m_WIN0_BIC_COE_SEL |
1098 m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1099 m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1100 m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1101 m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1102 m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1103 m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1104 m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1105 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1106 v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1107 v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1108 v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1109 v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1110 v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1111 v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1112 v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1113 v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1114 v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1115 v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1116 v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1117 v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1118 v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1119 v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1120 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1121 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1122 v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1123 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1124 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1125 win->area[0].y_addr);
1126 lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1127 win->area[0].uv_addr); */
1128 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1129 v_WIN0_ACT_HEIGHT(win->area[0].yact);
1130 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1132 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1133 v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1134 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1136 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1137 v_WIN0_DSP_YST(win->area[0].dsp_sty);
1138 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1140 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1141 v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1142 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1144 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1145 v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1146 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1147 if (win->alpha_en == 1) {
1148 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1150 mask = m_WIN0_SRC_ALPHA_EN;
1151 val = v_WIN0_SRC_ALPHA_EN(0);
1152 lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1157 val = v_WIN0_EN(win->state);
1158 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1163 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1165 struct lcdc_device *lcdc_dev =
1166 container_of(dev_drv, struct lcdc_device, driver);
1167 struct rk_lcdc_win *win = dev_drv->win[win_id];
1168 unsigned int mask, val, off;
1170 off = (win_id - 2) * 0x50;
1171 rk3368_lcdc_area_xst(win, win->area_num);
1173 if (win->state == 1) {
1174 rk3368_lcdc_csc_mode(lcdc_dev, win);
1175 if (win->area[0].fbdc_en) {
1176 rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1178 mask = m_IFBDC_CTRL_FBDC_EN;
1179 val = v_IFBDC_CTRL_FBDC_EN(0);
1180 lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1183 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1184 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1185 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1187 if (win->area[0].state == 1) {
1188 mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1190 val = v_WIN2_MST0_EN(win->area[0].state) |
1191 v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1192 v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1193 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1195 mask = m_WIN2_VIR_STRIDE0;
1196 val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1197 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1199 /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1200 win->area[0].y_addr); */
1201 val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1202 v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1203 lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1204 val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1205 v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1206 lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1208 mask = m_WIN2_MST0_EN;
1209 val = v_WIN2_MST0_EN(0);
1210 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1213 if (win->area[1].state == 1) {
1214 /*rk3368_win_area_check_var(win_id, 1,
1215 &win->area[0], &win->area[1]);
1218 mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1220 val = v_WIN2_MST1_EN(win->area[1].state) |
1221 v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1222 v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1223 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1225 mask = m_WIN2_VIR_STRIDE1;
1226 val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1227 lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1229 /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1230 win->area[1].y_addr); */
1231 val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1232 v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1233 lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1234 val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1235 v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1236 lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1238 mask = m_WIN2_MST1_EN;
1239 val = v_WIN2_MST1_EN(0);
1240 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1243 if (win->area[2].state == 1) {
1244 /*rk3368_win_area_check_var(win_id, 2,
1245 &win->area[1], &win->area[2]);
1248 mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1250 val = v_WIN2_MST2_EN(win->area[2].state) |
1251 v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1252 v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1253 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1255 mask = m_WIN2_VIR_STRIDE2;
1256 val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1257 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1259 /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1260 win->area[2].y_addr); */
1261 val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1262 v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1263 lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1264 val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1265 v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1266 lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1268 mask = m_WIN2_MST2_EN;
1269 val = v_WIN2_MST2_EN(0);
1270 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1273 if (win->area[3].state == 1) {
1274 /*rk3368_win_area_check_var(win_id, 3,
1275 &win->area[2], &win->area[3]);
1278 mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1280 val = v_WIN2_MST3_EN(win->area[3].state) |
1281 v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1282 v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1283 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1285 mask = m_WIN2_VIR_STRIDE3;
1286 val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1287 lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1289 /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1290 win->area[3].y_addr); */
1291 val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1292 v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1293 lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1294 val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1295 v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1296 lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1298 mask = m_WIN2_MST3_EN;
1299 val = v_WIN2_MST3_EN(0);
1300 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1303 if (win->alpha_en == 1) {
1304 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1306 mask = m_WIN2_SRC_ALPHA_EN;
1307 val = v_WIN2_SRC_ALPHA_EN(0);
1308 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1312 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1313 m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1314 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1315 v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1316 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1321 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1323 struct lcdc_device *lcdc_dev =
1324 container_of(dev_drv, struct lcdc_device, driver);
1325 struct rk_lcdc_win *win = dev_drv->win[win_id];
1326 unsigned int mask, val, hwc_size = 0;
1328 if (win->state == 1) {
1329 rk3368_lcdc_csc_mode(lcdc_dev, win);
1330 mask = m_HWC_EN | m_HWC_DATA_FMT |
1331 m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1332 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1333 v_HWC_RB_SWAP(win->area[0].swap_rb) |
1334 v_WIN0_CSC_MODE(win->csc_mode);
1335 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1337 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1339 else if ((win->area[0].xsize == 64) &&
1340 (win->area[0].ysize == 64))
1342 else if ((win->area[0].xsize == 96) &&
1343 (win->area[0].ysize == 96))
1345 else if ((win->area[0].xsize == 128) &&
1346 (win->area[0].ysize == 128))
1349 dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1352 val = v_HWC_SIZE(hwc_size);
1353 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1355 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1356 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1357 v_HWC_DSP_YST(win->area[0].dsp_sty);
1358 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1360 if (win->alpha_en == 1) {
1361 rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1363 mask = m_WIN2_SRC_ALPHA_EN;
1364 val = v_WIN2_SRC_ALPHA_EN(0);
1365 lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1369 val = v_HWC_EN(win->state);
1370 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1375 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1376 struct rk_lcdc_win *win)
1378 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1380 unsigned long flags;
1382 spin_lock(&lcdc_dev->reg_lock);
1383 if (likely(lcdc_dev->clk_on)) {
1384 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1385 v_STANDBY_EN(lcdc_dev->standby));
1386 if ((win->id == 0) || (win->id == 1))
1387 rk3368_win_0_1_reg_update(dev_drv, win->id);
1388 else if ((win->id == 2) || (win->id == 3))
1389 rk3368_win_2_3_reg_update(dev_drv, win->id);
1390 else if (win->id == 4)
1391 rk3368_hwc_reg_update(dev_drv, win->id);
1392 /*rk3368_lcdc_post_cfg(dev_drv); */
1393 lcdc_cfg_done(lcdc_dev);
1395 spin_unlock(&lcdc_dev->reg_lock);
1397 /*if (dev_drv->wait_fs) { */
1399 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1400 init_completion(&dev_drv->frame_done);
1401 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1403 wait_for_completion_timeout(&dev_drv->frame_done,
1405 (dev_drv->cur_screen->ft + 5));
1406 if (!timeout && (!dev_drv->frame_done.done)) {
1407 dev_warn(lcdc_dev->dev,
1408 "wait for new frame start time out!\n");
1412 DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1416 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1418 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1422 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1425 struct lcdc_device *lcdc_dev =
1426 container_of(dev_drv, struct lcdc_device, driver);
1428 #if defined(CONFIG_ROCKCHIP_IOMMU)
1429 if (dev_drv->iommu_enabled) {
1430 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1431 if (likely(lcdc_dev->clk_on)) {
1434 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1435 mask = m_AXI_MAX_OUTSTANDING_EN |
1436 m_AXI_OUTSTANDING_MAX_NUM;
1437 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1438 v_AXI_MAX_OUTSTANDING_EN(1);
1439 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1441 lcdc_dev->iommu_status = 1;
1442 rockchip_iovmm_activate(dev_drv->dev);
1449 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1451 int ret = 0, fps = 0;
1452 struct lcdc_device *lcdc_dev =
1453 container_of(dev_drv, struct lcdc_device, driver);
1454 struct rk_screen *screen = dev_drv->cur_screen;
1455 #ifdef CONFIG_RK_FPGA
1459 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1461 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1462 lcdc_dev->pixclock =
1463 div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1464 lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1466 fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1467 screen->ft = 1000 / fps;
1468 dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1469 lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1473 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1475 struct lcdc_device *lcdc_dev =
1476 container_of(dev_drv, struct lcdc_device, driver);
1477 struct rk_screen *screen = dev_drv->cur_screen;
1478 u16 hsync_len = screen->mode.hsync_len;
1479 u16 left_margin = screen->mode.left_margin;
1480 u16 right_margin = screen->mode.right_margin;
1481 u16 vsync_len = screen->mode.vsync_len;
1482 u16 upper_margin = screen->mode.upper_margin;
1483 u16 lower_margin = screen->mode.lower_margin;
1484 u16 x_res = screen->mode.xres;
1485 u16 y_res = screen->mode.yres;
1487 u16 h_total, v_total;
1488 u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1490 h_total = hsync_len + left_margin + x_res + right_margin;
1491 v_total = vsync_len + upper_margin + y_res + lower_margin;
1493 screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1494 screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1495 screen->post_xsize = x_res *
1496 (screen->overscan.left + screen->overscan.right) / 200;
1497 screen->post_ysize = y_res *
1498 (screen->overscan.top + screen->overscan.bottom) / 200;
1500 mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1501 val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1502 lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1504 mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1505 val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1506 v_DSP_HACT_ST(hsync_len + left_margin);
1507 lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1509 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1510 /* First Field Timing */
1511 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1512 val = v_DSP_VS_PW(vsync_len) |
1513 v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1514 lower_margin) + y_res + 1);
1515 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1517 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1518 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1519 v_DSP_VACT_ST(vsync_len + upper_margin);
1520 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1522 /* Second Field Timing */
1523 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1524 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1525 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1527 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1528 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1530 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1531 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1533 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1536 v_DSP_VACT_END_F1(vact_end_f1) |
1537 v_DSP_VAC_ST_F1(vact_st_f1);
1538 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1540 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1541 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1542 v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1544 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1547 v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1548 v_WIN0_CBR_DEFLICK(1);
1549 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1552 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1555 v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1556 v_WIN1_CBR_DEFLICK(1);
1557 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1559 mask = m_WIN2_INTERLACE_READ;
1560 val = v_WIN2_INTERLACE_READ(1);
1561 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1563 mask = m_WIN3_INTERLACE_READ;
1564 val = v_WIN3_INTERLACE_READ(1);
1565 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1567 mask = m_HWC_INTERLACE_READ;
1568 val = v_HWC_INTERLACE_READ(1);
1569 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1571 mask = m_DSP_LINE_FLAG0_NUM;
1573 v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1574 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1576 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1577 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1578 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1580 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1581 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1582 v_DSP_VACT_ST(vsync_len + upper_margin);
1583 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1585 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1586 m_DSP_INTERLACE | m_DSP_FIELD_POL,
1587 v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1590 m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1593 v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1594 v_WIN0_CBR_DEFLICK(0);
1595 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1598 m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1601 v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1602 v_WIN1_CBR_DEFLICK(0);
1603 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1605 mask = m_WIN2_INTERLACE_READ;
1606 val = v_WIN2_INTERLACE_READ(0);
1607 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1609 mask = m_WIN3_INTERLACE_READ;
1610 val = v_WIN3_INTERLACE_READ(0);
1611 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1613 mask = m_HWC_INTERLACE_READ;
1614 val = v_HWC_INTERLACE_READ(0);
1615 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1617 mask = m_DSP_LINE_FLAG0_NUM;
1618 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1619 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1621 rk3368_lcdc_post_cfg(dev_drv);
1625 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1627 struct lcdc_device *lcdc_dev =
1628 container_of(dev_drv, struct lcdc_device, driver);
1631 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1632 v_OVERLAY_MODE(dev_drv->overlay_mode));
1633 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1634 if (dev_drv->output_color == COLOR_YCBCR) /* bypass */
1635 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1636 m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1637 v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1639 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1640 m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1643 v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1645 } else { /* overlay_mode=VOP_RGB_DOMAIN */
1646 /* bypass --need check,if bcsh close? */
1647 if (dev_drv->output_color == COLOR_RGB) {
1648 bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1649 if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1650 (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1651 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1657 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1658 m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1661 } else /* RGB2YUV */
1662 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1664 m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1666 v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1671 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1672 u16 *yact, int *format, u32 *dsp_addr)
1674 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1675 struct lcdc_device, driver);
1678 spin_lock(&lcdc_dev->reg_lock);
1680 val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1681 *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1682 *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1684 val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1685 *format = (val & m_WIN0_DATA_FMT) >> 1;
1686 *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1688 spin_unlock(&lcdc_dev->reg_lock);
1693 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1694 int format, u16 xact, u16 yact, u16 xvir)
1696 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1697 struct lcdc_device, driver);
1699 int swap = (format == RGB888) ? 1 : 0;
1701 mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1702 val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1703 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1705 lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1706 v_WIN0_VIR_STRIDE(xvir));
1707 lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1708 v_WIN0_ACT_HEIGHT(yact));
1710 lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1712 lcdc_cfg_done(lcdc_dev);
1718 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1723 struct lcdc_device *lcdc_dev =
1724 container_of(dev_drv, struct lcdc_device, driver);
1725 struct rk_screen *screen = dev_drv->cur_screen;
1728 spin_lock(&lcdc_dev->reg_lock);
1729 if (likely(lcdc_dev->clk_on)) {
1730 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1731 if (!lcdc_dev->standby && !initscreen) {
1732 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1734 lcdc_cfg_done(lcdc_dev);
1737 switch (screen->face) {
1740 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1742 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1743 v_DITHER_DOWN_SEL(1);
1744 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1748 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1750 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1751 v_DITHER_DOWN_SEL(1);
1752 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1756 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1758 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1759 v_DITHER_DOWN_SEL(1);
1760 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1764 mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1766 val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1767 v_DITHER_DOWN_SEL(1);
1768 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1772 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1773 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1774 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1777 /*yuv420 output prefer yuv domain overlay */
1780 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1781 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1782 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1785 dev_err(lcdc_dev->dev, "un supported interface!\n");
1788 switch (screen->type) {
1790 mask = m_RGB_OUT_EN;
1791 val = v_RGB_OUT_EN(1);
1792 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1793 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1794 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1795 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1796 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1797 v_RGB_LVDS_DEN_POL(screen->pin_den) |
1798 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1799 v = 1 << 15 | (1 << (15 + 16));
1803 mask = m_RGB_OUT_EN;
1804 val = v_RGB_OUT_EN(1);
1805 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1806 mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1807 m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1808 val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1809 v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1810 v_RGB_LVDS_DEN_POL(screen->pin_den) |
1811 v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1812 v = 0 << 15 | (1 << (15 + 16));
1815 /*face = OUT_RGB_AAA;*/
1816 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1817 mask = m_HDMI_OUT_EN | m_RGB_OUT_EN;
1818 val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1819 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1820 mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1821 m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1822 val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1823 v_HDMI_VSYNC_POL(screen->pin_vsync) |
1824 v_HDMI_DEN_POL(screen->pin_den) |
1825 v_HDMI_DCLK_POL(screen->pin_dclk);
1828 mask = m_MIPI_OUT_EN | m_RGB_OUT_EN;
1829 val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1830 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1831 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1832 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1833 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1834 v_MIPI_VSYNC_POL(screen->pin_vsync) |
1835 v_MIPI_DEN_POL(screen->pin_den) |
1836 v_MIPI_DCLK_POL(screen->pin_dclk);
1838 case SCREEN_DUAL_MIPI:
1839 mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN |
1841 val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1843 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1844 mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1845 m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1846 val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1847 v_MIPI_VSYNC_POL(screen->pin_vsync) |
1848 v_MIPI_DEN_POL(screen->pin_den) |
1849 v_MIPI_DCLK_POL(screen->pin_dclk);
1852 face = OUT_P888; /*RGB 888 output */
1854 mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1855 val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1856 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1857 /*because edp have to sent aaa fmt */
1858 mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1859 val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1861 mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1862 m_EDP_DEN_POL | m_EDP_DCLK_POL;
1863 val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1864 v_EDP_VSYNC_POL(screen->pin_vsync) |
1865 v_EDP_DEN_POL(screen->pin_den) |
1866 v_EDP_DCLK_POL(screen->pin_dclk);
1869 /*hsync vsync den dclk polo,dither */
1870 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1871 #ifndef CONFIG_RK_FPGA
1872 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1873 move to lvds driver*/
1874 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1876 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1877 m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1878 m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1879 m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1880 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1881 v_DSP_BG_SWAP(screen->swap_gb) |
1882 v_DSP_RB_SWAP(screen->swap_rb) |
1883 v_DSP_RG_SWAP(screen->swap_rg) |
1884 v_DSP_DELTA_SWAP(screen->swap_delta) |
1885 v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1886 v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1887 v_DSP_X_MIR_EN(screen->x_mirror) |
1888 v_DSP_Y_MIR_EN(screen->y_mirror);
1889 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1891 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1892 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1893 val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1896 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1898 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1899 dev_drv->output_color = screen->color_mode;
1900 if (screen->dsp_lut == NULL)
1901 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1904 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1906 if (screen->cabc_lut == NULL) {
1907 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN,
1910 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
1913 rk3368_lcdc_bcsh_path_sel(dev_drv);
1914 rk3368_config_timing(dev_drv);
1916 spin_unlock(&lcdc_dev->reg_lock);
1917 rk3368_lcdc_set_dclk(dev_drv);
1918 if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1919 dev_drv->trsm_ops->enable)
1920 dev_drv->trsm_ops->enable();
1923 if (!lcdc_dev->standby)
1924 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1929 /*enable layer,open:1,enable;0 disable*/
1930 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1931 unsigned int win_id, bool open)
1933 spin_lock(&lcdc_dev->reg_lock);
1934 if (likely(lcdc_dev->clk_on) &&
1935 lcdc_dev->driver.win[win_id]->state != open) {
1937 if (!lcdc_dev->atv_layer_cnt) {
1938 dev_info(lcdc_dev->dev,
1939 "wakeup from standby!\n");
1940 lcdc_dev->standby = 0;
1942 lcdc_dev->atv_layer_cnt |= (1 << win_id);
1944 if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1945 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1947 lcdc_dev->driver.win[win_id]->state = open;
1949 /*rk3368_lcdc_reg_update(dev_drv);*/
1950 rk3368_lcdc_layer_update_regs
1951 (lcdc_dev, lcdc_dev->driver.win[win_id]);
1952 lcdc_cfg_done(lcdc_dev);
1954 /*if no layer used,disable lcdc */
1955 if (!lcdc_dev->atv_layer_cnt) {
1956 dev_info(lcdc_dev->dev,
1957 "no layer is used,go to standby!\n");
1958 lcdc_dev->standby = 1;
1961 spin_unlock(&lcdc_dev->reg_lock);
1964 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1966 struct lcdc_device *lcdc_dev = container_of(dev_drv,
1967 struct lcdc_device, driver);
1969 /*struct rk_screen *screen = dev_drv->cur_screen; */
1971 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1972 m_LINE_FLAG1_INTR_CLR;
1973 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1974 v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1975 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1977 mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1978 val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1979 v_BUS_ERROR_INTR_EN(1);
1980 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1982 #ifdef LCDC_IRQ_EMPTY_DEBUG
1983 mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1984 m_WIN2_EMPTY_INTR_EN |
1985 m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1986 m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1987 val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1988 v_WIN2_EMPTY_INTR_EN(1) |
1989 v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1990 v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1991 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1996 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1999 struct lcdc_device *lcdc_dev =
2000 container_of(dev_drv, struct lcdc_device, driver);
2001 #if 0/*ndef CONFIG_RK_FPGA*/
2003 (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2005 /*enable clk,when first layer open */
2006 if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2007 /*rockchip_set_system_status(sys_status);*/
2008 rk3368_lcdc_pre_init(dev_drv);
2009 rk3368_lcdc_clk_enable(lcdc_dev);
2010 #if defined(CONFIG_ROCKCHIP_IOMMU)
2011 if (dev_drv->iommu_enabled) {
2012 if (!dev_drv->mmu_dev) {
2014 rk_fb_get_sysmmu_device_by_compatible
2015 (dev_drv->mmu_dts_name);
2016 if (dev_drv->mmu_dev) {
2017 rk_fb_platform_set_sysmmu
2018 (dev_drv->mmu_dev, dev_drv->dev);
2020 dev_err(dev_drv->dev,
2021 "fail get rk iommu device\n");
2025 /*if (dev_drv->mmu_dev)
2026 rockchip_iovmm_activate(dev_drv->dev); */
2029 rk3368_lcdc_reg_restore(lcdc_dev);
2030 /*if (dev_drv->iommu_enabled)
2031 rk3368_lcdc_mmu_en(dev_drv); */
2032 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2033 /*rk3368_lcdc_set_dclk(dev_drv); */
2034 rk3368_lcdc_enable_irq(dev_drv);
2036 rk3368_load_screen(dev_drv, 1);
2038 if (dev_drv->bcsh.enable)
2039 rk3368_lcdc_set_bcsh(dev_drv, 1);
2040 spin_lock(&lcdc_dev->reg_lock);
2041 if (dev_drv->cur_screen->dsp_lut)
2042 rk3368_lcdc_set_lut(dev_drv,
2043 dev_drv->cur_screen->dsp_lut);
2044 if (dev_drv->cur_screen->cabc_lut)
2045 rk3368_set_cabc_lut(dev_drv,
2046 dev_drv->cur_screen->cabc_lut);
2047 spin_unlock(&lcdc_dev->reg_lock);
2050 if (win_id < ARRAY_SIZE(lcdc_win))
2051 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2053 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2056 /* when all layer closed,disable clk */
2057 /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2058 rk3368_lcdc_disable_irq(lcdc_dev);
2059 rk3368_lcdc_reg_update(dev_drv);
2060 #if defined(CONFIG_ROCKCHIP_IOMMU)
2061 if (dev_drv->iommu_enabled) {
2062 if (dev_drv->mmu_dev)
2063 rockchip_iovmm_deactivate(dev_drv->dev);
2066 rk3368_lcdc_clk_disable(lcdc_dev);
2067 #ifndef CONFIG_RK_FPGA
2068 rockchip_clear_system_status(sys_status);
2075 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2076 struct rk_lcdc_win *win)
2082 off = win->id * 0x40;
2083 /*win->smem_start + win->y_offset; */
2084 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2085 uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2086 DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2087 lcdc_dev->id, win->id, y_addr, uv_addr);
2088 DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2089 win->area[0].y_offset, win->area[0].c_offset);
2090 spin_lock(&lcdc_dev->reg_lock);
2091 if (likely(lcdc_dev->clk_on)) {
2092 win->area[0].y_addr = y_addr;
2093 win->area[0].uv_addr = uv_addr;
2094 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2095 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2096 /*lcdc_cfg_done(lcdc_dev); */
2098 spin_unlock(&lcdc_dev->reg_lock);
2103 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2104 struct rk_lcdc_win *win)
2109 off = (win->id - 2) * 0x50;
2110 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2111 DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2113 spin_lock(&lcdc_dev->reg_lock);
2114 if (likely(lcdc_dev->clk_on)) {
2115 for (i = 0; i < win->area_num; i++) {
2116 DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2117 i, win->area[i].y_addr, win->area[i].y_offset);
2118 win->area[i].y_addr =
2119 win->area[i].smem_start + win->area[i].y_offset;
2121 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2122 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2123 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2124 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2126 spin_unlock(&lcdc_dev->reg_lock);
2130 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2134 y_addr = win->area[0].smem_start + win->area[0].y_offset;
2135 DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2136 lcdc_dev->id, __func__, y_addr);
2137 spin_lock(&lcdc_dev->reg_lock);
2138 if (likely(lcdc_dev->clk_on)) {
2139 win->area[0].y_addr = y_addr;
2140 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2142 spin_unlock(&lcdc_dev->reg_lock);
2147 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2149 struct lcdc_device *lcdc_dev =
2150 container_of(dev_drv, struct lcdc_device, driver);
2151 struct rk_lcdc_win *win = NULL;
2152 struct rk_screen *screen = dev_drv->cur_screen;
2154 #if defined(WAIT_FOR_SYNC)
2156 unsigned long flags;
2158 win = dev_drv->win[win_id];
2160 dev_err(dev_drv->dev, "screen is null!\n");
2164 win_0_1_display(lcdc_dev, win);
2165 } else if (win_id == 1) {
2166 win_0_1_display(lcdc_dev, win);
2167 } else if (win_id == 2) {
2168 win_2_3_display(lcdc_dev, win);
2169 } else if (win_id == 3) {
2170 win_2_3_display(lcdc_dev, win);
2171 } else if (win_id == 4) {
2172 hwc_display(lcdc_dev, win);
2174 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2178 /*this is the first frame of the system ,enable frame start interrupt */
2179 if ((dev_drv->first_frame)) {
2180 dev_drv->first_frame = 0;
2181 rk3368_lcdc_enable_irq(dev_drv);
2183 #if defined(WAIT_FOR_SYNC)
2184 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2185 init_completion(&dev_drv->frame_done);
2186 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2188 wait_for_completion_timeout(&dev_drv->frame_done,
2189 msecs_to_jiffies(dev_drv->
2190 cur_screen->ft + 5));
2191 if (!timeout && (!dev_drv->frame_done.done)) {
2192 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2199 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2209 u32 yrgb_vscalednmult;
2210 u32 yrgb_xscl_factor;
2211 u32 yrgb_yscl_factor;
2212 u8 yrgb_vsd_bil_gt2 = 0;
2213 u8 yrgb_vsd_bil_gt4 = 0;
2219 u32 cbcr_vscalednmult;
2220 u32 cbcr_xscl_factor;
2221 u32 cbcr_yscl_factor;
2222 u8 cbcr_vsd_bil_gt2 = 0;
2223 u8 cbcr_vsd_bil_gt4 = 0;
2226 srcW = win->area[0].xact;
2227 srcH = win->area[0].yact;
2228 dstW = win->area[0].xsize;
2229 dstH = win->area[0].ysize;
2236 if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2237 pr_err("ERROR: yrgb scale exceed 8,");
2238 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2239 yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2241 if (yrgb_srcW < yrgb_dstW)
2242 win->yrgb_hor_scl_mode = SCALE_UP;
2243 else if (yrgb_srcW > yrgb_dstW)
2244 win->yrgb_hor_scl_mode = SCALE_DOWN;
2246 win->yrgb_hor_scl_mode = SCALE_NONE;
2248 if (yrgb_srcH < yrgb_dstH)
2249 win->yrgb_ver_scl_mode = SCALE_UP;
2250 else if (yrgb_srcH > yrgb_dstH)
2251 win->yrgb_ver_scl_mode = SCALE_DOWN;
2253 win->yrgb_ver_scl_mode = SCALE_NONE;
2256 switch (win->area[0].format) {
2259 cbcr_srcW = srcW / 2;
2267 cbcr_srcW = srcW / 2;
2269 cbcr_srcH = srcH / 2;
2290 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2291 (cbcr_dstH * 8 <= cbcr_srcH)) {
2292 pr_err("ERROR: cbcr scale exceed 8,");
2293 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2294 cbcr_srcH, cbcr_dstW, cbcr_dstH);
2298 if (cbcr_srcW < cbcr_dstW)
2299 win->cbr_hor_scl_mode = SCALE_UP;
2300 else if (cbcr_srcW > cbcr_dstW)
2301 win->cbr_hor_scl_mode = SCALE_DOWN;
2303 win->cbr_hor_scl_mode = SCALE_NONE;
2305 if (cbcr_srcH < cbcr_dstH)
2306 win->cbr_ver_scl_mode = SCALE_UP;
2307 else if (cbcr_srcH > cbcr_dstH)
2308 win->cbr_ver_scl_mode = SCALE_DOWN;
2310 win->cbr_ver_scl_mode = SCALE_NONE;
2312 /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2313 "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2314 "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2315 srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2316 win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2317 cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2318 win->cbr_ver_scl_mode);*/
2320 /*line buffer mode */
2321 if ((win->area[0].format == YUV422) ||
2322 (win->area[0].format == YUV420) ||
2323 (win->area[0].format == YUV422_A) ||
2324 (win->area[0].format == YUV420_A)) {
2325 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2326 if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2328 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2330 else if (cbcr_dstW > 1280)
2331 win->win_lb_mode = LB_YUV_3840X5;
2333 win->win_lb_mode = LB_YUV_2560X8;
2334 } else { /*SCALE_UP or SCALE_NONE */
2335 if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2337 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2339 else if (cbcr_srcW > 1280)
2340 win->win_lb_mode = LB_YUV_3840X5;
2342 win->win_lb_mode = LB_YUV_2560X8;
2345 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2346 if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2348 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2349 else if (yrgb_dstW > 2560)
2350 win->win_lb_mode = LB_RGB_3840X2;
2351 else if (yrgb_dstW > 1920)
2352 win->win_lb_mode = LB_RGB_2560X4;
2353 else if (yrgb_dstW > 1280)
2354 win->win_lb_mode = LB_RGB_1920X5;
2356 win->win_lb_mode = LB_RGB_1280X8;
2357 } else { /*SCALE_UP or SCALE_NONE */
2358 if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2360 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2361 else if (yrgb_srcW > 2560)
2362 win->win_lb_mode = LB_RGB_3840X2;
2363 else if (yrgb_srcW > 1920)
2364 win->win_lb_mode = LB_RGB_2560X4;
2365 else if (yrgb_srcW > 1280)
2366 win->win_lb_mode = LB_RGB_1920X5;
2368 win->win_lb_mode = LB_RGB_1280X8;
2371 DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2373 /*vsd/vsu scale ALGORITHM */
2374 win->yrgb_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2375 win->cbr_hsd_mode = SCALE_DOWN_BIL; /*not to specify */
2376 win->yrgb_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2377 win->cbr_vsd_mode = SCALE_DOWN_BIL; /*not to specify */
2378 switch (win->win_lb_mode) {
2383 win->yrgb_vsu_mode = SCALE_UP_BIC;
2384 win->cbr_vsu_mode = SCALE_UP_BIC;
2387 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2388 pr_err("ERROR : not allow yrgb ver scale\n");
2389 if (win->cbr_ver_scl_mode != SCALE_NONE)
2390 pr_err("ERROR : not allow cbcr ver scale\n");
2393 win->yrgb_vsu_mode = SCALE_UP_BIL;
2394 win->cbr_vsu_mode = SCALE_UP_BIL;
2397 pr_info("%s:un supported win_lb_mode:%d\n",
2398 __func__, win->win_lb_mode);
2401 if (win->mirror_en == 1) { /*interlace mode must bill */
2402 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2405 if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2406 (win->area[0].fbdc_en == 1)) {
2407 /*in this pattern,use bil mode,not support souble scd,
2408 use avg mode, support double scd, but aclk should be
2409 bigger than dclk,aclk>>dclk */
2410 if (yrgb_srcH >= 2 * yrgb_dstH) {
2411 pr_err("ERROR : fbdc mode,not support y scale down:");
2412 pr_err("srcH[%d] > 2 *dstH[%d]\n",
2413 yrgb_srcH, yrgb_dstH);
2416 DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2417 win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2418 win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2422 /*(1.1)YRGB HOR SCALE FACTOR */
2423 switch (win->yrgb_hor_scl_mode) {
2425 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2428 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2431 switch (win->yrgb_hsd_mode) {
2432 case SCALE_DOWN_BIL:
2434 GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2436 case SCALE_DOWN_AVG:
2438 GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2442 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2443 win->yrgb_hsd_mode);
2448 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2449 __func__, win->yrgb_hor_scl_mode);
2451 } /*win->yrgb_hor_scl_mode */
2453 /*(1.2)YRGB VER SCALE FACTOR */
2454 switch (win->yrgb_ver_scl_mode) {
2456 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2459 switch (win->yrgb_vsu_mode) {
2462 GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2465 if (yrgb_srcH < 3) {
2466 pr_err("yrgb_srcH should be");
2467 pr_err(" greater than 3 !!!\n");
2469 yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2473 pr_info("%s:un support yrgb_vsu_mode:%d\n",
2474 __func__, win->yrgb_vsu_mode);
2479 switch (win->yrgb_vsd_mode) {
2480 case SCALE_DOWN_BIL:
2482 rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2485 GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2487 if (yrgb_yscl_factor >= 0x2000) {
2488 pr_err("yrgb_yscl_factor should be ");
2489 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2492 if (yrgb_vscalednmult == 4) {
2493 yrgb_vsd_bil_gt4 = 1;
2494 yrgb_vsd_bil_gt2 = 0;
2495 } else if (yrgb_vscalednmult == 2) {
2496 yrgb_vsd_bil_gt4 = 0;
2497 yrgb_vsd_bil_gt2 = 1;
2499 yrgb_vsd_bil_gt4 = 0;
2500 yrgb_vsd_bil_gt2 = 0;
2503 case SCALE_DOWN_AVG:
2504 yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2508 pr_info("%s:un support yrgb_vsd_mode:%d\n",
2509 __func__, win->yrgb_vsd_mode);
2511 } /*win->yrgb_vsd_mode */
2514 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2515 __func__, win->yrgb_ver_scl_mode);
2518 win->scale_yrgb_x = yrgb_xscl_factor;
2519 win->scale_yrgb_y = yrgb_yscl_factor;
2520 win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2521 win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2522 DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2523 yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2525 /*(2.1)CBCR HOR SCALE FACTOR */
2526 switch (win->cbr_hor_scl_mode) {
2528 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2531 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2534 switch (win->cbr_hsd_mode) {
2535 case SCALE_DOWN_BIL:
2537 GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2539 case SCALE_DOWN_AVG:
2541 GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2544 pr_info("%s:un support cbr_hsd_mode:%d\n",
2545 __func__, win->cbr_hsd_mode);
2550 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2551 __func__, win->cbr_hor_scl_mode);
2553 } /*win->cbr_hor_scl_mode */
2555 /*(2.2)CBCR VER SCALE FACTOR */
2556 switch (win->cbr_ver_scl_mode) {
2558 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2561 switch (win->cbr_vsu_mode) {
2564 GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2567 if (cbcr_srcH < 3) {
2568 pr_err("cbcr_srcH should be ");
2569 pr_err("greater than 3 !!!\n");
2571 cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2575 pr_info("%s:un support cbr_vsu_mode:%d\n",
2576 __func__, win->cbr_vsu_mode);
2581 switch (win->cbr_vsd_mode) {
2582 case SCALE_DOWN_BIL:
2584 rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2587 GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2589 if (cbcr_yscl_factor >= 0x2000) {
2590 pr_err("cbcr_yscl_factor should be less ");
2591 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2595 if (cbcr_vscalednmult == 4) {
2596 cbcr_vsd_bil_gt4 = 1;
2597 cbcr_vsd_bil_gt2 = 0;
2598 } else if (cbcr_vscalednmult == 2) {
2599 cbcr_vsd_bil_gt4 = 0;
2600 cbcr_vsd_bil_gt2 = 1;
2602 cbcr_vsd_bil_gt4 = 0;
2603 cbcr_vsd_bil_gt2 = 0;
2606 case SCALE_DOWN_AVG:
2607 cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2611 pr_info("%s:un support cbr_vsd_mode:%d\n",
2612 __func__, win->cbr_vsd_mode);
2617 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2618 __func__, win->cbr_ver_scl_mode);
2621 win->scale_cbcr_x = cbcr_xscl_factor;
2622 win->scale_cbcr_y = cbcr_yscl_factor;
2623 win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2624 win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2626 DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2627 cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2631 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2632 struct rk_lcdc_win_area *area)
2636 if (screen->x_mirror && mirror_en)
2637 pr_err("not support both win and global mirror\n");
2639 if ((!mirror_en) && (!screen->x_mirror))
2640 pos = area->xpos + screen->mode.left_margin +
2641 screen->mode.hsync_len;
2643 pos = screen->mode.xres - area->xpos -
2644 area->xsize + screen->mode.left_margin +
2645 screen->mode.hsync_len;
2650 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2651 struct rk_lcdc_win_area *area)
2655 if (screen->y_mirror && mirror_en)
2656 pr_err("not support both win and global mirror\n");
2657 if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2658 if ((!mirror_en) && (!screen->y_mirror))
2659 pos = area->ypos + screen->mode.upper_margin +
2660 screen->mode.vsync_len;
2662 pos = screen->mode.yres - area->ypos -
2663 area->ysize + screen->mode.upper_margin +
2664 screen->mode.vsync_len;
2665 } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2666 pos = area->ypos / 2 + screen->mode.upper_margin +
2667 screen->mode.vsync_len;
2674 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2675 struct rk_screen *screen, struct rk_lcdc_win *win)
2677 u32 xact, yact, xvir, yvir, xpos, ypos;
2678 u8 fmt_cfg = 0, swap_rb;
2679 char fmt[9] = "NULL";
2681 xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2682 ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2684 spin_lock(&lcdc_dev->reg_lock);
2685 if (likely(lcdc_dev->clk_on)) {
2686 rk3368_lcdc_cal_scl_fac(win); /*fac,lb,gt2,gt4 */
2687 switch (win->area[0].format) {
2692 win->area[0].fbdc_fmt_cfg = 0x05;
2698 win->area[0].fbdc_fmt_cfg = 0x0c;
2704 win->area[0].fbdc_fmt_cfg = 0x3a;
2758 dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2762 win->area[0].fmt_cfg = fmt_cfg;
2763 win->area[0].swap_rb = swap_rb;
2764 win->area[0].dsp_stx = xpos;
2765 win->area[0].dsp_sty = ypos;
2766 xact = win->area[0].xact;
2767 yact = win->area[0].yact;
2768 xvir = win->area[0].xvir;
2769 yvir = win->area[0].yvir;
2771 if (win->area[0].fbdc_en)
2772 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2773 rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2774 spin_unlock(&lcdc_dev->reg_lock);
2776 DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2777 lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2778 xact, yact, win->area[0].xsize);
2779 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2780 win->area[0].ysize, xvir, yvir, xpos, ypos);
2786 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2787 struct rk_screen *screen, struct rk_lcdc_win *win)
2790 u8 fmt_cfg, swap_rb;
2791 char fmt[9] = "NULL";
2794 pr_err("win[%d] not support y mirror\n", win->id);
2795 spin_lock(&lcdc_dev->reg_lock);
2796 if (likely(lcdc_dev->clk_on)) {
2797 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2798 for (i = 0; i < win->area_num; i++) {
2799 switch (win->area[i].format) {
2804 win->area[0].fbdc_fmt_cfg = 0x05;
2810 win->area[0].fbdc_fmt_cfg = 0x0c;
2816 win->area[0].fbdc_fmt_cfg = 0x3a;
2836 dev_err(lcdc_dev->driver.dev,
2837 "%s:un supported format!\n", __func__);
2840 win->area[i].fmt_cfg = fmt_cfg;
2841 win->area[i].swap_rb = swap_rb;
2842 win->area[i].dsp_stx =
2843 dsp_x_pos(win->mirror_en, screen,
2845 win->area[i].dsp_sty =
2846 dsp_y_pos(win->mirror_en, screen,
2849 DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2850 get_format_string(win->area[i].format, fmt),
2851 win->area[i].xsize, win->area[i].ysize,
2852 win->area[i].xpos, win->area[i].ypos);
2855 if (win->area[0].fbdc_en)
2856 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2857 rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2858 spin_unlock(&lcdc_dev->reg_lock);
2862 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2863 struct rk_screen *screen, struct rk_lcdc_win *win)
2865 u32 xact, yact, xvir, yvir, xpos, ypos;
2866 u8 fmt_cfg = 0, swap_rb;
2867 char fmt[9] = "NULL";
2869 xpos = win->area[0].xpos + screen->mode.left_margin +
2870 screen->mode.hsync_len;
2871 ypos = win->area[0].ypos + screen->mode.upper_margin +
2872 screen->mode.vsync_len;
2874 spin_lock(&lcdc_dev->reg_lock);
2875 if (likely(lcdc_dev->clk_on)) {
2876 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2877 switch (win->area[0].format) {
2896 dev_err(lcdc_dev->driver.dev,
2897 "%s:un supported format!\n", __func__);
2900 win->area[0].fmt_cfg = fmt_cfg;
2901 win->area[0].swap_rb = swap_rb;
2902 win->area[0].dsp_stx = xpos;
2903 win->area[0].dsp_sty = ypos;
2904 xact = win->area[0].xact;
2905 yact = win->area[0].yact;
2906 xvir = win->area[0].xvir;
2907 yvir = win->area[0].yvir;
2909 rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2910 spin_unlock(&lcdc_dev->reg_lock);
2912 DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2913 lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2914 xact, yact, win->area[0].xsize);
2915 DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2916 win->area[0].ysize, xvir, yvir, xpos, ypos);
2920 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2922 struct lcdc_device *lcdc_dev =
2923 container_of(dev_drv, struct lcdc_device, driver);
2924 struct rk_lcdc_win *win = NULL;
2925 struct rk_screen *screen = dev_drv->cur_screen;
2927 win = dev_drv->win[win_id];
2930 win_0_1_set_par(lcdc_dev, screen, win);
2933 win_0_1_set_par(lcdc_dev, screen, win);
2936 win_2_3_set_par(lcdc_dev, screen, win);
2939 win_2_3_set_par(lcdc_dev, screen, win);
2942 hwc_set_par(lcdc_dev, screen, win);
2945 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2951 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2952 unsigned long arg, int win_id)
2954 struct lcdc_device *lcdc_dev =
2955 container_of(dev_drv, struct lcdc_device, driver);
2957 void __user *argp = (void __user *)arg;
2958 struct color_key_cfg clr_key_cfg;
2961 case RK_FBIOGET_PANEL_SIZE:
2962 panel_size[0] = lcdc_dev->screen->mode.xres;
2963 panel_size[1] = lcdc_dev->screen->mode.yres;
2964 if (copy_to_user(argp, panel_size, 8))
2967 case RK_FBIOPUT_COLOR_KEY_CFG:
2968 if (copy_from_user(&clr_key_cfg, argp,
2969 sizeof(struct color_key_cfg)))
2971 rk3368_lcdc_clr_key_cfg(dev_drv);
2972 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2973 clr_key_cfg.win0_color_key_cfg);
2974 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2975 clr_key_cfg.win1_color_key_cfg);
2984 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2986 struct lcdc_device *lcdc_dev = container_of(dev_drv,
2987 struct lcdc_device, driver);
2988 /*struct device_node *backlight;*/
2990 if (lcdc_dev->backlight)
2993 backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2995 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2996 if (!lcdc_dev->backlight)
2997 dev_info(lcdc_dev->dev, "No find backlight device\n");
2999 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3005 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3007 struct lcdc_device *lcdc_dev =
3008 container_of(dev_drv, struct lcdc_device, driver);
3009 if (dev_drv->suspend_flag)
3011 /* close the backlight */
3012 /*rk3368_lcdc_get_backlight_device(dev_drv);
3013 if (lcdc_dev->backlight) {
3014 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3015 backlight_update_status(lcdc_dev->backlight);
3018 dev_drv->suspend_flag = 1;
3019 flush_kthread_worker(&dev_drv->update_regs_worker);
3021 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3022 dev_drv->trsm_ops->disable();
3024 spin_lock(&lcdc_dev->reg_lock);
3025 if (likely(lcdc_dev->clk_on)) {
3026 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3028 lcdc_msk_reg(lcdc_dev,
3029 INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3030 v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3031 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3033 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3034 lcdc_cfg_done(lcdc_dev);
3036 if (dev_drv->iommu_enabled) {
3037 if (dev_drv->mmu_dev)
3038 rockchip_iovmm_deactivate(dev_drv->dev);
3041 spin_unlock(&lcdc_dev->reg_lock);
3043 spin_unlock(&lcdc_dev->reg_lock);
3046 rk3368_lcdc_clk_disable(lcdc_dev);
3047 rk_disp_pwr_disable(dev_drv);
3051 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3053 struct lcdc_device *lcdc_dev =
3054 container_of(dev_drv, struct lcdc_device, driver);
3056 if (!dev_drv->suspend_flag)
3058 rk_disp_pwr_enable(dev_drv);
3059 dev_drv->suspend_flag = 0;
3061 if (1/*lcdc_dev->atv_layer_cnt*/) {
3062 rk3368_lcdc_clk_enable(lcdc_dev);
3063 rk3368_lcdc_reg_restore(lcdc_dev);
3065 spin_lock(&lcdc_dev->reg_lock);
3066 if (dev_drv->cur_screen->dsp_lut)
3067 rk3368_lcdc_set_lut(dev_drv,
3068 dev_drv->cur_screen->dsp_lut);
3069 if (dev_drv->cur_screen->cabc_lut)
3070 rk3368_set_cabc_lut(dev_drv,
3071 dev_drv->cur_screen->cabc_lut);
3073 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3075 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3076 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3078 lcdc_cfg_done(lcdc_dev);
3080 if (dev_drv->iommu_enabled) {
3081 if (dev_drv->mmu_dev)
3082 rockchip_iovmm_activate(dev_drv->dev);
3085 spin_unlock(&lcdc_dev->reg_lock);
3088 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3089 dev_drv->trsm_ops->enable();
3094 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3095 int win_id, int blank_mode)
3097 switch (blank_mode) {
3098 case FB_BLANK_UNBLANK:
3099 rk3368_lcdc_early_resume(dev_drv);
3101 case FB_BLANK_NORMAL:
3102 rk3368_lcdc_early_suspend(dev_drv);
3105 rk3368_lcdc_early_suspend(dev_drv);
3109 dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3114 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3119 /*overlay will be do at regupdate*/
3120 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3123 struct lcdc_device *lcdc_dev =
3124 container_of(dev_drv, struct lcdc_device, driver);
3125 struct rk_lcdc_win *win = NULL;
3127 unsigned int mask, val;
3128 int z_order_num = 0;
3129 int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3132 for (i = 0; i < 4; i++) {
3133 win = dev_drv->win[i];
3134 if (win->state == 1)
3137 for (i = 0; i < 4; i++) {
3138 win = dev_drv->win[i];
3139 if (win->state == 0)
3140 win->z_order = z_order_num++;
3141 switch (win->z_order) {
3143 layer0_sel = win->id;
3146 layer1_sel = win->id;
3149 layer2_sel = win->id;
3152 layer3_sel = win->id;
3159 layer0_sel = swap % 10;
3160 layer1_sel = swap / 10 % 10;
3161 layer2_sel = swap / 100 % 10;
3162 layer3_sel = swap / 1000;
3165 spin_lock(&lcdc_dev->reg_lock);
3166 if (lcdc_dev->clk_on) {
3168 mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3169 m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3170 val = v_DSP_LAYER0_SEL(layer0_sel) |
3171 v_DSP_LAYER1_SEL(layer1_sel) |
3172 v_DSP_LAYER2_SEL(layer2_sel) |
3173 v_DSP_LAYER3_SEL(layer3_sel);
3174 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3176 layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3178 layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3180 layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3182 layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3184 ovl = layer3_sel * 1000 + layer2_sel * 100 +
3185 layer1_sel * 10 + layer0_sel;
3190 spin_unlock(&lcdc_dev->reg_lock);
3195 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3202 strcpy(fmt, "ARGB888");
3205 strcpy(fmt, "RGB888");
3208 strcpy(fmt, "RGB565");
3211 strcpy(fmt, "YCbCr420");
3214 strcpy(fmt, "YCbCr422");
3217 strcpy(fmt, "YCbCr444");
3220 strcpy(fmt, "invalid\n");
3225 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3226 char *buf, int win_id)
3228 struct lcdc_device *lcdc_dev =
3229 container_of(dev_drv, struct lcdc_device, driver);
3230 struct rk_screen *screen = dev_drv->cur_screen;
3231 u16 hsync_len = screen->mode.hsync_len;
3232 u16 left_margin = screen->mode.left_margin;
3233 u16 vsync_len = screen->mode.vsync_len;
3234 u16 upper_margin = screen->mode.upper_margin;
3235 u32 h_pw_bp = hsync_len + left_margin;
3236 u32 v_pw_bp = vsync_len + upper_margin;
3238 char format_w0[9] = "NULL";
3239 char format_w1[9] = "NULL";
3240 char format_w2_0[9] = "NULL";
3241 char format_w2_1[9] = "NULL";
3242 char format_w2_2[9] = "NULL";
3243 char format_w2_3[9] = "NULL";
3244 char format_w3_0[9] = "NULL";
3245 char format_w3_1[9] = "NULL";
3246 char format_w3_2[9] = "NULL";
3247 char format_w3_3[9] = "NULL";
3249 u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3250 u32 y_factor, uv_factor;
3251 u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3252 u8 w0_state, w1_state, w2_state, w3_state;
3253 u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3254 u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3256 u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3257 u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3258 u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3259 u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3260 u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3261 u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3263 u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3264 u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3265 u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3266 u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3267 u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3268 u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3269 u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3271 u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3272 u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3273 u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3274 u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3275 u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3276 u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3277 u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3281 dclk_freq = screen->mode.pixclock;
3282 /*rk3368_lcdc_reg_dump(dev_drv); */
3284 spin_lock(&lcdc_dev->reg_lock);
3285 if (lcdc_dev->clk_on) {
3286 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3287 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3288 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3289 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3290 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3292 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3293 w0_state = win_ctrl & m_WIN0_EN;
3294 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3295 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3296 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3297 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3298 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3299 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3300 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3301 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3302 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3303 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3304 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3305 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3306 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3307 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3309 w0_st_x = dsp_st & m_WIN0_DSP_XST;
3310 w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3312 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3313 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3314 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3315 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3318 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3319 w1_state = win_ctrl & m_WIN1_EN;
3320 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3321 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3322 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3323 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3324 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3325 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3326 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3327 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3328 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3329 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3330 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3331 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3332 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3333 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3335 w1_st_x = dsp_st & m_WIN1_DSP_XST;
3336 w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3338 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3339 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3340 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3341 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3343 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3344 w2_state = win_ctrl & m_WIN2_EN;
3345 w2_0_state = (win_ctrl & 0x10) >> 4;
3346 w2_1_state = (win_ctrl & 0x100) >> 8;
3347 w2_2_state = (win_ctrl & 0x1000) >> 12;
3348 w2_3_state = (win_ctrl & 0x10000) >> 16;
3349 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3350 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3351 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3352 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3353 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3354 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3356 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3357 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3358 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3359 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3360 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3361 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3362 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3363 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3365 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3366 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3367 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3368 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3370 w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3371 w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3373 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3374 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3375 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3376 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3378 w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3379 w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3381 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3382 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3383 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3384 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3386 w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3387 w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3389 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3390 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3391 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3392 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3394 w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3395 w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3399 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3400 w3_state = win_ctrl & m_WIN3_EN;
3401 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3402 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3403 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3404 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3405 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3406 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3407 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3408 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3409 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3410 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3411 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3412 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3413 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3414 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3415 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3416 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3417 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3418 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3419 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3420 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3421 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3422 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3424 w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3425 w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3428 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3429 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3430 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3431 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3433 w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3434 w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3437 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3438 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3439 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3440 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3442 w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3443 w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3446 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3447 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3448 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3449 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3451 w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3452 w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3456 spin_unlock(&lcdc_dev->reg_lock);
3459 spin_unlock(&lcdc_dev->reg_lock);
3460 size += snprintf(dsp_buf, 80,
3461 "z-order:\n win[%d]\n win[%d]\n win[%d]\n win[%d]\n",
3462 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3463 strcat(buf, dsp_buf);
3464 memset(dsp_buf, 0, sizeof(dsp_buf));
3466 size += snprintf(dsp_buf, 80,
3467 "win0:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3468 w0_state, format_w0, w0_vir_y, w0_vir_uv);
3469 strcat(buf, dsp_buf);
3470 memset(dsp_buf, 0, sizeof(dsp_buf));
3472 size += snprintf(dsp_buf, 80,
3473 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3474 w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3475 strcat(buf, dsp_buf);
3476 memset(dsp_buf, 0, sizeof(dsp_buf));
3478 size += snprintf(dsp_buf, 80,
3479 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3480 w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3481 strcat(buf, dsp_buf);
3482 memset(dsp_buf, 0, sizeof(dsp_buf));
3484 size += snprintf(dsp_buf, 80,
3485 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3486 w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3487 lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3488 strcat(buf, dsp_buf);
3489 memset(dsp_buf, 0, sizeof(dsp_buf));
3492 size += snprintf(dsp_buf, 80,
3493 "win1:\n state:%d, fmt:%7s\n y_vir:%4d, uv_vir:%4d,",
3494 w1_state, format_w1, w1_vir_y, w1_vir_uv);
3495 strcat(buf, dsp_buf);
3496 memset(dsp_buf, 0, sizeof(dsp_buf));
3498 size += snprintf(dsp_buf, 80,
3499 " x_act :%5d, y_act :%5d, dsp_x :%5d, dsp_y :%5d\n",
3500 w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3501 strcat(buf, dsp_buf);
3502 memset(dsp_buf, 0, sizeof(dsp_buf));
3504 size += snprintf(dsp_buf, 80,
3505 " x_st :%4d, y_st :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3506 w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3507 strcat(buf, dsp_buf);
3508 memset(dsp_buf, 0, sizeof(dsp_buf));
3510 size += snprintf(dsp_buf, 80,
3511 "uv_h_fac:%5d, uv_v_fac:%5d\n y_addr:0x%08x, uv_addr:0x%08x\n",
3512 w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3513 lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3514 strcat(buf, dsp_buf);
3515 memset(dsp_buf, 0, sizeof(dsp_buf));
3518 size += snprintf(dsp_buf, 80,
3519 "win2:\n state:%d\n",
3521 strcat(buf, dsp_buf);
3522 memset(dsp_buf, 0, sizeof(dsp_buf));
3524 size += snprintf(dsp_buf, 80,
3525 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3526 w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3527 strcat(buf, dsp_buf);
3528 memset(dsp_buf, 0, sizeof(dsp_buf));
3529 size += snprintf(dsp_buf, 80,
3530 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3531 w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3532 lcdc_readl(lcdc_dev, WIN2_MST0));
3533 strcat(buf, dsp_buf);
3534 memset(dsp_buf, 0, sizeof(dsp_buf));
3537 size += snprintf(dsp_buf, 80,
3538 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3539 w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3540 strcat(buf, dsp_buf);
3541 memset(dsp_buf, 0, sizeof(dsp_buf));
3542 size += snprintf(dsp_buf, 80,
3543 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3544 w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3545 lcdc_readl(lcdc_dev, WIN2_MST1));
3546 strcat(buf, dsp_buf);
3547 memset(dsp_buf, 0, sizeof(dsp_buf));
3550 size += snprintf(dsp_buf, 80,
3551 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3552 w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3553 strcat(buf, dsp_buf);
3554 memset(dsp_buf, 0, sizeof(dsp_buf));
3555 size += snprintf(dsp_buf, 80,
3556 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3557 w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3558 lcdc_readl(lcdc_dev, WIN2_MST2));
3559 strcat(buf, dsp_buf);
3560 memset(dsp_buf, 0, sizeof(dsp_buf));
3563 size += snprintf(dsp_buf, 80,
3564 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3565 w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3566 strcat(buf, dsp_buf);
3567 memset(dsp_buf, 0, sizeof(dsp_buf));
3568 size += snprintf(dsp_buf, 80,
3569 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3570 w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3571 lcdc_readl(lcdc_dev, WIN2_MST3));
3572 strcat(buf, dsp_buf);
3573 memset(dsp_buf, 0, sizeof(dsp_buf));
3576 size += snprintf(dsp_buf, 80,
3577 "win3:\n state:%d\n",
3579 strcat(buf, dsp_buf);
3580 memset(dsp_buf, 0, sizeof(dsp_buf));
3582 size += snprintf(dsp_buf, 80,
3583 " area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3584 w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3585 strcat(buf, dsp_buf);
3586 memset(dsp_buf, 0, sizeof(dsp_buf));
3587 size += snprintf(dsp_buf, 80,
3588 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3589 w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3590 lcdc_readl(lcdc_dev, WIN3_MST0));
3591 strcat(buf, dsp_buf);
3592 memset(dsp_buf, 0, sizeof(dsp_buf));
3595 size += snprintf(dsp_buf, 80,
3596 " area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3597 w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3598 strcat(buf, dsp_buf);
3599 memset(dsp_buf, 0, sizeof(dsp_buf));
3600 size += snprintf(dsp_buf, 80,
3601 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3602 w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3603 lcdc_readl(lcdc_dev, WIN3_MST1));
3604 strcat(buf, dsp_buf);
3605 memset(dsp_buf, 0, sizeof(dsp_buf));
3608 size += snprintf(dsp_buf, 80,
3609 " area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3610 w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3611 strcat(buf, dsp_buf);
3612 memset(dsp_buf, 0, sizeof(dsp_buf));
3613 size += snprintf(dsp_buf, 80,
3614 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3615 w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3616 lcdc_readl(lcdc_dev, WIN3_MST2));
3617 strcat(buf, dsp_buf);
3618 memset(dsp_buf, 0, sizeof(dsp_buf));
3621 size += snprintf(dsp_buf, 80,
3622 " area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3623 w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3624 strcat(buf, dsp_buf);
3625 memset(dsp_buf, 0, sizeof(dsp_buf));
3626 size += snprintf(dsp_buf, 80,
3627 " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3628 w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3629 lcdc_readl(lcdc_dev, WIN3_MST3));
3630 strcat(buf, dsp_buf);
3631 memset(dsp_buf, 0, sizeof(dsp_buf));
3636 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3639 struct lcdc_device *lcdc_dev =
3640 container_of(dev_drv, struct lcdc_device, driver);
3641 struct rk_screen *screen = dev_drv->cur_screen;
3646 u32 x_total, y_total;
3650 dev_info(dev_drv->dev, "unsupport set fps=0\n");
3653 ft = div_u64(1000000000000llu, fps);
3655 screen->mode.upper_margin + screen->mode.lower_margin +
3656 screen->mode.yres + screen->mode.vsync_len;
3658 screen->mode.left_margin + screen->mode.right_margin +
3659 screen->mode.xres + screen->mode.hsync_len;
3660 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3661 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3662 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3665 pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3666 lcdc_dev->pixclock = pixclock;
3667 dev_drv->pixclock = lcdc_dev->pixclock;
3668 fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3669 screen->ft = 1000 / fps; /*one frame time in ms */
3672 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3673 clk_get_rate(lcdc_dev->dclk), fps);
3678 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3680 mutex_lock(&dev_drv->fb_win_id_mutex);
3681 if (order == FB_DEFAULT_ORDER)
3682 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3683 dev_drv->fb4_win_id = order / 10000;
3684 dev_drv->fb3_win_id = (order / 1000) % 10;
3685 dev_drv->fb2_win_id = (order / 100) % 10;
3686 dev_drv->fb1_win_id = (order / 10) % 10;
3687 dev_drv->fb0_win_id = order % 10;
3688 mutex_unlock(&dev_drv->fb_win_id_mutex);
3693 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3698 mutex_lock(&dev_drv->fb_win_id_mutex);
3699 if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3700 win_id = dev_drv->fb0_win_id;
3701 else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3702 win_id = dev_drv->fb1_win_id;
3703 else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3704 win_id = dev_drv->fb2_win_id;
3705 else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3706 win_id = dev_drv->fb3_win_id;
3707 else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3708 win_id = dev_drv->fb4_win_id;
3709 mutex_unlock(&dev_drv->fb_win_id_mutex);
3714 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3716 struct lcdc_device *lcdc_dev =
3717 container_of(dev_drv, struct lcdc_device, driver);
3719 unsigned int mask, val;
3720 struct rk_lcdc_win *win = NULL;
3722 spin_lock(&lcdc_dev->reg_lock);
3723 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3724 v_STANDBY_EN(lcdc_dev->standby));
3725 for (i = 0; i < 4; i++) {
3726 win = dev_drv->win[i];
3727 if ((win->state == 0) && (win->last_state == 1)) {
3730 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3731 for rk3288 to fix hw bug? */
3734 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3737 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3738 for rk3288 to fix hw bug? */
3741 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3744 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3746 m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3747 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3749 v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3750 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3753 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3755 m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3756 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3758 v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3759 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3764 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3770 win->last_state = win->state;
3772 lcdc_cfg_done(lcdc_dev);
3773 spin_unlock(&lcdc_dev->reg_lock);
3777 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3779 struct lcdc_device *lcdc_dev =
3780 container_of(dev_drv, struct lcdc_device, driver);
3781 spin_lock(&lcdc_dev->reg_lock);
3782 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3783 v_DIRECT_PATH_EN(open));
3784 lcdc_cfg_done(lcdc_dev);
3785 spin_unlock(&lcdc_dev->reg_lock);
3789 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3791 struct lcdc_device *lcdc_dev = container_of(dev_drv,
3792 struct lcdc_device, driver);
3793 spin_lock(&lcdc_dev->reg_lock);
3794 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3795 v_DIRECT_PATCH_SEL(win_id));
3796 lcdc_cfg_done(lcdc_dev);
3797 spin_unlock(&lcdc_dev->reg_lock);
3801 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3803 struct lcdc_device *lcdc_dev =
3804 container_of(dev_drv, struct lcdc_device, driver);
3807 spin_lock(&lcdc_dev->reg_lock);
3808 ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3809 spin_unlock(&lcdc_dev->reg_lock);
3813 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3816 struct lcdc_device *lcdc_dev =
3817 container_of(dev_drv, struct lcdc_device, driver);
3819 enable_irq(lcdc_dev->irq);
3821 disable_irq(lcdc_dev->irq);
3825 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3827 struct lcdc_device *lcdc_dev =
3828 container_of(dev_drv, struct lcdc_device, driver);
3832 if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3833 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3834 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3835 lcdc_dev->driver.frame_time.last_framedone_t =
3836 lcdc_dev->driver.frame_time.framedone_t;
3837 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3838 lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3839 m_LINE_FLAG0_INTR_CLR,
3840 v_LINE_FLAG0_INTR_CLR(1));
3841 ret = RK_LF_STATUS_FC;
3843 ret = RK_LF_STATUS_FR;
3846 ret = RK_LF_STATUS_NC;
3852 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3853 unsigned int *dsp_addr)
3855 struct lcdc_device *lcdc_dev =
3856 container_of(dev_drv, struct lcdc_device, driver);
3857 spin_lock(&lcdc_dev->reg_lock);
3858 if (lcdc_dev->clk_on) {
3859 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3860 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3861 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3862 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3864 spin_unlock(&lcdc_dev->reg_lock);
3868 static struct lcdc_cabc_mode cabc_mode[4] = {
3869 /* calc, up, down, global_limit */
3870 {5, 256, 256, 256}, /*mode 1 0*/
3871 {5, 258, 253, 277}, /*mode 2 15%*/
3872 {5, 259, 252, 330}, /*mode 3 40%*/
3873 {5, 267, 244, 400}, /*mode 4 60%*/
3876 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3878 struct lcdc_device *lcdc_dev =
3879 container_of(dev_drv, struct lcdc_device, driver);
3880 struct rk_screen *screen = dev_drv->cur_screen;
3881 u32 total_pixel, calc_pixel, stage_up, stage_down;
3882 u32 pixel_num, global_su;
3883 u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
3884 u32 mask = 0, val = 0, cabc_en = 0;
3885 int *cabc_lut = NULL;
3887 if (!screen->cabc_lut) {
3888 pr_err("screen cabc lut not config, so not open cabc\n");
3891 cabc_lut = screen->cabc_lut;
3894 dev_drv->cabc_mode = mode;
3895 cabc_en = (mode > 0) ? 1 : 0;
3898 spin_lock(&lcdc_dev->reg_lock);
3899 if (lcdc_dev->clk_on) {
3900 lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3901 m_CABC_EN, v_CABC_EN(0));
3902 lcdc_cfg_done(lcdc_dev);
3904 spin_unlock(&lcdc_dev->reg_lock);
3908 total_pixel = screen->mode.xres * screen->mode.yres;
3909 pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3910 calc_pixel = (total_pixel * pixel_num) / 1000;
3911 stage_up = cabc_mode[mode - 1].stage_up;
3912 stage_down = cabc_mode[mode - 1].stage_down;
3913 global_su = cabc_mode[mode - 1].global_su;
3915 stage_up_rec = 256 * 256 / stage_up;
3916 stage_down_rec = 256 * 256 / stage_down;
3917 global_su_rec = (256 * 256 / global_su) - 1;
3918 gamma_global_su_rec = cabc_lut[global_su_rec];
3920 spin_lock(&lcdc_dev->reg_lock);
3921 if (lcdc_dev->clk_on) {
3922 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3923 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3925 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3927 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3928 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
3929 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3931 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3932 m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3933 val = v_CABC_STAGE_UP(stage_up) |
3934 v_CABC_STAGE_UP_REC(stage_up_rec) |
3935 v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3936 v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
3937 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3939 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3941 val = v_CABC_STAGE_DOWN(stage_down) |
3942 v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3943 v_CABC_GLOBAL_SU(global_su);
3944 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3945 lcdc_cfg_done(lcdc_dev);
3947 spin_unlock(&lcdc_dev->reg_lock);
3954 sin_hue = sin(a)*256 +0x100;
3955 cos_hue = cos(a)*256;
3957 sin_hue = sin(a)*256;
3958 cos_hue = cos(a)*256;
3960 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3963 struct lcdc_device *lcdc_dev =
3964 container_of(dev_drv, struct lcdc_device, driver);
3967 spin_lock(&lcdc_dev->reg_lock);
3968 if (lcdc_dev->clk_on) {
3969 val = lcdc_readl(lcdc_dev, BCSH_H);
3972 val &= m_BCSH_SIN_HUE;
3975 val &= m_BCSH_COS_HUE;
3982 spin_unlock(&lcdc_dev->reg_lock);
3987 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3988 int sin_hue, int cos_hue)
3990 struct lcdc_device *lcdc_dev =
3991 container_of(dev_drv, struct lcdc_device, driver);
3994 spin_lock(&lcdc_dev->reg_lock);
3995 if (lcdc_dev->clk_on) {
3996 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3997 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3998 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3999 lcdc_cfg_done(lcdc_dev);
4001 spin_unlock(&lcdc_dev->reg_lock);
4006 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4007 bcsh_bcs_mode mode, int value)
4009 struct lcdc_device *lcdc_dev =
4010 container_of(dev_drv, struct lcdc_device, driver);
4013 spin_lock(&lcdc_dev->reg_lock);
4014 if (lcdc_dev->clk_on) {
4017 /*from 0 to 255,typical is 128 */
4020 else if (value >= 0x80)
4021 value = value - 0x80;
4022 mask = m_BCSH_BRIGHTNESS;
4023 val = v_BCSH_BRIGHTNESS(value);
4026 /*from 0 to 510,typical is 256 */
4027 mask = m_BCSH_CONTRAST;
4028 val = v_BCSH_CONTRAST(value);
4031 /*from 0 to 1015,typical is 256 */
4032 mask = m_BCSH_SAT_CON;
4033 val = v_BCSH_SAT_CON(value);
4038 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4039 lcdc_cfg_done(lcdc_dev);
4041 spin_unlock(&lcdc_dev->reg_lock);
4045 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4048 struct lcdc_device *lcdc_dev =
4049 container_of(dev_drv, struct lcdc_device, driver);
4052 spin_lock(&lcdc_dev->reg_lock);
4053 if (lcdc_dev->clk_on) {
4054 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4057 val &= m_BCSH_BRIGHTNESS;
4064 val &= m_BCSH_CONTRAST;
4068 val &= m_BCSH_SAT_CON;
4075 spin_unlock(&lcdc_dev->reg_lock);
4079 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4081 struct lcdc_device *lcdc_dev =
4082 container_of(dev_drv, struct lcdc_device, driver);
4085 spin_lock(&lcdc_dev->reg_lock);
4086 if (lcdc_dev->clk_on) {
4088 lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4089 lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4090 lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4091 dev_drv->bcsh.enable = 1;
4095 lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4096 dev_drv->bcsh.enable = 0;
4098 rk3368_lcdc_bcsh_path_sel(dev_drv);
4099 lcdc_cfg_done(lcdc_dev);
4101 spin_unlock(&lcdc_dev->reg_lock);
4105 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4107 if (!enable || !dev_drv->bcsh.enable) {
4108 rk3368_lcdc_open_bcsh(dev_drv, false);
4112 if (dev_drv->bcsh.brightness <= 255 ||
4113 dev_drv->bcsh.contrast <= 510 ||
4114 dev_drv->bcsh.sat_con <= 1015 ||
4115 (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4116 rk3368_lcdc_open_bcsh(dev_drv, true);
4117 if (dev_drv->bcsh.brightness <= 255)
4118 rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4119 dev_drv->bcsh.brightness);
4120 if (dev_drv->bcsh.contrast <= 510)
4121 rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4122 dev_drv->bcsh.contrast);
4123 if (dev_drv->bcsh.sat_con <= 1015)
4124 rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4125 dev_drv->bcsh.sat_con);
4126 if (dev_drv->bcsh.sin_hue <= 511 &&
4127 dev_drv->bcsh.cos_hue <= 511)
4128 rk3368_lcdc_set_bcsh_hue(dev_drv,
4129 dev_drv->bcsh.sin_hue,
4130 dev_drv->bcsh.cos_hue);
4135 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4137 struct lcdc_device *lcdc_dev =
4138 container_of(dev_drv, struct lcdc_device, driver);
4141 spin_lock(&lcdc_dev->reg_lock);
4142 if (likely(lcdc_dev->clk_on)) {
4143 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4145 lcdc_cfg_done(lcdc_dev);
4147 spin_unlock(&lcdc_dev->reg_lock);
4149 spin_lock(&lcdc_dev->reg_lock);
4150 if (likely(lcdc_dev->clk_on)) {
4151 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4154 lcdc_cfg_done(lcdc_dev);
4156 spin_unlock(&lcdc_dev->reg_lock);
4163 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4166 struct lcdc_device *lcdc_dev =
4167 container_of(dev_drv, struct lcdc_device, driver);
4169 rk3368_lcdc_get_backlight_device(dev_drv);
4172 /* close the backlight */
4173 if (lcdc_dev->backlight) {
4174 lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4175 backlight_update_status(lcdc_dev->backlight);
4177 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4178 dev_drv->trsm_ops->disable();
4180 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4181 dev_drv->trsm_ops->enable();
4183 /* open the backlight */
4184 if (lcdc_dev->backlight) {
4185 lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4186 backlight_update_status(lcdc_dev->backlight);
4193 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4194 .open = rk3368_lcdc_open,
4195 .win_direct_en = rk3368_lcdc_win_direct_en,
4196 .load_screen = rk3368_load_screen,
4197 .get_dspbuf_info = rk3368_get_dspbuf_info,
4198 .post_dspbuf = rk3368_post_dspbuf,
4199 .set_par = rk3368_lcdc_set_par,
4200 .pan_display = rk3368_lcdc_pan_display,
4201 .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4202 /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4203 .blank = rk3368_lcdc_blank,
4204 .ioctl = rk3368_lcdc_ioctl,
4205 .suspend = rk3368_lcdc_early_suspend,
4206 .resume = rk3368_lcdc_early_resume,
4207 .get_win_state = rk3368_lcdc_get_win_state,
4208 .ovl_mgr = rk3368_lcdc_ovl_mgr,
4209 .get_disp_info = rk3368_lcdc_get_disp_info,
4210 .fps_mgr = rk3368_lcdc_fps_mgr,
4211 .fb_get_win_id = rk3368_lcdc_get_win_id,
4212 .fb_win_remap = rk3368_fb_win_remap,
4213 .set_dsp_lut = rk3368_lcdc_set_lut,
4214 .set_cabc_lut = rk3368_set_cabc_lut,
4215 .poll_vblank = rk3368_lcdc_poll_vblank,
4216 .dpi_open = rk3368_lcdc_dpi_open,
4217 .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4218 .dpi_status = rk3368_lcdc_dpi_status,
4219 .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4220 .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4221 .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4222 .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4223 .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4224 .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4225 .open_bcsh = rk3368_lcdc_open_bcsh,
4226 .dump_reg = rk3368_lcdc_reg_dump,
4227 .cfg_done = rk3368_lcdc_config_done,
4228 .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4229 .dsp_black = rk3368_lcdc_dsp_black,
4230 .backlight_close = rk3368_lcdc_backlight_close,
4231 .mmu_en = rk3368_lcdc_mmu_en,
4234 #ifdef LCDC_IRQ_EMPTY_DEBUG
4235 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4236 unsigned int intr_status)
4238 if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4239 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4240 v_WIN0_EMPTY_INTR_CLR(1));
4241 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4242 } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4243 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4244 v_WIN1_EMPTY_INTR_CLR(1));
4245 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4246 } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4247 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4248 v_WIN2_EMPTY_INTR_CLR(1));
4249 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4250 } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4251 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4252 v_WIN3_EMPTY_INTR_CLR(1));
4253 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4254 } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4255 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4256 v_HWC_EMPTY_INTR_CLR(1));
4257 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4258 } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4259 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4260 v_POST_BUF_EMPTY_INTR_CLR(1));
4261 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4262 } else if (intr_status & m_PWM_GEN_INTR_STS) {
4263 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4264 v_PWM_GEN_INTR_CLR(1));
4265 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4271 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4273 struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4274 ktime_t timestamp = ktime_get();
4277 intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4279 if (intr_status & m_FS_INTR_STS) {
4280 timestamp = ktime_get();
4281 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4283 /*if(lcdc_dev->driver.wait_fs){ */
4285 spin_lock(&(lcdc_dev->driver.cpl_lock));
4286 complete(&(lcdc_dev->driver.frame_done));
4287 spin_unlock(&(lcdc_dev->driver.cpl_lock));
4289 #ifdef CONFIG_DRM_ROCKCHIP
4290 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4292 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4293 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4295 } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4296 lcdc_dev->driver.frame_time.last_framedone_t =
4297 lcdc_dev->driver.frame_time.framedone_t;
4298 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4299 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4300 v_LINE_FLAG0_INTR_CLR(1));
4301 } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4303 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4304 v_LINE_FLAG1_INTR_CLR(1));
4305 } else if (intr_status & m_FS_NEW_INTR_STS) {
4306 /*new frame start */
4307 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4308 v_FS_NEW_INTR_CLR(1));
4309 } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4310 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4311 v_BUS_ERROR_INTR_CLR(1));
4312 dev_warn(lcdc_dev->dev, "bus error!");
4315 /* for win empty debug */
4316 #ifdef LCDC_IRQ_EMPTY_DEBUG
4317 rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4322 #if defined(CONFIG_PM)
4323 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4328 static int rk3368_lcdc_resume(struct platform_device *pdev)
4333 #define rk3368_lcdc_suspend NULL
4334 #define rk3368_lcdc_resume NULL
4337 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4339 struct device_node *np = lcdc_dev->dev->of_node;
4340 struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4343 if (of_property_read_u32(np, "rockchip,prop", &val))
4344 lcdc_dev->prop = PRMRY; /*default set it as primary */
4346 lcdc_dev->prop = val;
4348 if (of_property_read_u32(np, "rockchip,mirror", &val))
4349 dev_drv->rotate_mode = NO_MIRROR;
4351 dev_drv->rotate_mode = val;
4353 if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4354 dev_drv->cabc_mode = 0; /* default set close cabc */
4356 dev_drv->cabc_mode = val;
4358 if (of_property_read_u32(np, "rockchip,pwr18", &val))
4359 /*default set it as 3.xv power supply */
4360 lcdc_dev->pwr18 = false;
4362 lcdc_dev->pwr18 = (val ? true : false);
4364 if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4365 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4367 dev_drv->fb_win_map = val;
4369 if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4370 dev_drv->bcsh.enable = false;
4372 dev_drv->bcsh.enable = (val ? true : false);
4374 if (of_property_read_u32(np, "rockchip,brightness", &val))
4375 dev_drv->bcsh.brightness = 0xffff;
4377 dev_drv->bcsh.brightness = val;
4379 if (of_property_read_u32(np, "rockchip,contrast", &val))
4380 dev_drv->bcsh.contrast = 0xffff;
4382 dev_drv->bcsh.contrast = val;
4384 if (of_property_read_u32(np, "rockchip,sat-con", &val))
4385 dev_drv->bcsh.sat_con = 0xffff;
4387 dev_drv->bcsh.sat_con = val;
4389 if (of_property_read_u32(np, "rockchip,hue", &val)) {
4390 dev_drv->bcsh.sin_hue = 0xffff;
4391 dev_drv->bcsh.cos_hue = 0xffff;
4393 dev_drv->bcsh.sin_hue = val & 0xff;
4394 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4397 #if defined(CONFIG_ROCKCHIP_IOMMU)
4398 if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4399 dev_drv->iommu_enabled = 0;
4401 dev_drv->iommu_enabled = val;
4403 dev_drv->iommu_enabled = 0;
4408 static int rk3368_lcdc_probe(struct platform_device *pdev)
4410 struct lcdc_device *lcdc_dev = NULL;
4411 struct rk_lcdc_driver *dev_drv;
4412 struct device *dev = &pdev->dev;
4413 struct resource *res;
4414 struct device_node *np = pdev->dev.of_node;
4418 /*if the primary lcdc has not registered ,the extend
4419 lcdc register later */
4420 of_property_read_u32(np, "rockchip,prop", &prop);
4421 if (prop == EXTEND) {
4422 if (!is_prmry_rk_lcdc_registered())
4423 return -EPROBE_DEFER;
4425 lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4427 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4430 platform_set_drvdata(pdev, lcdc_dev);
4431 lcdc_dev->dev = dev;
4432 rk3368_lcdc_parse_dt(lcdc_dev);
4433 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4434 lcdc_dev->reg_phy_base = res->start;
4435 lcdc_dev->len = resource_size(res);
4436 lcdc_dev->regs = devm_ioremap_resource(dev, res);
4437 if (IS_ERR(lcdc_dev->regs))
4438 return PTR_ERR(lcdc_dev->regs);
4440 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4442 lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4443 if (IS_ERR(lcdc_dev->regsbak))
4444 return PTR_ERR(lcdc_dev->regsbak);
4445 lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4446 lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4447 lcdc_dev->grf_base =
4448 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4449 if (IS_ERR(lcdc_dev->grf_base)) {
4450 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4451 return PTR_ERR(lcdc_dev->grf_base);
4453 lcdc_dev->pmugrf_base =
4454 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4455 if (IS_ERR(lcdc_dev->pmugrf_base)) {
4456 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4457 return PTR_ERR(lcdc_dev->pmugrf_base);
4460 dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4461 dev_drv = &lcdc_dev->driver;
4463 dev_drv->prop = prop;
4464 dev_drv->id = lcdc_dev->id;
4465 dev_drv->ops = &lcdc_drv_ops;
4466 dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4467 spin_lock_init(&lcdc_dev->reg_lock);
4469 lcdc_dev->irq = platform_get_irq(pdev, 0);
4470 if (lcdc_dev->irq < 0) {
4471 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4476 ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4477 IRQF_DISABLED | IRQF_SHARED,
4478 dev_name(dev), lcdc_dev);
4480 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4481 lcdc_dev->irq, ret);
4485 if (dev_drv->iommu_enabled) {
4486 if (lcdc_dev->id == 0) {
4487 strcpy(dev_drv->mmu_dts_name,
4488 VOPB_IOMMU_COMPATIBLE_NAME);
4490 strcpy(dev_drv->mmu_dts_name,
4491 VOPL_IOMMU_COMPATIBLE_NAME);
4495 ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4497 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4500 lcdc_dev->screen = dev_drv->screen0;
4501 dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4502 lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4507 static int rk3368_lcdc_remove(struct platform_device *pdev)
4512 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4514 struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4516 rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4517 rk3368_lcdc_deint(lcdc_dev);
4520 #if defined(CONFIG_OF)
4521 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4522 {.compatible = "rockchip,rk3368-lcdc",},
4527 static struct platform_driver rk3368_lcdc_driver = {
4528 .probe = rk3368_lcdc_probe,
4529 .remove = rk3368_lcdc_remove,
4531 .name = "rk3368-lcdc",
4532 .owner = THIS_MODULE,
4533 .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4535 .suspend = rk3368_lcdc_suspend,
4536 .resume = rk3368_lcdc_resume,
4537 .shutdown = rk3368_lcdc_shutdown,
4540 static int __init rk3368_lcdc_module_init(void)
4542 return platform_driver_register(&rk3368_lcdc_driver);
4545 static void __exit rk3368_lcdc_module_exit(void)
4547 platform_driver_unregister(&rk3368_lcdc_driver);
4550 fs_initcall(rk3368_lcdc_module_init);
4551 module_exit(rk3368_lcdc_module_exit);