drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 /*clk_prepare_enable(lcdc_dev->pd);*/
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 420
 421         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 447
 448         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 449         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 450         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 451         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 452         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 453         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 454
 455         mask = m_AUTO_GATING_EN;
 456         val = v_AUTO_GATING_EN(0);
 457         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 458         lcdc_cfg_done(lcdc_dev);
 459         /*disable win0 to workaround iommu pagefault */
 460         /*if (dev_drv->iommu_enabled) */
 461         /*      win0_enable(lcdc_dev, 0); */
 462         lcdc_dev->pre_init = true;
 463
 464         return 0;
 465 }
 466
 467 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 468 {
 469 }
 470
 471 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 472 {
 473         struct lcdc_device *lcdc_dev =
 474             container_of(dev_drv, struct lcdc_device, driver);
 475         struct rk_screen *screen = dev_drv->cur_screen;
 476         u16 x_res = screen->mode.xres;
 477         u16 y_res = screen->mode.yres;
 478         u32 mask, val;
 479         u16 h_total, v_total;
 480         u16 post_hsd_en, post_vsd_en;
 481         u16 post_dsp_hact_st, post_dsp_hact_end;
 482         u16 post_dsp_vact_st, post_dsp_vact_end;
 483         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 484         u16 post_h_fac, post_v_fac;
 485
 486         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 487             x_res + screen->mode.right_margin;
 488         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 489             y_res + screen->mode.lower_margin;
 490
 491         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 492                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 493                          screen->post_dsp_stx, screen->post_xsize, x_res);
 494                 screen->post_dsp_stx = x_res - screen->post_xsize;
 495         }
 496         if (screen->x_mirror == 0) {
 497                 post_dsp_hact_st = screen->post_dsp_stx +
 498                     screen->mode.hsync_len + screen->mode.left_margin;
 499                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 500         } else {
 501                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 502                     screen->post_dsp_stx;
 503                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 504         }
 505         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 506                 post_hsd_en = 1;
 507                 post_h_fac =
 508                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 509         } else {
 510                 post_hsd_en = 0;
 511                 post_h_fac = 0x1000;
 512         }
 513
 514         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 515                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 516                          screen->post_dsp_sty, screen->post_ysize, y_res);
 517                 screen->post_dsp_sty = y_res - screen->post_ysize;
 518         }
 519
 520         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 521                 post_vsd_en = 1;
 522                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 523                                                       screen->post_ysize);
 524         } else {
 525                 post_vsd_en = 0;
 526                 post_v_fac = 0x1000;
 527         }
 528
 529         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 530                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 531                                         screen->mode.vsync_len +
 532                                         screen->mode.upper_margin;
 533                 post_dsp_vact_end = post_dsp_vact_st +
 534                                         screen->post_ysize / 2;
 535
 536                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 537                                       screen->mode.upper_margin +
 538                                       y_res/2 +
 539                                       screen->mode.lower_margin +
 540                                       screen->mode.vsync_len +
 541                                       screen->mode.upper_margin +
 542                                       screen->post_dsp_sty / 2 +
 543                                       1;
 544                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 545                                         screen->post_ysize/2;
 546         } else {
 547                 if (screen->y_mirror == 0) {
 548                         post_dsp_vact_st = screen->post_dsp_sty +
 549                             screen->mode.vsync_len +
 550                             screen->mode.upper_margin;
 551                         post_dsp_vact_end = post_dsp_vact_st +
 552                                 screen->post_ysize;
 553                 } else {
 554                         post_dsp_vact_end = v_total -
 555                                 screen->mode.lower_margin -
 556                             screen->post_dsp_sty;
 557                         post_dsp_vact_st = post_dsp_vact_end -
 558                                 screen->post_ysize;
 559                 }
 560                 post_dsp_vact_st_f1 = 0;
 561                 post_dsp_vact_end_f1 = 0;
 562         }
 563         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 564             screen->post_xsize, screen->post_ysize, screen->xpos);
 565         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 566             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 567         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 568         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 569             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 570         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 571
 572         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 573         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 574             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 575         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 576
 577         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 578         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 579             v_POST_VS_FACTOR_YRGB(post_v_fac);
 580         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 581
 582         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 583         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 584             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 585         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 586
 587         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 588         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 589         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 590         return 0;
 591 }
 592
 593 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 594 {
 595         struct lcdc_device *lcdc_dev =
 596             container_of(dev_drv, struct lcdc_device, driver);
 597         struct rk_lcdc_win *win;
 598         u32 colorkey_r, colorkey_g, colorkey_b;
 599         int i, key_val;
 600
 601         for (i = 0; i < 4; i++) {
 602                 win = dev_drv->win[i];
 603                 key_val = win->color_key_val;
 604                 colorkey_r = (key_val & 0xff) << 2;
 605                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 606                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 607                 /*color key dither 565/888->aaa */
 608                 key_val = colorkey_r | colorkey_g | colorkey_b;
 609                 switch (i) {
 610                 case 0:
 611                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 612                         break;
 613                 case 1:
 614                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 615                         break;
 616                 case 2:
 617                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 618                         break;
 619                 case 3:
 620                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 621                         break;
 622                 default:
 623                         pr_info("%s:un support win num:%d\n",
 624                                 __func__, i);
 625                         break;
 626                 }
 627         }
 628         return 0;
 629 }
 630
 631 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 632 {
 633         struct lcdc_device *lcdc_dev =
 634             container_of(dev_drv, struct lcdc_device, driver);
 635         struct rk_lcdc_win *win = dev_drv->win[win_id];
 636         struct alpha_config alpha_config;
 637         u32 mask, val;
 638         int ppixel_alpha = 0, global_alpha = 0, i;
 639         u32 src_alpha_ctl, dst_alpha_ctl;
 640
 641         for (i = 0; i < win->area_num; i++) {
 642                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 643                                  (win->area[i].format == FBDC_ARGB_888) ||
 644                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 645         }
 646         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 647         alpha_config.src_global_alpha_val = win->g_alpha_val;
 648         win->alpha_mode = AB_SRC_OVER;
 649         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 650            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 651            global_alpha); */
 652         switch (win->alpha_mode) {
 653         case AB_USER_DEFINE:
 654                 break;
 655         case AB_CLEAR:
 656                 alpha_config.src_factor_mode = AA_ZERO;
 657                 alpha_config.dst_factor_mode = AA_ZERO;
 658                 break;
 659         case AB_SRC:
 660                 alpha_config.src_factor_mode = AA_ONE;
 661                 alpha_config.dst_factor_mode = AA_ZERO;
 662                 break;
 663         case AB_DST:
 664                 alpha_config.src_factor_mode = AA_ZERO;
 665                 alpha_config.dst_factor_mode = AA_ONE;
 666                 break;
 667         case AB_SRC_OVER:
 668                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 669                 if (global_alpha)
 670                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 671                 else
 672                         alpha_config.src_factor_mode = AA_ONE;
 673                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 674                 break;
 675         case AB_DST_OVER:
 676                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 677                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 678                 alpha_config.dst_factor_mode = AA_ONE;
 679                 break;
 680         case AB_SRC_IN:
 681                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 682                 alpha_config.src_factor_mode = AA_SRC;
 683                 alpha_config.dst_factor_mode = AA_ZERO;
 684                 break;
 685         case AB_DST_IN:
 686                 alpha_config.src_factor_mode = AA_ZERO;
 687                 alpha_config.dst_factor_mode = AA_SRC;
 688                 break;
 689         case AB_SRC_OUT:
 690                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 691                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 692                 alpha_config.dst_factor_mode = AA_ZERO;
 693                 break;
 694         case AB_DST_OUT:
 695                 alpha_config.src_factor_mode = AA_ZERO;
 696                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 697                 break;
 698         case AB_SRC_ATOP:
 699                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 700                 alpha_config.src_factor_mode = AA_SRC;
 701                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 702                 break;
 703         case AB_DST_ATOP:
 704                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 705                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 706                 alpha_config.dst_factor_mode = AA_SRC;
 707                 break;
 708         case XOR:
 709                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 710                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 711                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 712                 break;
 713         case AB_SRC_OVER_GLOBAL:
 714                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 715                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 716                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 717                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 718                 break;
 719         default:
 720                 pr_err("alpha mode error\n");
 721                 break;
 722         }
 723         if ((ppixel_alpha == 1) && (global_alpha == 1))
 724                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 725         else if (ppixel_alpha == 1)
 726                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 727         else if (global_alpha == 1)
 728                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 729         else
 730                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 731         alpha_config.src_alpha_mode = AA_STRAIGHT;
 732         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 733
 734         switch (win_id) {
 735         case 0:
 736                 src_alpha_ctl = 0x60;
 737                 dst_alpha_ctl = 0x64;
 738                 break;
 739         case 1:
 740                 src_alpha_ctl = 0xa0;
 741                 dst_alpha_ctl = 0xa4;
 742                 break;
 743         case 2:
 744                 src_alpha_ctl = 0xdc;
 745                 dst_alpha_ctl = 0xec;
 746                 break;
 747         case 3:
 748                 src_alpha_ctl = 0x12c;
 749                 dst_alpha_ctl = 0x13c;
 750                 break;
 751         case 4:
 752                 src_alpha_ctl = 0x160;
 753                 dst_alpha_ctl = 0x164;
 754                 break;
 755         }
 756         mask = m_WIN0_DST_FACTOR_M0;
 757         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 758         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 759         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 760             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 761             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 762             m_WIN0_SRC_GLOBAL_ALPHA;
 763         val = v_WIN0_SRC_ALPHA_EN(1) |
 764             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 765             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 766             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 767             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 768             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 769             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 770         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 771
 772         return 0;
 773 }
 774
 775 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 776 {
 777         struct rk_lcdc_win_area area_temp;
 778         int i, j;
 779
 780         for (i = 0; i < area_num; i++) {
 781                 for (j = i + 1; j < area_num; j++) {
 782                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 783                                 memcpy(&area_temp, &win->area[i],
 784                                        sizeof(struct rk_lcdc_win_area));
 785                                 memcpy(&win->area[i], &win->area[j],
 786                                        sizeof(struct rk_lcdc_win_area));
 787                                 memcpy(&win->area[j], &area_temp,
 788                                        sizeof(struct rk_lcdc_win_area));
 789                         }
 790                 }
 791         }
 792
 793         return 0;
 794 }
 795
 796 static int __maybe_unused
 797         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 798 {
 799         struct rk_lcdc_win_area area_temp;
 800
 801         switch (area_num) {
 802         case 2:
 803                 area_temp = win->area[0];
 804                 win->area[0] = win->area[1];
 805                 win->area[1] = area_temp;
 806                 break;
 807         case 3:
 808                 area_temp = win->area[0];
 809                 win->area[0] = win->area[2];
 810                 win->area[2] = area_temp;
 811                 break;
 812         case 4:
 813                 area_temp = win->area[0];
 814                 win->area[0] = win->area[3];
 815                 win->area[3] = area_temp;
 816
 817                 area_temp = win->area[1];
 818                 win->area[1] = win->area[2];
 819                 win->area[2] = area_temp;
 820                 break;
 821         default:
 822                 pr_info("un supported area num!\n");
 823                 break;
 824         }
 825         return 0;
 826 }
 827
 828 static int __maybe_unused
 829 rk3368_win_area_check_var(int win_id, int area_num,
 830                           struct rk_lcdc_win_area *area_pre,
 831                           struct rk_lcdc_win_area *area_now)
 832 {
 833         if ((area_pre->xpos > area_now->xpos) ||
 834             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 835              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 836                 area_now->state = 0;
 837                 pr_err("win[%d]:\n"
 838                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 839                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 840                        win_id,
 841                        area_num - 1, area_pre->xpos, area_pre->xsize,
 842                        area_pre->ypos, area_pre->ysize,
 843                        area_num, area_now->xpos, area_now->xsize,
 844                        area_now->ypos, area_now->ysize);
 845                 return -EINVAL;
 846         }
 847         return 0;
 848 }
 849
 850 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 851 {
 852         struct lcdc_device *lcdc_dev =
 853             container_of(dev_drv, struct lcdc_device, driver);
 854         u32 val, i;
 855
 856         for (i = 0; i < 100; i++) {
 857                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 858                 val &= m_DBG_IFBDC_IDLE;
 859                 if (val)
 860                         continue;
 861                 else
 862                         mdelay(10);
 863         };
 864         return val;
 865 }
 866
 867 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 868 {
 869         struct lcdc_device *lcdc_dev =
 870             container_of(dev_drv, struct lcdc_device, driver);
 871         struct rk_lcdc_win *win = dev_drv->win[win_id];
 872         u32 mask, val;
 873
 874         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 875             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 876             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 877         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 878             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 879             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 880             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 881             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 882             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 883         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 884
 885         mask = m_IFBDC_TILES_NUM;
 886         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 887         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 888
 889         mask = m_IFBDC_BASE_ADDR;
 890         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 891         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 892
 893         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 894         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 895             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 896         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 897
 898         mask = m_IFBDC_CMP_INDEX_INIT;
 899         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 900         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 901
 902         mask = m_IFBDC_MB_VIR_WIDTH;
 903         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 904         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 905
 906         return 0;
 907 }
 908
 909 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 910 {
 911         struct lcdc_device *lcdc_dev =
 912             container_of(dev_drv, struct lcdc_device, driver);
 913         struct rk_lcdc_win *win = dev_drv->win[win_id];
 914         u8 fbdc_dsp_width_ratio;
 915         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 916         u16 fbdc_mb_width, fbdc_mb_height;
 917         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 918         u16 fbdc_cmp_index_init;
 919         u8 mb_w_size, mb_h_size;
 920         struct rk_screen *screen = dev_drv->cur_screen;
 921
 922         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 923                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 924                 return 0;
 925         }
 926
 927         switch (win->area[0].fmt_cfg) {
 928         case VOP_FORMAT_ARGB888:
 929                 fbdc_dsp_width_ratio = 0;
 930                 mb_w_size = 16;
 931                 break;
 932         case VOP_FORMAT_RGB888:
 933                 fbdc_dsp_width_ratio = 0;
 934                 mb_w_size = 16;
 935                 break;
 936         case VOP_FORMAT_RGB565:
 937                 fbdc_dsp_width_ratio = 1;
 938                 mb_w_size = 32;
 939                 break;
 940         default:
 941                 dev_err(lcdc_dev->dev,
 942                         "in fbdc mode,unsupport fmt:%d!\n",
 943                         win->area[0].fmt_cfg);
 944                 break;
 945         }
 946         mb_h_size = 4;
 947
 948         /*macro block xvir and yvir */
 949         if ((win->area[0].xvir % mb_w_size == 0) &&
 950             (win->area[0].yvir % mb_h_size == 0)) {
 951                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 952                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 953         } else {
 954                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 955                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 956                        win->area[0].xvir, win->area[0].yvir,
 957                        mb_w_size, mb_h_size);
 958         }
 959         /*macro block xact and yact */
 960         if ((win->area[0].xact % mb_w_size == 0) &&
 961             (win->area[0].yact % mb_h_size == 0)) {
 962                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 963                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 964         } else {
 965                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 966                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 967                        win->area[0].xact, win->area[0].yact,
 968                        mb_w_size, mb_h_size);
 969         }
 970         /*macro block xoff and yoff */
 971         if ((win->area[0].xoff % mb_w_size == 0) &&
 972             (win->area[0].yoff % mb_h_size == 0)) {
 973                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 974                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 975         } else {
 976                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 977                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 978                        win->area[0].xoff, win->area[0].yoff,
 979                        mb_w_size, mb_h_size);
 980         }
 981
 982         /*FBDC tiles */
 983         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 984
 985         /*
 986            switch (fbdc_rotation_mode)  {
 987            case FBDC_ROT_NONE:
 988            fbdc_cmp_index_init =
 989            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 990            break;
 991            case FBDC_X_MIRROR:
 992            fbdc_cmp_index_init =
 993            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 994            (fbdc_mb_width-1));
 995            break;
 996            case FBDC_Y_MIRROR:
 997            fbdc_cmp_index_init =
 998            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 999            fbdc_mb_xst;
1000            break;
1001            case FBDC_ROT_180:
1002            fbdc_cmp_index_init =
1003            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1004            (fbdc_mb_xst+(fbdc_mb_width-1));
1005            break;
1006            }
1007          */
1008         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1009                 fbdc_cmp_index_init =
1010                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1011                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1012         } else {
1013                 fbdc_cmp_index_init =
1014                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1015         }
1016         /*fbdc fmt maybe need to change*/
1017         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1018         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1019         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1020         win->area[0].fbdc_mb_width = fbdc_mb_width;
1021         win->area[0].fbdc_mb_height = fbdc_mb_height;
1022         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1023         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1024         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1025         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1026
1027         return 0;
1028 }
1029
1030 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1031                                  struct rk_lcdc_win *win)
1032 {
1033         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1034         struct rk_screen *screen = dev_drv->cur_screen;
1035
1036         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1037                 switch (win->area[0].fmt_cfg) {
1038                 case VOP_FORMAT_ARGB888:
1039                 case VOP_FORMAT_RGB888:
1040                 case VOP_FORMAT_RGB565:
1041                         if ((screen->mode.xres < 1280) &&
1042                             (screen->mode.yres < 720)) {
1043                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1044                         } else {
1045                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1046                         }
1047                         break;
1048                 default:
1049                         break;
1050                 }
1051         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1052                 switch (win->area[0].fmt_cfg) {
1053                 case VOP_FORMAT_YCBCR420:
1054                         if ((win->id == 0) || (win->id == 1))
1055                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1056                         break;
1057                 default:
1058                         break;
1059                 }
1060         }
1061 }
1062
1063 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1064 {
1065         struct lcdc_device *lcdc_dev =
1066             container_of(dev_drv, struct lcdc_device, driver);
1067         struct rk_lcdc_win *win = dev_drv->win[win_id];
1068         unsigned int mask, val, off;
1069
1070         off = win_id * 0x40;
1071         /*if(win->win_lb_mode == 5)
1072            win->win_lb_mode = 4;
1073            for rk3288 to fix hw bug? */
1074
1075         if (win->state == 1) {
1076                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1077                 if (win->area[0].fbdc_en) {
1078                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1079                 } else {
1080                         mask = m_IFBDC_CTRL_FBDC_EN;
1081                         val = v_IFBDC_CTRL_FBDC_EN(0);
1082                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1083                 }
1084                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1085                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1086                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1087                 val = v_WIN0_EN(win->state) |
1088                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1089                     v_WIN0_FMT_10(win->fmt_10) |
1090                     v_WIN0_LB_MODE(win->win_lb_mode) |
1091                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1092                     v_WIN0_X_MIRROR(win->mirror_en) |
1093                     v_WIN0_Y_MIRROR(win->mirror_en) |
1094                     v_WIN0_CSC_MODE(win->csc_mode);
1095                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1096
1097                 mask = m_WIN0_BIC_COE_SEL |
1098                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1099                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1100                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1101                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1102                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1103                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1104                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1105                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1106                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1107                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1108                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1109                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1110                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1111                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1112                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1113                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1114                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1115                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1116                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1117                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1118                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1119                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1120                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1121                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1122                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1123                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1124                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1125                                 win->area[0].y_addr);
1126                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1127                                 win->area[0].uv_addr); */
1128                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1129                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1130                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1131
1132                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1133                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1134                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1135
1136                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1137                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1138                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1139
1140                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1141                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1142                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1143
1144                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1145                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1146                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1147                 if (win->alpha_en == 1) {
1148                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1149                 } else {
1150                         mask = m_WIN0_SRC_ALPHA_EN;
1151                         val = v_WIN0_SRC_ALPHA_EN(0);
1152                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1153                                      mask, val);
1154                 }
1155         } else {
1156                 mask = m_WIN0_EN;
1157                 val = v_WIN0_EN(win->state);
1158                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1159         }
1160         return 0;
1161 }
1162
1163 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1164 {
1165         struct lcdc_device *lcdc_dev =
1166             container_of(dev_drv, struct lcdc_device, driver);
1167         struct rk_lcdc_win *win = dev_drv->win[win_id];
1168         unsigned int mask, val, off;
1169
1170         off = (win_id - 2) * 0x50;
1171         rk3368_lcdc_area_xst(win, win->area_num);
1172
1173         if (win->state == 1) {
1174                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1175                 if (win->area[0].fbdc_en) {
1176                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1177                 } else {
1178                         mask = m_IFBDC_CTRL_FBDC_EN;
1179                         val = v_IFBDC_CTRL_FBDC_EN(0);
1180                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1181                 }
1182
1183                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1184                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1185                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1186                 /*area 0 */
1187                 if (win->area[0].state == 1) {
1188                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1189                             m_WIN2_RB_SWAP0;
1190                         val = v_WIN2_MST0_EN(win->area[0].state) |
1191                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1192                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1193                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1194
1195                         mask = m_WIN2_VIR_STRIDE0;
1196                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1197                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1198
1199                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1200                            win->area[0].y_addr); */
1201                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1202                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1203                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1204                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1205                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1206                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1207                 } else {
1208                         mask = m_WIN2_MST0_EN;
1209                         val = v_WIN2_MST0_EN(0);
1210                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1211                 }
1212                 /*area 1 */
1213                 if (win->area[1].state == 1) {
1214                         /*rk3368_win_area_check_var(win_id, 1,
1215                                                   &win->area[0], &win->area[1]);
1216                         */
1217
1218                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1219                             m_WIN2_RB_SWAP1;
1220                         val = v_WIN2_MST1_EN(win->area[1].state) |
1221                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1222                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1223                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1224
1225                         mask = m_WIN2_VIR_STRIDE1;
1226                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1227                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1228
1229                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1230                            win->area[1].y_addr); */
1231                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1232                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1233                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1234                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1235                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1236                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1237                 } else {
1238                         mask = m_WIN2_MST1_EN;
1239                         val = v_WIN2_MST1_EN(0);
1240                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1241                 }
1242                 /*area 2 */
1243                 if (win->area[2].state == 1) {
1244                         /*rk3368_win_area_check_var(win_id, 2,
1245                                                   &win->area[1], &win->area[2]);
1246                         */
1247
1248                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1249                             m_WIN2_RB_SWAP2;
1250                         val = v_WIN2_MST2_EN(win->area[2].state) |
1251                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1252                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1253                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1254
1255                         mask = m_WIN2_VIR_STRIDE2;
1256                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1257                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1258
1259                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1260                            win->area[2].y_addr); */
1261                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1262                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1263                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1264                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1265                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1266                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1267                 } else {
1268                         mask = m_WIN2_MST2_EN;
1269                         val = v_WIN2_MST2_EN(0);
1270                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1271                 }
1272                 /*area 3 */
1273                 if (win->area[3].state == 1) {
1274                         /*rk3368_win_area_check_var(win_id, 3,
1275                                                   &win->area[2], &win->area[3]);
1276                         */
1277
1278                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1279                             m_WIN2_RB_SWAP3;
1280                         val = v_WIN2_MST3_EN(win->area[3].state) |
1281                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1282                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1283                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1284
1285                         mask = m_WIN2_VIR_STRIDE3;
1286                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1287                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1288
1289                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1290                            win->area[3].y_addr); */
1291                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1292                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1293                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1294                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1295                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1296                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1297                 } else {
1298                         mask = m_WIN2_MST3_EN;
1299                         val = v_WIN2_MST3_EN(0);
1300                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1301                 }
1302
1303                 if (win->alpha_en == 1) {
1304                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1305                 } else {
1306                         mask = m_WIN2_SRC_ALPHA_EN;
1307                         val = v_WIN2_SRC_ALPHA_EN(0);
1308                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1309                                      mask, val);
1310                 }
1311         } else {
1312                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1313                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1314                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1315                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1316                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1317         }
1318         return 0;
1319 }
1320
1321 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1322 {
1323         struct lcdc_device *lcdc_dev =
1324             container_of(dev_drv, struct lcdc_device, driver);
1325         struct rk_lcdc_win *win = dev_drv->win[win_id];
1326         unsigned int mask, val, hwc_size = 0;
1327
1328         if (win->state == 1) {
1329                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1330                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1331                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1332                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1333                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1334                     v_WIN0_CSC_MODE(win->csc_mode);
1335                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1336
1337                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1338                         hwc_size = 0;
1339                 else if ((win->area[0].xsize == 64) &&
1340                          (win->area[0].ysize == 64))
1341                         hwc_size = 1;
1342                 else if ((win->area[0].xsize == 96) &&
1343                          (win->area[0].ysize == 96))
1344                         hwc_size = 2;
1345                 else if ((win->area[0].xsize == 128) &&
1346                          (win->area[0].ysize == 128))
1347                         hwc_size = 3;
1348                 else
1349                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1350
1351                 mask = m_HWC_SIZE;
1352                 val = v_HWC_SIZE(hwc_size);
1353                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1354
1355                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1356                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1357                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1358                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1359
1360                 if (win->alpha_en == 1) {
1361                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1362                 } else {
1363                         mask = m_WIN2_SRC_ALPHA_EN;
1364                         val = v_WIN2_SRC_ALPHA_EN(0);
1365                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1366                 }
1367         } else {
1368                 mask = m_HWC_EN;
1369                 val = v_HWC_EN(win->state);
1370                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1371         }
1372         return 0;
1373 }
1374
1375 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1376                                          struct rk_lcdc_win *win)
1377 {
1378         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1379         int timeout;
1380         unsigned long flags;
1381
1382         spin_lock(&lcdc_dev->reg_lock);
1383         if (likely(lcdc_dev->clk_on)) {
1384                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1385                              v_STANDBY_EN(lcdc_dev->standby));
1386                 if ((win->id == 0) || (win->id == 1))
1387                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1388                 else if ((win->id == 2) || (win->id == 3))
1389                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1390                 else if (win->id == 4)
1391                         rk3368_hwc_reg_update(dev_drv, win->id);
1392                 /*rk3368_lcdc_post_cfg(dev_drv); */
1393                 lcdc_cfg_done(lcdc_dev);
1394         }
1395         spin_unlock(&lcdc_dev->reg_lock);
1396
1397         /*if (dev_drv->wait_fs) { */
1398         if (0) {
1399                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1400                 init_completion(&dev_drv->frame_done);
1401                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1402                 timeout =
1403                     wait_for_completion_timeout(&dev_drv->frame_done,
1404                                                 msecs_to_jiffies
1405                                                 (dev_drv->cur_screen->ft + 5));
1406                 if (!timeout && (!dev_drv->frame_done.done)) {
1407                         dev_warn(lcdc_dev->dev,
1408                                  "wait for new frame start time out!\n");
1409                         return -ETIMEDOUT;
1410                 }
1411         }
1412         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1413         return 0;
1414 }
1415
1416 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1417 {
1418         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1419         return 0;
1420 }
1421
1422 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1423 {
1424         u32 mask, val;
1425         struct lcdc_device *lcdc_dev =
1426             container_of(dev_drv, struct lcdc_device, driver);
1427
1428 #if defined(CONFIG_ROCKCHIP_IOMMU)
1429         if (dev_drv->iommu_enabled) {
1430                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1431                         if (likely(lcdc_dev->clk_on)) {
1432                                 mask = m_MMU_EN;
1433                                 val = v_MMU_EN(1);
1434                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1435                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1436                                         m_AXI_OUTSTANDING_MAX_NUM;
1437                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1438                                         v_AXI_MAX_OUTSTANDING_EN(1);
1439                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1440                         }
1441                         lcdc_dev->iommu_status = 1;
1442                         rockchip_iovmm_activate(dev_drv->dev);
1443                 }
1444         }
1445 #endif
1446         return 0;
1447 }
1448
1449 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1450 {
1451         int ret = 0, fps = 0;
1452         struct lcdc_device *lcdc_dev =
1453             container_of(dev_drv, struct lcdc_device, driver);
1454         struct rk_screen *screen = dev_drv->cur_screen;
1455 #ifdef CONFIG_RK_FPGA
1456         return 0;
1457 #endif
1458
1459         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1460         if (ret)
1461                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1462         lcdc_dev->pixclock =
1463             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1464         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1465
1466         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1467         screen->ft = 1000 / fps;
1468         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1469                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1470         return 0;
1471 }
1472
1473 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1474 {
1475         struct lcdc_device *lcdc_dev =
1476             container_of(dev_drv, struct lcdc_device, driver);
1477         struct rk_screen *screen = dev_drv->cur_screen;
1478         u16 hsync_len = screen->mode.hsync_len;
1479         u16 left_margin = screen->mode.left_margin;
1480         u16 right_margin = screen->mode.right_margin;
1481         u16 vsync_len = screen->mode.vsync_len;
1482         u16 upper_margin = screen->mode.upper_margin;
1483         u16 lower_margin = screen->mode.lower_margin;
1484         u16 x_res = screen->mode.xres;
1485         u16 y_res = screen->mode.yres;
1486         u32 mask, val;
1487         u16 h_total, v_total;
1488         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1489
1490         h_total = hsync_len + left_margin + x_res + right_margin;
1491         v_total = vsync_len + upper_margin + y_res + lower_margin;
1492
1493         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1494         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1495         screen->post_xsize = x_res *
1496             (screen->overscan.left + screen->overscan.right) / 200;
1497         screen->post_ysize = y_res *
1498             (screen->overscan.top + screen->overscan.bottom) / 200;
1499
1500         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1501         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1502         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1503
1504         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1505         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1506             v_DSP_HACT_ST(hsync_len + left_margin);
1507         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1508
1509         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1510                 /* First Field Timing */
1511                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1512                 val = v_DSP_VS_PW(vsync_len) |
1513                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1514                                       lower_margin) + y_res + 1);
1515                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1516
1517                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1518                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1519                     v_DSP_VACT_ST(vsync_len + upper_margin);
1520                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1521
1522                 /* Second Field Timing */
1523                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1524                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1525                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1526                     lower_margin;
1527                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1528                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1529
1530                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1531                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1532                     lower_margin + 1;
1533                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1534                     lower_margin + 1;
1535                 val =
1536                     v_DSP_VACT_END_F1(vact_end_f1) |
1537                     v_DSP_VAC_ST_F1(vact_st_f1);
1538                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1539
1540                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1541                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1542                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1543                 mask =
1544                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1545                     m_WIN0_CBR_DEFLICK;
1546                 val =
1547                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1548                     v_WIN0_CBR_DEFLICK(1);
1549                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1550
1551                 mask =
1552                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1553                     m_WIN1_CBR_DEFLICK;
1554                 val =
1555                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1556                     v_WIN1_CBR_DEFLICK(1);
1557                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1558
1559                 mask = m_WIN2_INTERLACE_READ;
1560                 val = v_WIN2_INTERLACE_READ(1);
1561                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1562
1563                 mask = m_WIN3_INTERLACE_READ;
1564                 val = v_WIN3_INTERLACE_READ(1);
1565                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1566
1567                 mask = m_HWC_INTERLACE_READ;
1568                 val = v_HWC_INTERLACE_READ(1);
1569                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1570
1571                 mask = m_DSP_LINE_FLAG0_NUM;
1572                 val =
1573                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1574                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1575         } else {
1576                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1577                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1578                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1579
1580                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1581                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1582                     v_DSP_VACT_ST(vsync_len + upper_margin);
1583                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1584
1585                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1586                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1587                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1588
1589                 mask =
1590                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1591                     m_WIN0_CBR_DEFLICK;
1592                 val =
1593                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1594                     v_WIN0_CBR_DEFLICK(0);
1595                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1596
1597                 mask =
1598                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1599                     m_WIN1_CBR_DEFLICK;
1600                 val =
1601                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1602                     v_WIN1_CBR_DEFLICK(0);
1603                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1604
1605                 mask = m_WIN2_INTERLACE_READ;
1606                 val = v_WIN2_INTERLACE_READ(0);
1607                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1608
1609                 mask = m_WIN3_INTERLACE_READ;
1610                 val = v_WIN3_INTERLACE_READ(0);
1611                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1612
1613                 mask = m_HWC_INTERLACE_READ;
1614                 val = v_HWC_INTERLACE_READ(0);
1615                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1616
1617                 mask = m_DSP_LINE_FLAG0_NUM;
1618                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1619                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1620         }
1621         rk3368_lcdc_post_cfg(dev_drv);
1622         return 0;
1623 }
1624
1625 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1626 {
1627         struct lcdc_device *lcdc_dev =
1628             container_of(dev_drv, struct lcdc_device, driver);
1629         u32 bcsh_ctrl;
1630
1631         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1632                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1633         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1634                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1635                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1636                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1637                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1638                 else            /* YUV2RGB */
1639                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1640                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1641                                      m_BCSH_R2Y_EN,
1642                                      v_BCSH_Y2R_EN(1) |
1643                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1644                                      v_BCSH_R2Y_EN(0));
1645         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1646                 /* bypass  --need check,if bcsh close? */
1647                 if (dev_drv->output_color == COLOR_RGB) {
1648                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1649                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1650                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1651                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1652                                              m_BCSH_R2Y_EN |
1653                                              m_BCSH_Y2R_EN,
1654                                              v_BCSH_R2Y_EN(1) |
1655                                              v_BCSH_Y2R_EN(1));
1656                         else
1657                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1658                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1659                                              v_BCSH_R2Y_EN(0) |
1660                                              v_BCSH_Y2R_EN(0));
1661                 } else          /* RGB2YUV */
1662                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1663                                      m_BCSH_R2Y_EN |
1664                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1665                                      v_BCSH_R2Y_EN(1) |
1666                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1667                                      v_BCSH_Y2R_EN(0));
1668         }
1669 }
1670
1671 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1672                                   u16 *yact, int *format, u32 *dsp_addr)
1673 {
1674         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1675                                                     struct lcdc_device, driver);
1676         u32 val;
1677
1678         spin_lock(&lcdc_dev->reg_lock);
1679
1680         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1681         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1682         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1683
1684         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1685         *format = (val & m_WIN0_DATA_FMT) >> 1;
1686         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1687
1688         spin_unlock(&lcdc_dev->reg_lock);
1689
1690         return 0;
1691 }
1692
1693 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1694                               int format, u16 xact, u16 yact, u16 xvir)
1695 {
1696         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1697                                                     struct lcdc_device, driver);
1698         u32 val, mask;
1699         int swap = (format == RGB888) ? 1 : 0;
1700
1701         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1702         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1703         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1704
1705         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1706                         v_WIN0_VIR_STRIDE(xvir));
1707         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1708                     v_WIN0_ACT_HEIGHT(yact));
1709
1710         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1711
1712         lcdc_cfg_done(lcdc_dev);
1713
1714         return 0;
1715 }
1716
1717
1718 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1719 {
1720         u16 face = 0;
1721         u16 dclk_ddr = 0;
1722         u32 v = 0;
1723         struct lcdc_device *lcdc_dev =
1724             container_of(dev_drv, struct lcdc_device, driver);
1725         struct rk_screen *screen = dev_drv->cur_screen;
1726         u32 mask, val;
1727
1728         spin_lock(&lcdc_dev->reg_lock);
1729         if (likely(lcdc_dev->clk_on)) {
1730                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1731                 if (!lcdc_dev->standby && !initscreen) {
1732                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1733                                      v_STANDBY_EN(1));
1734                         lcdc_cfg_done(lcdc_dev);
1735                         mdelay(50);
1736                 }
1737                 switch (screen->face) {
1738                 case OUT_P565:
1739                         face = OUT_P565;
1740                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1741                             m_DITHER_DOWN_SEL;
1742                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1743                             v_DITHER_DOWN_SEL(1);
1744                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1745                         break;
1746                 case OUT_P666:
1747                         face = OUT_P666;
1748                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1749                             m_DITHER_DOWN_SEL;
1750                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1751                             v_DITHER_DOWN_SEL(1);
1752                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1753                         break;
1754                 case OUT_D888_P565:
1755                         face = OUT_P888;
1756                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1757                             m_DITHER_DOWN_SEL;
1758                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1759                             v_DITHER_DOWN_SEL(1);
1760                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1761                         break;
1762                 case OUT_D888_P666:
1763                         face = OUT_P888;
1764                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1765                             m_DITHER_DOWN_SEL;
1766                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1767                             v_DITHER_DOWN_SEL(1);
1768                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1769                         break;
1770                 case OUT_P888:
1771                         face = OUT_P888;
1772                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1773                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1774                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1775                         break;
1776                 case OUT_YUV_420:
1777                         /*yuv420 output prefer yuv domain overlay */
1778                         face = OUT_YUV_420;
1779                         dclk_ddr = 1;
1780                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1781                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1782                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1783                         break;
1784                 default:
1785                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1786                         break;
1787                 }
1788                 switch (screen->type) {
1789                 case SCREEN_RGB:
1790                         mask = m_RGB_OUT_EN;
1791                         val = v_RGB_OUT_EN(1);
1792                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1793                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1794                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1795                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1796                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1797                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1798                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1799                         v = 1 << 15 | (1 << (15 + 16));
1800
1801                         break;
1802                 case SCREEN_LVDS:
1803                         mask = m_RGB_OUT_EN;
1804                         val = v_RGB_OUT_EN(1);
1805                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1806                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1807                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1808                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1809                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1810                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1811                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1812                         v = 0 << 15 | (1 << (15 + 16));
1813                         break;
1814                 case SCREEN_HDMI:
1815                         /*face = OUT_RGB_AAA;*/
1816                         if (screen->color_mode == COLOR_RGB)
1817                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1818                         else
1819                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1820                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1821                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1822                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1823                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1824                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1825                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1826                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1827                             v_HDMI_DEN_POL(screen->pin_den) |
1828                             v_HDMI_DCLK_POL(screen->pin_dclk);
1829                         break;
1830                 case SCREEN_MIPI:
1831                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1832                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1833                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1834                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1835                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1836                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1837                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1838                             v_MIPI_DEN_POL(screen->pin_den) |
1839                             v_MIPI_DCLK_POL(screen->pin_dclk);
1840                         break;
1841                 case SCREEN_DUAL_MIPI:
1842                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1843                                 m_RGB_OUT_EN;
1844                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1845                                 v_RGB_OUT_EN(0);
1846                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1847                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1848                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1849                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1850                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1851                             v_MIPI_DEN_POL(screen->pin_den) |
1852                             v_MIPI_DCLK_POL(screen->pin_dclk);
1853                         break;
1854                 case SCREEN_EDP:
1855                         face = OUT_P888;        /*RGB 888 output */
1856
1857                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1858                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1859                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1860                         /*because edp have to sent aaa fmt */
1861                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1862                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1863
1864                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1865                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1866                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1867                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1868                             v_EDP_DEN_POL(screen->pin_den) |
1869                             v_EDP_DCLK_POL(screen->pin_dclk);
1870                         break;
1871                 }
1872                 /*hsync vsync den dclk polo,dither */
1873                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1874 #ifndef CONFIG_RK_FPGA
1875                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1876                 move to  lvds driver*/
1877                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1878 #endif
1879                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1880                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1881                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1882                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1883                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1884                     v_DSP_BG_SWAP(screen->swap_gb) |
1885                     v_DSP_RB_SWAP(screen->swap_rb) |
1886                     v_DSP_RG_SWAP(screen->swap_rg) |
1887                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1888                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1889                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1890                     v_DSP_X_MIR_EN(screen->x_mirror) |
1891                     v_DSP_Y_MIR_EN(screen->y_mirror);
1892                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1893                 /*BG color */
1894                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1895                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1896                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1897                                 v_DSP_BG_RED(0x80);
1898                 else
1899                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1900                                 v_DSP_BG_RED(0);
1901                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1902                 dev_drv->output_color = screen->color_mode;
1903                 if (screen->dsp_lut == NULL)
1904                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1905                                      v_DSP_LUT_EN(0));
1906                 else
1907                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1908                                      v_DSP_LUT_EN(1));
1909                 if (screen->cabc_lut == NULL) {
1910                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN,
1911                                      v_CABC_EN(0));
1912                 } else {
1913                         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
1914                                      v_CABC_LUT_EN(1));
1915                 }
1916                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1917                 rk3368_config_timing(dev_drv);
1918         }
1919         spin_unlock(&lcdc_dev->reg_lock);
1920         rk3368_lcdc_set_dclk(dev_drv);
1921         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1922             dev_drv->trsm_ops->enable)
1923                 dev_drv->trsm_ops->enable();
1924         if (screen->init)
1925                 screen->init();
1926         if (!lcdc_dev->standby)
1927                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1928         return 0;
1929 }
1930
1931
1932 /*enable layer,open:1,enable;0 disable*/
1933 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1934                                      unsigned int win_id, bool open)
1935 {
1936         spin_lock(&lcdc_dev->reg_lock);
1937         if (likely(lcdc_dev->clk_on) &&
1938             lcdc_dev->driver.win[win_id]->state != open) {
1939                 if (open) {
1940                         if (!lcdc_dev->atv_layer_cnt) {
1941                                 dev_info(lcdc_dev->dev,
1942                                          "wakeup from standby!\n");
1943                                 lcdc_dev->standby = 0;
1944                         }
1945                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1946                 } else {
1947                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1948                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1949                 }
1950                 lcdc_dev->driver.win[win_id]->state = open;
1951                 if (!open) {
1952                         /*rk3368_lcdc_reg_update(dev_drv);*/
1953                         rk3368_lcdc_layer_update_regs
1954                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1955                         lcdc_cfg_done(lcdc_dev);
1956                 }
1957                 /*if no layer used,disable lcdc */
1958                 if (!lcdc_dev->atv_layer_cnt) {
1959                         dev_info(lcdc_dev->dev,
1960                                  "no layer is used,go to standby!\n");
1961                         lcdc_dev->standby = 1;
1962                 }
1963         }
1964         spin_unlock(&lcdc_dev->reg_lock);
1965 }
1966
1967 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1968 {
1969         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1970                                                     struct lcdc_device, driver);
1971         u32 mask, val;
1972         /*struct rk_screen *screen = dev_drv->cur_screen; */
1973
1974         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1975             m_LINE_FLAG1_INTR_CLR;
1976         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1977             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1978         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1979
1980         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1981         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1982             v_BUS_ERROR_INTR_EN(1);
1983         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1984
1985 #ifdef LCDC_IRQ_EMPTY_DEBUG
1986         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1987             m_WIN2_EMPTY_INTR_EN |
1988             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1989             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1990         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1991             v_WIN2_EMPTY_INTR_EN(1) |
1992             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1993             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1994         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1995 #endif
1996         return 0;
1997 }
1998
1999 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
2000                             bool open)
2001 {
2002         struct lcdc_device *lcdc_dev =
2003             container_of(dev_drv, struct lcdc_device, driver);
2004 #if 0/*ndef CONFIG_RK_FPGA*/
2005         int sys_status =
2006             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2007 #endif
2008         /*enable clk,when first layer open */
2009         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2010                 /*rockchip_set_system_status(sys_status);*/
2011                 rk3368_lcdc_pre_init(dev_drv);
2012                 rk3368_lcdc_clk_enable(lcdc_dev);
2013 #if defined(CONFIG_ROCKCHIP_IOMMU)
2014                 if (dev_drv->iommu_enabled) {
2015                         if (!dev_drv->mmu_dev) {
2016                                 dev_drv->mmu_dev =
2017                                     rk_fb_get_sysmmu_device_by_compatible
2018                                     (dev_drv->mmu_dts_name);
2019                                 if (dev_drv->mmu_dev) {
2020                                         rk_fb_platform_set_sysmmu
2021                                             (dev_drv->mmu_dev, dev_drv->dev);
2022                                 } else {
2023                                         dev_err(dev_drv->dev,
2024                                                 "fail get rk iommu device\n");
2025                                         return -1;
2026                                 }
2027                         }
2028                         /*if (dev_drv->mmu_dev)
2029                            rockchip_iovmm_activate(dev_drv->dev); */
2030                 }
2031 #endif
2032                 rk3368_lcdc_reg_restore(lcdc_dev);
2033                 /*if (dev_drv->iommu_enabled)
2034                    rk3368_lcdc_mmu_en(dev_drv); */
2035                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2036                         /*rk3368_lcdc_set_dclk(dev_drv); */
2037                         rk3368_lcdc_enable_irq(dev_drv);
2038                 } else {
2039                         rk3368_load_screen(dev_drv, 1);
2040                 }
2041                 if (dev_drv->bcsh.enable)
2042                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2043                 spin_lock(&lcdc_dev->reg_lock);
2044                 if (dev_drv->cur_screen->dsp_lut)
2045                         rk3368_lcdc_set_lut(dev_drv,
2046                                             dev_drv->cur_screen->dsp_lut);
2047                 if (dev_drv->cur_screen->cabc_lut)
2048                         rk3368_set_cabc_lut(dev_drv,
2049                                             dev_drv->cur_screen->cabc_lut);
2050                 spin_unlock(&lcdc_dev->reg_lock);
2051         }
2052
2053         if (win_id < ARRAY_SIZE(lcdc_win))
2054                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2055         else
2056                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2057
2058
2059         /* when all layer closed,disable clk */
2060         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2061            rk3368_lcdc_disable_irq(lcdc_dev);
2062            rk3368_lcdc_reg_update(dev_drv);
2063            #if defined(CONFIG_ROCKCHIP_IOMMU)
2064            if (dev_drv->iommu_enabled) {
2065            if (dev_drv->mmu_dev)
2066            rockchip_iovmm_deactivate(dev_drv->dev);
2067            }
2068            #endif
2069            rk3368_lcdc_clk_disable(lcdc_dev);
2070            #ifndef CONFIG_RK_FPGA
2071            rockchip_clear_system_status(sys_status);
2072            #endif
2073            } */
2074
2075         return 0;
2076 }
2077
2078 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2079                            struct rk_lcdc_win *win)
2080 {
2081         u32 y_addr;
2082         u32 uv_addr;
2083         unsigned int off;
2084
2085         off = win->id * 0x40;
2086         /*win->smem_start + win->y_offset; */
2087         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2088         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2089         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2090             lcdc_dev->id, win->id, y_addr, uv_addr);
2091         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2092             win->area[0].y_offset, win->area[0].c_offset);
2093         spin_lock(&lcdc_dev->reg_lock);
2094         if (likely(lcdc_dev->clk_on)) {
2095                 win->area[0].y_addr = y_addr;
2096                 win->area[0].uv_addr = uv_addr;
2097                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2098                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2099                 /*lcdc_cfg_done(lcdc_dev); */
2100         }
2101         spin_unlock(&lcdc_dev->reg_lock);
2102
2103         return 0;
2104 }
2105
2106 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2107                            struct rk_lcdc_win *win)
2108 {
2109         u32 i, y_addr;
2110         unsigned int off;
2111
2112         off = (win->id - 2) * 0x50;
2113         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2114         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2115
2116         spin_lock(&lcdc_dev->reg_lock);
2117         if (likely(lcdc_dev->clk_on)) {
2118                 for (i = 0; i < win->area_num; i++) {
2119                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2120                             i, win->area[i].y_addr, win->area[i].y_offset);
2121                         win->area[i].y_addr =
2122                             win->area[i].smem_start + win->area[i].y_offset;
2123                         }
2124                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2125                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2126                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2127                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2128         }
2129         spin_unlock(&lcdc_dev->reg_lock);
2130         return 0;
2131 }
2132
2133 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2134 {
2135         u32 y_addr;
2136
2137         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2138         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2139             lcdc_dev->id, __func__, y_addr);
2140         spin_lock(&lcdc_dev->reg_lock);
2141         if (likely(lcdc_dev->clk_on)) {
2142                 win->area[0].y_addr = y_addr;
2143                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2144         }
2145         spin_unlock(&lcdc_dev->reg_lock);
2146
2147         return 0;
2148 }
2149
2150 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2151 {
2152         struct lcdc_device *lcdc_dev =
2153             container_of(dev_drv, struct lcdc_device, driver);
2154         struct rk_lcdc_win *win = NULL;
2155         struct rk_screen *screen = dev_drv->cur_screen;
2156
2157 #if defined(WAIT_FOR_SYNC)
2158         int timeout;
2159         unsigned long flags;
2160 #endif
2161         win = dev_drv->win[win_id];
2162         if (!screen) {
2163                 dev_err(dev_drv->dev, "screen is null!\n");
2164                 return -ENOENT;
2165         }
2166         if (win_id == 0) {
2167                 win_0_1_display(lcdc_dev, win);
2168         } else if (win_id == 1) {
2169                 win_0_1_display(lcdc_dev, win);
2170         } else if (win_id == 2) {
2171                 win_2_3_display(lcdc_dev, win);
2172         } else if (win_id == 3) {
2173                 win_2_3_display(lcdc_dev, win);
2174         } else if (win_id == 4) {
2175                 hwc_display(lcdc_dev, win);
2176         } else {
2177                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2178                 return -EINVAL;
2179         }
2180
2181         /*this is the first frame of the system ,enable frame start interrupt */
2182         if ((dev_drv->first_frame)) {
2183                 dev_drv->first_frame = 0;
2184                 rk3368_lcdc_enable_irq(dev_drv);
2185         }
2186 #if defined(WAIT_FOR_SYNC)
2187         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2188         init_completion(&dev_drv->frame_done);
2189         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2190         timeout =
2191             wait_for_completion_timeout(&dev_drv->frame_done,
2192                                         msecs_to_jiffies(dev_drv->
2193                                                          cur_screen->ft + 5));
2194         if (!timeout && (!dev_drv->frame_done.done)) {
2195                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2196                 return -ETIMEDOUT;
2197         }
2198 #endif
2199         return 0;
2200 }
2201
2202 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2203 {
2204         u16 srcW;
2205         u16 srcH;
2206         u16 dstW;
2207         u16 dstH;
2208         u16 yrgb_srcW;
2209         u16 yrgb_srcH;
2210         u16 yrgb_dstW;
2211         u16 yrgb_dstH;
2212         u32 yrgb_vscalednmult;
2213         u32 yrgb_xscl_factor;
2214         u32 yrgb_yscl_factor;
2215         u8 yrgb_vsd_bil_gt2 = 0;
2216         u8 yrgb_vsd_bil_gt4 = 0;
2217
2218         u16 cbcr_srcW;
2219         u16 cbcr_srcH;
2220         u16 cbcr_dstW;
2221         u16 cbcr_dstH;
2222         u32 cbcr_vscalednmult;
2223         u32 cbcr_xscl_factor;
2224         u32 cbcr_yscl_factor;
2225         u8 cbcr_vsd_bil_gt2 = 0;
2226         u8 cbcr_vsd_bil_gt4 = 0;
2227         u8 yuv_fmt = 0;
2228
2229         srcW = win->area[0].xact;
2230         srcH = win->area[0].yact;
2231         dstW = win->area[0].xsize;
2232         dstH = win->area[0].ysize;
2233
2234         /*yrgb scl mode */
2235         yrgb_srcW = srcW;
2236         yrgb_srcH = srcH;
2237         yrgb_dstW = dstW;
2238         yrgb_dstH = dstH;
2239         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2240                 pr_err("ERROR: yrgb scale exceed 8,");
2241                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2242                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2243         }
2244         if (yrgb_srcW < yrgb_dstW)
2245                 win->yrgb_hor_scl_mode = SCALE_UP;
2246         else if (yrgb_srcW > yrgb_dstW)
2247                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2248         else
2249                 win->yrgb_hor_scl_mode = SCALE_NONE;
2250
2251         if (yrgb_srcH < yrgb_dstH)
2252                 win->yrgb_ver_scl_mode = SCALE_UP;
2253         else if (yrgb_srcH > yrgb_dstH)
2254                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2255         else
2256                 win->yrgb_ver_scl_mode = SCALE_NONE;
2257
2258         /*cbcr scl mode */
2259         switch (win->area[0].format) {
2260         case YUV422:
2261         case YUV422_A:
2262                 cbcr_srcW = srcW / 2;
2263                 cbcr_dstW = dstW;
2264                 cbcr_srcH = srcH;
2265                 cbcr_dstH = dstH;
2266                 yuv_fmt = 1;
2267                 break;
2268         case YUV420:
2269         case YUV420_A:
2270                 cbcr_srcW = srcW / 2;
2271                 cbcr_dstW = dstW;
2272                 cbcr_srcH = srcH / 2;
2273                 cbcr_dstH = dstH;
2274                 yuv_fmt = 1;
2275                 break;
2276         case YUV444:
2277         case YUV444_A:
2278                 cbcr_srcW = srcW;
2279                 cbcr_dstW = dstW;
2280                 cbcr_srcH = srcH;
2281                 cbcr_dstH = dstH;
2282                 yuv_fmt = 1;
2283                 break;
2284         default:
2285                 cbcr_srcW = 0;
2286                 cbcr_dstW = 0;
2287                 cbcr_srcH = 0;
2288                 cbcr_dstH = 0;
2289                 yuv_fmt = 0;
2290                 break;
2291         }
2292         if (yuv_fmt) {
2293                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2294                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2295                         pr_err("ERROR: cbcr scale exceed 8,");
2296                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2297                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2298                 }
2299         }
2300
2301         if (cbcr_srcW < cbcr_dstW)
2302                 win->cbr_hor_scl_mode = SCALE_UP;
2303         else if (cbcr_srcW > cbcr_dstW)
2304                 win->cbr_hor_scl_mode = SCALE_DOWN;
2305         else
2306                 win->cbr_hor_scl_mode = SCALE_NONE;
2307
2308         if (cbcr_srcH < cbcr_dstH)
2309                 win->cbr_ver_scl_mode = SCALE_UP;
2310         else if (cbcr_srcH > cbcr_dstH)
2311                 win->cbr_ver_scl_mode = SCALE_DOWN;
2312         else
2313                 win->cbr_ver_scl_mode = SCALE_NONE;
2314
2315         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2316             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2317             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2318             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2319             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2320             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2321             win->cbr_ver_scl_mode);*/
2322
2323         /*line buffer mode */
2324         if ((win->area[0].format == YUV422) ||
2325             (win->area[0].format == YUV420) ||
2326             (win->area[0].format == YUV422_A) ||
2327             (win->area[0].format == YUV420_A)) {
2328                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2329                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2330                             (cbcr_dstW == 0))
2331                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2332                                        cbcr_dstW);
2333                         else if (cbcr_dstW > 1280)
2334                                 win->win_lb_mode = LB_YUV_3840X5;
2335                         else
2336                                 win->win_lb_mode = LB_YUV_2560X8;
2337                 } else {        /*SCALE_UP or SCALE_NONE */
2338                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2339                             (cbcr_srcW == 0))
2340                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2341                                        cbcr_srcW);
2342                         else if (cbcr_srcW > 1280)
2343                                 win->win_lb_mode = LB_YUV_3840X5;
2344                         else
2345                                 win->win_lb_mode = LB_YUV_2560X8;
2346                 }
2347         } else {
2348                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2349                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2350                             (yrgb_dstW == 0))
2351                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2352                         else if (yrgb_dstW > 2560)
2353                                 win->win_lb_mode = LB_RGB_3840X2;
2354                         else if (yrgb_dstW > 1920)
2355                                 win->win_lb_mode = LB_RGB_2560X4;
2356                         else if (yrgb_dstW > 1280)
2357                                 win->win_lb_mode = LB_RGB_1920X5;
2358                         else
2359                                 win->win_lb_mode = LB_RGB_1280X8;
2360                 } else {        /*SCALE_UP or SCALE_NONE */
2361                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2362                             (yrgb_srcW == 0))
2363                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2364                         else if (yrgb_srcW > 2560)
2365                                 win->win_lb_mode = LB_RGB_3840X2;
2366                         else if (yrgb_srcW > 1920)
2367                                 win->win_lb_mode = LB_RGB_2560X4;
2368                         else if (yrgb_srcW > 1280)
2369                                 win->win_lb_mode = LB_RGB_1920X5;
2370                         else
2371                                 win->win_lb_mode = LB_RGB_1280X8;
2372                 }
2373         }
2374         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2375
2376         /*vsd/vsu scale ALGORITHM */
2377         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2378         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2379         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2380         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2381         switch (win->win_lb_mode) {
2382         case LB_YUV_3840X5:
2383         case LB_YUV_2560X8:
2384         case LB_RGB_1920X5:
2385         case LB_RGB_1280X8:
2386                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2387                 win->cbr_vsu_mode = SCALE_UP_BIC;
2388                 break;
2389         case LB_RGB_3840X2:
2390                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2391                         pr_err("ERROR : not allow yrgb ver scale\n");
2392                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2393                         pr_err("ERROR : not allow cbcr ver scale\n");
2394                 break;
2395         case LB_RGB_2560X4:
2396                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2397                 win->cbr_vsu_mode = SCALE_UP_BIL;
2398                 break;
2399         default:
2400                 pr_info("%s:un supported win_lb_mode:%d\n",
2401                         __func__, win->win_lb_mode);
2402                 break;
2403         }
2404         if (win->mirror_en == 1) {      /*interlace mode must bill */
2405                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2406         }
2407
2408         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2409             (win->area[0].fbdc_en == 1)) {
2410                 /*in this pattern,use bil mode,not support souble scd,
2411                 use avg mode, support double scd, but aclk should be
2412                 bigger than dclk,aclk>>dclk */
2413                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2414                         pr_err("ERROR : fbdc mode,not support y scale down:");
2415                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2416                                yrgb_srcH, yrgb_dstH);
2417                 }
2418         }
2419         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2420             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2421             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2422
2423         /*SCALE FACTOR */
2424
2425         /*(1.1)YRGB HOR SCALE FACTOR */
2426         switch (win->yrgb_hor_scl_mode) {
2427         case SCALE_NONE:
2428                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2429                 break;
2430         case SCALE_UP:
2431                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2432                 break;
2433         case SCALE_DOWN:
2434                 switch (win->yrgb_hsd_mode) {
2435                 case SCALE_DOWN_BIL:
2436                         yrgb_xscl_factor =
2437                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2438                         break;
2439                 case SCALE_DOWN_AVG:
2440                         yrgb_xscl_factor =
2441                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2442                         break;
2443                 default:
2444                         pr_info(
2445                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2446                                win->yrgb_hsd_mode);
2447                         break;
2448                 }
2449                 break;
2450         default:
2451                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2452                         __func__, win->yrgb_hor_scl_mode);
2453                 break;
2454         }                       /*win->yrgb_hor_scl_mode */
2455
2456         /*(1.2)YRGB VER SCALE FACTOR */
2457         switch (win->yrgb_ver_scl_mode) {
2458         case SCALE_NONE:
2459                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2460                 break;
2461         case SCALE_UP:
2462                 switch (win->yrgb_vsu_mode) {
2463                 case SCALE_UP_BIL:
2464                         yrgb_yscl_factor =
2465                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2466                         break;
2467                 case SCALE_UP_BIC:
2468                         if (yrgb_srcH < 3) {
2469                                 pr_err("yrgb_srcH should be");
2470                                 pr_err(" greater than 3 !!!\n");
2471                         }
2472                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2473                                                                 yrgb_dstH);
2474                         break;
2475                 default:
2476                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2477                                 __func__, win->yrgb_vsu_mode);
2478                         break;
2479                 }
2480                 break;
2481         case SCALE_DOWN:
2482                 switch (win->yrgb_vsd_mode) {
2483                 case SCALE_DOWN_BIL:
2484                         yrgb_vscalednmult =
2485                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2486                                                             yrgb_dstH);
2487                         yrgb_yscl_factor =
2488                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2489                                                            yrgb_vscalednmult);
2490                         if (yrgb_yscl_factor >= 0x2000) {
2491                                 pr_err("yrgb_yscl_factor should be ");
2492                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2493                                        yrgb_yscl_factor);
2494                         }
2495                         if (yrgb_vscalednmult == 4) {
2496                                 yrgb_vsd_bil_gt4 = 1;
2497                                 yrgb_vsd_bil_gt2 = 0;
2498                         } else if (yrgb_vscalednmult == 2) {
2499                                 yrgb_vsd_bil_gt4 = 0;
2500                                 yrgb_vsd_bil_gt2 = 1;
2501                         } else {
2502                                 yrgb_vsd_bil_gt4 = 0;
2503                                 yrgb_vsd_bil_gt2 = 0;
2504                         }
2505                         break;
2506                 case SCALE_DOWN_AVG:
2507                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2508                                                                  yrgb_dstH);
2509                         break;
2510                 default:
2511                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2512                                 __func__, win->yrgb_vsd_mode);
2513                         break;
2514                 }               /*win->yrgb_vsd_mode */
2515                 break;
2516         default:
2517                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2518                         __func__, win->yrgb_ver_scl_mode);
2519                 break;
2520         }
2521         win->scale_yrgb_x = yrgb_xscl_factor;
2522         win->scale_yrgb_y = yrgb_yscl_factor;
2523         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2524         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2525         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2526             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2527
2528         /*(2.1)CBCR HOR SCALE FACTOR */
2529         switch (win->cbr_hor_scl_mode) {
2530         case SCALE_NONE:
2531                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2532                 break;
2533         case SCALE_UP:
2534                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2535                 break;
2536         case SCALE_DOWN:
2537                 switch (win->cbr_hsd_mode) {
2538                 case SCALE_DOWN_BIL:
2539                         cbcr_xscl_factor =
2540                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2541                         break;
2542                 case SCALE_DOWN_AVG:
2543                         cbcr_xscl_factor =
2544                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2545                         break;
2546                 default:
2547                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2548                                 __func__, win->cbr_hsd_mode);
2549                         break;
2550                 }
2551                 break;
2552         default:
2553                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2554                         __func__, win->cbr_hor_scl_mode);
2555                 break;
2556         }                       /*win->cbr_hor_scl_mode */
2557
2558         /*(2.2)CBCR VER SCALE FACTOR */
2559         switch (win->cbr_ver_scl_mode) {
2560         case SCALE_NONE:
2561                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2562                 break;
2563         case SCALE_UP:
2564                 switch (win->cbr_vsu_mode) {
2565                 case SCALE_UP_BIL:
2566                         cbcr_yscl_factor =
2567                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2568                         break;
2569                 case SCALE_UP_BIC:
2570                         if (cbcr_srcH < 3) {
2571                                 pr_err("cbcr_srcH should be ");
2572                                 pr_err("greater than 3 !!!\n");
2573                         }
2574                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2575                                                                 cbcr_dstH);
2576                         break;
2577                 default:
2578                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2579                                 __func__, win->cbr_vsu_mode);
2580                         break;
2581                 }
2582                 break;
2583         case SCALE_DOWN:
2584                 switch (win->cbr_vsd_mode) {
2585                 case SCALE_DOWN_BIL:
2586                         cbcr_vscalednmult =
2587                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2588                                                             cbcr_dstH);
2589                         cbcr_yscl_factor =
2590                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2591                                                            cbcr_vscalednmult);
2592                         if (cbcr_yscl_factor >= 0x2000) {
2593                                 pr_err("cbcr_yscl_factor should be less ");
2594                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2595                                        cbcr_yscl_factor);
2596                         }
2597
2598                         if (cbcr_vscalednmult == 4) {
2599                                 cbcr_vsd_bil_gt4 = 1;
2600                                 cbcr_vsd_bil_gt2 = 0;
2601                         } else if (cbcr_vscalednmult == 2) {
2602                                 cbcr_vsd_bil_gt4 = 0;
2603                                 cbcr_vsd_bil_gt2 = 1;
2604                         } else {
2605                                 cbcr_vsd_bil_gt4 = 0;
2606                                 cbcr_vsd_bil_gt2 = 0;
2607                         }
2608                         break;
2609                 case SCALE_DOWN_AVG:
2610                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2611                                                                  cbcr_dstH);
2612                         break;
2613                 default:
2614                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2615                                 __func__, win->cbr_vsd_mode);
2616                         break;
2617                 }
2618                 break;
2619         default:
2620                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2621                         __func__, win->cbr_ver_scl_mode);
2622                 break;
2623         }
2624         win->scale_cbcr_x = cbcr_xscl_factor;
2625         win->scale_cbcr_y = cbcr_yscl_factor;
2626         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2627         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2628
2629         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2630             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2631         return 0;
2632 }
2633
2634 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2635                      struct rk_lcdc_win_area *area)
2636 {
2637         int pos;
2638
2639         if (screen->x_mirror && mirror_en)
2640                 pr_err("not support both win and global mirror\n");
2641
2642         if ((!mirror_en) && (!screen->x_mirror))
2643                 pos = area->xpos + screen->mode.left_margin +
2644                         screen->mode.hsync_len;
2645         else
2646                 pos = screen->mode.xres - area->xpos -
2647                         area->xsize + screen->mode.left_margin +
2648                         screen->mode.hsync_len;
2649
2650         return pos;
2651 }
2652
2653 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2654                      struct rk_lcdc_win_area *area)
2655 {
2656         int pos;
2657
2658         if (screen->y_mirror && mirror_en)
2659                 pr_err("not support both win and global mirror\n");
2660         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2661                 if ((!mirror_en) && (!screen->y_mirror))
2662                         pos = area->ypos + screen->mode.upper_margin +
2663                                 screen->mode.vsync_len;
2664                 else
2665                         pos = screen->mode.yres - area->ypos -
2666                                 area->ysize + screen->mode.upper_margin +
2667                                 screen->mode.vsync_len;
2668         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2669                 pos = area->ypos / 2 + screen->mode.upper_margin +
2670                         screen->mode.vsync_len;
2671                 area->ysize /= 2;
2672         }
2673
2674         return pos;
2675 }
2676
2677 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2678                            struct rk_screen *screen, struct rk_lcdc_win *win)
2679 {
2680         u32 xact, yact, xvir, yvir, xpos, ypos;
2681         u8 fmt_cfg = 0, swap_rb;
2682         char fmt[9] = "NULL";
2683
2684         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2685         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2686
2687         spin_lock(&lcdc_dev->reg_lock);
2688         if (likely(lcdc_dev->clk_on)) {
2689                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2690                 switch (win->area[0].format) {
2691                 case FBDC_RGB_565:
2692                         fmt_cfg = 2;
2693                         swap_rb = 0;
2694                         win->fmt_10 = 0;
2695                         win->area[0].fbdc_fmt_cfg = 0x05;
2696                         break;
2697                 case FBDC_ARGB_888:
2698                         fmt_cfg = 0;
2699                         swap_rb = 0;
2700                         win->fmt_10 = 0;
2701                         win->area[0].fbdc_fmt_cfg = 0x0c;
2702                         break;
2703                 case FBDC_RGBX_888:
2704                         fmt_cfg = 0;
2705                         swap_rb = 0;
2706                         win->fmt_10 = 0;
2707                         win->area[0].fbdc_fmt_cfg = 0x3a;
2708                         break;
2709                 case ARGB888:
2710                         fmt_cfg = 0;
2711                         swap_rb = 0;
2712                         win->fmt_10 = 0;
2713                         break;
2714                 case XBGR888:
2715                 case ABGR888:
2716                         fmt_cfg = 0;
2717                         swap_rb = 1;
2718                         win->fmt_10 = 0;
2719                         break;
2720                 case RGB888:
2721                         fmt_cfg = 1;
2722                         swap_rb = 0;
2723                         win->fmt_10 = 0;
2724                         break;
2725                 case RGB565:
2726                         fmt_cfg = 2;
2727                         swap_rb = 0;
2728                         win->fmt_10 = 0;
2729                         break;
2730                 case YUV422:
2731                         fmt_cfg = 5;
2732                         swap_rb = 0;
2733                         win->fmt_10 = 0;
2734                         break;
2735                 case YUV420:
2736                         fmt_cfg = 4;
2737                         swap_rb = 0;
2738                         win->fmt_10 = 0;
2739                         break;
2740                 case YUV444:
2741                         fmt_cfg = 6;
2742                         swap_rb = 0;
2743                         win->fmt_10 = 0;
2744                         break;
2745                 case YUV422_A:
2746                         fmt_cfg = 5;
2747                         swap_rb = 0;
2748                         win->fmt_10 = 1;
2749                         break;
2750                 case YUV420_A:
2751                         fmt_cfg = 4;
2752                         swap_rb = 0;
2753                         win->fmt_10 = 1;
2754                         break;
2755                 case YUV444_A:
2756                         fmt_cfg = 6;
2757                         swap_rb = 0;
2758                         win->fmt_10 = 1;
2759                         break;
2760                 default:
2761                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2762                                 __func__);
2763                         break;
2764                 }
2765                 win->area[0].fmt_cfg = fmt_cfg;
2766                 win->area[0].swap_rb = swap_rb;
2767                 win->area[0].dsp_stx = xpos;
2768                 win->area[0].dsp_sty = ypos;
2769                 xact = win->area[0].xact;
2770                 yact = win->area[0].yact;
2771                 xvir = win->area[0].xvir;
2772                 yvir = win->area[0].yvir;
2773         }
2774         if (win->area[0].fbdc_en)
2775                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2776         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2777         spin_unlock(&lcdc_dev->reg_lock);
2778
2779         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2780             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2781             xact, yact, win->area[0].xsize);
2782         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2783             win->area[0].ysize, xvir, yvir, xpos, ypos);
2784
2785         return 0;
2786 }
2787
2788
2789 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2790                            struct rk_screen *screen, struct rk_lcdc_win *win)
2791 {
2792         int i;
2793         u8 fmt_cfg, swap_rb;
2794         char fmt[9] = "NULL";
2795
2796         if (win->mirror_en)
2797                 pr_err("win[%d] not support y mirror\n", win->id);
2798         spin_lock(&lcdc_dev->reg_lock);
2799         if (likely(lcdc_dev->clk_on)) {
2800                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2801                 for (i = 0; i < win->area_num; i++) {
2802                         switch (win->area[i].format) {
2803                         case FBDC_RGB_565:
2804                                 fmt_cfg = 2;
2805                                 swap_rb = 0;
2806                                 win->fmt_10 = 0;
2807                                 win->area[0].fbdc_fmt_cfg = 0x05;
2808                                 break;
2809                         case FBDC_ARGB_888:
2810                                 fmt_cfg = 0;
2811                                 swap_rb = 0;
2812                                 win->fmt_10 = 0;
2813                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2814                                 break;
2815                         case FBDC_RGBX_888:
2816                                 fmt_cfg = 0;
2817                                 swap_rb = 0;
2818                                 win->fmt_10 = 0;
2819                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2820                                 break;
2821                         case ARGB888:
2822                                 fmt_cfg = 0;
2823                                 swap_rb = 0;
2824                                 break;
2825                         case XBGR888:
2826                         case ABGR888:
2827                                 fmt_cfg = 0;
2828                                 swap_rb = 1;
2829                                 break;
2830                         case RGB888:
2831                                 fmt_cfg = 1;
2832                                 swap_rb = 0;
2833                                 break;
2834                         case RGB565:
2835                                 fmt_cfg = 2;
2836                                 swap_rb = 0;
2837                                 break;
2838                         default:
2839                                 dev_err(lcdc_dev->driver.dev,
2840                                         "%s:un supported format!\n", __func__);
2841                                 break;
2842                         }
2843                         win->area[i].fmt_cfg = fmt_cfg;
2844                         win->area[i].swap_rb = swap_rb;
2845                         win->area[i].dsp_stx =
2846                                         dsp_x_pos(win->mirror_en, screen,
2847                                                   &win->area[i]);
2848                         win->area[i].dsp_sty =
2849                                         dsp_y_pos(win->mirror_en, screen,
2850                                                   &win->area[i]);
2851
2852                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2853                             get_format_string(win->area[i].format, fmt),
2854                             win->area[i].xsize, win->area[i].ysize,
2855                             win->area[i].xpos, win->area[i].ypos);
2856                 }
2857         }
2858         if (win->area[0].fbdc_en)
2859                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2860         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2861         spin_unlock(&lcdc_dev->reg_lock);
2862         return 0;
2863 }
2864
2865 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2866                        struct rk_screen *screen, struct rk_lcdc_win *win)
2867 {
2868         u32 xact, yact, xvir, yvir, xpos, ypos;
2869         u8 fmt_cfg = 0, swap_rb;
2870         char fmt[9] = "NULL";
2871
2872         xpos = win->area[0].xpos + screen->mode.left_margin +
2873             screen->mode.hsync_len;
2874         ypos = win->area[0].ypos + screen->mode.upper_margin +
2875             screen->mode.vsync_len;
2876
2877         spin_lock(&lcdc_dev->reg_lock);
2878         if (likely(lcdc_dev->clk_on)) {
2879                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2880                 switch (win->area[0].format) {
2881                 case ARGB888:
2882                         fmt_cfg = 0;
2883                         swap_rb = 0;
2884                         break;
2885                 case XBGR888:
2886                 case ABGR888:
2887                         fmt_cfg = 0;
2888                         swap_rb = 1;
2889                         break;
2890                 case RGB888:
2891                         fmt_cfg = 1;
2892                         swap_rb = 0;
2893                         break;
2894                 case RGB565:
2895                         fmt_cfg = 2;
2896                         swap_rb = 0;
2897                         break;
2898                 default:
2899                         dev_err(lcdc_dev->driver.dev,
2900                                 "%s:un supported format!\n", __func__);
2901                         break;
2902                 }
2903                 win->area[0].fmt_cfg = fmt_cfg;
2904                 win->area[0].swap_rb = swap_rb;
2905                 win->area[0].dsp_stx = xpos;
2906                 win->area[0].dsp_sty = ypos;
2907                 xact = win->area[0].xact;
2908                 yact = win->area[0].yact;
2909                 xvir = win->area[0].xvir;
2910                 yvir = win->area[0].yvir;
2911         }
2912         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2913         spin_unlock(&lcdc_dev->reg_lock);
2914
2915         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2916             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2917             xact, yact, win->area[0].xsize);
2918         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2919             win->area[0].ysize, xvir, yvir, xpos, ypos);
2920         return 0;
2921 }
2922
2923 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2924 {
2925         struct lcdc_device *lcdc_dev =
2926             container_of(dev_drv, struct lcdc_device, driver);
2927         struct rk_lcdc_win *win = NULL;
2928         struct rk_screen *screen = dev_drv->cur_screen;
2929
2930         win = dev_drv->win[win_id];
2931         switch (win_id) {
2932         case 0:
2933                 win_0_1_set_par(lcdc_dev, screen, win);
2934                 break;
2935         case 1:
2936                 win_0_1_set_par(lcdc_dev, screen, win);
2937                 break;
2938         case 2:
2939                 win_2_3_set_par(lcdc_dev, screen, win);
2940                 break;
2941         case 3:
2942                 win_2_3_set_par(lcdc_dev, screen, win);
2943                 break;
2944         case 4:
2945                 hwc_set_par(lcdc_dev, screen, win);
2946                 break;
2947         default:
2948                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2949                 break;
2950         }
2951         return 0;
2952 }
2953
2954 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2955                              unsigned long arg, int win_id)
2956 {
2957         struct lcdc_device *lcdc_dev =
2958             container_of(dev_drv, struct lcdc_device, driver);
2959         u32 panel_size[2];
2960         void __user *argp = (void __user *)arg;
2961         struct color_key_cfg clr_key_cfg;
2962
2963         switch (cmd) {
2964         case RK_FBIOGET_PANEL_SIZE:
2965                 panel_size[0] = lcdc_dev->screen->mode.xres;
2966                 panel_size[1] = lcdc_dev->screen->mode.yres;
2967                 if (copy_to_user(argp, panel_size, 8))
2968                         return -EFAULT;
2969                 break;
2970         case RK_FBIOPUT_COLOR_KEY_CFG:
2971                 if (copy_from_user(&clr_key_cfg, argp,
2972                                    sizeof(struct color_key_cfg)))
2973                         return -EFAULT;
2974                 rk3368_lcdc_clr_key_cfg(dev_drv);
2975                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2976                             clr_key_cfg.win0_color_key_cfg);
2977                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2978                             clr_key_cfg.win1_color_key_cfg);
2979                 break;
2980
2981         default:
2982                 break;
2983         }
2984         return 0;
2985 }
2986
2987 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2988 {
2989         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2990                                                     struct lcdc_device, driver);
2991         /*struct device_node *backlight;*/
2992
2993         if (lcdc_dev->backlight)
2994                 return 0;
2995 #if 0
2996         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2997         if (backlight) {
2998                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2999                 if (!lcdc_dev->backlight)
3000                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3001         } else {
3002                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3003         }
3004 #endif
3005         return 0;
3006 }
3007
3008 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3009 {
3010         struct lcdc_device *lcdc_dev =
3011             container_of(dev_drv, struct lcdc_device, driver);
3012         if (dev_drv->suspend_flag)
3013                 return 0;
3014         /* close the backlight */
3015         /*rk3368_lcdc_get_backlight_device(dev_drv);
3016         if (lcdc_dev->backlight) {
3017                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3018                 backlight_update_status(lcdc_dev->backlight);
3019         }*/
3020
3021         dev_drv->suspend_flag = 1;
3022         flush_kthread_worker(&dev_drv->update_regs_worker);
3023
3024         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3025                 dev_drv->trsm_ops->disable();
3026
3027         spin_lock(&lcdc_dev->reg_lock);
3028         if (likely(lcdc_dev->clk_on)) {
3029                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3030                              v_DSP_BLANK_EN(1));
3031                 lcdc_msk_reg(lcdc_dev,
3032                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3033                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3034                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3035                              v_DSP_OUT_ZERO(1));
3036                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3037                 lcdc_cfg_done(lcdc_dev);
3038
3039                 if (dev_drv->iommu_enabled) {
3040                         if (dev_drv->mmu_dev)
3041                                 rockchip_iovmm_deactivate(dev_drv->dev);
3042                 }
3043
3044                 spin_unlock(&lcdc_dev->reg_lock);
3045         } else {
3046                 spin_unlock(&lcdc_dev->reg_lock);
3047                 return 0;
3048         }
3049         rk3368_lcdc_clk_disable(lcdc_dev);
3050         rk_disp_pwr_disable(dev_drv);
3051         return 0;
3052 }
3053
3054 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3055 {
3056         struct lcdc_device *lcdc_dev =
3057             container_of(dev_drv, struct lcdc_device, driver);
3058
3059         if (!dev_drv->suspend_flag)
3060                 return 0;
3061         rk_disp_pwr_enable(dev_drv);
3062         dev_drv->suspend_flag = 0;
3063
3064         if (1/*lcdc_dev->atv_layer_cnt*/) {
3065                 rk3368_lcdc_clk_enable(lcdc_dev);
3066                 rk3368_lcdc_reg_restore(lcdc_dev);
3067
3068                 spin_lock(&lcdc_dev->reg_lock);
3069                 if (dev_drv->cur_screen->dsp_lut)
3070                         rk3368_lcdc_set_lut(dev_drv,
3071                                             dev_drv->cur_screen->dsp_lut);
3072                 if (dev_drv->cur_screen->cabc_lut)
3073                         rk3368_set_cabc_lut(dev_drv,
3074                                             dev_drv->cur_screen->cabc_lut);
3075
3076                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3077                              v_DSP_OUT_ZERO(0));
3078                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3079                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3080                              v_DSP_BLANK_EN(0));
3081                 lcdc_cfg_done(lcdc_dev);
3082
3083                 if (dev_drv->iommu_enabled) {
3084                         if (dev_drv->mmu_dev)
3085                                 rockchip_iovmm_activate(dev_drv->dev);
3086                 }
3087
3088                 spin_unlock(&lcdc_dev->reg_lock);
3089         }
3090
3091         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3092                 dev_drv->trsm_ops->enable();
3093
3094         return 0;
3095 }
3096
3097 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3098                              int win_id, int blank_mode)
3099 {
3100         switch (blank_mode) {
3101         case FB_BLANK_UNBLANK:
3102                 rk3368_lcdc_early_resume(dev_drv);
3103                 break;
3104         case FB_BLANK_NORMAL:
3105                 rk3368_lcdc_early_suspend(dev_drv);
3106                 break;
3107         default:
3108                 rk3368_lcdc_early_suspend(dev_drv);
3109                 break;
3110         }
3111
3112         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3113
3114         return 0;
3115 }
3116
3117 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3118 {
3119         return 0;
3120 }
3121
3122 /*overlay will be do at regupdate*/
3123 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3124                                bool set)
3125 {
3126         struct lcdc_device *lcdc_dev =
3127             container_of(dev_drv, struct lcdc_device, driver);
3128         struct rk_lcdc_win *win = NULL;
3129         int i, ovl;
3130         unsigned int mask, val;
3131         int z_order_num = 0;
3132         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3133
3134         if (swap == 0) {
3135                 for (i = 0; i < 4; i++) {
3136                         win = dev_drv->win[i];
3137                         if (win->state == 1)
3138                                 z_order_num++;
3139                 }
3140                 for (i = 0; i < 4; i++) {
3141                         win = dev_drv->win[i];
3142                         if (win->state == 0)
3143                                 win->z_order = z_order_num++;
3144                         switch (win->z_order) {
3145                         case 0:
3146                                 layer0_sel = win->id;
3147                                 break;
3148                         case 1:
3149                                 layer1_sel = win->id;
3150                                 break;
3151                         case 2:
3152                                 layer2_sel = win->id;
3153                                 break;
3154                         case 3:
3155                                 layer3_sel = win->id;
3156                                 break;
3157                         default:
3158                                 break;
3159                         }
3160                 }
3161         } else {
3162                 layer0_sel = swap % 10;
3163                 layer1_sel = swap / 10 % 10;
3164                 layer2_sel = swap / 100 % 10;
3165                 layer3_sel = swap / 1000;
3166         }
3167
3168         spin_lock(&lcdc_dev->reg_lock);
3169         if (lcdc_dev->clk_on) {
3170                 if (set) {
3171                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3172                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3173                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3174                             v_DSP_LAYER1_SEL(layer1_sel) |
3175                             v_DSP_LAYER2_SEL(layer2_sel) |
3176                             v_DSP_LAYER3_SEL(layer3_sel);
3177                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3178                 } else {
3179                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3180                                                    m_DSP_LAYER0_SEL);
3181                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3182                                                    m_DSP_LAYER1_SEL);
3183                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3184                                                    m_DSP_LAYER2_SEL);
3185                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3186                                                    m_DSP_LAYER3_SEL);
3187                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3188                             layer1_sel * 10 + layer0_sel;
3189                 }
3190         } else {
3191                 ovl = -EPERM;
3192         }
3193         spin_unlock(&lcdc_dev->reg_lock);
3194
3195         return ovl;
3196 }
3197
3198 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3199 {
3200         if (!fmt)
3201                 return NULL;
3202
3203         switch (format) {
3204         case 0:
3205                 strcpy(fmt, "ARGB888");
3206                 break;
3207         case 1:
3208                 strcpy(fmt, "RGB888");
3209                 break;
3210         case 2:
3211                 strcpy(fmt, "RGB565");
3212                 break;
3213         case 4:
3214                 strcpy(fmt, "YCbCr420");
3215                 break;
3216         case 5:
3217                 strcpy(fmt, "YCbCr422");
3218                 break;
3219         case 6:
3220                 strcpy(fmt, "YCbCr444");
3221                 break;
3222         default:
3223                 strcpy(fmt, "invalid\n");
3224                 break;
3225         }
3226         return fmt;
3227 }
3228 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3229                                          char *buf, int win_id)
3230 {
3231         struct lcdc_device *lcdc_dev =
3232             container_of(dev_drv, struct lcdc_device, driver);
3233         struct rk_screen *screen = dev_drv->cur_screen;
3234         u16 hsync_len = screen->mode.hsync_len;
3235         u16 left_margin = screen->mode.left_margin;
3236         u16 vsync_len = screen->mode.vsync_len;
3237         u16 upper_margin = screen->mode.upper_margin;
3238         u32 h_pw_bp = hsync_len + left_margin;
3239         u32 v_pw_bp = vsync_len + upper_margin;
3240         u32 fmt_id;
3241         char format_w0[9] = "NULL";
3242         char format_w1[9] = "NULL";
3243         char format_w2_0[9] = "NULL";
3244         char format_w2_1[9] = "NULL";
3245         char format_w2_2[9] = "NULL";
3246         char format_w2_3[9] = "NULL";
3247         char format_w3_0[9] = "NULL";
3248         char format_w3_1[9] = "NULL";
3249         char format_w3_2[9] = "NULL";
3250         char format_w3_3[9] = "NULL";
3251         char dsp_buf[100];
3252         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3253         u32 y_factor, uv_factor;
3254         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3255         u8 w0_state, w1_state, w2_state, w3_state;
3256         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3257         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3258
3259         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3260         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3261         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3262         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3263         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3264         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3265
3266         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3267         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3268         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3269         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3270         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3271         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3272         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3273
3274         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3275         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3276         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3277         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3278         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3279         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3280         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3281         u32 dclk_freq;
3282         int size = 0;
3283
3284         dclk_freq = screen->mode.pixclock;
3285         /*rk3368_lcdc_reg_dump(dev_drv); */
3286
3287         spin_lock(&lcdc_dev->reg_lock);
3288         if (lcdc_dev->clk_on) {
3289                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3290                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3291                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3292                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3293                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3294                 /*WIN0 */
3295                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3296                 w0_state = win_ctrl & m_WIN0_EN;
3297                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3298                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3299                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3300                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3301                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3302                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3303                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3304                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3305                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3306                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3307                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3308                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3309                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3310                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3311                 if (w0_state) {
3312                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3313                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3314                 }
3315                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3316                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3317                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3318                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3319
3320                 /*WIN1 */
3321                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3322                 w1_state = win_ctrl & m_WIN1_EN;
3323                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3324                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3325                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3326                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3327                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3328                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3329                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3330                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3331                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3332                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3333                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3334                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3335                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3336                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3337                 if (w1_state) {
3338                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3339                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3340                 }
3341                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3342                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3343                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3344                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3345                 /*WIN2 */
3346                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3347                 w2_state = win_ctrl & m_WIN2_EN;
3348                 w2_0_state = (win_ctrl & 0x10) >> 4;
3349                 w2_1_state = (win_ctrl & 0x100) >> 8;
3350                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3351                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3352                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3353                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3354                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3355                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3356                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3357                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3358
3359                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3360                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3361                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3362                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3363                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3364                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3365                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3366                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3367
3368                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3369                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3370                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3371                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3372                 if (w2_0_state) {
3373                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3374                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3375                 }
3376                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3377                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3378                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3379                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3380                 if (w2_1_state) {
3381                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3382                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3383                 }
3384                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3385                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3386                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3387                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3388                 if (w2_2_state) {
3389                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3390                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3391                 }
3392                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3393                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3394                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3395                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3396                 if (w2_3_state) {
3397                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3398                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3399                 }
3400
3401                 /*WIN3 */
3402                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3403                 w3_state = win_ctrl & m_WIN3_EN;
3404                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3405                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3406                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3407                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3408                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3409                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3410                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3411                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3412                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3413                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3414                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3415                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3416                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3417                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3418                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3419                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3420                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3421                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3422                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3423                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3424                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3425                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3426                 if (w3_0_state) {
3427                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3428                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3429                 }
3430
3431                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3432                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3433                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3434                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3435                 if (w3_1_state) {
3436                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3437                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3438                 }
3439
3440                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3441                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3442                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3443                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3444                 if (w3_2_state) {
3445                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3446                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3447                 }
3448
3449                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3450                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3451                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3452                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3453                 if (w3_3_state) {
3454                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3455                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3456                 }
3457
3458         } else {
3459                 spin_unlock(&lcdc_dev->reg_lock);
3460                 return -EPERM;
3461         }
3462         spin_unlock(&lcdc_dev->reg_lock);
3463         size += snprintf(dsp_buf, 80,
3464                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3465                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3466         strcat(buf, dsp_buf);
3467         memset(dsp_buf, 0, sizeof(dsp_buf));
3468         /*win0*/
3469         size += snprintf(dsp_buf, 80,
3470                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3471                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3472         strcat(buf, dsp_buf);
3473         memset(dsp_buf, 0, sizeof(dsp_buf));
3474
3475         size += snprintf(dsp_buf, 80,
3476                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3477                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3478         strcat(buf, dsp_buf);
3479         memset(dsp_buf, 0, sizeof(dsp_buf));
3480
3481         size += snprintf(dsp_buf, 80,
3482                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3483                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3484         strcat(buf, dsp_buf);
3485         memset(dsp_buf, 0, sizeof(dsp_buf));
3486
3487         size += snprintf(dsp_buf, 80,
3488                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3489                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3490                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3491         strcat(buf, dsp_buf);
3492         memset(dsp_buf, 0, sizeof(dsp_buf));
3493
3494         /*win1*/
3495         size += snprintf(dsp_buf, 80,
3496                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3497                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3498         strcat(buf, dsp_buf);
3499         memset(dsp_buf, 0, sizeof(dsp_buf));
3500
3501         size += snprintf(dsp_buf, 80,
3502                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3503                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3504         strcat(buf, dsp_buf);
3505         memset(dsp_buf, 0, sizeof(dsp_buf));
3506
3507         size += snprintf(dsp_buf, 80,
3508                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3509                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3510         strcat(buf, dsp_buf);
3511         memset(dsp_buf, 0, sizeof(dsp_buf));
3512
3513         size += snprintf(dsp_buf, 80,
3514                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3515                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3516                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3517         strcat(buf, dsp_buf);
3518         memset(dsp_buf, 0, sizeof(dsp_buf));
3519
3520         /*win2*/
3521         size += snprintf(dsp_buf, 80,
3522                  "win2:\n  state:%d\n",
3523                  w2_state);
3524         strcat(buf, dsp_buf);
3525         memset(dsp_buf, 0, sizeof(dsp_buf));
3526         /*area 0*/
3527         size += snprintf(dsp_buf, 80,
3528                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3529                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3530         strcat(buf, dsp_buf);
3531         memset(dsp_buf, 0, sizeof(dsp_buf));
3532         size += snprintf(dsp_buf, 80,
3533                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3534                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3535                  lcdc_readl(lcdc_dev, WIN2_MST0));
3536         strcat(buf, dsp_buf);
3537         memset(dsp_buf, 0, sizeof(dsp_buf));
3538
3539         /*area 1*/
3540         size += snprintf(dsp_buf, 80,
3541                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3542                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3543         strcat(buf, dsp_buf);
3544         memset(dsp_buf, 0, sizeof(dsp_buf));
3545         size += snprintf(dsp_buf, 80,
3546                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3547                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3548                  lcdc_readl(lcdc_dev, WIN2_MST1));
3549         strcat(buf, dsp_buf);
3550         memset(dsp_buf, 0, sizeof(dsp_buf));
3551
3552         /*area 2*/
3553         size += snprintf(dsp_buf, 80,
3554                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3555                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3556         strcat(buf, dsp_buf);
3557         memset(dsp_buf, 0, sizeof(dsp_buf));
3558         size += snprintf(dsp_buf, 80,
3559                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3560                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3561                  lcdc_readl(lcdc_dev, WIN2_MST2));
3562         strcat(buf, dsp_buf);
3563         memset(dsp_buf, 0, sizeof(dsp_buf));
3564
3565         /*area 3*/
3566         size += snprintf(dsp_buf, 80,
3567                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3568                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3569         strcat(buf, dsp_buf);
3570         memset(dsp_buf, 0, sizeof(dsp_buf));
3571         size += snprintf(dsp_buf, 80,
3572                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3573                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3574                  lcdc_readl(lcdc_dev, WIN2_MST3));
3575         strcat(buf, dsp_buf);
3576         memset(dsp_buf, 0, sizeof(dsp_buf));
3577
3578         /*win3*/
3579         size += snprintf(dsp_buf, 80,
3580                  "win3:\n  state:%d\n",
3581                  w3_state);
3582         strcat(buf, dsp_buf);
3583         memset(dsp_buf, 0, sizeof(dsp_buf));
3584         /*area 0*/
3585         size += snprintf(dsp_buf, 80,
3586                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3587                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3588         strcat(buf, dsp_buf);
3589         memset(dsp_buf, 0, sizeof(dsp_buf));
3590         size += snprintf(dsp_buf, 80,
3591                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3592                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3593                  lcdc_readl(lcdc_dev, WIN3_MST0));
3594         strcat(buf, dsp_buf);
3595         memset(dsp_buf, 0, sizeof(dsp_buf));
3596
3597         /*area 1*/
3598         size += snprintf(dsp_buf, 80,
3599                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3600                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3601         strcat(buf, dsp_buf);
3602         memset(dsp_buf, 0, sizeof(dsp_buf));
3603         size += snprintf(dsp_buf, 80,
3604                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3605                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3606                  lcdc_readl(lcdc_dev, WIN3_MST1));
3607         strcat(buf, dsp_buf);
3608         memset(dsp_buf, 0, sizeof(dsp_buf));
3609
3610         /*area 2*/
3611         size += snprintf(dsp_buf, 80,
3612                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3613                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3614         strcat(buf, dsp_buf);
3615         memset(dsp_buf, 0, sizeof(dsp_buf));
3616         size += snprintf(dsp_buf, 80,
3617                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3618                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3619                  lcdc_readl(lcdc_dev, WIN3_MST2));
3620         strcat(buf, dsp_buf);
3621         memset(dsp_buf, 0, sizeof(dsp_buf));
3622
3623         /*area 3*/
3624         size += snprintf(dsp_buf, 80,
3625                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3626                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3627         strcat(buf, dsp_buf);
3628         memset(dsp_buf, 0, sizeof(dsp_buf));
3629         size += snprintf(dsp_buf, 80,
3630                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3631                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3632                  lcdc_readl(lcdc_dev, WIN3_MST3));
3633         strcat(buf, dsp_buf);
3634         memset(dsp_buf, 0, sizeof(dsp_buf));
3635
3636         return size;
3637 }
3638
3639 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3640                                bool set)
3641 {
3642         struct lcdc_device *lcdc_dev =
3643             container_of(dev_drv, struct lcdc_device, driver);
3644         struct rk_screen *screen = dev_drv->cur_screen;
3645         u64 ft = 0;
3646         u32 dotclk;
3647         int ret;
3648         u32 pixclock;
3649         u32 x_total, y_total;
3650
3651         if (set) {
3652                 if (fps == 0) {
3653                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3654                         return 0;
3655                 }
3656                 ft = div_u64(1000000000000llu, fps);
3657                 x_total =
3658                     screen->mode.upper_margin + screen->mode.lower_margin +
3659                     screen->mode.yres + screen->mode.vsync_len;
3660                 y_total =
3661                     screen->mode.left_margin + screen->mode.right_margin +
3662                     screen->mode.xres + screen->mode.hsync_len;
3663                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3664                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3665                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3666         }
3667
3668         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3669         lcdc_dev->pixclock = pixclock;
3670         dev_drv->pixclock = lcdc_dev->pixclock;
3671         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3672         screen->ft = 1000 / fps;        /*one frame time in ms */
3673
3674         if (set)
3675                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3676                          clk_get_rate(lcdc_dev->dclk), fps);
3677
3678         return fps;
3679 }
3680
3681 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3682 {
3683         mutex_lock(&dev_drv->fb_win_id_mutex);
3684         if (order == FB_DEFAULT_ORDER)
3685                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3686         dev_drv->fb4_win_id = order / 10000;
3687         dev_drv->fb3_win_id = (order / 1000) % 10;
3688         dev_drv->fb2_win_id = (order / 100) % 10;
3689         dev_drv->fb1_win_id = (order / 10) % 10;
3690         dev_drv->fb0_win_id = order % 10;
3691         mutex_unlock(&dev_drv->fb_win_id_mutex);
3692
3693         return 0;
3694 }
3695
3696 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3697                                   const char *id)
3698 {
3699         int win_id = 0;
3700
3701         mutex_lock(&dev_drv->fb_win_id_mutex);
3702         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3703                 win_id = dev_drv->fb0_win_id;
3704         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3705                 win_id = dev_drv->fb1_win_id;
3706         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3707                 win_id = dev_drv->fb2_win_id;
3708         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3709                 win_id = dev_drv->fb3_win_id;
3710         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3711                 win_id = dev_drv->fb4_win_id;
3712         mutex_unlock(&dev_drv->fb_win_id_mutex);
3713
3714         return win_id;
3715 }
3716
3717 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3718 {
3719         struct lcdc_device *lcdc_dev =
3720             container_of(dev_drv, struct lcdc_device, driver);
3721         int i;
3722         unsigned int mask, val;
3723         struct rk_lcdc_win *win = NULL;
3724
3725         spin_lock(&lcdc_dev->reg_lock);
3726         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3727                      v_STANDBY_EN(lcdc_dev->standby));
3728         for (i = 0; i < 4; i++) {
3729                 win = dev_drv->win[i];
3730                 if ((win->state == 0) && (win->last_state == 1)) {
3731                         switch (win->id) {
3732                         case 0:
3733                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3734                                    for rk3288 to fix hw bug? */
3735                                 mask = m_WIN0_EN;
3736                                 val = v_WIN0_EN(0);
3737                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3738                                 break;
3739                         case 1:
3740                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3741                                    for rk3288 to fix hw bug? */
3742                                 mask = m_WIN1_EN;
3743                                 val = v_WIN1_EN(0);
3744                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3745                                 break;
3746                         case 2:
3747                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3748                                     m_WIN2_MST1_EN |
3749                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3750                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3751                                     v_WIN2_MST1_EN(0) |
3752                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3753                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3754                                 break;
3755                         case 3:
3756                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3757                                     m_WIN3_MST1_EN |
3758                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3759                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3760                                     v_WIN3_MST1_EN(0) |
3761                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3762                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3763                                 break;
3764                         case 4:
3765                                 mask = m_HWC_EN;
3766                                 val = v_HWC_EN(0);
3767                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3768                                 break;
3769                         default:
3770                                 break;
3771                         }
3772                 }
3773                 win->last_state = win->state;
3774         }
3775         lcdc_cfg_done(lcdc_dev);
3776         spin_unlock(&lcdc_dev->reg_lock);
3777         return 0;
3778 }
3779
3780 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3781 {
3782         struct lcdc_device *lcdc_dev =
3783             container_of(dev_drv, struct lcdc_device, driver);
3784         spin_lock(&lcdc_dev->reg_lock);
3785         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3786                      v_DIRECT_PATH_EN(open));
3787         lcdc_cfg_done(lcdc_dev);
3788         spin_unlock(&lcdc_dev->reg_lock);
3789         return 0;
3790 }
3791
3792 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3793 {
3794         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3795                                                     struct lcdc_device, driver);
3796         spin_lock(&lcdc_dev->reg_lock);
3797         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3798                      v_DIRECT_PATCH_SEL(win_id));
3799         lcdc_cfg_done(lcdc_dev);
3800         spin_unlock(&lcdc_dev->reg_lock);
3801         return 0;
3802 }
3803
3804 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3805 {
3806         struct lcdc_device *lcdc_dev =
3807             container_of(dev_drv, struct lcdc_device, driver);
3808         int ovl;
3809
3810         spin_lock(&lcdc_dev->reg_lock);
3811         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3812         spin_unlock(&lcdc_dev->reg_lock);
3813         return ovl;
3814 }
3815
3816 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3817                                       int enable)
3818 {
3819         struct lcdc_device *lcdc_dev =
3820             container_of(dev_drv, struct lcdc_device, driver);
3821         if (enable)
3822                 enable_irq(lcdc_dev->irq);
3823         else
3824                 disable_irq(lcdc_dev->irq);
3825         return 0;
3826 }
3827
3828 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3829 {
3830         struct lcdc_device *lcdc_dev =
3831             container_of(dev_drv, struct lcdc_device, driver);
3832         u32 int_reg;
3833         int ret;
3834
3835         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3836                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3837                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3838                         lcdc_dev->driver.frame_time.last_framedone_t =
3839                             lcdc_dev->driver.frame_time.framedone_t;
3840                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3841                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3842                                      m_LINE_FLAG0_INTR_CLR,
3843                                      v_LINE_FLAG0_INTR_CLR(1));
3844                         ret = RK_LF_STATUS_FC;
3845                 } else {
3846                         ret = RK_LF_STATUS_FR;
3847                 }
3848         } else {
3849                 ret = RK_LF_STATUS_NC;
3850         }
3851
3852         return ret;
3853 }
3854
3855 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3856                                     unsigned int *dsp_addr)
3857 {
3858         struct lcdc_device *lcdc_dev =
3859             container_of(dev_drv, struct lcdc_device, driver);
3860         spin_lock(&lcdc_dev->reg_lock);
3861         if (lcdc_dev->clk_on) {
3862                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3863                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3864                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3865                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3866         }
3867         spin_unlock(&lcdc_dev->reg_lock);
3868         return 0;
3869 }
3870
3871 static struct lcdc_cabc_mode cabc_mode[4] = {
3872       /* calc,     up,     down,   global_limit   */
3873         {5,    256,  256,   256},  /*mode 1   0*/
3874         {5,    258,  253,   277},  /*mode 2   15%*/
3875         {5,    259,  252,   330},  /*mode 3   40%*/
3876         {5,    267,  244,   400},  /*mode 4   60%*/
3877 };
3878
3879 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3880 {
3881         struct lcdc_device *lcdc_dev =
3882             container_of(dev_drv, struct lcdc_device, driver);
3883         struct rk_screen *screen = dev_drv->cur_screen;
3884         u32 total_pixel, calc_pixel, stage_up, stage_down;
3885         u32 pixel_num, global_su;
3886         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
3887         u32 mask = 0, val = 0, cabc_en = 0;
3888         int *cabc_lut = NULL;
3889
3890         if (!screen->cabc_lut) {
3891                 pr_err("screen cabc lut not config, so not open cabc\n");
3892                 return 0;
3893         } else {
3894                 cabc_lut = screen->cabc_lut;
3895         }
3896
3897         dev_drv->cabc_mode = mode;
3898         cabc_en = (mode > 0) ? 1 : 0;
3899
3900         if (cabc_en == 0) {
3901                 spin_lock(&lcdc_dev->reg_lock);
3902                 if (lcdc_dev->clk_on) {
3903                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3904                                      m_CABC_EN, v_CABC_EN(0));
3905                         lcdc_cfg_done(lcdc_dev);
3906                 }
3907                 spin_unlock(&lcdc_dev->reg_lock);
3908                 return 0;
3909         }
3910
3911         total_pixel = screen->mode.xres * screen->mode.yres;
3912         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3913         calc_pixel = (total_pixel * pixel_num) / 1000;
3914         stage_up = cabc_mode[mode - 1].stage_up;
3915         stage_down = cabc_mode[mode - 1].stage_down;
3916         global_su = cabc_mode[mode - 1].global_su;
3917
3918         stage_up_rec = 256 * 256 / stage_up;
3919         stage_down_rec = 256 * 256 / stage_down;
3920         global_su_rec = (256 * 256 / global_su) - 1;
3921         gamma_global_su_rec = cabc_lut[global_su_rec];
3922
3923         spin_lock(&lcdc_dev->reg_lock);
3924         if (lcdc_dev->clk_on) {
3925                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3926                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3927                         v_CABC_EN(cabc_en);
3928                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3929
3930                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3931                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
3932                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3933
3934                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3935                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3936                 val = v_CABC_STAGE_UP(stage_up) |
3937                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3938                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3939                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
3940                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3941
3942                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3943                     m_CABC_GLOBAL_SU;
3944                 val = v_CABC_STAGE_DOWN(stage_down) |
3945                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3946                     v_CABC_GLOBAL_SU(global_su);
3947                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3948                 lcdc_cfg_done(lcdc_dev);
3949         }
3950         spin_unlock(&lcdc_dev->reg_lock);
3951
3952         return 0;
3953 }
3954
3955 /*
3956         a:[-30~0]:
3957             sin_hue = sin(a)*256 +0x100;
3958             cos_hue = cos(a)*256;
3959         a:[0~30]
3960             sin_hue = sin(a)*256;
3961             cos_hue = cos(a)*256;
3962 */
3963 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3964                                     bcsh_hue_mode mode)
3965 {
3966         struct lcdc_device *lcdc_dev =
3967             container_of(dev_drv, struct lcdc_device, driver);
3968         u32 val;
3969
3970         spin_lock(&lcdc_dev->reg_lock);
3971         if (lcdc_dev->clk_on) {
3972                 val = lcdc_readl(lcdc_dev, BCSH_H);
3973                 switch (mode) {
3974                 case H_SIN:
3975                         val &= m_BCSH_SIN_HUE;
3976                         break;
3977                 case H_COS:
3978                         val &= m_BCSH_COS_HUE;
3979                         val >>= 16;
3980                         break;
3981                 default:
3982                         break;
3983                 }
3984         }
3985         spin_unlock(&lcdc_dev->reg_lock);
3986
3987         return val;
3988 }
3989
3990 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3991                                     int sin_hue, int cos_hue)
3992 {
3993         struct lcdc_device *lcdc_dev =
3994             container_of(dev_drv, struct lcdc_device, driver);
3995         u32 mask, val;
3996
3997         spin_lock(&lcdc_dev->reg_lock);
3998         if (lcdc_dev->clk_on) {
3999                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4000                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4001                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4002                 lcdc_cfg_done(lcdc_dev);
4003         }
4004         spin_unlock(&lcdc_dev->reg_lock);
4005
4006         return 0;
4007 }
4008
4009 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4010                                     bcsh_bcs_mode mode, int value)
4011 {
4012         struct lcdc_device *lcdc_dev =
4013             container_of(dev_drv, struct lcdc_device, driver);
4014         u32 mask, val;
4015
4016         spin_lock(&lcdc_dev->reg_lock);
4017         if (lcdc_dev->clk_on) {
4018                 switch (mode) {
4019                 case BRIGHTNESS:
4020                         /*from 0 to 255,typical is 128 */
4021                         if (value < 0x80)
4022                                 value += 0x80;
4023                         else if (value >= 0x80)
4024                                 value = value - 0x80;
4025                         mask = m_BCSH_BRIGHTNESS;
4026                         val = v_BCSH_BRIGHTNESS(value);
4027                         break;
4028                 case CONTRAST:
4029                         /*from 0 to 510,typical is 256 */
4030                         mask = m_BCSH_CONTRAST;
4031                         val = v_BCSH_CONTRAST(value);
4032                         break;
4033                 case SAT_CON:
4034                         /*from 0 to 1015,typical is 256 */
4035                         mask = m_BCSH_SAT_CON;
4036                         val = v_BCSH_SAT_CON(value);
4037                         break;
4038                 default:
4039                         break;
4040                 }
4041                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4042                 lcdc_cfg_done(lcdc_dev);
4043         }
4044         spin_unlock(&lcdc_dev->reg_lock);
4045         return val;
4046 }
4047
4048 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4049                                     bcsh_bcs_mode mode)
4050 {
4051         struct lcdc_device *lcdc_dev =
4052             container_of(dev_drv, struct lcdc_device, driver);
4053         u32 val;
4054
4055         spin_lock(&lcdc_dev->reg_lock);
4056         if (lcdc_dev->clk_on) {
4057                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4058                 switch (mode) {
4059                 case BRIGHTNESS:
4060                         val &= m_BCSH_BRIGHTNESS;
4061                         if (val > 0x80)
4062                                 val -= 0x80;
4063                         else
4064                                 val += 0x80;
4065                         break;
4066                 case CONTRAST:
4067                         val &= m_BCSH_CONTRAST;
4068                         val >>= 8;
4069                         break;
4070                 case SAT_CON:
4071                         val &= m_BCSH_SAT_CON;
4072                         val >>= 20;
4073                         break;
4074                 default:
4075                         break;
4076                 }
4077         }
4078         spin_unlock(&lcdc_dev->reg_lock);
4079         return val;
4080 }
4081
4082 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4083 {
4084         struct lcdc_device *lcdc_dev =
4085             container_of(dev_drv, struct lcdc_device, driver);
4086         u32 mask, val;
4087
4088         spin_lock(&lcdc_dev->reg_lock);
4089         if (lcdc_dev->clk_on) {
4090                 if (open) {
4091                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4092                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4093                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4094                         dev_drv->bcsh.enable = 1;
4095                 } else {
4096                         mask = m_BCSH_EN;
4097                         val = v_BCSH_EN(0);
4098                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4099                         dev_drv->bcsh.enable = 0;
4100                 }
4101                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4102                 lcdc_cfg_done(lcdc_dev);
4103         }
4104         spin_unlock(&lcdc_dev->reg_lock);
4105         return 0;
4106 }
4107
4108 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4109 {
4110         if (!enable || !dev_drv->bcsh.enable) {
4111                 rk3368_lcdc_open_bcsh(dev_drv, false);
4112                 return 0;
4113         }
4114
4115         if (dev_drv->bcsh.brightness <= 255 ||
4116             dev_drv->bcsh.contrast <= 510 ||
4117             dev_drv->bcsh.sat_con <= 1015 ||
4118             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4119                 rk3368_lcdc_open_bcsh(dev_drv, true);
4120                 if (dev_drv->bcsh.brightness <= 255)
4121                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4122                                                  dev_drv->bcsh.brightness);
4123                 if (dev_drv->bcsh.contrast <= 510)
4124                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4125                                                  dev_drv->bcsh.contrast);
4126                 if (dev_drv->bcsh.sat_con <= 1015)
4127                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4128                                                  dev_drv->bcsh.sat_con);
4129                 if (dev_drv->bcsh.sin_hue <= 511 &&
4130                     dev_drv->bcsh.cos_hue <= 511)
4131                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4132                                                  dev_drv->bcsh.sin_hue,
4133                                                  dev_drv->bcsh.cos_hue);
4134         }
4135         return 0;
4136 }
4137
4138 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4139 {
4140         struct lcdc_device *lcdc_dev =
4141             container_of(dev_drv, struct lcdc_device, driver);
4142
4143         if (enable) {
4144                 spin_lock(&lcdc_dev->reg_lock);
4145                 if (likely(lcdc_dev->clk_on)) {
4146                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4147                                      v_DSP_BLACK_EN(1));
4148                         lcdc_cfg_done(lcdc_dev);
4149                 }
4150                 spin_unlock(&lcdc_dev->reg_lock);
4151         } else {
4152                 spin_lock(&lcdc_dev->reg_lock);
4153                 if (likely(lcdc_dev->clk_on)) {
4154                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4155                                      v_DSP_BLACK_EN(0));
4156
4157                         lcdc_cfg_done(lcdc_dev);
4158                 }
4159                 spin_unlock(&lcdc_dev->reg_lock);
4160         }
4161
4162         return 0;
4163 }
4164
4165
4166 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4167                                        int enable)
4168 {
4169         struct lcdc_device *lcdc_dev =
4170             container_of(dev_drv, struct lcdc_device, driver);
4171
4172         rk3368_lcdc_get_backlight_device(dev_drv);
4173
4174         if (enable) {
4175                 /* close the backlight */
4176                 if (lcdc_dev->backlight) {
4177                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4178                         backlight_update_status(lcdc_dev->backlight);
4179                 }
4180                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4181                         dev_drv->trsm_ops->disable();
4182         } else {
4183                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4184                         dev_drv->trsm_ops->enable();
4185                 msleep(100);
4186                 /* open the backlight */
4187                 if (lcdc_dev->backlight) {
4188                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4189                         backlight_update_status(lcdc_dev->backlight);
4190                 }
4191         }
4192
4193         return 0;
4194 }
4195
4196 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4197         .open = rk3368_lcdc_open,
4198         .win_direct_en = rk3368_lcdc_win_direct_en,
4199         .load_screen = rk3368_load_screen,
4200         .get_dspbuf_info = rk3368_get_dspbuf_info,
4201         .post_dspbuf = rk3368_post_dspbuf,
4202         .set_par = rk3368_lcdc_set_par,
4203         .pan_display = rk3368_lcdc_pan_display,
4204         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4205         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4206         .blank = rk3368_lcdc_blank,
4207         .ioctl = rk3368_lcdc_ioctl,
4208         .suspend = rk3368_lcdc_early_suspend,
4209         .resume = rk3368_lcdc_early_resume,
4210         .get_win_state = rk3368_lcdc_get_win_state,
4211         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4212         .get_disp_info = rk3368_lcdc_get_disp_info,
4213         .fps_mgr = rk3368_lcdc_fps_mgr,
4214         .fb_get_win_id = rk3368_lcdc_get_win_id,
4215         .fb_win_remap = rk3368_fb_win_remap,
4216         .set_dsp_lut = rk3368_lcdc_set_lut,
4217         .set_cabc_lut = rk3368_set_cabc_lut,
4218         .poll_vblank = rk3368_lcdc_poll_vblank,
4219         .dpi_open = rk3368_lcdc_dpi_open,
4220         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4221         .dpi_status = rk3368_lcdc_dpi_status,
4222         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4223         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4224         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4225         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4226         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4227         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4228         .open_bcsh = rk3368_lcdc_open_bcsh,
4229         .dump_reg = rk3368_lcdc_reg_dump,
4230         .cfg_done = rk3368_lcdc_config_done,
4231         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4232         .dsp_black = rk3368_lcdc_dsp_black,
4233         .backlight_close = rk3368_lcdc_backlight_close,
4234         .mmu_en    = rk3368_lcdc_mmu_en,
4235 };
4236
4237 #ifdef LCDC_IRQ_EMPTY_DEBUG
4238 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4239                                  unsigned int intr_status)
4240 {
4241         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4242                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4243                              v_WIN0_EMPTY_INTR_CLR(1));
4244                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4245         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4246                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4247                              v_WIN1_EMPTY_INTR_CLR(1));
4248                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4249         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4250                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4251                              v_WIN2_EMPTY_INTR_CLR(1));
4252                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4253         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4254                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4255                              v_WIN3_EMPTY_INTR_CLR(1));
4256                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4257         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4258                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4259                              v_HWC_EMPTY_INTR_CLR(1));
4260                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4261         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4262                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4263                              v_POST_BUF_EMPTY_INTR_CLR(1));
4264                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4265         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4266                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4267                              v_PWM_GEN_INTR_CLR(1));
4268                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4269         }
4270         return 0;
4271 }
4272 #endif
4273
4274 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4275 {
4276         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4277         ktime_t timestamp = ktime_get();
4278         u32 intr_status;
4279
4280         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4281
4282         if (intr_status & m_FS_INTR_STS) {
4283                 timestamp = ktime_get();
4284                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4285                              v_FS_INTR_CLR(1));
4286                 /*if(lcdc_dev->driver.wait_fs){ */
4287                 if (0) {
4288                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4289                         complete(&(lcdc_dev->driver.frame_done));
4290                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4291                 }
4292 #ifdef CONFIG_DRM_ROCKCHIP
4293                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4294 #endif
4295                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4296                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4297
4298         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4299                 lcdc_dev->driver.frame_time.last_framedone_t =
4300                     lcdc_dev->driver.frame_time.framedone_t;
4301                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4302                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4303                              v_LINE_FLAG0_INTR_CLR(1));
4304         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4305                 /*line flag1 */
4306                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4307                              v_LINE_FLAG1_INTR_CLR(1));
4308         } else if (intr_status & m_FS_NEW_INTR_STS) {
4309                 /*new frame start */
4310                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4311                              v_FS_NEW_INTR_CLR(1));
4312         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4313                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4314                              v_BUS_ERROR_INTR_CLR(1));
4315                 dev_warn(lcdc_dev->dev, "bus error!");
4316         }
4317
4318         /* for win empty debug */
4319 #ifdef LCDC_IRQ_EMPTY_DEBUG
4320         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4321 #endif
4322         return IRQ_HANDLED;
4323 }
4324
4325 #if defined(CONFIG_PM)
4326 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4327 {
4328         return 0;
4329 }
4330
4331 static int rk3368_lcdc_resume(struct platform_device *pdev)
4332 {
4333         return 0;
4334 }
4335 #else
4336 #define rk3368_lcdc_suspend NULL
4337 #define rk3368_lcdc_resume  NULL
4338 #endif
4339
4340 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4341 {
4342         struct device_node *np = lcdc_dev->dev->of_node;
4343         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4344         int val;
4345
4346         if (of_property_read_u32(np, "rockchip,prop", &val))
4347                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4348         else
4349                 lcdc_dev->prop = val;
4350
4351         if (of_property_read_u32(np, "rockchip,mirror", &val))
4352                 dev_drv->rotate_mode = NO_MIRROR;
4353         else
4354                 dev_drv->rotate_mode = val;
4355
4356         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4357                 dev_drv->cabc_mode = 0; /* default set close cabc */
4358         else
4359                 dev_drv->cabc_mode = val;
4360
4361         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4362                 /*default set it as 3.xv power supply */
4363                 lcdc_dev->pwr18 = false;
4364         else
4365                 lcdc_dev->pwr18 = (val ? true : false);
4366
4367         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4368                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4369         else
4370                 dev_drv->fb_win_map = val;
4371
4372         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4373                 dev_drv->bcsh.enable = false;
4374         else
4375                 dev_drv->bcsh.enable = (val ? true : false);
4376
4377         if (of_property_read_u32(np, "rockchip,brightness", &val))
4378                 dev_drv->bcsh.brightness = 0xffff;
4379         else
4380                 dev_drv->bcsh.brightness = val;
4381
4382         if (of_property_read_u32(np, "rockchip,contrast", &val))
4383                 dev_drv->bcsh.contrast = 0xffff;
4384         else
4385                 dev_drv->bcsh.contrast = val;
4386
4387         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4388                 dev_drv->bcsh.sat_con = 0xffff;
4389         else
4390                 dev_drv->bcsh.sat_con = val;
4391
4392         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4393                 dev_drv->bcsh.sin_hue = 0xffff;
4394                 dev_drv->bcsh.cos_hue = 0xffff;
4395         } else {
4396                 dev_drv->bcsh.sin_hue = val & 0xff;
4397                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4398         }
4399
4400 #if defined(CONFIG_ROCKCHIP_IOMMU)
4401         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4402                 dev_drv->iommu_enabled = 0;
4403         else
4404                 dev_drv->iommu_enabled = val;
4405 #else
4406         dev_drv->iommu_enabled = 0;
4407 #endif
4408         return 0;
4409 }
4410
4411 static int rk3368_lcdc_probe(struct platform_device *pdev)
4412 {
4413         struct lcdc_device *lcdc_dev = NULL;
4414         struct rk_lcdc_driver *dev_drv;
4415         struct device *dev = &pdev->dev;
4416         struct resource *res;
4417         struct device_node *np = pdev->dev.of_node;
4418         int prop;
4419         int ret = 0;
4420
4421         /*if the primary lcdc has not registered ,the extend
4422            lcdc register later */
4423         of_property_read_u32(np, "rockchip,prop", &prop);
4424         if (prop == EXTEND) {
4425                 if (!is_prmry_rk_lcdc_registered())
4426                         return -EPROBE_DEFER;
4427         }
4428         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4429         if (!lcdc_dev) {
4430                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4431                 return -ENOMEM;
4432         }
4433         platform_set_drvdata(pdev, lcdc_dev);
4434         lcdc_dev->dev = dev;
4435         rk3368_lcdc_parse_dt(lcdc_dev);
4436         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4437         lcdc_dev->reg_phy_base = res->start;
4438         lcdc_dev->len = resource_size(res);
4439         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4440         if (IS_ERR(lcdc_dev->regs))
4441                 return PTR_ERR(lcdc_dev->regs);
4442         else
4443                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4444
4445         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4446         if (IS_ERR(lcdc_dev->regsbak))
4447                 return PTR_ERR(lcdc_dev->regsbak);
4448         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4449         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4450         lcdc_dev->grf_base =
4451                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4452         if (IS_ERR(lcdc_dev->grf_base)) {
4453                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4454                 return PTR_ERR(lcdc_dev->grf_base);
4455         }
4456         lcdc_dev->pmugrf_base =
4457                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4458         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4459                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4460                 return PTR_ERR(lcdc_dev->pmugrf_base);
4461         }
4462         lcdc_dev->id = 0;
4463         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4464         dev_drv = &lcdc_dev->driver;
4465         dev_drv->dev = dev;
4466         dev_drv->prop = prop;
4467         dev_drv->id = lcdc_dev->id;
4468         dev_drv->ops = &lcdc_drv_ops;
4469         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4470         spin_lock_init(&lcdc_dev->reg_lock);
4471
4472         lcdc_dev->irq = platform_get_irq(pdev, 0);
4473         if (lcdc_dev->irq < 0) {
4474                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4475                         lcdc_dev->id);
4476                 return -ENXIO;
4477         }
4478
4479         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4480                                IRQF_DISABLED | IRQF_SHARED,
4481                                dev_name(dev), lcdc_dev);
4482         if (ret) {
4483                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4484                         lcdc_dev->irq, ret);
4485                 return ret;
4486         }
4487
4488         if (dev_drv->iommu_enabled) {
4489                 if (lcdc_dev->id == 0) {
4490                         strcpy(dev_drv->mmu_dts_name,
4491                                VOPB_IOMMU_COMPATIBLE_NAME);
4492                 } else {
4493                         strcpy(dev_drv->mmu_dts_name,
4494                                VOPL_IOMMU_COMPATIBLE_NAME);
4495                 }
4496         }
4497
4498         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4499         if (ret < 0) {
4500                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4501                 return ret;
4502         }
4503         lcdc_dev->screen = dev_drv->screen0;
4504         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4505                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4506
4507         return 0;
4508 }
4509
4510 static int rk3368_lcdc_remove(struct platform_device *pdev)
4511 {
4512         return 0;
4513 }
4514
4515 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4516 {
4517         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4518
4519         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4520         rk3368_lcdc_deint(lcdc_dev);
4521 }
4522
4523 #if defined(CONFIG_OF)
4524 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4525         {.compatible = "rockchip,rk3368-lcdc",},
4526         {}
4527 };
4528 #endif
4529
4530 static struct platform_driver rk3368_lcdc_driver = {
4531         .probe = rk3368_lcdc_probe,
4532         .remove = rk3368_lcdc_remove,
4533         .driver = {
4534                    .name = "rk3368-lcdc",
4535                    .owner = THIS_MODULE,
4536                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4537                    },
4538         .suspend = rk3368_lcdc_suspend,
4539         .resume = rk3368_lcdc_resume,
4540         .shutdown = rk3368_lcdc_shutdown,
4541 };
4542
4543 static int __init rk3368_lcdc_module_init(void)
4544 {
4545         return platform_driver_register(&rk3368_lcdc_driver);
4546 }
4547
4548 static void __exit rk3368_lcdc_module_exit(void)
4549 {
4550         platform_driver_unregister(&rk3368_lcdc_driver);
4551 }
4552
4553 fs_initcall(rk3368_lcdc_module_init);
4554 module_exit(rk3368_lcdc_module_exit);