drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
  99 {
 100         int i;
 101         int __iomem *c;
 102         u32 v;
 103         struct lcdc_device *lcdc_dev =
 104             container_of(dev_drv, struct lcdc_device, driver);
 105         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 106         lcdc_cfg_done(lcdc_dev);
 107         mdelay(25);
 108         for (i = 0; i < 256; i++) {
 109                 v = dsp_lut[i];
 110                 c = lcdc_dev->dsp_lut_addr_base + i;
 111                 writel_relaxed(v, c);
 112         }
 113         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 114
 115         return 0;
 116 }
 117
 118 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 1;
 122         return 0;
 123 #endif
 124         if (!lcdc_dev->clk_on) {
 125                 clk_prepare_enable(lcdc_dev->hclk);
 126                 clk_prepare_enable(lcdc_dev->dclk);
 127                 clk_prepare_enable(lcdc_dev->aclk);
 128                 /*clk_prepare_enable(lcdc_dev->pd);*/
 129                 spin_lock(&lcdc_dev->reg_lock);
 130                 lcdc_dev->clk_on = 1;
 131                 spin_unlock(&lcdc_dev->reg_lock);
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 138 {
 139 #ifdef CONFIG_RK_FPGA
 140         lcdc_dev->clk_on = 0;
 141         return 0;
 142 #endif
 143         if (lcdc_dev->clk_on) {
 144                 spin_lock(&lcdc_dev->reg_lock);
 145                 lcdc_dev->clk_on = 0;
 146                 spin_unlock(&lcdc_dev->reg_lock);
 147                 mdelay(25);
 148                 clk_disable_unprepare(lcdc_dev->dclk);
 149                 clk_disable_unprepare(lcdc_dev->hclk);
 150                 clk_disable_unprepare(lcdc_dev->aclk);
 151                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 152         }
 153
 154         return 0;
 155 }
 156
 157 static int rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 158 {
 159         u32 mask, val;
 160
 161         spin_lock(&lcdc_dev->reg_lock);
 162         if (likely(lcdc_dev->clk_on)) {
 163                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 164                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 165                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 166                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 167                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 168                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 169                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 170                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 171                     v_ADDR_SAME_INTR_EN(0) |
 172                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 173                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 174                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 175                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 176                     v_POST_BUF_EMPTY_INTR_EN(0) |
 177                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 178                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 179
 180                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 181                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 182                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 183                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 184                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 185                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 186                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 187                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 188                     v_ADDR_SAME_INTR_CLR(1) |
 189                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 190                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 191                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 192                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 193                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 194                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 195                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 196                 lcdc_cfg_done(lcdc_dev);
 197                 spin_unlock(&lcdc_dev->reg_lock);
 198         } else {
 199                 spin_unlock(&lcdc_dev->reg_lock);
 200         }
 201         mdelay(1);
 202         return 0;
 203 }
 204
 205 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 206 {
 207         struct lcdc_device *lcdc_dev =
 208             container_of(dev_drv, struct lcdc_device, driver);
 209         int *cbase = (int *)lcdc_dev->regs;
 210         int *regsbak = (int *)lcdc_dev->regsbak;
 211         int i, j, val;
 212         char dbg_message[30];
 213         char buf[10];
 214
 215         pr_info("lcd back up reg:\n");
 216         memset(dbg_message, 0, sizeof(dbg_message));
 217         memset(buf, 0, sizeof(buf));
 218         for (i = 0; i <= (0x200 >> 4); i++) {
 219                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 220                 for (j = 0; j < 4; j++) {
 221                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 222                         strcat(dbg_message, buf);
 223                 }
 224                 pr_info("%s\n", dbg_message);
 225                 memset(dbg_message, 0, sizeof(dbg_message));
 226                 memset(buf, 0, sizeof(buf));
 227         }
 228
 229         pr_info("lcdc reg:\n");
 230         for (i = 0; i <= (0x200 >> 4); i++) {
 231                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 232                 for (j = 0; j < 4; j++) {
 233                         sprintf(buf, "%08x  ",
 234                                 readl_relaxed(cbase + i * 4 + j));
 235                         strcat(dbg_message, buf);
 236                 }
 237                 pr_info("%s\n", dbg_message);
 238                 memset(dbg_message, 0, sizeof(dbg_message));
 239                 memset(buf, 0, sizeof(buf));
 240         }
 241
 242         return 0;
 243 }
 244
 245 #define WIN_EN(id)              \
 246 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 247 { \
 248         u32 msk, val;                                                   \
 249         spin_lock(&lcdc_dev->reg_lock);                                 \
 250         msk =  m_WIN##id##_EN;                                          \
 251         val  =  v_WIN##id##_EN(en);                                     \
 252         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 253         lcdc_cfg_done(lcdc_dev);                                        \
 254         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 255         while (val !=  (!!en))  {                                       \
 256                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 257         }                                                               \
 258         spin_unlock(&lcdc_dev->reg_lock);                               \
 259         return 0;                                                       \
 260 }
 261
 262 WIN_EN(0);
 263 WIN_EN(1);
 264 WIN_EN(2);
 265 WIN_EN(3);
 266 /*enable/disable win directly*/
 267 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 268                                      int win_id, int en)
 269 {
 270         struct lcdc_device *lcdc_dev =
 271             container_of(drv, struct lcdc_device, driver);
 272         if (win_id == 0)
 273                 win0_enable(lcdc_dev, en);
 274         else if (win_id == 1)
 275                 win1_enable(lcdc_dev, en);
 276         else if (win_id == 2)
 277                 win2_enable(lcdc_dev, en);
 278         else if (win_id == 3)
 279                 win3_enable(lcdc_dev, en);
 280         else
 281                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 282         return 0;
 283 }
 284
 285 #define SET_WIN_ADDR(id) \
 286 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 287 {                                                       \
 288         u32 msk, val;                                   \
 289         spin_lock(&lcdc_dev->reg_lock);                 \
 290         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 291         msk =  m_WIN##id##_EN;                          \
 292         val  =  v_WIN0_EN(1);                           \
 293         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 294         lcdc_cfg_done(lcdc_dev);                        \
 295         spin_unlock(&lcdc_dev->reg_lock);               \
 296         return 0;                                       \
 297 }
 298
 299 SET_WIN_ADDR(0);
 300 SET_WIN_ADDR(1);
 301 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 302                                     int win_id, u32 addr)
 303 {
 304         struct lcdc_device *lcdc_dev =
 305             container_of(dev_drv, struct lcdc_device, driver);
 306         if (win_id == 0)
 307                 set_win0_addr(lcdc_dev, addr);
 308         else
 309                 set_win1_addr(lcdc_dev, addr);
 310
 311         return 0;
 312 }
 313
 314 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 315 {
 316         int reg = 0;
 317         u32 val = 0;
 318         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 319         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 320         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 321         u32 st_x, st_y;
 322         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 323
 324         spin_lock(&lcdc_dev->reg_lock);
 325         for (reg = 0; reg < FRC_LOWER11_1; reg += 4) {
 326                 val = lcdc_readl_backup(lcdc_dev, reg);
 327                 switch (reg) {
 328                 case WIN0_ACT_INFO:
 329                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 330                         win0->area[0].yact =
 331                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 332                         break;
 333                 case WIN0_DSP_INFO:
 334                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 335                         win0->area[0].ysize =
 336                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 337                         break;
 338                 case WIN0_DSP_ST:
 339                         st_x = val & m_WIN0_DSP_XST;
 340                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 341                         win0->area[0].xpos = st_x - h_pw_bp;
 342                         win0->area[0].ypos = st_y - v_pw_bp;
 343                         break;
 344                 case WIN0_CTRL0:
 345                         win0->state = val & m_WIN0_EN;
 346                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 347                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 348                         win0->area[0].format = win0->area[0].fmt_cfg;
 349                         break;
 350                 case WIN0_VIR:
 351                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 352                         win0->area[0].uv_vir_stride =
 353                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 354                         if (win0->area[0].format == ARGB888)
 355                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 356                         else if (win0->area[0].format == RGB888)
 357                                 win0->area[0].xvir =
 358                                     win0->area[0].y_vir_stride * 4 / 3;
 359                         else if (win0->area[0].format == RGB565)
 360                                 win0->area[0].xvir =
 361                                     2 * win0->area[0].y_vir_stride;
 362                         else    /* YUV */
 363                                 win0->area[0].xvir =
 364                                     4 * win0->area[0].y_vir_stride;
 365                         break;
 366                 case WIN0_YRGB_MST:
 367                         win0->area[0].smem_start = val;
 368                         break;
 369                 case WIN0_CBR_MST:
 370                         win0->area[0].cbr_start = val;
 371                         break;
 372                 default:
 373                         break;
 374                 }
 375         }
 376         spin_unlock(&lcdc_dev->reg_lock);
 377 }
 378
 379 /********do basic init*********/
 380 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 381 {
 382         u32 mask, val, v;
 383         struct lcdc_device *lcdc_dev =
 384             container_of(dev_drv, struct lcdc_device, driver);
 385         if (lcdc_dev->pre_init)
 386                 return 0;
 387
 388         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 389         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 390         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 391         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 392
 393         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 394             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 395                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 396                         lcdc_dev->id);
 397         }
 398
 399         rk_disp_pwr_enable(dev_drv);
 400         rk3368_lcdc_clk_enable(lcdc_dev);
 401
 402         /*backup reg config at uboot */
 403         lcdc_read_reg_defalut_cfg(lcdc_dev);
 404         if (lcdc_dev->pwr18 == 1) {
 405                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 406                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 407                                 PMUGRF_SOC_CON0_VOP, v);
 408         } else {
 409                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 410                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 411                                 PMUGRF_SOC_CON0_VOP, v);
 412         }
 413         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 414         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 415         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 416         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 417         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 418         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 419
 420         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 421         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 422         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 423         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 424         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 425         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 426
 427         mask = m_AUTO_GATING_EN;
 428         val = v_AUTO_GATING_EN(0);
 429         lcdc_cfg_done(lcdc_dev);
 430         /*disable win0 to workaround iommu pagefault */
 431         /*if (dev_drv->iommu_enabled) */
 432         /*      win0_enable(lcdc_dev, 0); */
 433         lcdc_dev->pre_init = true;
 434
 435         return 0;
 436 }
 437
 438 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 439 {
 440         rk3368_lcdc_disable_irq(lcdc_dev);
 441         spin_lock(&lcdc_dev->reg_lock);
 442         if (likely(lcdc_dev->clk_on)) {
 443                 lcdc_dev->clk_on = 0;
 444                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 445                 lcdc_cfg_done(lcdc_dev);
 446                 spin_unlock(&lcdc_dev->reg_lock);
 447         } else {
 448                 spin_unlock(&lcdc_dev->reg_lock);
 449         }
 450         mdelay(1);
 451 }
 452
 453 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 454 {
 455         struct lcdc_device *lcdc_dev =
 456             container_of(dev_drv, struct lcdc_device, driver);
 457         struct rk_screen *screen = dev_drv->cur_screen;
 458         u16 x_res = screen->mode.xres;
 459         u16 y_res = screen->mode.yres;
 460         u32 mask, val;
 461         u16 h_total, v_total;
 462         u16 post_hsd_en, post_vsd_en;
 463         u16 post_dsp_hact_st, post_dsp_hact_end;
 464         u16 post_dsp_vact_st, post_dsp_vact_end;
 465         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 466         u16 post_h_fac, post_v_fac;
 467
 468         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 469             x_res + screen->mode.right_margin;
 470         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 471             y_res + screen->mode.lower_margin;
 472
 473         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 474                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 475                          screen->post_dsp_stx, screen->post_xsize, x_res);
 476                 screen->post_dsp_stx = x_res - screen->post_xsize;
 477         }
 478         if (screen->x_mirror == 0) {
 479                 post_dsp_hact_st = screen->post_dsp_stx +
 480                     screen->mode.hsync_len + screen->mode.left_margin;
 481                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 482         } else {
 483                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 484                     screen->post_dsp_stx;
 485                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 486         }
 487         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 488                 post_hsd_en = 1;
 489                 post_h_fac =
 490                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 491         } else {
 492                 post_hsd_en = 0;
 493                 post_h_fac = 0x1000;
 494         }
 495
 496         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 497                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 498                          screen->post_dsp_sty, screen->post_ysize, y_res);
 499                 screen->post_dsp_sty = y_res - screen->post_ysize;
 500         }
 501
 502         if (screen->y_mirror == 0) {
 503                 post_dsp_vact_st = screen->post_dsp_sty +
 504                     screen->mode.vsync_len + screen->mode.upper_margin;
 505                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 506         } else {
 507                 post_dsp_vact_end = v_total - screen->mode.lower_margin -
 508                     screen->post_dsp_sty;
 509                 post_dsp_vact_st = post_dsp_vact_end - screen->post_ysize;
 510         }
 511         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 512                 post_vsd_en = 1;
 513                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 514                                                       screen->post_ysize);
 515         } else {
 516                 post_vsd_en = 0;
 517                 post_v_fac = 0x1000;
 518         }
 519
 520         if (screen->interlace == 1) {
 521                 post_dsp_vact_st_f1 = v_total + post_dsp_vact_st;
 522                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 + screen->post_ysize;
 523         } else {
 524                 post_dsp_vact_st_f1 = 0;
 525                 post_dsp_vact_end_f1 = 0;
 526         }
 527         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 528             screen->post_xsize, screen->post_ysize, screen->xpos);
 529         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 530             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 531         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 532         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 533             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 534         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 535
 536         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 537         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 538             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 539         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 540
 541         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 542         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 543             v_POST_VS_FACTOR_YRGB(post_v_fac);
 544         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 545
 546         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 547         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 548             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 549         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 550
 551         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 552         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 553         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 554         return 0;
 555 }
 556
 557 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 558 {
 559         struct lcdc_device *lcdc_dev =
 560             container_of(dev_drv, struct lcdc_device, driver);
 561         struct rk_lcdc_win *win;
 562         u32 colorkey_r, colorkey_g, colorkey_b;
 563         int i, key_val;
 564
 565         for (i = 0; i < 4; i++) {
 566                 win = dev_drv->win[i];
 567                 key_val = win->color_key_val;
 568                 colorkey_r = (key_val & 0xff) << 2;
 569                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 570                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 571                 /*color key dither 565/888->aaa */
 572                 key_val = colorkey_r | colorkey_g | colorkey_b;
 573                 switch (i) {
 574                 case 0:
 575                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 576                         break;
 577                 case 1:
 578                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 579                         break;
 580                 case 2:
 581                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 582                         break;
 583                 case 3:
 584                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 585                         break;
 586                 default:
 587                         pr_info("%s:un support win num:%d\n",
 588                                 __func__, i);
 589                         break;
 590                 }
 591         }
 592         return 0;
 593 }
 594
 595 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 596 {
 597         struct lcdc_device *lcdc_dev =
 598             container_of(dev_drv, struct lcdc_device, driver);
 599         struct rk_lcdc_win *win = dev_drv->win[win_id];
 600         struct alpha_config alpha_config;
 601         u32 mask, val;
 602         int ppixel_alpha = 0, global_alpha = 0, i;
 603         u32 src_alpha_ctl, dst_alpha_ctl;
 604
 605         for (i = 0; i < win->area_num; i++) {
 606                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 607                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 608         }
 609         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 610         alpha_config.src_global_alpha_val = win->g_alpha_val;
 611         win->alpha_mode = AB_SRC_OVER;
 612         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 613            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 614            global_alpha); */
 615         switch (win->alpha_mode) {
 616         case AB_USER_DEFINE:
 617                 break;
 618         case AB_CLEAR:
 619                 alpha_config.src_factor_mode = AA_ZERO;
 620                 alpha_config.dst_factor_mode = AA_ZERO;
 621                 break;
 622         case AB_SRC:
 623                 alpha_config.src_factor_mode = AA_ONE;
 624                 alpha_config.dst_factor_mode = AA_ZERO;
 625                 break;
 626         case AB_DST:
 627                 alpha_config.src_factor_mode = AA_ZERO;
 628                 alpha_config.dst_factor_mode = AA_ONE;
 629                 break;
 630         case AB_SRC_OVER:
 631                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 632                 if (global_alpha)
 633                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 634                 else
 635                         alpha_config.src_factor_mode = AA_ONE;
 636                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 637                 break;
 638         case AB_DST_OVER:
 639                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 640                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 641                 alpha_config.dst_factor_mode = AA_ONE;
 642                 break;
 643         case AB_SRC_IN:
 644                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 645                 alpha_config.src_factor_mode = AA_SRC;
 646                 alpha_config.dst_factor_mode = AA_ZERO;
 647                 break;
 648         case AB_DST_IN:
 649                 alpha_config.src_factor_mode = AA_ZERO;
 650                 alpha_config.dst_factor_mode = AA_SRC;
 651                 break;
 652         case AB_SRC_OUT:
 653                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 654                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 655                 alpha_config.dst_factor_mode = AA_ZERO;
 656                 break;
 657         case AB_DST_OUT:
 658                 alpha_config.src_factor_mode = AA_ZERO;
 659                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 660                 break;
 661         case AB_SRC_ATOP:
 662                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 663                 alpha_config.src_factor_mode = AA_SRC;
 664                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 665                 break;
 666         case AB_DST_ATOP:
 667                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 668                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 669                 alpha_config.dst_factor_mode = AA_SRC;
 670                 break;
 671         case XOR:
 672                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 673                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 674                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 675                 break;
 676         case AB_SRC_OVER_GLOBAL:
 677                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 678                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 679                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 680                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 681                 break;
 682         default:
 683                 pr_err("alpha mode error\n");
 684                 break;
 685         }
 686         if ((ppixel_alpha == 1) && (global_alpha == 1))
 687                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 688         else if (ppixel_alpha == 1)
 689                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 690         else if (global_alpha == 1)
 691                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 692         else
 693                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 694         alpha_config.src_alpha_mode = AA_STRAIGHT;
 695         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 696
 697         switch (win_id) {
 698         case 0:
 699                 src_alpha_ctl = 0x60;
 700                 dst_alpha_ctl = 0x64;
 701                 break;
 702         case 1:
 703                 src_alpha_ctl = 0xa0;
 704                 dst_alpha_ctl = 0xa4;
 705                 break;
 706         case 2:
 707                 src_alpha_ctl = 0xdc;
 708                 dst_alpha_ctl = 0xec;
 709                 break;
 710         case 3:
 711                 src_alpha_ctl = 0x12c;
 712                 dst_alpha_ctl = 0x13c;
 713                 break;
 714         case 4:
 715                 src_alpha_ctl = 0x160;
 716                 dst_alpha_ctl = 0x164;
 717                 break;
 718         }
 719         mask = m_WIN0_DST_FACTOR_M0;
 720         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 721         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 722         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 723             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 724             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 725             m_WIN0_SRC_GLOBAL_ALPHA;
 726         val = v_WIN0_SRC_ALPHA_EN(1) |
 727             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 728             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 729             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 730             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 731             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 732             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 733         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 734
 735         return 0;
 736 }
 737
 738 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 739 {
 740         struct rk_lcdc_win_area area_temp;
 741         int i, j;
 742
 743         for (i = 0; i < area_num; i++) {
 744                 for (j = i + 1; j < area_num; j++) {
 745                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 746                                 memcpy(&area_temp, &win->area[i],
 747                                        sizeof(struct rk_lcdc_win_area));
 748                                 memcpy(&win->area[i], &win->area[j],
 749                                        sizeof(struct rk_lcdc_win_area));
 750                                 memcpy(&win->area[j], &area_temp,
 751                                        sizeof(struct rk_lcdc_win_area));
 752                         }
 753                 }
 754         }
 755
 756         return 0;
 757 }
 758
 759 static int rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 760 {
 761         struct rk_lcdc_win_area area_temp;
 762
 763         switch (area_num) {
 764         case 2:
 765                 area_temp = win->area[0];
 766                 win->area[0] = win->area[1];
 767                 win->area[1] = area_temp;
 768                 break;
 769         case 3:
 770                 area_temp = win->area[0];
 771                 win->area[0] = win->area[2];
 772                 win->area[2] = area_temp;
 773                 break;
 774         case 4:
 775                 area_temp = win->area[0];
 776                 win->area[0] = win->area[3];
 777                 win->area[3] = area_temp;
 778
 779                 area_temp = win->area[1];
 780                 win->area[1] = win->area[2];
 781                 win->area[2] = area_temp;
 782                 break;
 783         default:
 784                 pr_info("un supported area num!\n");
 785                 break;
 786         }
 787         return 0;
 788 }
 789
 790 static int rk3368_win_area_check_var(int win_id, int area_num,
 791                                      struct rk_lcdc_win_area *area_pre,
 792                                      struct rk_lcdc_win_area *area_now)
 793 {
 794         if ((area_pre->xpos > area_now->xpos) ||
 795             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 796              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 797                 area_now->state = 0;
 798                 pr_err("win[%d]:\n"
 799                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 800                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 801                        win_id,
 802                        area_num - 1, area_pre->xpos, area_pre->xsize,
 803                        area_pre->ypos, area_pre->ysize,
 804                        area_num, area_now->xpos, area_now->xsize,
 805                        area_now->ypos, area_now->ysize);
 806                 return -EINVAL;
 807         }
 808         return 0;
 809 }
 810
 811 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 812 {
 813         struct lcdc_device *lcdc_dev =
 814             container_of(dev_drv, struct lcdc_device, driver);
 815         u32 val, i;
 816
 817         for (i = 0; i < 100; i++) {
 818                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 819                 val &= m_DBG_IFBDC_IDLE;
 820                 if (val)
 821                         continue;
 822                 else
 823                         mdelay(10);
 824         };
 825         return val;
 826 }
 827
 828 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 829 {
 830         struct lcdc_device *lcdc_dev =
 831             container_of(dev_drv, struct lcdc_device, driver);
 832         struct rk_lcdc_win *win = dev_drv->win[win_id];
 833         u32 mask, val;
 834
 835         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 836             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 837             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 838         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 839             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 840             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 841             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 842             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 843             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 844         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 845
 846         mask = m_IFBDC_TILES_NUM;
 847         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 848         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 849
 850         mask = m_IFBDC_BASE_ADDR;
 851         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 852         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 853
 854         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 855         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 856             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 857         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 858
 859         mask = m_IFBDC_CMP_INDEX_INIT;
 860         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 861         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 862
 863         mask = m_IFBDC_MB_VIR_WIDTH;
 864         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 865         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 866
 867         return 0;
 868 }
 869
 870 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 871 {
 872         struct lcdc_device *lcdc_dev =
 873             container_of(dev_drv, struct lcdc_device, driver);
 874         struct rk_lcdc_win *win = dev_drv->win[win_id];
 875         u8 fbdc_dsp_width_ratio;
 876         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 877         u16 fbdc_mb_width, fbdc_mb_height;
 878         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 879         u16 fbdc_cmp_index_init;
 880         u8 mb_w_size, mb_h_size;
 881         struct rk_screen *screen = dev_drv->cur_screen;
 882
 883         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 884                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 885                 return 0;
 886         }
 887
 888         switch (win->area[0].fmt_cfg) {
 889         case VOP_FORMAT_ARGB888:
 890                 fbdc_dsp_width_ratio = 0;
 891                 mb_w_size = 16;
 892                 break;
 893         case VOP_FORMAT_RGB888:
 894                 fbdc_dsp_width_ratio = 0;
 895                 mb_w_size = 16;
 896                 break;
 897         case VOP_FORMAT_RGB565:
 898                 mb_w_size = 32;
 899                 break;
 900         default:
 901                 dev_err(lcdc_dev->dev,
 902                         "in fbdc mode,unsupport fmt:%d!\n",
 903                         win->area[0].fmt_cfg);
 904                 break;
 905         }
 906         mb_h_size = 4;
 907
 908         /*macro block xvir and yvir */
 909         if ((win->area[0].xvir % mb_w_size == 0) &&
 910             (win->area[0].yvir % mb_h_size == 0)) {
 911                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 912                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 913         } else {
 914                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 915                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 916                        win->area[0].xvir, win->area[0].yvir,
 917                        mb_w_size, mb_h_size);
 918         }
 919         /*macro block xact and yact */
 920         if ((win->area[0].xact % mb_w_size == 0) &&
 921             (win->area[0].yact % mb_h_size == 0)) {
 922                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 923                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 924         } else {
 925                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 926                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 927                        win->area[0].xact, win->area[0].yact,
 928                        mb_w_size, mb_h_size);
 929         }
 930         /*macro block xoff and yoff */
 931         if ((win->area[0].xoff % mb_w_size == 0) &&
 932             (win->area[0].yoff % mb_h_size == 0)) {
 933                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 934                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 935         } else {
 936                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 937                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 938                        win->area[0].xoff, win->area[0].yoff,
 939                        mb_w_size, mb_h_size);
 940         }
 941
 942         /*FBDC tiles */
 943         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 944
 945         /*
 946            switch (fbdc_rotation_mode)  {
 947            case FBDC_ROT_NONE:
 948            fbdc_cmp_index_init =
 949            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 950            break;
 951            case FBDC_X_MIRROR:
 952            fbdc_cmp_index_init =
 953            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 954            (fbdc_mb_width-1));
 955            break;
 956            case FBDC_Y_MIRROR:
 957            fbdc_cmp_index_init =
 958            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 959            fbdc_mb_xst;
 960            break;
 961            case FBDC_ROT_180:
 962            fbdc_cmp_index_init =
 963            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
 964            (fbdc_mb_xst+(fbdc_mb_width-1));
 965            break;
 966            }
 967          */
 968         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
 969                 fbdc_cmp_index_init =
 970                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
 971                     (fbdc_mb_xst + (fbdc_mb_width - 1));
 972         } else {
 973                 fbdc_cmp_index_init =
 974                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
 975         }
 976         /*fbdc fmt maybe need to change*/
 977         win->area[0].fbdc_fmt_cfg = win->area[0].fbdc_data_format;
 978         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
 979         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
 980         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
 981         win->area[0].fbdc_mb_width = fbdc_mb_width;
 982         win->area[0].fbdc_mb_height = fbdc_mb_height;
 983         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
 984         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
 985         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
 986         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
 987
 988         return 0;
 989 }
 990
 991 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
 992                                  struct rk_lcdc_win *win)
 993 {
 994         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
 995         struct rk_screen *screen = dev_drv->cur_screen;
 996
 997         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
 998                 switch (win->area[0].fmt_cfg) {
 999                 case VOP_FORMAT_ARGB888:
1000                 case VOP_FORMAT_RGB888:
1001                 case VOP_FORMAT_RGB565:
1002                         if ((screen->mode.xres < 1280) &&
1003                             (screen->mode.yres < 720)) {
1004                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1005                         } else {
1006                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1007                         }
1008                         break;
1009                 default:
1010                         break;
1011                 }
1012         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1013                 switch (win->area[0].fmt_cfg) {
1014                 case VOP_FORMAT_YCBCR420:
1015                         if ((win->id == 0) || (win->id == 1))
1016                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1017                         break;
1018                 default:
1019                         break;
1020                 }
1021         }
1022 }
1023
1024 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1025 {
1026         struct lcdc_device *lcdc_dev =
1027             container_of(dev_drv, struct lcdc_device, driver);
1028         struct rk_lcdc_win *win = dev_drv->win[win_id];
1029         unsigned int mask, val, off;
1030
1031         off = win_id * 0x40;
1032         /*if(win->win_lb_mode == 5)
1033            win->win_lb_mode = 4;
1034            for rk3288 to fix hw bug? */
1035
1036         if (win->state == 1) {
1037                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1038                 if (win->area[0].fbdc_en)
1039                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1040                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1041                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1042                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1043                 val = v_WIN0_EN(win->state) |
1044                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1045                     v_WIN0_FMT_10(win->fmt_10) |
1046                     v_WIN0_LB_MODE(win->win_lb_mode) |
1047                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1048                     v_WIN0_X_MIRROR(win->mirror_en) |
1049                     v_WIN0_Y_MIRROR(win->mirror_en) |
1050                     v_WIN0_CSC_MODE(win->csc_mode);
1051                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1052
1053                 mask = m_WIN0_BIC_COE_SEL |
1054                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1055                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1056                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1057                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1058                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1059                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1060                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1061                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1062                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1063                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1064                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1065                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1066                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1067                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1068                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1069                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1070                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1071                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1072                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1073                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1074                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1075                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1076                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1077                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1078                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1079                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1080                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1081                                 win->area[0].y_addr);
1082                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1083                                 win->area[0].uv_addr); */
1084                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1085                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1086                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1087
1088                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1089                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1090                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1091
1092                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1093                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1094                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1095
1096                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1097                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1098                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1099
1100                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1101                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1102                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1103                 if (win->alpha_en == 1) {
1104                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1105                 } else {
1106                         mask = m_WIN0_SRC_ALPHA_EN;
1107                         val = v_WIN0_SRC_ALPHA_EN(0);
1108                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1109                                      mask, val);
1110                 }
1111         } else {
1112                 mask = m_WIN0_EN;
1113                 val = v_WIN0_EN(win->state);
1114                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1115         }
1116         return 0;
1117 }
1118
1119 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1120 {
1121         struct lcdc_device *lcdc_dev =
1122             container_of(dev_drv, struct lcdc_device, driver);
1123         struct rk_lcdc_win *win = dev_drv->win[win_id];
1124         struct rk_screen *screen = dev_drv->cur_screen;
1125         unsigned int mask, val, off;
1126
1127         off = (win_id - 2) * 0x50;
1128         rk3368_lcdc_area_xst(win, win->area_num);
1129         if (((screen->y_mirror == 1) || (win->mirror_en)) &&
1130             (win->area_num > 1)) {
1131                 rk3368_lcdc_area_swap(win, win->area_num);
1132         }
1133
1134         if (win->state == 1) {
1135                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1136                 if (win->area[0].fbdc_en)
1137                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1138
1139                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1140                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1141                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1142                 /*area 0 */
1143                 if (win->area[0].state == 1) {
1144                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1145                             m_WIN2_RB_SWAP0;
1146                         val = v_WIN2_MST0_EN(win->area[0].state) |
1147                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1148                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1149                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1150
1151                         mask = m_WIN2_VIR_STRIDE0;
1152                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1153                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1154
1155                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1156                            win->area[0].y_addr); */
1157                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1158                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1159                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1160                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1161                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1162                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1163                 } else {
1164                         mask = m_WIN2_MST0_EN;
1165                         val = v_WIN2_MST0_EN(0);
1166                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1167                 }
1168                 /*area 1 */
1169                 if (win->area[1].state == 1) {
1170                         rk3368_win_area_check_var(win_id, 1,
1171                                                   &win->area[0], &win->area[1]);
1172
1173                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1174                             m_WIN2_RB_SWAP1;
1175                         val = v_WIN2_MST1_EN(win->area[1].state) |
1176                             v_WIN2_DATA_FMT0(win->area[1].fmt_cfg) |
1177                             v_WIN2_RB_SWAP0(win->area[1].swap_rb);
1178                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1179
1180                         mask = m_WIN2_VIR_STRIDE1;
1181                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1182                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1183
1184                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1185                            win->area[1].y_addr); */
1186                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1187                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1188                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1189                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1190                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1191                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1192                 } else {
1193                         mask = m_WIN2_MST1_EN;
1194                         val = v_WIN2_MST1_EN(0);
1195                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1196                 }
1197                 /*area 2 */
1198                 if (win->area[2].state == 1) {
1199                         rk3368_win_area_check_var(win_id, 2,
1200                                                   &win->area[1], &win->area[2]);
1201
1202                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1203                             m_WIN2_RB_SWAP2;
1204                         val = v_WIN2_MST2_EN(win->area[2].state) |
1205                             v_WIN2_DATA_FMT0(win->area[2].fmt_cfg) |
1206                             v_WIN2_RB_SWAP0(win->area[2].swap_rb);
1207                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1208
1209                         mask = m_WIN2_VIR_STRIDE2;
1210                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1211                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1212
1213                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1214                            win->area[2].y_addr); */
1215                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1216                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1217                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1218                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1219                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1220                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1221                 } else {
1222                         mask = m_WIN2_MST2_EN;
1223                         val = v_WIN2_MST2_EN(0);
1224                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1225                 }
1226                 /*area 3 */
1227                 if (win->area[3].state == 1) {
1228                         rk3368_win_area_check_var(win_id, 3,
1229                                                   &win->area[2], &win->area[3]);
1230
1231                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1232                             m_WIN2_RB_SWAP3;
1233                         val = v_WIN2_MST3_EN(win->area[3].state) |
1234                             v_WIN2_DATA_FMT0(win->area[3].fmt_cfg) |
1235                             v_WIN2_RB_SWAP0(win->area[3].swap_rb);
1236                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1237
1238                         mask = m_WIN2_VIR_STRIDE3;
1239                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1240                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1241
1242                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1243                            win->area[3].y_addr); */
1244                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1245                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1246                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1247                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1248                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1249                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1250                 } else {
1251                         mask = m_WIN2_MST3_EN;
1252                         val = v_WIN2_MST3_EN(0);
1253                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1254                 }
1255
1256                 if (win->alpha_en == 1) {
1257                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1258                 } else {
1259                         mask = m_WIN2_SRC_ALPHA_EN;
1260                         val = v_WIN2_SRC_ALPHA_EN(0);
1261                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1262                                      mask, val);
1263                 }
1264         } else {
1265                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1266                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1267                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1268                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1269                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1270         }
1271         return 0;
1272 }
1273
1274 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1275 {
1276         struct lcdc_device *lcdc_dev =
1277             container_of(dev_drv, struct lcdc_device, driver);
1278         struct rk_lcdc_win *win = dev_drv->win[win_id];
1279         unsigned int mask, val, hwc_size = 0;
1280
1281         if (win->state == 1) {
1282                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1283                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1284                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1285                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1286                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1287                     v_WIN0_CSC_MODE(win->csc_mode);
1288                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1289
1290                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1291                         hwc_size = 0;
1292                 else if ((win->area[0].xsize == 64) &&
1293                          (win->area[0].ysize == 64))
1294                         hwc_size = 1;
1295                 else if ((win->area[0].xsize == 96) &&
1296                          (win->area[0].ysize == 96))
1297                         hwc_size = 2;
1298                 else if ((win->area[0].xsize == 128) &&
1299                          (win->area[0].ysize == 128))
1300                         hwc_size = 3;
1301                 else
1302                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1303
1304                 mask = m_HWC_SIZE;
1305                 val = v_HWC_SIZE(hwc_size);
1306                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1307
1308                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1309                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1310                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1311                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1312
1313                 if (win->alpha_en == 1) {
1314                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1315                 } else {
1316                         mask = m_WIN2_SRC_ALPHA_EN;
1317                         val = v_WIN2_SRC_ALPHA_EN(0);
1318                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1319                 }
1320         } else {
1321                 mask = m_HWC_EN;
1322                 val = v_HWC_EN(win->state);
1323                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1324         }
1325         return 0;
1326 }
1327
1328 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1329                                          struct rk_lcdc_win *win)
1330 {
1331         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1332         int timeout;
1333         unsigned long flags;
1334
1335         spin_lock(&lcdc_dev->reg_lock);
1336         if (likely(lcdc_dev->clk_on)) {
1337                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1338                              v_STANDBY_EN(lcdc_dev->standby));
1339                 if ((win->id == 0) || (win->id == 1))
1340                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1341                 else if ((win->id == 2) || (win->id == 3))
1342                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1343                 else if (win->id == 4)
1344                         rk3368_hwc_reg_update(dev_drv, win->id);
1345                 /*rk3368_lcdc_post_cfg(dev_drv); */
1346                 lcdc_cfg_done(lcdc_dev);
1347         }
1348         spin_unlock(&lcdc_dev->reg_lock);
1349
1350         /*if (dev_drv->wait_fs) { */
1351         if (0) {
1352                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1353                 init_completion(&dev_drv->frame_done);
1354                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1355                 timeout =
1356                     wait_for_completion_timeout(&dev_drv->frame_done,
1357                                                 msecs_to_jiffies
1358                                                 (dev_drv->cur_screen->ft + 5));
1359                 if (!timeout && (!dev_drv->frame_done.done)) {
1360                         dev_warn(lcdc_dev->dev,
1361                                  "wait for new frame start time out!\n");
1362                         return -ETIMEDOUT;
1363                 }
1364         }
1365         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1366         return 0;
1367 }
1368
1369 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1370 {
1371         if (lcdc_dev->driver.iommu_enabled)
1372                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x330);
1373         else
1374                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x260);
1375         return 0;
1376 }
1377
1378 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1379 {
1380         u32 mask, val;
1381         struct lcdc_device *lcdc_dev =
1382             container_of(dev_drv, struct lcdc_device, driver);
1383         /*spin_lock(&lcdc_dev->reg_lock); */
1384         if (likely(lcdc_dev->clk_on)) {
1385                 mask = m_MMU_EN;
1386                 val = v_MMU_EN(1);
1387                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1388                 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1389                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1390                     v_AXI_MAX_OUTSTANDING_EN(1);
1391                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1392         }
1393         /*spin_unlock(&lcdc_dev->reg_lock); */
1394 #if defined(CONFIG_ROCKCHIP_IOMMU)
1395         if (dev_drv->iommu_enabled) {
1396                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1397                         lcdc_dev->iommu_status = 1;
1398                         rockchip_iovmm_activate(dev_drv->dev);
1399                 }
1400         }
1401 #endif
1402         return 0;
1403 }
1404
1405 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1406 {
1407         int ret = 0, fps = 0;
1408         struct lcdc_device *lcdc_dev =
1409             container_of(dev_drv, struct lcdc_device, driver);
1410         struct rk_screen *screen = dev_drv->cur_screen;
1411 #ifdef CONFIG_RK_FPGA
1412         return 0;
1413 #endif
1414
1415         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1416         if (ret)
1417                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1418         lcdc_dev->pixclock =
1419             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1420         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1421
1422         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1423         screen->ft = 1000 / fps;
1424         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1425                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1426         return 0;
1427 }
1428
1429 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1430 {
1431         struct lcdc_device *lcdc_dev =
1432             container_of(dev_drv, struct lcdc_device, driver);
1433         struct rk_screen *screen = dev_drv->cur_screen;
1434         u16 hsync_len = screen->mode.hsync_len;
1435         u16 left_margin = screen->mode.left_margin;
1436         u16 right_margin = screen->mode.right_margin;
1437         u16 vsync_len = screen->mode.vsync_len;
1438         u16 upper_margin = screen->mode.upper_margin;
1439         u16 lower_margin = screen->mode.lower_margin;
1440         u16 x_res = screen->mode.xres;
1441         u16 y_res = screen->mode.yres;
1442         u32 mask, val;
1443         u16 h_total, v_total;
1444         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1445
1446         h_total = hsync_len + left_margin + x_res + right_margin;
1447         v_total = vsync_len + upper_margin + y_res + lower_margin;
1448
1449         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1450         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1451         screen->post_xsize = x_res *
1452             (screen->overscan.left + screen->overscan.right) / 200;
1453         screen->post_ysize = y_res *
1454             (screen->overscan.top + screen->overscan.bottom) / 200;
1455
1456         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1457         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1458         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1459
1460         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1461         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1462             v_DSP_HACT_ST(hsync_len + left_margin);
1463         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1464
1465         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1466                 /* First Field Timing */
1467                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1468                 val = v_DSP_VS_PW(vsync_len) |
1469                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1470                                       lower_margin) + y_res + 1);
1471                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1472
1473                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1474                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1475                     v_DSP_VACT_ST(vsync_len + upper_margin);
1476                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1477
1478                 /* Second Field Timing */
1479                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1480                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1481                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1482                     lower_margin;
1483                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1484                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1485
1486                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1487                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1488                     lower_margin + 1;
1489                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1490                     lower_margin + 1;
1491                 val =
1492                     v_DSP_VACT_END_F1(vact_end_f1) |
1493                     v_DSP_VAC_ST_F1(vact_st_f1);
1494                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1495
1496                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1497                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1498                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1499                 mask =
1500                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1501                     m_WIN0_CBR_DEFLICK;
1502                 val =
1503                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1504                     v_WIN0_CBR_DEFLICK(1);
1505                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1506
1507                 mask =
1508                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1509                     m_WIN1_CBR_DEFLICK;
1510                 val =
1511                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1512                     v_WIN1_CBR_DEFLICK(1);
1513                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1514
1515                 mask = m_WIN2_INTERLACE_READ;
1516                 val = v_WIN2_INTERLACE_READ(1);
1517                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1518
1519                 mask = m_WIN3_INTERLACE_READ;
1520                 val = v_WIN3_INTERLACE_READ(1);
1521                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1522
1523                 mask = m_HWC_INTERLACE_READ;
1524                 val = v_HWC_INTERLACE_READ(1);
1525                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1526
1527                 mask = m_DSP_LINE_FLAG0_NUM;
1528                 val =
1529                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1530                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1531         } else {
1532                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1533                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1534                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1535
1536                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1537                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1538                     v_DSP_VACT_ST(vsync_len + upper_margin);
1539                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1540
1541                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1542                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1543                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1544
1545                 mask =
1546                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1547                     m_WIN0_CBR_DEFLICK;
1548                 val =
1549                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1550                     v_WIN0_CBR_DEFLICK(0);
1551                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1552
1553                 mask =
1554                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1555                     m_WIN1_CBR_DEFLICK;
1556                 val =
1557                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1558                     v_WIN1_CBR_DEFLICK(0);
1559                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1560
1561                 mask = m_WIN2_INTERLACE_READ;
1562                 val = v_WIN2_INTERLACE_READ(0);
1563                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1564
1565                 mask = m_WIN3_INTERLACE_READ;
1566                 val = v_WIN3_INTERLACE_READ(0);
1567                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1568
1569                 mask = m_HWC_INTERLACE_READ;
1570                 val = v_HWC_INTERLACE_READ(0);
1571                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1572
1573                 mask = m_DSP_LINE_FLAG0_NUM;
1574                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1575                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1576         }
1577         rk3368_lcdc_post_cfg(dev_drv);
1578         return 0;
1579 }
1580
1581 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1582 {
1583         struct lcdc_device *lcdc_dev =
1584             container_of(dev_drv, struct lcdc_device, driver);
1585         u32 bcsh_ctrl;
1586
1587         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1588                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1589         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1590                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1591                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1592                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1593                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1594                 else            /* YUV2RGB */
1595                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1596                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1597                                      m_BCSH_R2Y_EN,
1598                                      v_BCSH_Y2R_EN(1) |
1599                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1600                                      v_BCSH_R2Y_EN(0));
1601         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1602                 /* bypass  --need check,if bcsh close? */
1603                 if (dev_drv->output_color == COLOR_RGB) {
1604                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1605                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1606                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1607                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1608                                              m_BCSH_R2Y_EN |
1609                                              m_BCSH_Y2R_EN,
1610                                              v_BCSH_R2Y_EN(1) |
1611                                              v_BCSH_Y2R_EN(1));
1612                         else
1613                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1614                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1615                                              v_BCSH_R2Y_EN(0) |
1616                                              v_BCSH_Y2R_EN(0));
1617                 } else          /* RGB2YUV */
1618                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1619                                      m_BCSH_R2Y_EN |
1620                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1621                                      v_BCSH_R2Y_EN(1) |
1622                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1623                                      v_BCSH_Y2R_EN(0));
1624         }
1625 }
1626
1627 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1628 {
1629         u16 face = 0;
1630         u16 dclk_ddr = 0;
1631         u32 v = 0;
1632         struct lcdc_device *lcdc_dev =
1633             container_of(dev_drv, struct lcdc_device, driver);
1634         struct rk_screen *screen = dev_drv->cur_screen;
1635         u32 mask, val;
1636
1637         spin_lock(&lcdc_dev->reg_lock);
1638         if (likely(lcdc_dev->clk_on)) {
1639                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1640                 if (!lcdc_dev->standby && !initscreen) {
1641                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1642                                      v_STANDBY_EN(1));
1643                         lcdc_cfg_done(lcdc_dev);
1644                         mdelay(50);
1645                 }
1646                 switch (screen->face) {
1647                 case OUT_P565:
1648                         face = OUT_P565;
1649                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1650                             m_DITHER_DOWN_SEL;
1651                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1652                             v_DITHER_DOWN_SEL(1);
1653                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1654                         break;
1655                 case OUT_P666:
1656                         face = OUT_P666;
1657                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1658                             m_DITHER_DOWN_SEL;
1659                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1660                             v_DITHER_DOWN_SEL(1);
1661                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1662                         break;
1663                 case OUT_D888_P565:
1664                         face = OUT_P888;
1665                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1666                             m_DITHER_DOWN_SEL;
1667                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1668                             v_DITHER_DOWN_SEL(1);
1669                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1670                         break;
1671                 case OUT_D888_P666:
1672                         face = OUT_P888;
1673                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1674                             m_DITHER_DOWN_SEL;
1675                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1676                             v_DITHER_DOWN_SEL(1);
1677                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1678                         break;
1679                 case OUT_P888:
1680                         face = OUT_P888;
1681                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1682                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1683                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1684                         break;
1685                 case OUT_YUV_420:
1686                         /*yuv420 output prefer yuv domain overlay */
1687                         face = OUT_YUV_420;
1688                         dclk_ddr = 1;
1689                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1690                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1691                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1692                         break;
1693                 default:
1694                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1695                         break;
1696                 }
1697                 switch (screen->type) {
1698                 case SCREEN_RGB:
1699                         mask = m_RGB_OUT_EN;
1700                         val = v_RGB_OUT_EN(1);
1701                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1702                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1703                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1704                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1705                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1706                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1707                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1708                         v = 1 << 15 | (1 << (15 + 16));
1709
1710                         break;
1711                 case SCREEN_LVDS:
1712                         mask = m_RGB_OUT_EN;
1713                         val = v_RGB_OUT_EN(1);
1714                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1715                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1716                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1717                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1718                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1719                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1720                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1721                         v = 0 << 15 | (1 << (15 + 16));
1722                         break;
1723                 case SCREEN_HDMI:
1724                         /*face = OUT_RGB_AAA;*/
1725                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1726                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1727                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1728                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1729                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1730                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1731                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1732                             v_HDMI_DEN_POL(screen->pin_den) |
1733                             v_HDMI_DCLK_POL(screen->pin_dclk);
1734                         break;
1735                 case SCREEN_MIPI:
1736                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1737                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1738                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1739                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1740                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1741                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1742                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1743                             v_MIPI_DEN_POL(screen->pin_den) |
1744                             v_MIPI_DCLK_POL(screen->pin_dclk);
1745                         break;
1746                 case SCREEN_DUAL_MIPI:
1747                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1748                                 m_RGB_OUT_EN;
1749                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1750                                 v_RGB_OUT_EN(0);
1751                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1752                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1753                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1754                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1755                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1756                             v_MIPI_DEN_POL(screen->pin_den) |
1757                             v_MIPI_DCLK_POL(screen->pin_dclk);
1758                         break;
1759                 case SCREEN_EDP:
1760                         face = OUT_P888;        /*RGB 888 output */
1761
1762                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1763                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1764                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1765                         /*because edp have to sent aaa fmt */
1766                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1767                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1768
1769                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1770                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1771                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1772                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1773                             v_EDP_DEN_POL(screen->pin_den) |
1774                             v_EDP_DCLK_POL(screen->pin_dclk);
1775                         break;
1776                 }
1777                 /*hsync vsync den dclk polo,dither */
1778                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1779 #ifndef CONFIG_RK_FPGA
1780                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1781                 move to  lvds driver*/
1782                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1783 #endif
1784                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1785                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1786                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1787                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1788                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1789                     v_DSP_BG_SWAP(screen->swap_gb) |
1790                     v_DSP_RB_SWAP(screen->swap_rb) |
1791                     v_DSP_RG_SWAP(screen->swap_rg) |
1792                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1793                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1794                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1795                     v_DSP_X_MIR_EN(screen->x_mirror) |
1796                     v_DSP_Y_MIR_EN(screen->y_mirror);
1797                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1798                 /*BG color */
1799                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1800                 val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) | v_DSP_BG_RED(0);
1801                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1802                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1803                 rk3368_config_timing(dev_drv);
1804         }
1805         spin_unlock(&lcdc_dev->reg_lock);
1806         rk3368_lcdc_set_dclk(dev_drv);
1807         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1808             dev_drv->trsm_ops->enable)
1809                 dev_drv->trsm_ops->enable();
1810         if (screen->init)
1811                 screen->init();
1812         if (!lcdc_dev->standby)
1813                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1814         return 0;
1815 }
1816
1817
1818 /*enable layer,open:1,enable;0 disable*/
1819 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1820                                      unsigned int win_id, bool open)
1821 {
1822         spin_lock(&lcdc_dev->reg_lock);
1823         if (likely(lcdc_dev->clk_on) &&
1824             lcdc_dev->driver.win[win_id]->state != open) {
1825                 if (open) {
1826                         if (!lcdc_dev->atv_layer_cnt) {
1827                                 dev_info(lcdc_dev->dev,
1828                                          "wakeup from standby!\n");
1829                                 lcdc_dev->standby = 0;
1830                         }
1831                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1832                 } else {
1833                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1834                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1835                 }
1836                 lcdc_dev->driver.win[win_id]->state = open;
1837                 if (!open) {
1838                         /*rk3368_lcdc_reg_update(dev_drv);*/
1839                         rk3368_lcdc_layer_update_regs
1840                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1841                         lcdc_cfg_done(lcdc_dev);
1842                 }
1843                 /*if no layer used,disable lcdc */
1844                 if (!lcdc_dev->atv_layer_cnt) {
1845                         dev_info(lcdc_dev->dev,
1846                                  "no layer is used,go to standby!\n");
1847                         lcdc_dev->standby = 1;
1848                 }
1849         }
1850         spin_unlock(&lcdc_dev->reg_lock);
1851 }
1852
1853 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1854 {
1855         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1856                                                     struct lcdc_device, driver);
1857         u32 mask, val;
1858         /*struct rk_screen *screen = dev_drv->cur_screen; */
1859
1860         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1861             m_LINE_FLAG1_INTR_CLR;
1862         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1863             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1864         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1865
1866         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1867         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1868             v_BUS_ERROR_INTR_EN(1);
1869         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1870
1871 #ifdef LCDC_IRQ_EMPTY_DEBUG
1872         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1873             m_WIN2_EMPTY_INTR_EN |
1874             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1875             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1876         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1877             v_WIN2_EMPTY_INTR_EN(1) |
1878             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1879             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1880         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1881 #endif
1882         return 0;
1883 }
1884
1885 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1886                             bool open)
1887 {
1888         struct lcdc_device *lcdc_dev =
1889             container_of(dev_drv, struct lcdc_device, driver);
1890 #if 0/*ndef CONFIG_RK_FPGA*/
1891         int sys_status =
1892             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1893 #endif
1894         /*enable clk,when first layer open */
1895         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1896                 /*rockchip_set_system_status(sys_status);*/
1897                 rk3368_lcdc_pre_init(dev_drv);
1898                 rk3368_lcdc_clk_enable(lcdc_dev);
1899 #if defined(CONFIG_ROCKCHIP_IOMMU)
1900                 if (dev_drv->iommu_enabled) {
1901                         if (!dev_drv->mmu_dev) {
1902                                 dev_drv->mmu_dev =
1903                                     rk_fb_get_sysmmu_device_by_compatible
1904                                     (dev_drv->mmu_dts_name);
1905                                 if (dev_drv->mmu_dev) {
1906                                         rk_fb_platform_set_sysmmu
1907                                             (dev_drv->mmu_dev, dev_drv->dev);
1908                                 } else {
1909                                         dev_err(dev_drv->dev,
1910                                                 "fail get rk iommu device\n");
1911                                         return -1;
1912                                 }
1913                         }
1914                         /*if (dev_drv->mmu_dev)
1915                            rockchip_iovmm_activate(dev_drv->dev); */
1916                 }
1917 #endif
1918                 rk3368_lcdc_reg_restore(lcdc_dev);
1919                 /*if (dev_drv->iommu_enabled)
1920                    rk3368_lcdc_mmu_en(dev_drv); */
1921                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1922                         /*rk3368_lcdc_set_dclk(dev_drv); */
1923                         rk3368_lcdc_enable_irq(dev_drv);
1924                 } else {
1925                         rk3368_load_screen(dev_drv, 1);
1926                 }
1927                 if (dev_drv->bcsh.enable)
1928                         rk3368_lcdc_set_bcsh(dev_drv, 1);
1929                 spin_lock(&lcdc_dev->reg_lock);
1930                 if (dev_drv->cur_screen->dsp_lut)
1931                         rk3368_lcdc_set_lut(dev_drv,
1932                                             dev_drv->cur_screen->dsp_lut);
1933                 spin_unlock(&lcdc_dev->reg_lock);
1934         }
1935
1936         if (win_id < ARRAY_SIZE(lcdc_win))
1937                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
1938         else
1939                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1940
1941
1942         /* when all layer closed,disable clk */
1943         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1944            rk3368_lcdc_disable_irq(lcdc_dev);
1945            rk3368_lcdc_reg_update(dev_drv);
1946            #if defined(CONFIG_ROCKCHIP_IOMMU)
1947            if (dev_drv->iommu_enabled) {
1948            if (dev_drv->mmu_dev)
1949            rockchip_iovmm_deactivate(dev_drv->dev);
1950            }
1951            #endif
1952            rk3368_lcdc_clk_disable(lcdc_dev);
1953            #ifndef CONFIG_RK_FPGA
1954            rockchip_clear_system_status(sys_status);
1955            #endif
1956            } */
1957
1958         return 0;
1959 }
1960
1961 static int win_0_1_display(struct lcdc_device *lcdc_dev,
1962                            struct rk_lcdc_win *win)
1963 {
1964         u32 y_addr;
1965         u32 uv_addr;
1966         unsigned int off;
1967
1968         off = win->id * 0x40;
1969         /*win->smem_start + win->y_offset; */
1970         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1971         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1972         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1973             lcdc_dev->id, win->id, y_addr, uv_addr);
1974         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
1975             win->area[0].y_offset, win->area[0].c_offset);
1976         spin_lock(&lcdc_dev->reg_lock);
1977         if (likely(lcdc_dev->clk_on)) {
1978                 win->area[0].y_addr = y_addr;
1979                 win->area[0].uv_addr = uv_addr;
1980                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
1981                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
1982                 /*lcdc_cfg_done(lcdc_dev); */
1983         }
1984         spin_unlock(&lcdc_dev->reg_lock);
1985
1986         return 0;
1987 }
1988
1989 static int win_2_3_display(struct lcdc_device *lcdc_dev,
1990                            struct rk_lcdc_win *win)
1991 {
1992         u32 i, y_addr;
1993         unsigned int off;
1994
1995         off = (win->id - 2) * 0x50;
1996         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1997         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
1998
1999         spin_lock(&lcdc_dev->reg_lock);
2000         if (likely(lcdc_dev->clk_on)) {
2001                 for (i = 0; i < win->area_num; i++) {
2002                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2003                             i, win->area[i].y_addr, win->area[i].y_offset);
2004                         win->area[i].y_addr =
2005                             win->area[i].smem_start + win->area[i].y_offset;
2006                         }
2007                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2008                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2009                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2010                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2011         }
2012         spin_unlock(&lcdc_dev->reg_lock);
2013         return 0;
2014 }
2015
2016 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2017 {
2018         u32 y_addr;
2019
2020         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2021         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2022             lcdc_dev->id, __func__, y_addr);
2023         spin_lock(&lcdc_dev->reg_lock);
2024         if (likely(lcdc_dev->clk_on)) {
2025                 win->area[0].y_addr = y_addr;
2026                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2027         }
2028         spin_unlock(&lcdc_dev->reg_lock);
2029
2030         return 0;
2031 }
2032
2033 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2034 {
2035         struct lcdc_device *lcdc_dev =
2036             container_of(dev_drv, struct lcdc_device, driver);
2037         struct rk_lcdc_win *win = NULL;
2038         struct rk_screen *screen = dev_drv->cur_screen;
2039
2040 #if defined(WAIT_FOR_SYNC)
2041         int timeout;
2042         unsigned long flags;
2043 #endif
2044         win = dev_drv->win[win_id];
2045         if (!screen) {
2046                 dev_err(dev_drv->dev, "screen is null!\n");
2047                 return -ENOENT;
2048         }
2049         if (win_id == 0) {
2050                 win_0_1_display(lcdc_dev, win);
2051         } else if (win_id == 1) {
2052                 win_0_1_display(lcdc_dev, win);
2053         } else if (win_id == 2) {
2054                 win_2_3_display(lcdc_dev, win);
2055         } else if (win_id == 3) {
2056                 win_2_3_display(lcdc_dev, win);
2057         } else if (win_id == 4) {
2058                 hwc_display(lcdc_dev, win);
2059         } else {
2060                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2061                 return -EINVAL;
2062         }
2063
2064         /*this is the first frame of the system ,enable frame start interrupt */
2065         if ((dev_drv->first_frame)) {
2066                 dev_drv->first_frame = 0;
2067                 rk3368_lcdc_enable_irq(dev_drv);
2068         }
2069 #if defined(WAIT_FOR_SYNC)
2070         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2071         init_completion(&dev_drv->frame_done);
2072         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2073         timeout =
2074             wait_for_completion_timeout(&dev_drv->frame_done,
2075                                         msecs_to_jiffies(dev_drv->
2076                                                          cur_screen->ft + 5));
2077         if (!timeout && (!dev_drv->frame_done.done)) {
2078                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2079                 return -ETIMEDOUT;
2080         }
2081 #endif
2082         return 0;
2083 }
2084
2085 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2086 {
2087         u16 srcW;
2088         u16 srcH;
2089         u16 dstW;
2090         u16 dstH;
2091         u16 yrgb_srcW;
2092         u16 yrgb_srcH;
2093         u16 yrgb_dstW;
2094         u16 yrgb_dstH;
2095         u32 yrgb_vscalednmult;
2096         u32 yrgb_xscl_factor;
2097         u32 yrgb_yscl_factor;
2098         u8 yrgb_vsd_bil_gt2 = 0;
2099         u8 yrgb_vsd_bil_gt4 = 0;
2100
2101         u16 cbcr_srcW;
2102         u16 cbcr_srcH;
2103         u16 cbcr_dstW;
2104         u16 cbcr_dstH;
2105         u32 cbcr_vscalednmult;
2106         u32 cbcr_xscl_factor;
2107         u32 cbcr_yscl_factor;
2108         u8 cbcr_vsd_bil_gt2 = 0;
2109         u8 cbcr_vsd_bil_gt4 = 0;
2110         u8 yuv_fmt = 0;
2111
2112         srcW = win->area[0].xact;
2113         srcH = win->area[0].yact;
2114         dstW = win->area[0].xsize;
2115         dstH = win->area[0].ysize;
2116
2117         /*yrgb scl mode */
2118         yrgb_srcW = srcW;
2119         yrgb_srcH = srcH;
2120         yrgb_dstW = dstW;
2121         yrgb_dstH = dstH;
2122         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2123                 pr_err("ERROR: yrgb scale exceed 8,");
2124                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2125                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2126         }
2127         if (yrgb_srcW < yrgb_dstW)
2128                 win->yrgb_hor_scl_mode = SCALE_UP;
2129         else if (yrgb_srcW > yrgb_dstW)
2130                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2131         else
2132                 win->yrgb_hor_scl_mode = SCALE_NONE;
2133
2134         if (yrgb_srcH < yrgb_dstH)
2135                 win->yrgb_ver_scl_mode = SCALE_UP;
2136         else if (yrgb_srcH > yrgb_dstH)
2137                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2138         else
2139                 win->yrgb_ver_scl_mode = SCALE_NONE;
2140
2141         /*cbcr scl mode */
2142         switch (win->area[0].format) {
2143         case YUV422:
2144         case YUV422_A:
2145                 cbcr_srcW = srcW / 2;
2146                 cbcr_dstW = dstW;
2147                 cbcr_srcH = srcH;
2148                 cbcr_dstH = dstH;
2149                 yuv_fmt = 1;
2150                 break;
2151         case YUV420:
2152         case YUV420_A:
2153                 cbcr_srcW = srcW / 2;
2154                 cbcr_dstW = dstW;
2155                 cbcr_srcH = srcH / 2;
2156                 cbcr_dstH = dstH;
2157                 yuv_fmt = 1;
2158                 break;
2159         case YUV444:
2160         case YUV444_A:
2161                 cbcr_srcW = srcW;
2162                 cbcr_dstW = dstW;
2163                 cbcr_srcH = srcH;
2164                 cbcr_dstH = dstH;
2165                 yuv_fmt = 1;
2166                 break;
2167         default:
2168                 cbcr_srcW = 0;
2169                 cbcr_dstW = 0;
2170                 cbcr_srcH = 0;
2171                 cbcr_dstH = 0;
2172                 yuv_fmt = 0;
2173                 break;
2174         }
2175         if (yuv_fmt) {
2176                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2177                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2178                         pr_err("ERROR: cbcr scale exceed 8,");
2179                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2180                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2181                 }
2182         }
2183
2184         if (cbcr_srcW < cbcr_dstW)
2185                 win->cbr_hor_scl_mode = SCALE_UP;
2186         else if (cbcr_srcW > cbcr_dstW)
2187                 win->cbr_hor_scl_mode = SCALE_DOWN;
2188         else
2189                 win->cbr_hor_scl_mode = SCALE_NONE;
2190
2191         if (cbcr_srcH < cbcr_dstH)
2192                 win->cbr_ver_scl_mode = SCALE_UP;
2193         else if (cbcr_srcH > cbcr_dstH)
2194                 win->cbr_ver_scl_mode = SCALE_DOWN;
2195         else
2196                 win->cbr_ver_scl_mode = SCALE_NONE;
2197
2198         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2199             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2200             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2201             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2202             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2203             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2204             win->cbr_ver_scl_mode);*/
2205
2206         /*line buffer mode */
2207         if ((win->area[0].format == YUV422) ||
2208             (win->area[0].format == YUV420) ||
2209             (win->area[0].format == YUV422_A) ||
2210             (win->area[0].format == YUV420_A)) {
2211                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2212                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2213                             (cbcr_dstW == 0))
2214                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2215                                        cbcr_dstW);
2216                         else if (cbcr_dstW > 1280)
2217                                 win->win_lb_mode = LB_YUV_3840X5;
2218                         else
2219                                 win->win_lb_mode = LB_YUV_2560X8;
2220                 } else {        /*SCALE_UP or SCALE_NONE */
2221                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2222                             (cbcr_srcW == 0))
2223                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2224                                        cbcr_srcW);
2225                         else if (cbcr_srcW > 1280)
2226                                 win->win_lb_mode = LB_YUV_3840X5;
2227                         else
2228                                 win->win_lb_mode = LB_YUV_2560X8;
2229                 }
2230         } else {
2231                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2232                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2233                             (yrgb_dstW == 0))
2234                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2235                         else if (yrgb_dstW > 2560)
2236                                 win->win_lb_mode = LB_RGB_3840X2;
2237                         else if (yrgb_dstW > 1920)
2238                                 win->win_lb_mode = LB_RGB_2560X4;
2239                         else if (yrgb_dstW > 1280)
2240                                 win->win_lb_mode = LB_RGB_1920X5;
2241                         else
2242                                 win->win_lb_mode = LB_RGB_1280X8;
2243                 } else {        /*SCALE_UP or SCALE_NONE */
2244                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2245                             (yrgb_srcW == 0))
2246                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2247                         else if (yrgb_srcW > 2560)
2248                                 win->win_lb_mode = LB_RGB_3840X2;
2249                         else if (yrgb_srcW > 1920)
2250                                 win->win_lb_mode = LB_RGB_2560X4;
2251                         else if (yrgb_srcW > 1280)
2252                                 win->win_lb_mode = LB_RGB_1920X5;
2253                         else
2254                                 win->win_lb_mode = LB_RGB_1280X8;
2255                 }
2256         }
2257         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2258
2259         /*vsd/vsu scale ALGORITHM */
2260         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2261         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2262         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2263         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2264         switch (win->win_lb_mode) {
2265         case LB_YUV_3840X5:
2266         case LB_YUV_2560X8:
2267         case LB_RGB_1920X5:
2268         case LB_RGB_1280X8:
2269                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2270                 win->cbr_vsu_mode = SCALE_UP_BIC;
2271                 break;
2272         case LB_RGB_3840X2:
2273                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2274                         pr_err("ERROR : not allow yrgb ver scale\n");
2275                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2276                         pr_err("ERROR : not allow cbcr ver scale\n");
2277                 break;
2278         case LB_RGB_2560X4:
2279                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2280                 win->cbr_vsu_mode = SCALE_UP_BIL;
2281                 break;
2282         default:
2283                 pr_info("%s:un supported win_lb_mode:%d\n",
2284                         __func__, win->win_lb_mode);
2285                 break;
2286         }
2287         if (win->mirror_en == 1) {      /*interlace mode must bill */
2288                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2289         }
2290
2291         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2292             (win->area[0].fbdc_en == 1)) {
2293                 /*in this pattern,use bil mode,not support souble scd,
2294                 use avg mode, support double scd, but aclk should be
2295                 bigger than dclk,aclk>>dclk */
2296                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2297                         pr_err("ERROR : fbdc mode,not support y scale down:");
2298                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2299                                yrgb_srcH, yrgb_dstH);
2300                 }
2301         }
2302         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2303             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2304             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2305
2306         /*SCALE FACTOR */
2307
2308         /*(1.1)YRGB HOR SCALE FACTOR */
2309         switch (win->yrgb_hor_scl_mode) {
2310         case SCALE_NONE:
2311                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2312                 break;
2313         case SCALE_UP:
2314                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2315                 break;
2316         case SCALE_DOWN:
2317                 switch (win->yrgb_hsd_mode) {
2318                 case SCALE_DOWN_BIL:
2319                         yrgb_xscl_factor =
2320                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2321                         break;
2322                 case SCALE_DOWN_AVG:
2323                         yrgb_xscl_factor =
2324                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2325                         break;
2326                 default:
2327                         pr_info(
2328                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2329                                win->yrgb_hsd_mode);
2330                         break;
2331                 }
2332                 break;
2333         default:
2334                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2335                         __func__, win->yrgb_hor_scl_mode);
2336                 break;
2337         }                       /*win->yrgb_hor_scl_mode */
2338
2339         /*(1.2)YRGB VER SCALE FACTOR */
2340         switch (win->yrgb_ver_scl_mode) {
2341         case SCALE_NONE:
2342                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2343                 break;
2344         case SCALE_UP:
2345                 switch (win->yrgb_vsu_mode) {
2346                 case SCALE_UP_BIL:
2347                         yrgb_yscl_factor =
2348                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2349                         break;
2350                 case SCALE_UP_BIC:
2351                         if (yrgb_srcH < 3) {
2352                                 pr_err("yrgb_srcH should be");
2353                                 pr_err(" greater than 3 !!!\n");
2354                         }
2355                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2356                                                                 yrgb_dstH);
2357                         break;
2358                 default:
2359                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2360                                 __func__, win->yrgb_vsu_mode);
2361                         break;
2362                 }
2363                 break;
2364         case SCALE_DOWN:
2365                 switch (win->yrgb_vsd_mode) {
2366                 case SCALE_DOWN_BIL:
2367                         yrgb_vscalednmult =
2368                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2369                                                             yrgb_dstH);
2370                         yrgb_yscl_factor =
2371                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2372                                                            yrgb_vscalednmult);
2373                         if (yrgb_yscl_factor >= 0x2000) {
2374                                 pr_err("yrgb_yscl_factor should be ");
2375                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2376                                        yrgb_yscl_factor);
2377                         }
2378                         if (yrgb_vscalednmult == 4) {
2379                                 yrgb_vsd_bil_gt4 = 1;
2380                                 yrgb_vsd_bil_gt2 = 0;
2381                         } else if (yrgb_vscalednmult == 2) {
2382                                 yrgb_vsd_bil_gt4 = 0;
2383                                 yrgb_vsd_bil_gt2 = 1;
2384                         } else {
2385                                 yrgb_vsd_bil_gt4 = 0;
2386                                 yrgb_vsd_bil_gt2 = 0;
2387                         }
2388                         break;
2389                 case SCALE_DOWN_AVG:
2390                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2391                                                                  yrgb_dstH);
2392                         break;
2393                 default:
2394                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2395                                 __func__, win->yrgb_vsd_mode);
2396                         break;
2397                 }               /*win->yrgb_vsd_mode */
2398                 break;
2399         default:
2400                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2401                         __func__, win->yrgb_ver_scl_mode);
2402                 break;
2403         }
2404         win->scale_yrgb_x = yrgb_xscl_factor;
2405         win->scale_yrgb_y = yrgb_yscl_factor;
2406         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2407         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2408         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2409             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2410
2411         /*(2.1)CBCR HOR SCALE FACTOR */
2412         switch (win->cbr_hor_scl_mode) {
2413         case SCALE_NONE:
2414                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2415                 break;
2416         case SCALE_UP:
2417                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2418                 break;
2419         case SCALE_DOWN:
2420                 switch (win->cbr_hsd_mode) {
2421                 case SCALE_DOWN_BIL:
2422                         cbcr_xscl_factor =
2423                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2424                         break;
2425                 case SCALE_DOWN_AVG:
2426                         cbcr_xscl_factor =
2427                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2428                         break;
2429                 default:
2430                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2431                                 __func__, win->cbr_hsd_mode);
2432                         break;
2433                 }
2434                 break;
2435         default:
2436                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2437                         __func__, win->cbr_hor_scl_mode);
2438                 break;
2439         }                       /*win->cbr_hor_scl_mode */
2440
2441         /*(2.2)CBCR VER SCALE FACTOR */
2442         switch (win->cbr_ver_scl_mode) {
2443         case SCALE_NONE:
2444                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2445                 break;
2446         case SCALE_UP:
2447                 switch (win->cbr_vsu_mode) {
2448                 case SCALE_UP_BIL:
2449                         cbcr_yscl_factor =
2450                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2451                         break;
2452                 case SCALE_UP_BIC:
2453                         if (cbcr_srcH < 3) {
2454                                 pr_err("cbcr_srcH should be ");
2455                                 pr_err("greater than 3 !!!\n");
2456                         }
2457                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2458                                                                 cbcr_dstH);
2459                         break;
2460                 default:
2461                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2462                                 __func__, win->cbr_vsu_mode);
2463                         break;
2464                 }
2465                 break;
2466         case SCALE_DOWN:
2467                 switch (win->cbr_vsd_mode) {
2468                 case SCALE_DOWN_BIL:
2469                         cbcr_vscalednmult =
2470                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2471                                                             cbcr_dstH);
2472                         cbcr_yscl_factor =
2473                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2474                                                            cbcr_vscalednmult);
2475                         if (cbcr_yscl_factor >= 0x2000) {
2476                                 pr_err("cbcr_yscl_factor should be less ");
2477                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2478                                        cbcr_yscl_factor);
2479                         }
2480
2481                         if (cbcr_vscalednmult == 4) {
2482                                 cbcr_vsd_bil_gt4 = 1;
2483                                 cbcr_vsd_bil_gt2 = 0;
2484                         } else if (cbcr_vscalednmult == 2) {
2485                                 cbcr_vsd_bil_gt4 = 0;
2486                                 cbcr_vsd_bil_gt2 = 1;
2487                         } else {
2488                                 cbcr_vsd_bil_gt4 = 0;
2489                                 cbcr_vsd_bil_gt2 = 0;
2490                         }
2491                         break;
2492                 case SCALE_DOWN_AVG:
2493                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2494                                                                  cbcr_dstH);
2495                         break;
2496                 default:
2497                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2498                                 __func__, win->cbr_vsd_mode);
2499                         break;
2500                 }
2501                 break;
2502         default:
2503                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2504                         __func__, win->cbr_ver_scl_mode);
2505                 break;
2506         }
2507         win->scale_cbcr_x = cbcr_xscl_factor;
2508         win->scale_cbcr_y = cbcr_yscl_factor;
2509         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2510         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2511
2512         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2513             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2514         return 0;
2515 }
2516
2517 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2518                      struct rk_lcdc_win_area *area)
2519 {
2520         int pos;
2521
2522         if (screen->x_mirror && mirror_en)
2523                 pr_err("not support both win and global mirror\n");
2524
2525         if ((!mirror_en) && (!screen->x_mirror))
2526                 pos = area->xpos + screen->mode.left_margin +
2527                         screen->mode.hsync_len;
2528         else
2529                 pos = screen->mode.xres - area->xpos -
2530                         area->xsize + screen->mode.left_margin +
2531                         screen->mode.hsync_len;
2532
2533         return pos;
2534 }
2535
2536 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2537                      struct rk_lcdc_win_area *area)
2538 {
2539         int pos;
2540
2541         if (screen->y_mirror && mirror_en)
2542                 pr_err("not support both win and global mirror\n");
2543
2544         if ((!mirror_en) && (!screen->y_mirror))
2545                 pos = area->ypos + screen->mode.upper_margin +
2546                         screen->mode.vsync_len;
2547         else
2548                 pos = screen->mode.yres - area->ypos -
2549                         area->ysize + screen->mode.upper_margin +
2550                         screen->mode.vsync_len;
2551
2552         return pos;
2553 }
2554
2555 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2556                            struct rk_screen *screen, struct rk_lcdc_win *win)
2557 {
2558         u32 xact, yact, xvir, yvir, xpos, ypos;
2559         u8 fmt_cfg = 0, swap_rb;
2560         char fmt[9] = "NULL";
2561
2562         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2563         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2564
2565         spin_lock(&lcdc_dev->reg_lock);
2566         if (likely(lcdc_dev->clk_on)) {
2567                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2568                 switch (win->area[0].format) {
2569                 case ARGB888:
2570                         fmt_cfg = 0;
2571                         swap_rb = 0;
2572                         win->fmt_10 = 0;
2573                         break;
2574                 case XBGR888:
2575                 case ABGR888:
2576                         fmt_cfg = 0;
2577                         swap_rb = 1;
2578                         win->fmt_10 = 0;
2579                         break;
2580                 case RGB888:
2581                         fmt_cfg = 1;
2582                         swap_rb = 0;
2583                         win->fmt_10 = 0;
2584                         break;
2585                 case RGB565:
2586                         fmt_cfg = 2;
2587                         swap_rb = 0;
2588                         win->fmt_10 = 0;
2589                         break;
2590                 case YUV422:
2591                         fmt_cfg = 5;
2592                         swap_rb = 0;
2593                         win->fmt_10 = 0;
2594                         break;
2595                 case YUV420:
2596                         fmt_cfg = 4;
2597                         swap_rb = 0;
2598                         win->fmt_10 = 0;
2599                         break;
2600                 case YUV444:
2601                         fmt_cfg = 6;
2602                         swap_rb = 0;
2603                         win->fmt_10 = 0;
2604                         break;
2605                 case YUV422_A:
2606                         fmt_cfg = 5;
2607                         swap_rb = 0;
2608                         win->fmt_10 = 1;
2609                         break;
2610                 case YUV420_A:
2611                         fmt_cfg = 4;
2612                         swap_rb = 0;
2613                         win->fmt_10 = 1;
2614                         break;
2615                 case YUV444_A:
2616                         fmt_cfg = 6;
2617                         swap_rb = 0;
2618                         win->fmt_10 = 1;
2619                         break;
2620                 default:
2621                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2622                                 __func__);
2623                         break;
2624                 }
2625                 win->area[0].fmt_cfg = fmt_cfg;
2626                 win->area[0].swap_rb = swap_rb;
2627                 win->area[0].dsp_stx = xpos;
2628                 win->area[0].dsp_sty = ypos;
2629                 xact = win->area[0].xact;
2630                 yact = win->area[0].yact;
2631                 xvir = win->area[0].xvir;
2632                 yvir = win->area[0].yvir;
2633         }
2634         if (win->area[0].fbdc_en)
2635                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2636         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2637         spin_unlock(&lcdc_dev->reg_lock);
2638
2639         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2640             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2641             xact, yact, win->area[0].xsize);
2642         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2643             win->area[0].ysize, xvir, yvir, xpos, ypos);
2644
2645         return 0;
2646 }
2647
2648
2649 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2650                            struct rk_screen *screen, struct rk_lcdc_win *win)
2651 {
2652         int i;
2653         u8 fmt_cfg, swap_rb;
2654         char fmt[9] = "NULL";
2655
2656         if (win->mirror_en)
2657                 pr_err("win[%d] not support y mirror\n", win->id);
2658         spin_lock(&lcdc_dev->reg_lock);
2659         if (likely(lcdc_dev->clk_on)) {
2660                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2661                 for (i = 0; i < win->area_num; i++) {
2662                         switch (win->area[i].format) {
2663                         case ARGB888:
2664                                 fmt_cfg = 0;
2665                                 swap_rb = 0;
2666                                 break;
2667                         case XBGR888:
2668                         case ABGR888:
2669                                 fmt_cfg = 0;
2670                                 swap_rb = 1;
2671                                 break;
2672                         case RGB888:
2673                                 fmt_cfg = 1;
2674                                 swap_rb = 0;
2675                                 break;
2676                         case RGB565:
2677                                 fmt_cfg = 2;
2678                                 swap_rb = 0;
2679                                 break;
2680                         default:
2681                                 dev_err(lcdc_dev->driver.dev,
2682                                         "%s:un supported format!\n", __func__);
2683                                 break;
2684                         }
2685                         win->area[i].fmt_cfg = fmt_cfg;
2686                         win->area[i].swap_rb = swap_rb;
2687                         win->area[i].dsp_stx =
2688                                         dsp_x_pos(win->mirror_en, screen,
2689                                                   &win->area[i]);
2690                         win->area[i].dsp_sty =
2691                                         dsp_y_pos(win->mirror_en, screen,
2692                                                   &win->area[i]);
2693
2694                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2695                             get_format_string(win->area[i].format, fmt),
2696                             win->area[i].xsize, win->area[i].ysize,
2697                             win->area[i].xpos, win->area[i].ypos);
2698                 }
2699         }
2700         if (win->area[0].fbdc_en)
2701                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2702         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2703         spin_unlock(&lcdc_dev->reg_lock);
2704         return 0;
2705 }
2706
2707 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2708                        struct rk_screen *screen, struct rk_lcdc_win *win)
2709 {
2710         u32 xact, yact, xvir, yvir, xpos, ypos;
2711         u8 fmt_cfg = 0, swap_rb;
2712         char fmt[9] = "NULL";
2713
2714         xpos = win->area[0].xpos + screen->mode.left_margin +
2715             screen->mode.hsync_len;
2716         ypos = win->area[0].ypos + screen->mode.upper_margin +
2717             screen->mode.vsync_len;
2718
2719         spin_lock(&lcdc_dev->reg_lock);
2720         if (likely(lcdc_dev->clk_on)) {
2721                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2722                 switch (win->area[0].format) {
2723                 case ARGB888:
2724                         fmt_cfg = 0;
2725                         swap_rb = 0;
2726                         break;
2727                 case XBGR888:
2728                 case ABGR888:
2729                         fmt_cfg = 0;
2730                         swap_rb = 1;
2731                         break;
2732                 case RGB888:
2733                         fmt_cfg = 1;
2734                         swap_rb = 0;
2735                         break;
2736                 case RGB565:
2737                         fmt_cfg = 2;
2738                         swap_rb = 0;
2739                         break;
2740                 default:
2741                         dev_err(lcdc_dev->driver.dev,
2742                                 "%s:un supported format!\n", __func__);
2743                         break;
2744                 }
2745                 win->area[0].fmt_cfg = fmt_cfg;
2746                 win->area[0].swap_rb = swap_rb;
2747                 win->area[0].dsp_stx = xpos;
2748                 win->area[0].dsp_sty = ypos;
2749                 xact = win->area[0].xact;
2750                 yact = win->area[0].yact;
2751                 xvir = win->area[0].xvir;
2752                 yvir = win->area[0].yvir;
2753         }
2754         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2755         spin_unlock(&lcdc_dev->reg_lock);
2756
2757         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2758             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2759             xact, yact, win->area[0].xsize);
2760         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2761             win->area[0].ysize, xvir, yvir, xpos, ypos);
2762         return 0;
2763 }
2764
2765 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2766 {
2767         struct lcdc_device *lcdc_dev =
2768             container_of(dev_drv, struct lcdc_device, driver);
2769         struct rk_lcdc_win *win = NULL;
2770         struct rk_screen *screen = dev_drv->cur_screen;
2771
2772         win = dev_drv->win[win_id];
2773         switch (win_id) {
2774         case 0:
2775                 win_0_1_set_par(lcdc_dev, screen, win);
2776                 break;
2777         case 1:
2778                 win_0_1_set_par(lcdc_dev, screen, win);
2779                 break;
2780         case 2:
2781                 win_2_3_set_par(lcdc_dev, screen, win);
2782                 break;
2783         case 3:
2784                 win_2_3_set_par(lcdc_dev, screen, win);
2785                 break;
2786         case 4:
2787                 hwc_set_par(lcdc_dev, screen, win);
2788                 break;
2789         default:
2790                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2791                 break;
2792         }
2793         return 0;
2794 }
2795
2796 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2797                              unsigned long arg, int win_id)
2798 {
2799         struct lcdc_device *lcdc_dev =
2800             container_of(dev_drv, struct lcdc_device, driver);
2801         u32 panel_size[2];
2802         void __user *argp = (void __user *)arg;
2803         struct color_key_cfg clr_key_cfg;
2804
2805         switch (cmd) {
2806         case RK_FBIOGET_PANEL_SIZE:
2807                 panel_size[0] = lcdc_dev->screen->mode.xres;
2808                 panel_size[1] = lcdc_dev->screen->mode.yres;
2809                 if (copy_to_user(argp, panel_size, 8))
2810                         return -EFAULT;
2811                 break;
2812         case RK_FBIOPUT_COLOR_KEY_CFG:
2813                 if (copy_from_user(&clr_key_cfg, argp,
2814                                    sizeof(struct color_key_cfg)))
2815                         return -EFAULT;
2816                 rk3368_lcdc_clr_key_cfg(dev_drv);
2817                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2818                             clr_key_cfg.win0_color_key_cfg);
2819                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2820                             clr_key_cfg.win1_color_key_cfg);
2821                 break;
2822
2823         default:
2824                 break;
2825         }
2826         return 0;
2827 }
2828
2829 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2830 {
2831         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2832                                                     struct lcdc_device, driver);
2833         /*struct device_node *backlight;*/
2834
2835         if (lcdc_dev->backlight)
2836                 return 0;
2837 #if 0
2838         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2839         if (backlight) {
2840                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2841                 if (!lcdc_dev->backlight)
2842                         dev_info(lcdc_dev->dev, "No find backlight device\n");
2843         } else {
2844                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
2845         }
2846 #endif
2847         return 0;
2848 }
2849
2850 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2851 {
2852         u32 reg;
2853         struct lcdc_device *lcdc_dev =
2854             container_of(dev_drv, struct lcdc_device, driver);
2855         if (dev_drv->suspend_flag)
2856                 return 0;
2857         /* close the backlight */
2858         /*rk3368_lcdc_get_backlight_device(dev_drv);
2859         if (lcdc_dev->backlight) {
2860                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
2861                 backlight_update_status(lcdc_dev->backlight);
2862         }*/
2863
2864         dev_drv->suspend_flag = 1;
2865         flush_kthread_worker(&dev_drv->update_regs_worker);
2866
2867         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg += 4)
2868                 lcdc_readl_backup(lcdc_dev, reg);
2869         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2870                 dev_drv->trsm_ops->disable();
2871
2872         spin_lock(&lcdc_dev->reg_lock);
2873         if (likely(lcdc_dev->clk_on)) {
2874                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2875                              v_DSP_BLANK_EN(1));
2876                 lcdc_msk_reg(lcdc_dev,
2877                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
2878                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
2879                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2880                              v_DSP_OUT_ZERO(1));
2881                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
2882                 lcdc_cfg_done(lcdc_dev);
2883
2884                 if (dev_drv->iommu_enabled) {
2885                         if (dev_drv->mmu_dev)
2886                                 rockchip_iovmm_deactivate(dev_drv->dev);
2887                 }
2888
2889                 spin_unlock(&lcdc_dev->reg_lock);
2890         } else {
2891                 spin_unlock(&lcdc_dev->reg_lock);
2892                 return 0;
2893         }
2894         rk3368_lcdc_clk_disable(lcdc_dev);
2895         rk_disp_pwr_disable(dev_drv);
2896         return 0;
2897 }
2898
2899 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2900 {
2901         struct lcdc_device *lcdc_dev =
2902             container_of(dev_drv, struct lcdc_device, driver);
2903
2904         if (!dev_drv->suspend_flag)
2905                 return 0;
2906         rk_disp_pwr_enable(dev_drv);
2907         dev_drv->suspend_flag = 0;
2908
2909         if (1/*lcdc_dev->atv_layer_cnt*/) {
2910                 rk3368_lcdc_clk_enable(lcdc_dev);
2911                 rk3368_lcdc_reg_restore(lcdc_dev);
2912
2913                 spin_lock(&lcdc_dev->reg_lock);
2914                 if (dev_drv->cur_screen->dsp_lut)
2915                         rk3368_lcdc_set_lut(dev_drv,
2916                                             dev_drv->cur_screen->dsp_lut);
2917
2918                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2919                              v_DSP_OUT_ZERO(0));
2920                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2921                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2922                              v_DSP_BLANK_EN(0));
2923                 lcdc_cfg_done(lcdc_dev);
2924
2925                 if (dev_drv->iommu_enabled) {
2926                         if (dev_drv->mmu_dev)
2927                                 rockchip_iovmm_activate(dev_drv->dev);
2928                 }
2929
2930                 spin_unlock(&lcdc_dev->reg_lock);
2931         }
2932
2933         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2934                 dev_drv->trsm_ops->enable();
2935
2936         return 0;
2937 }
2938
2939 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2940                              int win_id, int blank_mode)
2941 {
2942         switch (blank_mode) {
2943         case FB_BLANK_UNBLANK:
2944                 rk3368_lcdc_early_resume(dev_drv);
2945                 break;
2946         case FB_BLANK_NORMAL:
2947                 rk3368_lcdc_early_suspend(dev_drv);
2948                 break;
2949         default:
2950                 rk3368_lcdc_early_suspend(dev_drv);
2951                 break;
2952         }
2953
2954         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2955
2956         return 0;
2957 }
2958
2959 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2960 {
2961         return 0;
2962 }
2963
2964 /*overlay will be do at regupdate*/
2965 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2966                                bool set)
2967 {
2968         struct lcdc_device *lcdc_dev =
2969             container_of(dev_drv, struct lcdc_device, driver);
2970         struct rk_lcdc_win *win = NULL;
2971         int i, ovl;
2972         unsigned int mask, val;
2973         int z_order_num = 0;
2974         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
2975
2976         if (swap == 0) {
2977                 for (i = 0; i < 4; i++) {
2978                         win = dev_drv->win[i];
2979                         if (win->state == 1)
2980                                 z_order_num++;
2981                 }
2982                 for (i = 0; i < 4; i++) {
2983                         win = dev_drv->win[i];
2984                         if (win->state == 0)
2985                                 win->z_order = z_order_num++;
2986                         switch (win->z_order) {
2987                         case 0:
2988                                 layer0_sel = win->id;
2989                                 break;
2990                         case 1:
2991                                 layer1_sel = win->id;
2992                                 break;
2993                         case 2:
2994                                 layer2_sel = win->id;
2995                                 break;
2996                         case 3:
2997                                 layer3_sel = win->id;
2998                                 break;
2999                         default:
3000                                 break;
3001                         }
3002                 }
3003         } else {
3004                 layer0_sel = swap % 10;
3005                 layer1_sel = swap / 10 % 10;
3006                 layer2_sel = swap / 100 % 10;
3007                 layer3_sel = swap / 1000;
3008         }
3009
3010         spin_lock(&lcdc_dev->reg_lock);
3011         if (lcdc_dev->clk_on) {
3012                 if (set) {
3013                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3014                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3015                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3016                             v_DSP_LAYER1_SEL(layer1_sel) |
3017                             v_DSP_LAYER2_SEL(layer2_sel) |
3018                             v_DSP_LAYER3_SEL(layer3_sel);
3019                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3020                 } else {
3021                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3022                                                    m_DSP_LAYER0_SEL);
3023                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3024                                                    m_DSP_LAYER1_SEL);
3025                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3026                                                    m_DSP_LAYER2_SEL);
3027                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3028                                                    m_DSP_LAYER3_SEL);
3029                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3030                             layer1_sel * 10 + layer0_sel;
3031                 }
3032         } else {
3033                 ovl = -EPERM;
3034         }
3035         spin_unlock(&lcdc_dev->reg_lock);
3036
3037         return ovl;
3038 }
3039
3040 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3041 {
3042         if (!fmt)
3043                 return NULL;
3044
3045         switch (format) {
3046         case 0:
3047                 strcpy(fmt, "ARGB888");
3048                 break;
3049         case 1:
3050                 strcpy(fmt, "RGB888");
3051                 break;
3052         case 2:
3053                 strcpy(fmt, "RGB565");
3054                 break;
3055         case 4:
3056                 strcpy(fmt, "YCbCr420");
3057                 break;
3058         case 5:
3059                 strcpy(fmt, "YCbCr422");
3060                 break;
3061         case 6:
3062                 strcpy(fmt, "YCbCr444");
3063                 break;
3064         default:
3065                 strcpy(fmt, "invalid\n");
3066                 break;
3067         }
3068         return fmt;
3069 }
3070 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3071                                          char *buf, int win_id)
3072 {
3073         struct lcdc_device *lcdc_dev =
3074             container_of(dev_drv, struct lcdc_device, driver);
3075         struct rk_screen *screen = dev_drv->cur_screen;
3076         u16 hsync_len = screen->mode.hsync_len;
3077         u16 left_margin = screen->mode.left_margin;
3078         u16 vsync_len = screen->mode.vsync_len;
3079         u16 upper_margin = screen->mode.upper_margin;
3080         u32 h_pw_bp = hsync_len + left_margin;
3081         u32 v_pw_bp = vsync_len + upper_margin;
3082         u32 fmt_id;
3083         char format_w0[9] = "NULL";
3084         char format_w1[9] = "NULL";
3085         char format_w2_0[9] = "NULL";
3086         char format_w2_1[9] = "NULL";
3087         char format_w2_2[9] = "NULL";
3088         char format_w2_3[9] = "NULL";
3089         char format_w3_0[9] = "NULL";
3090         char format_w3_1[9] = "NULL";
3091         char format_w3_2[9] = "NULL";
3092         char format_w3_3[9] = "NULL";
3093         char dsp_buf[100];
3094         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3095         u32 y_factor, uv_factor;
3096         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3097         u8 w0_state, w1_state, w2_state, w3_state;
3098         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3099         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3100
3101         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3102         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3103         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3104         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3105         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3106         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3107
3108         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3109         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3110         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3111         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3112         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3113         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3114         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3115
3116         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3117         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3118         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3119         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3120         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3121         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3122         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3123         u32 dclk_freq;
3124         int size = 0;
3125
3126         dclk_freq = screen->mode.pixclock;
3127         /*rk3368_lcdc_reg_dump(dev_drv); */
3128
3129         spin_lock(&lcdc_dev->reg_lock);
3130         if (lcdc_dev->clk_on) {
3131                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3132                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3133                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3134                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3135                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3136                 /*WIN0 */
3137                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3138                 w0_state = win_ctrl & m_WIN0_EN;
3139                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3140                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3141                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3142                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3143                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3144                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3145                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3146                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3147                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3148                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3149                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3150                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3151                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3152                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3153                 if (w0_state) {
3154                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3155                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3156                 }
3157                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3158                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3159                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3160                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3161
3162                 /*WIN1 */
3163                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3164                 w1_state = win_ctrl & m_WIN1_EN;
3165                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3166                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3167                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3168                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3169                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3170                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3171                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3172                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3173                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3174                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3175                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3176                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3177                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3178                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3179                 if (w1_state) {
3180                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3181                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3182                 }
3183                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3184                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3185                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3186                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3187                 /*WIN2 */
3188                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3189                 w2_state = win_ctrl & m_WIN2_EN;
3190                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN) >> 4;
3191                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN) >> 5;
3192                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN) >> 6;
3193                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN) >> 7;
3194                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3195                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3196                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3197                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3198                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3199                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3200
3201                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3202                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3203                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3204                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3205                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3206                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3207                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3208                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3209
3210                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3211                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3212                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3213                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3214                 if (w2_0_state) {
3215                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3216                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3217                 }
3218                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3219                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3220                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3221                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3222                 if (w2_1_state) {
3223                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3224                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3225                 }
3226                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3227                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3228                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3229                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3230                 if (w2_2_state) {
3231                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3232                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3233                 }
3234                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3235                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3236                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3237                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3238                 if (w2_3_state) {
3239                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3240                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3241                 }
3242
3243                 /*WIN3 */
3244                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3245                 w3_state = win_ctrl & m_WIN3_EN;
3246                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3247                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 5;
3248                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 6;
3249                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 7;
3250                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3251                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3252                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3253                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3254                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3255                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3256                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3257                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3258                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3259                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3260                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3261                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3262                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3263                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3264                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3265                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3266                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3267                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3268                 if (w3_0_state) {
3269                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3270                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3271                 }
3272
3273                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3274                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3275                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3276                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3277                 if (w3_1_state) {
3278                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3279                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3280                 }
3281
3282                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3283                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3284                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3285                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3286                 if (w3_2_state) {
3287                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3288                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3289                 }
3290
3291                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3292                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3293                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3294                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3295                 if (w3_3_state) {
3296                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3297                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3298                 }
3299
3300         } else {
3301                 spin_unlock(&lcdc_dev->reg_lock);
3302                 return -EPERM;
3303         }
3304         spin_unlock(&lcdc_dev->reg_lock);
3305         size += snprintf(dsp_buf, 80,
3306                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3307                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3308         strcat(buf, dsp_buf);
3309         memset(dsp_buf, 0, sizeof(dsp_buf));
3310         /*win0*/
3311         size += snprintf(dsp_buf, 80,
3312                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3313                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3314         strcat(buf, dsp_buf);
3315         memset(dsp_buf, 0, sizeof(dsp_buf));
3316
3317         size += snprintf(dsp_buf, 80,
3318                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3319                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3320         strcat(buf, dsp_buf);
3321         memset(dsp_buf, 0, sizeof(dsp_buf));
3322
3323         size += snprintf(dsp_buf, 80,
3324                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3325                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3326         strcat(buf, dsp_buf);
3327         memset(dsp_buf, 0, sizeof(dsp_buf));
3328
3329         size += snprintf(dsp_buf, 80,
3330                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3331                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3332                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3333         strcat(buf, dsp_buf);
3334         memset(dsp_buf, 0, sizeof(dsp_buf));
3335
3336         /*win1*/
3337         size += snprintf(dsp_buf, 80,
3338                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3339                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3340         strcat(buf, dsp_buf);
3341         memset(dsp_buf, 0, sizeof(dsp_buf));
3342
3343         size += snprintf(dsp_buf, 80,
3344                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3345                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3346         strcat(buf, dsp_buf);
3347         memset(dsp_buf, 0, sizeof(dsp_buf));
3348
3349         size += snprintf(dsp_buf, 80,
3350                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3351                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3352         strcat(buf, dsp_buf);
3353         memset(dsp_buf, 0, sizeof(dsp_buf));
3354
3355         size += snprintf(dsp_buf, 80,
3356                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3357                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3358                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3359         strcat(buf, dsp_buf);
3360         memset(dsp_buf, 0, sizeof(dsp_buf));
3361
3362         /*win2*/
3363         size += snprintf(dsp_buf, 80,
3364                  "win2:\n  state:%d\n",
3365                  w2_state);
3366         strcat(buf, dsp_buf);
3367         memset(dsp_buf, 0, sizeof(dsp_buf));
3368         /*area 0*/
3369         size += snprintf(dsp_buf, 80,
3370                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3371                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3372         strcat(buf, dsp_buf);
3373         memset(dsp_buf, 0, sizeof(dsp_buf));
3374         size += snprintf(dsp_buf, 80,
3375                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3376                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3377                  lcdc_readl(lcdc_dev, WIN2_MST0));
3378         strcat(buf, dsp_buf);
3379         memset(dsp_buf, 0, sizeof(dsp_buf));
3380
3381         /*area 1*/
3382         size += snprintf(dsp_buf, 80,
3383                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3384                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3385         strcat(buf, dsp_buf);
3386         memset(dsp_buf, 0, sizeof(dsp_buf));
3387         size += snprintf(dsp_buf, 80,
3388                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3389                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3390                  lcdc_readl(lcdc_dev, WIN2_MST1));
3391         strcat(buf, dsp_buf);
3392         memset(dsp_buf, 0, sizeof(dsp_buf));
3393
3394         /*area 2*/
3395         size += snprintf(dsp_buf, 80,
3396                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3397                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3398         strcat(buf, dsp_buf);
3399         memset(dsp_buf, 0, sizeof(dsp_buf));
3400         size += snprintf(dsp_buf, 80,
3401                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3402                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3403                  lcdc_readl(lcdc_dev, WIN2_MST2));
3404         strcat(buf, dsp_buf);
3405         memset(dsp_buf, 0, sizeof(dsp_buf));
3406
3407         /*area 3*/
3408         size += snprintf(dsp_buf, 80,
3409                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3410                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3411         strcat(buf, dsp_buf);
3412         memset(dsp_buf, 0, sizeof(dsp_buf));
3413         size += snprintf(dsp_buf, 80,
3414                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3415                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3416                  lcdc_readl(lcdc_dev, WIN2_MST3));
3417         strcat(buf, dsp_buf);
3418         memset(dsp_buf, 0, sizeof(dsp_buf));
3419
3420         /*win3*/
3421         size += snprintf(dsp_buf, 80,
3422                  "win3:\n  state:%d\n",
3423                  w3_state);
3424         strcat(buf, dsp_buf);
3425         memset(dsp_buf, 0, sizeof(dsp_buf));
3426         /*area 0*/
3427         size += snprintf(dsp_buf, 80,
3428                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3429                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3430         strcat(buf, dsp_buf);
3431         memset(dsp_buf, 0, sizeof(dsp_buf));
3432         size += snprintf(dsp_buf, 80,
3433                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3434                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3435                  lcdc_readl(lcdc_dev, WIN3_MST0));
3436         strcat(buf, dsp_buf);
3437         memset(dsp_buf, 0, sizeof(dsp_buf));
3438
3439         /*area 1*/
3440         size += snprintf(dsp_buf, 80,
3441                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3442                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3443         strcat(buf, dsp_buf);
3444         memset(dsp_buf, 0, sizeof(dsp_buf));
3445         size += snprintf(dsp_buf, 80,
3446                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3447                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3448                  lcdc_readl(lcdc_dev, WIN3_MST1));
3449         strcat(buf, dsp_buf);
3450         memset(dsp_buf, 0, sizeof(dsp_buf));
3451
3452         /*area 2*/
3453         size += snprintf(dsp_buf, 80,
3454                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3455                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3456         strcat(buf, dsp_buf);
3457         memset(dsp_buf, 0, sizeof(dsp_buf));
3458         size += snprintf(dsp_buf, 80,
3459                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3460                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3461                  lcdc_readl(lcdc_dev, WIN3_MST2));
3462         strcat(buf, dsp_buf);
3463         memset(dsp_buf, 0, sizeof(dsp_buf));
3464
3465         /*area 3*/
3466         size += snprintf(dsp_buf, 80,
3467                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3468                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3469         strcat(buf, dsp_buf);
3470         memset(dsp_buf, 0, sizeof(dsp_buf));
3471         size += snprintf(dsp_buf, 80,
3472                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3473                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3474                  lcdc_readl(lcdc_dev, WIN3_MST3));
3475         strcat(buf, dsp_buf);
3476         memset(dsp_buf, 0, sizeof(dsp_buf));
3477
3478         return size;
3479 }
3480
3481 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3482                                bool set)
3483 {
3484         struct lcdc_device *lcdc_dev =
3485             container_of(dev_drv, struct lcdc_device, driver);
3486         struct rk_screen *screen = dev_drv->cur_screen;
3487         u64 ft = 0;
3488         u32 dotclk;
3489         int ret;
3490         u32 pixclock;
3491         u32 x_total, y_total;
3492
3493         if (set) {
3494                 if (fps == 0) {
3495                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3496                         return 0;
3497                 }
3498                 ft = div_u64(1000000000000llu, fps);
3499                 x_total =
3500                     screen->mode.upper_margin + screen->mode.lower_margin +
3501                     screen->mode.yres + screen->mode.vsync_len;
3502                 y_total =
3503                     screen->mode.left_margin + screen->mode.right_margin +
3504                     screen->mode.xres + screen->mode.hsync_len;
3505                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3506                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3507                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3508         }
3509
3510         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3511         lcdc_dev->pixclock = pixclock;
3512         dev_drv->pixclock = lcdc_dev->pixclock;
3513         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3514         screen->ft = 1000 / fps;        /*one frame time in ms */
3515
3516         if (set)
3517                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3518                          clk_get_rate(lcdc_dev->dclk), fps);
3519
3520         return fps;
3521 }
3522
3523 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3524 {
3525         mutex_lock(&dev_drv->fb_win_id_mutex);
3526         if (order == FB_DEFAULT_ORDER)
3527                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3528         dev_drv->fb4_win_id = order / 10000;
3529         dev_drv->fb3_win_id = (order / 1000) % 10;
3530         dev_drv->fb2_win_id = (order / 100) % 10;
3531         dev_drv->fb1_win_id = (order / 10) % 10;
3532         dev_drv->fb0_win_id = order % 10;
3533         mutex_unlock(&dev_drv->fb_win_id_mutex);
3534
3535         return 0;
3536 }
3537
3538 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3539                                   const char *id)
3540 {
3541         int win_id = 0;
3542
3543         mutex_lock(&dev_drv->fb_win_id_mutex);
3544         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3545                 win_id = dev_drv->fb0_win_id;
3546         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3547                 win_id = dev_drv->fb1_win_id;
3548         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3549                 win_id = dev_drv->fb2_win_id;
3550         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3551                 win_id = dev_drv->fb3_win_id;
3552         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3553                 win_id = dev_drv->fb4_win_id;
3554         mutex_unlock(&dev_drv->fb_win_id_mutex);
3555
3556         return win_id;
3557 }
3558
3559 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3560 {
3561         struct lcdc_device *lcdc_dev =
3562             container_of(dev_drv, struct lcdc_device, driver);
3563         int i;
3564         unsigned int mask, val;
3565         struct rk_lcdc_win *win = NULL;
3566
3567         spin_lock(&lcdc_dev->reg_lock);
3568         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3569                      v_STANDBY_EN(lcdc_dev->standby));
3570         for (i = 0; i < 4; i++) {
3571                 win = dev_drv->win[i];
3572                 if ((win->state == 0) && (win->last_state == 1)) {
3573                         switch (win->id) {
3574                         case 0:
3575                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3576                                    for rk3288 to fix hw bug? */
3577                                 mask = m_WIN0_EN;
3578                                 val = v_WIN0_EN(0);
3579                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3580                                 break;
3581                         case 1:
3582                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3583                                    for rk3288 to fix hw bug? */
3584                                 mask = m_WIN1_EN;
3585                                 val = v_WIN1_EN(0);
3586                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3587                                 break;
3588                         case 2:
3589                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3590                                     m_WIN2_MST1_EN |
3591                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3592                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3593                                     v_WIN2_MST1_EN(0) |
3594                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3595                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3596                                 break;
3597                         case 3:
3598                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3599                                     m_WIN3_MST1_EN |
3600                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3601                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3602                                     v_WIN3_MST1_EN(0) |
3603                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3604                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3605                                 break;
3606                         case 4:
3607                                 mask = m_HWC_EN;
3608                                 val = v_HWC_EN(0);
3609                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3610                                 break;
3611                         default:
3612                                 break;
3613                         }
3614                 }
3615                 win->last_state = win->state;
3616         }
3617         lcdc_cfg_done(lcdc_dev);
3618         spin_unlock(&lcdc_dev->reg_lock);
3619         return 0;
3620 }
3621
3622 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3623 {
3624         struct lcdc_device *lcdc_dev =
3625             container_of(dev_drv, struct lcdc_device, driver);
3626         spin_lock(&lcdc_dev->reg_lock);
3627         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3628                      v_DIRECT_PATH_EN(open));
3629         lcdc_cfg_done(lcdc_dev);
3630         spin_unlock(&lcdc_dev->reg_lock);
3631         return 0;
3632 }
3633
3634 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3635 {
3636         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3637                                                     struct lcdc_device, driver);
3638         spin_lock(&lcdc_dev->reg_lock);
3639         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3640                      v_DIRECT_PATCH_SEL(win_id));
3641         lcdc_cfg_done(lcdc_dev);
3642         spin_unlock(&lcdc_dev->reg_lock);
3643         return 0;
3644 }
3645
3646 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3647 {
3648         struct lcdc_device *lcdc_dev =
3649             container_of(dev_drv, struct lcdc_device, driver);
3650         int ovl;
3651
3652         spin_lock(&lcdc_dev->reg_lock);
3653         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3654         spin_unlock(&lcdc_dev->reg_lock);
3655         return ovl;
3656 }
3657
3658 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3659                                       int enable)
3660 {
3661         struct lcdc_device *lcdc_dev =
3662             container_of(dev_drv, struct lcdc_device, driver);
3663         if (enable)
3664                 enable_irq(lcdc_dev->irq);
3665         else
3666                 disable_irq(lcdc_dev->irq);
3667         return 0;
3668 }
3669
3670 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3671 {
3672         struct lcdc_device *lcdc_dev =
3673             container_of(dev_drv, struct lcdc_device, driver);
3674         u32 int_reg;
3675         int ret;
3676
3677         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3678                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3679                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3680                         lcdc_dev->driver.frame_time.last_framedone_t =
3681                             lcdc_dev->driver.frame_time.framedone_t;
3682                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3683                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3684                                      m_LINE_FLAG0_INTR_CLR,
3685                                      v_LINE_FLAG0_INTR_CLR(1));
3686                         ret = RK_LF_STATUS_FC;
3687                 } else {
3688                         ret = RK_LF_STATUS_FR;
3689                 }
3690         } else {
3691                 ret = RK_LF_STATUS_NC;
3692         }
3693
3694         return ret;
3695 }
3696
3697 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3698                                     unsigned int *dsp_addr)
3699 {
3700         struct lcdc_device *lcdc_dev =
3701             container_of(dev_drv, struct lcdc_device, driver);
3702         spin_lock(&lcdc_dev->reg_lock);
3703         if (lcdc_dev->clk_on) {
3704                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3705                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3706                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3707                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3708         }
3709         spin_unlock(&lcdc_dev->reg_lock);
3710         return 0;
3711 }
3712
3713 static struct lcdc_cabc_mode cabc_mode[4] = {
3714         /* pixel_num,8 stage_up, stage_down */
3715         {5, 148, 20, 300},      /*mode 1 */
3716         {10, 148, 20, 300},     /*mode 2 */
3717         {15, 148, 20, 300},     /*mode 3 */
3718         {20, 148, 20, 300},     /*mode 4 */
3719 };
3720
3721 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3722 {
3723         struct lcdc_device *lcdc_dev =
3724             container_of(dev_drv, struct lcdc_device, driver);
3725         struct rk_screen *screen = dev_drv->cur_screen;
3726         u32 total_pixel, calc_pixel, stage_up, stage_down;
3727         u32 pixel_num, global_su;
3728         u32 stage_up_rec, stage_down_rec, global_su_rec;
3729         u32 mask = 0, val = 0, cabc_en = 0;
3730         u32 __maybe_unused max_mode_num =
3731             sizeof(cabc_mode) / sizeof(struct lcdc_cabc_mode);
3732
3733         dev_drv->cabc_mode = mode;
3734 #if 0/*ndef CONFIG_RK_FPGA*/
3735         /* iomux connect to vop or pwm */
3736         if (mode == 0) {
3737                 DBG(3, "close cabc and select rk pwm\n");
3738                 val = 0x30002;
3739                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3740                 cabc_en = 0;
3741         } else if (mode > 0 && mode <= max_mode_num) {
3742                 DBG(3, "open cabc and select vop pwm\n");
3743                 val = 0x30003;
3744                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3745                 cabc_en = 1;
3746         } else if (mode > 0x10 && mode <= (max_mode_num + 0x10)) {
3747                 DBG(3, "open cabc and select rk pwm\n");
3748                 val = 0x30003;
3749                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3750                 cabc_en = 1;
3751                 mode -= 0x10;
3752         } else if (mode == 0xff) {
3753                 DBG(3, "close cabc and select vop pwm\n");
3754                 val = 0x30002;
3755                 writel_relaxed(val, RK_GRF_VIRT + rk3368_GRF_GPIO3C_IOMUX);
3756                 cabc_en = 0;
3757         } else {
3758                 dev_err(lcdc_dev->dev, "invalid cabc mode value:%d", mode);
3759                 return 0;
3760         }
3761 #endif
3762         if (cabc_en == 0) {
3763                 spin_lock(&lcdc_dev->reg_lock);
3764                 if (lcdc_dev->clk_on) {
3765                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3766                                      m_CABC_EN, v_CABC_EN(0));
3767                         lcdc_cfg_done(lcdc_dev);
3768                 }
3769                 spin_unlock(&lcdc_dev->reg_lock);
3770                 return 0;
3771         }
3772
3773         total_pixel = screen->mode.xres * screen->mode.yres;
3774         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3775         calc_pixel = (total_pixel * pixel_num) / 1000;
3776         stage_up = cabc_mode[mode - 1].stage_up;
3777         stage_down = cabc_mode[mode - 1].stage_down;
3778         global_su = cabc_mode[mode - 1].global_su;
3779
3780         stage_up_rec = 256 * 256 / stage_up;
3781         stage_down_rec = 256 * 256 / stage_down;
3782         global_su_rec = 256 * 256 / global_su;
3783
3784         spin_lock(&lcdc_dev->reg_lock);
3785         if (lcdc_dev->clk_on) {
3786                 mask = m_CABC_CALC_PIXEL_NUM;
3787                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel);
3788                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3789
3790                 mask = m_CABC_TOTAL_PIXEL_NUM;
3791                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel);
3792                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3793
3794                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3795                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3796                 val = v_CABC_STAGE_UP(stage_up) |
3797                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3798                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3799                     v_CABC_GLOBAL_SU_REC(global_su_rec);
3800                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3801
3802                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3803                     m_CABC_GLOBAL_SU;
3804                 val = v_CABC_STAGE_DOWN(stage_down) |
3805                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3806                     v_CABC_GLOBAL_SU(global_su);
3807                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3808                 lcdc_cfg_done(lcdc_dev);
3809         }
3810         spin_unlock(&lcdc_dev->reg_lock);
3811
3812         return 0;
3813 }
3814
3815 /*
3816         a:[-30~0]:
3817             sin_hue = sin(a)*256 +0x100;
3818             cos_hue = cos(a)*256;
3819         a:[0~30]
3820             sin_hue = sin(a)*256;
3821             cos_hue = cos(a)*256;
3822 */
3823 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3824                                     bcsh_hue_mode mode)
3825 {
3826         struct lcdc_device *lcdc_dev =
3827             container_of(dev_drv, struct lcdc_device, driver);
3828         u32 val;
3829
3830         spin_lock(&lcdc_dev->reg_lock);
3831         if (lcdc_dev->clk_on) {
3832                 val = lcdc_readl(lcdc_dev, BCSH_H);
3833                 switch (mode) {
3834                 case H_SIN:
3835                         val &= m_BCSH_SIN_HUE;
3836                         break;
3837                 case H_COS:
3838                         val &= m_BCSH_COS_HUE;
3839                         val >>= 16;
3840                         break;
3841                 default:
3842                         break;
3843                 }
3844         }
3845         spin_unlock(&lcdc_dev->reg_lock);
3846
3847         return val;
3848 }
3849
3850 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3851                                     int sin_hue, int cos_hue)
3852 {
3853         struct lcdc_device *lcdc_dev =
3854             container_of(dev_drv, struct lcdc_device, driver);
3855         u32 mask, val;
3856
3857         spin_lock(&lcdc_dev->reg_lock);
3858         if (lcdc_dev->clk_on) {
3859                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3860                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3861                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3862                 lcdc_cfg_done(lcdc_dev);
3863         }
3864         spin_unlock(&lcdc_dev->reg_lock);
3865
3866         return 0;
3867 }
3868
3869 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3870                                     bcsh_bcs_mode mode, int value)
3871 {
3872         struct lcdc_device *lcdc_dev =
3873             container_of(dev_drv, struct lcdc_device, driver);
3874         u32 mask, val;
3875
3876         spin_lock(&lcdc_dev->reg_lock);
3877         if (lcdc_dev->clk_on) {
3878                 switch (mode) {
3879                 case BRIGHTNESS:
3880                         /*from 0 to 255,typical is 128 */
3881                         if (value < 0x80)
3882                                 value += 0x80;
3883                         else if (value >= 0x80)
3884                                 value = value - 0x80;
3885                         mask = m_BCSH_BRIGHTNESS;
3886                         val = v_BCSH_BRIGHTNESS(value);
3887                         break;
3888                 case CONTRAST:
3889                         /*from 0 to 510,typical is 256 */
3890                         mask = m_BCSH_CONTRAST;
3891                         val = v_BCSH_CONTRAST(value);
3892                         break;
3893                 case SAT_CON:
3894                         /*from 0 to 1015,typical is 256 */
3895                         mask = m_BCSH_SAT_CON;
3896                         val = v_BCSH_SAT_CON(value);
3897                         break;
3898                 default:
3899                         break;
3900                 }
3901                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3902                 lcdc_cfg_done(lcdc_dev);
3903         }
3904         spin_unlock(&lcdc_dev->reg_lock);
3905         return val;
3906 }
3907
3908 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3909                                     bcsh_bcs_mode mode)
3910 {
3911         struct lcdc_device *lcdc_dev =
3912             container_of(dev_drv, struct lcdc_device, driver);
3913         u32 val;
3914
3915         spin_lock(&lcdc_dev->reg_lock);
3916         if (lcdc_dev->clk_on) {
3917                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3918                 switch (mode) {
3919                 case BRIGHTNESS:
3920                         val &= m_BCSH_BRIGHTNESS;
3921                         if (val > 0x80)
3922                                 val -= 0x80;
3923                         else
3924                                 val += 0x80;
3925                         break;
3926                 case CONTRAST:
3927                         val &= m_BCSH_CONTRAST;
3928                         val >>= 8;
3929                         break;
3930                 case SAT_CON:
3931                         val &= m_BCSH_SAT_CON;
3932                         val >>= 20;
3933                         break;
3934                 default:
3935                         break;
3936                 }
3937         }
3938         spin_unlock(&lcdc_dev->reg_lock);
3939         return val;
3940 }
3941
3942 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3943 {
3944         struct lcdc_device *lcdc_dev =
3945             container_of(dev_drv, struct lcdc_device, driver);
3946         u32 mask, val;
3947
3948         spin_lock(&lcdc_dev->reg_lock);
3949         if (lcdc_dev->clk_on) {
3950                 if (open) {
3951                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
3952                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
3953                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
3954                         dev_drv->bcsh.enable = 1;
3955                 } else {
3956                         mask = m_BCSH_EN;
3957                         val = v_BCSH_EN(0);
3958                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3959                         dev_drv->bcsh.enable = 0;
3960                 }
3961                 rk3368_lcdc_bcsh_path_sel(dev_drv);
3962                 lcdc_cfg_done(lcdc_dev);
3963         }
3964         spin_unlock(&lcdc_dev->reg_lock);
3965         return 0;
3966 }
3967
3968 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
3969 {
3970         if (!enable || !dev_drv->bcsh.enable) {
3971                 rk3368_lcdc_open_bcsh(dev_drv, false);
3972                 return 0;
3973         }
3974
3975         if (dev_drv->bcsh.brightness <= 255 ||
3976             dev_drv->bcsh.contrast <= 510 ||
3977             dev_drv->bcsh.sat_con <= 1015 ||
3978             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3979                 rk3368_lcdc_open_bcsh(dev_drv, true);
3980                 if (dev_drv->bcsh.brightness <= 255)
3981                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3982                                                  dev_drv->bcsh.brightness);
3983                 if (dev_drv->bcsh.contrast <= 510)
3984                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3985                                                  dev_drv->bcsh.contrast);
3986                 if (dev_drv->bcsh.sat_con <= 1015)
3987                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3988                                                  dev_drv->bcsh.sat_con);
3989                 if (dev_drv->bcsh.sin_hue <= 511 &&
3990                     dev_drv->bcsh.cos_hue <= 511)
3991                         rk3368_lcdc_set_bcsh_hue(dev_drv,
3992                                                  dev_drv->bcsh.sin_hue,
3993                                                  dev_drv->bcsh.cos_hue);
3994         }
3995         return 0;
3996 }
3997
3998 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
3999 {
4000         struct lcdc_device *lcdc_dev =
4001             container_of(dev_drv, struct lcdc_device, driver);
4002
4003         if (enable) {
4004                 spin_lock(&lcdc_dev->reg_lock);
4005                 if (likely(lcdc_dev->clk_on)) {
4006                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4007                                      v_DSP_BLACK_EN(1));
4008                         lcdc_cfg_done(lcdc_dev);
4009                 }
4010                 spin_unlock(&lcdc_dev->reg_lock);
4011         } else {
4012                 spin_lock(&lcdc_dev->reg_lock);
4013                 if (likely(lcdc_dev->clk_on)) {
4014                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4015                                      v_DSP_BLACK_EN(0));
4016
4017                         lcdc_cfg_done(lcdc_dev);
4018                 }
4019                 spin_unlock(&lcdc_dev->reg_lock);
4020         }
4021
4022         return 0;
4023 }
4024
4025
4026 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4027                                        int enable)
4028 {
4029         struct lcdc_device *lcdc_dev =
4030             container_of(dev_drv, struct lcdc_device, driver);
4031
4032         rk3368_lcdc_get_backlight_device(dev_drv);
4033
4034         if (enable) {
4035                 /* close the backlight */
4036                 if (lcdc_dev->backlight) {
4037                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4038                         backlight_update_status(lcdc_dev->backlight);
4039                 }
4040                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4041                         dev_drv->trsm_ops->disable();
4042         } else {
4043                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4044                         dev_drv->trsm_ops->enable();
4045                 msleep(100);
4046                 /* open the backlight */
4047                 if (lcdc_dev->backlight) {
4048                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4049                         backlight_update_status(lcdc_dev->backlight);
4050                 }
4051         }
4052
4053         return 0;
4054 }
4055
4056 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4057         .open = rk3368_lcdc_open,
4058         .win_direct_en = rk3368_lcdc_win_direct_en,
4059         .load_screen = rk3368_load_screen,
4060         .set_par = rk3368_lcdc_set_par,
4061         .pan_display = rk3368_lcdc_pan_display,
4062         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4063         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4064         .blank = rk3368_lcdc_blank,
4065         .ioctl = rk3368_lcdc_ioctl,
4066         .suspend = rk3368_lcdc_early_suspend,
4067         .resume = rk3368_lcdc_early_resume,
4068         .get_win_state = rk3368_lcdc_get_win_state,
4069         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4070         .get_disp_info = rk3368_lcdc_get_disp_info,
4071         .fps_mgr = rk3368_lcdc_fps_mgr,
4072         .fb_get_win_id = rk3368_lcdc_get_win_id,
4073         .fb_win_remap = rk3368_fb_win_remap,
4074         .set_dsp_lut = rk3368_lcdc_set_lut,
4075         .poll_vblank = rk3368_lcdc_poll_vblank,
4076         .dpi_open = rk3368_lcdc_dpi_open,
4077         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4078         .dpi_status = rk3368_lcdc_dpi_status,
4079         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4080         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4081         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4082         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4083         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4084         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4085         .open_bcsh = rk3368_lcdc_open_bcsh,
4086         .dump_reg = rk3368_lcdc_reg_dump,
4087         .cfg_done = rk3368_lcdc_config_done,
4088         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4089         .dsp_black = rk3368_lcdc_dsp_black,
4090         .backlight_close = rk3368_lcdc_backlight_close,
4091         .mmu_en    = rk3368_lcdc_mmu_en,
4092 };
4093
4094 #ifdef LCDC_IRQ_EMPTY_DEBUG
4095 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4096                                  unsigned int intr_status)
4097 {
4098         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4099                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4100                              v_WIN0_EMPTY_INTR_CLR(1));
4101                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4102         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4103                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4104                              v_WIN1_EMPTY_INTR_CLR(1));
4105                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4106         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4107                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4108                              v_WIN2_EMPTY_INTR_CLR(1));
4109                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4110         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4111                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4112                              v_WIN3_EMPTY_INTR_CLR(1));
4113                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4114         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4115                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4116                              v_HWC_EMPTY_INTR_CLR(1));
4117                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4118         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4119                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4120                              v_POST_BUF_EMPTY_INTR_CLR(1));
4121                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4122         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4123                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4124                              v_PWM_GEN_INTR_CLR(1));
4125                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4126         }
4127         return 0;
4128 }
4129 #endif
4130
4131 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4132 {
4133         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4134         ktime_t timestamp = ktime_get();
4135         u32 intr_status;
4136
4137         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4138
4139         if (intr_status & m_FS_INTR_STS) {
4140                 timestamp = ktime_get();
4141                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4142                              v_FS_INTR_CLR(1));
4143                 /*if(lcdc_dev->driver.wait_fs){ */
4144                 if (0) {
4145                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4146                         complete(&(lcdc_dev->driver.frame_done));
4147                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4148                 }
4149 #ifdef CONFIG_DRM_ROCKCHIP
4150                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4151 #endif
4152                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4153                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4154
4155         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4156                 lcdc_dev->driver.frame_time.last_framedone_t =
4157                     lcdc_dev->driver.frame_time.framedone_t;
4158                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4159                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4160                              v_LINE_FLAG0_INTR_CLR(1));
4161         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4162                 /*line flag1 */
4163                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4164                              v_LINE_FLAG1_INTR_CLR(1));
4165         } else if (intr_status & m_FS_NEW_INTR_STS) {
4166                 /*new frame start */
4167                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4168                              v_FS_NEW_INTR_CLR(1));
4169         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4170                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4171                              v_BUS_ERROR_INTR_CLR(1));
4172                 dev_warn(lcdc_dev->dev, "bus error!");
4173         }
4174
4175         /* for win empty debug */
4176 #ifdef LCDC_IRQ_EMPTY_DEBUG
4177         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4178 #endif
4179         return IRQ_HANDLED;
4180 }
4181
4182 #if defined(CONFIG_PM)
4183 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4184 {
4185         return 0;
4186 }
4187
4188 static int rk3368_lcdc_resume(struct platform_device *pdev)
4189 {
4190         return 0;
4191 }
4192 #else
4193 #define rk3368_lcdc_suspend NULL
4194 #define rk3368_lcdc_resume  NULL
4195 #endif
4196
4197 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4198 {
4199         struct device_node *np = lcdc_dev->dev->of_node;
4200         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4201         int val;
4202
4203         if (of_property_read_u32(np, "rockchip,prop", &val))
4204                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4205         else
4206                 lcdc_dev->prop = val;
4207
4208         if (of_property_read_u32(np, "rockchip,mirror", &val))
4209                 dev_drv->rotate_mode = NO_MIRROR;
4210         else
4211                 dev_drv->rotate_mode = val;
4212
4213         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4214                 dev_drv->cabc_mode = 0; /* default set close cabc */
4215         else
4216                 dev_drv->cabc_mode = val;
4217
4218         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4219                 /*default set it as 3.xv power supply */
4220                 lcdc_dev->pwr18 = false;
4221         else
4222                 lcdc_dev->pwr18 = (val ? true : false);
4223
4224         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4225                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4226         else
4227                 dev_drv->fb_win_map = val;
4228
4229         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4230                 dev_drv->bcsh.enable = false;
4231         else
4232                 dev_drv->bcsh.enable = (val ? true : false);
4233
4234         if (of_property_read_u32(np, "rockchip,brightness", &val))
4235                 dev_drv->bcsh.brightness = 0xffff;
4236         else
4237                 dev_drv->bcsh.brightness = val;
4238
4239         if (of_property_read_u32(np, "rockchip,contrast", &val))
4240                 dev_drv->bcsh.contrast = 0xffff;
4241         else
4242                 dev_drv->bcsh.contrast = val;
4243
4244         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4245                 dev_drv->bcsh.sat_con = 0xffff;
4246         else
4247                 dev_drv->bcsh.sat_con = val;
4248
4249         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4250                 dev_drv->bcsh.sin_hue = 0xffff;
4251                 dev_drv->bcsh.cos_hue = 0xffff;
4252         } else {
4253                 dev_drv->bcsh.sin_hue = val & 0xff;
4254                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4255         }
4256
4257 #if defined(CONFIG_ROCKCHIP_IOMMU)
4258         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4259                 dev_drv->iommu_enabled = 0;
4260         else
4261                 dev_drv->iommu_enabled = val;
4262 #else
4263         dev_drv->iommu_enabled = 0;
4264 #endif
4265         return 0;
4266 }
4267
4268 static int rk3368_lcdc_probe(struct platform_device *pdev)
4269 {
4270         struct lcdc_device *lcdc_dev = NULL;
4271         struct rk_lcdc_driver *dev_drv;
4272         struct device *dev = &pdev->dev;
4273         struct resource *res;
4274         struct device_node *np = pdev->dev.of_node;
4275         int prop;
4276         int ret = 0;
4277
4278         /*if the primary lcdc has not registered ,the extend
4279            lcdc register later */
4280         of_property_read_u32(np, "rockchip,prop", &prop);
4281         if (prop == EXTEND) {
4282                 if (!is_prmry_rk_lcdc_registered())
4283                         return -EPROBE_DEFER;
4284         }
4285         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4286         if (!lcdc_dev) {
4287                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4288                 return -ENOMEM;
4289         }
4290         platform_set_drvdata(pdev, lcdc_dev);
4291         lcdc_dev->dev = dev;
4292         rk3368_lcdc_parse_dt(lcdc_dev);
4293         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4294         lcdc_dev->reg_phy_base = res->start;
4295         lcdc_dev->len = resource_size(res);
4296         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4297         if (IS_ERR(lcdc_dev->regs))
4298                 return PTR_ERR(lcdc_dev->regs);
4299         else
4300                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4301
4302         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4303         if (IS_ERR(lcdc_dev->regsbak))
4304                 return PTR_ERR(lcdc_dev->regsbak);
4305         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4306         lcdc_dev->grf_base =
4307                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4308         if (IS_ERR(lcdc_dev->grf_base)) {
4309                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4310                 return PTR_ERR(lcdc_dev->grf_base);
4311         }
4312         lcdc_dev->pmugrf_base =
4313                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmu");
4314         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4315                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4316                 return PTR_ERR(lcdc_dev->pmugrf_base);
4317         }
4318         lcdc_dev->id = 0;
4319         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4320         dev_drv = &lcdc_dev->driver;
4321         dev_drv->dev = dev;
4322         dev_drv->prop = prop;
4323         dev_drv->id = lcdc_dev->id;
4324         dev_drv->ops = &lcdc_drv_ops;
4325         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4326         spin_lock_init(&lcdc_dev->reg_lock);
4327
4328         lcdc_dev->irq = platform_get_irq(pdev, 0);
4329         if (lcdc_dev->irq < 0) {
4330                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4331                         lcdc_dev->id);
4332                 return -ENXIO;
4333         }
4334
4335         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4336                                IRQF_DISABLED | IRQF_SHARED,
4337                                dev_name(dev), lcdc_dev);
4338         if (ret) {
4339                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4340                         lcdc_dev->irq, ret);
4341                 return ret;
4342         }
4343
4344         if (dev_drv->iommu_enabled) {
4345                 if (lcdc_dev->id == 0) {
4346                         strcpy(dev_drv->mmu_dts_name,
4347                                VOPB_IOMMU_COMPATIBLE_NAME);
4348                 } else {
4349                         strcpy(dev_drv->mmu_dts_name,
4350                                VOPL_IOMMU_COMPATIBLE_NAME);
4351                 }
4352         }
4353
4354         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4355         if (ret < 0) {
4356                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4357                 return ret;
4358         }
4359         lcdc_dev->screen = dev_drv->screen0;
4360         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4361                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4362
4363         return 0;
4364 }
4365
4366 static int rk3368_lcdc_remove(struct platform_device *pdev)
4367 {
4368         return 0;
4369 }
4370
4371 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4372 {
4373         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4374
4375         rk3368_lcdc_deint(lcdc_dev);
4376         rk_disp_pwr_disable(&lcdc_dev->driver);
4377 }
4378
4379 #if defined(CONFIG_OF)
4380 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4381         {.compatible = "rockchip,rk3368-lcdc",},
4382         {}
4383 };
4384 #endif
4385
4386 static struct platform_driver rk3368_lcdc_driver = {
4387         .probe = rk3368_lcdc_probe,
4388         .remove = rk3368_lcdc_remove,
4389         .driver = {
4390                    .name = "rk3368-lcdc",
4391                    .owner = THIS_MODULE,
4392                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4393                    },
4394         .suspend = rk3368_lcdc_suspend,
4395         .resume = rk3368_lcdc_resume,
4396         .shutdown = rk3368_lcdc_shutdown,
4397 };
4398
4399 static int __init rk3368_lcdc_module_init(void)
4400 {
4401         return platform_driver_register(&rk3368_lcdc_driver);
4402 }
4403
4404 static void __exit rk3368_lcdc_module_exit(void)
4405 {
4406         platform_driver_unregister(&rk3368_lcdc_driver);
4407 }
4408
4409 fs_initcall(rk3368_lcdc_module_init);
4410 module_exit(rk3368_lcdc_module_exit);