drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
  99 {
 100         int i;
 101         int __iomem *c;
 102         u32 v;
 103         struct lcdc_device *lcdc_dev =
 104             container_of(dev_drv, struct lcdc_device, driver);
 105         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(0));
 106         lcdc_cfg_done(lcdc_dev);
 107         mdelay(25);
 108         for (i = 0; i < 256; i++) {
 109                 v = dsp_lut[i];
 110                 c = lcdc_dev->dsp_lut_addr_base + i;
 111                 writel_relaxed(v, c);
 112         }
 113         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN, v_DSP_LUT_EN(1));
 114
 115         return 0;
 116 }
 117
 118 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 1;
 122         return 0;
 123 #endif
 124         if (!lcdc_dev->clk_on) {
 125                 clk_prepare_enable(lcdc_dev->hclk);
 126                 clk_prepare_enable(lcdc_dev->dclk);
 127                 clk_prepare_enable(lcdc_dev->aclk);
 128                 /*clk_prepare_enable(lcdc_dev->pd);*/
 129                 spin_lock(&lcdc_dev->reg_lock);
 130                 lcdc_dev->clk_on = 1;
 131                 spin_unlock(&lcdc_dev->reg_lock);
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 138 {
 139 #ifdef CONFIG_RK_FPGA
 140         lcdc_dev->clk_on = 0;
 141         return 0;
 142 #endif
 143         if (lcdc_dev->clk_on) {
 144                 spin_lock(&lcdc_dev->reg_lock);
 145                 lcdc_dev->clk_on = 0;
 146                 spin_unlock(&lcdc_dev->reg_lock);
 147                 mdelay(25);
 148                 clk_disable_unprepare(lcdc_dev->dclk);
 149                 clk_disable_unprepare(lcdc_dev->hclk);
 150                 clk_disable_unprepare(lcdc_dev->aclk);
 151                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 152         }
 153
 154         return 0;
 155 }
 156
 157 static int rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 158 {
 159         u32 mask, val;
 160
 161         spin_lock(&lcdc_dev->reg_lock);
 162         if (likely(lcdc_dev->clk_on)) {
 163                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 164                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 165                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 166                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 167                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 168                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 169                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 170                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 171                     v_ADDR_SAME_INTR_EN(0) |
 172                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 173                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 174                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 175                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 176                     v_POST_BUF_EMPTY_INTR_EN(0) |
 177                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 178                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 179
 180                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 181                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 182                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 183                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 184                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 185                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 186                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 187                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 188                     v_ADDR_SAME_INTR_CLR(1) |
 189                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 190                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 191                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 192                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 193                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 194                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 195                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 196                 lcdc_cfg_done(lcdc_dev);
 197                 spin_unlock(&lcdc_dev->reg_lock);
 198         } else {
 199                 spin_unlock(&lcdc_dev->reg_lock);
 200         }
 201         mdelay(1);
 202         return 0;
 203 }
 204
 205 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 206 {
 207         struct lcdc_device *lcdc_dev =
 208             container_of(dev_drv, struct lcdc_device, driver);
 209         int *cbase = (int *)lcdc_dev->regs;
 210         int *regsbak = (int *)lcdc_dev->regsbak;
 211         int i, j, val;
 212         char dbg_message[30];
 213         char buf[10];
 214
 215         pr_info("lcd back up reg:\n");
 216         memset(dbg_message, 0, sizeof(dbg_message));
 217         memset(buf, 0, sizeof(buf));
 218         for (i = 0; i <= (0x200 >> 4); i++) {
 219                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 220                 for (j = 0; j < 4; j++) {
 221                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 222                         strcat(dbg_message, buf);
 223                 }
 224                 pr_info("%s\n", dbg_message);
 225                 memset(dbg_message, 0, sizeof(dbg_message));
 226                 memset(buf, 0, sizeof(buf));
 227         }
 228
 229         pr_info("lcdc reg:\n");
 230         for (i = 0; i <= (0x200 >> 4); i++) {
 231                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 232                 for (j = 0; j < 4; j++) {
 233                         sprintf(buf, "%08x  ",
 234                                 readl_relaxed(cbase + i * 4 + j));
 235                         strcat(dbg_message, buf);
 236                 }
 237                 pr_info("%s\n", dbg_message);
 238                 memset(dbg_message, 0, sizeof(dbg_message));
 239                 memset(buf, 0, sizeof(buf));
 240         }
 241
 242         return 0;
 243 }
 244
 245 #define WIN_EN(id)              \
 246 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 247 { \
 248         u32 msk, val;                                                   \
 249         spin_lock(&lcdc_dev->reg_lock);                                 \
 250         msk =  m_WIN##id##_EN;                                          \
 251         val  =  v_WIN##id##_EN(en);                                     \
 252         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 253         lcdc_cfg_done(lcdc_dev);                                        \
 254         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 255         while (val !=  (!!en))  {                                       \
 256                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 257         }                                                               \
 258         spin_unlock(&lcdc_dev->reg_lock);                               \
 259         return 0;                                                       \
 260 }
 261
 262 WIN_EN(0);
 263 WIN_EN(1);
 264 WIN_EN(2);
 265 WIN_EN(3);
 266 /*enable/disable win directly*/
 267 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 268                                      int win_id, int en)
 269 {
 270         struct lcdc_device *lcdc_dev =
 271             container_of(drv, struct lcdc_device, driver);
 272         if (win_id == 0)
 273                 win0_enable(lcdc_dev, en);
 274         else if (win_id == 1)
 275                 win1_enable(lcdc_dev, en);
 276         else if (win_id == 2)
 277                 win2_enable(lcdc_dev, en);
 278         else if (win_id == 3)
 279                 win3_enable(lcdc_dev, en);
 280         else
 281                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 282         return 0;
 283 }
 284
 285 #define SET_WIN_ADDR(id) \
 286 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 287 {                                                       \
 288         u32 msk, val;                                   \
 289         spin_lock(&lcdc_dev->reg_lock);                 \
 290         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 291         msk =  m_WIN##id##_EN;                          \
 292         val  =  v_WIN0_EN(1);                           \
 293         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 294         lcdc_cfg_done(lcdc_dev);                        \
 295         spin_unlock(&lcdc_dev->reg_lock);               \
 296         return 0;                                       \
 297 }
 298
 299 SET_WIN_ADDR(0);
 300 SET_WIN_ADDR(1);
 301 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 302                                     int win_id, u32 addr)
 303 {
 304         struct lcdc_device *lcdc_dev =
 305             container_of(dev_drv, struct lcdc_device, driver);
 306         if (win_id == 0)
 307                 set_win0_addr(lcdc_dev, addr);
 308         else
 309                 set_win1_addr(lcdc_dev, addr);
 310
 311         return 0;
 312 }
 313
 314 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 315 {
 316         int reg = 0;
 317         u32 val = 0;
 318         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 319         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 320         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 321         u32 st_x, st_y;
 322         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 323
 324         spin_lock(&lcdc_dev->reg_lock);
 325         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 326                 val = lcdc_readl_backup(lcdc_dev, reg);
 327                 switch (reg) {
 328                 case WIN0_ACT_INFO:
 329                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 330                         win0->area[0].yact =
 331                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 332                         break;
 333                 case WIN0_DSP_INFO:
 334                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 335                         win0->area[0].ysize =
 336                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 337                         break;
 338                 case WIN0_DSP_ST:
 339                         st_x = val & m_WIN0_DSP_XST;
 340                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 341                         win0->area[0].xpos = st_x - h_pw_bp;
 342                         win0->area[0].ypos = st_y - v_pw_bp;
 343                         break;
 344                 case WIN0_CTRL0:
 345                         win0->state = val & m_WIN0_EN;
 346                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 347                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 348                         win0->area[0].format = win0->area[0].fmt_cfg;
 349                         break;
 350                 case WIN0_VIR:
 351                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 352                         win0->area[0].uv_vir_stride =
 353                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 354                         if (win0->area[0].format == ARGB888)
 355                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 356                         else if (win0->area[0].format == RGB888)
 357                                 win0->area[0].xvir =
 358                                     win0->area[0].y_vir_stride * 4 / 3;
 359                         else if (win0->area[0].format == RGB565)
 360                                 win0->area[0].xvir =
 361                                     2 * win0->area[0].y_vir_stride;
 362                         else    /* YUV */
 363                                 win0->area[0].xvir =
 364                                     4 * win0->area[0].y_vir_stride;
 365                         break;
 366                 case WIN0_YRGB_MST:
 367                         win0->area[0].smem_start = val;
 368                         break;
 369                 case WIN0_CBR_MST:
 370                         win0->area[0].cbr_start = val;
 371                         break;
 372                 default:
 373                         break;
 374                 }
 375         }
 376         spin_unlock(&lcdc_dev->reg_lock);
 377 }
 378
 379 /********do basic init*********/
 380 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 381 {
 382         u32 mask, val, v;
 383         struct lcdc_device *lcdc_dev =
 384             container_of(dev_drv, struct lcdc_device, driver);
 385         if (lcdc_dev->pre_init)
 386                 return 0;
 387
 388         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 389         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 390         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 391         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 392
 393         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 394             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 395                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 396                         lcdc_dev->id);
 397         }
 398
 399         rk_disp_pwr_enable(dev_drv);
 400         rk3368_lcdc_clk_enable(lcdc_dev);
 401
 402         /*backup reg config at uboot */
 403         lcdc_read_reg_defalut_cfg(lcdc_dev);
 404         if (lcdc_dev->pwr18 == 1) {
 405                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 406                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 407                                 PMUGRF_SOC_CON0_VOP, v);
 408         } else {
 409                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 410                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 411                                 PMUGRF_SOC_CON0_VOP, v);
 412         }
 413         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 414         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 415         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 416         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 417         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 418         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 419
 420         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 421         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 422         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 423         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 424         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 425         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 426
 427         mask = m_AUTO_GATING_EN;
 428         val = v_AUTO_GATING_EN(0);
 429         lcdc_cfg_done(lcdc_dev);
 430         /*disable win0 to workaround iommu pagefault */
 431         /*if (dev_drv->iommu_enabled) */
 432         /*      win0_enable(lcdc_dev, 0); */
 433         lcdc_dev->pre_init = true;
 434
 435         return 0;
 436 }
 437
 438 static void __maybe_unused
 439         rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 440 {
 441         rk3368_lcdc_disable_irq(lcdc_dev);
 442         spin_lock(&lcdc_dev->reg_lock);
 443         if (likely(lcdc_dev->clk_on)) {
 444                 lcdc_dev->clk_on = 0;
 445                 lcdc_set_bit(lcdc_dev, SYS_CTRL, m_STANDBY_EN);
 446                 lcdc_cfg_done(lcdc_dev);
 447                 spin_unlock(&lcdc_dev->reg_lock);
 448         } else {
 449                 spin_unlock(&lcdc_dev->reg_lock);
 450         }
 451         mdelay(1);
 452 }
 453
 454 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 455 {
 456         struct lcdc_device *lcdc_dev =
 457             container_of(dev_drv, struct lcdc_device, driver);
 458         struct rk_screen *screen = dev_drv->cur_screen;
 459         u16 x_res = screen->mode.xres;
 460         u16 y_res = screen->mode.yres;
 461         u32 mask, val;
 462         u16 h_total, v_total;
 463         u16 post_hsd_en, post_vsd_en;
 464         u16 post_dsp_hact_st, post_dsp_hact_end;
 465         u16 post_dsp_vact_st, post_dsp_vact_end;
 466         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 467         u16 post_h_fac, post_v_fac;
 468
 469         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 470             x_res + screen->mode.right_margin;
 471         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 472             y_res + screen->mode.lower_margin;
 473
 474         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 475                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 476                          screen->post_dsp_stx, screen->post_xsize, x_res);
 477                 screen->post_dsp_stx = x_res - screen->post_xsize;
 478         }
 479         if (screen->x_mirror == 0) {
 480                 post_dsp_hact_st = screen->post_dsp_stx +
 481                     screen->mode.hsync_len + screen->mode.left_margin;
 482                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 483         } else {
 484                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 485                     screen->post_dsp_stx;
 486                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 487         }
 488         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 489                 post_hsd_en = 1;
 490                 post_h_fac =
 491                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 492         } else {
 493                 post_hsd_en = 0;
 494                 post_h_fac = 0x1000;
 495         }
 496
 497         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 498                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 499                          screen->post_dsp_sty, screen->post_ysize, y_res);
 500                 screen->post_dsp_sty = y_res - screen->post_ysize;
 501         }
 502
 503         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 504                 post_vsd_en = 1;
 505                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 506                                                       screen->post_ysize);
 507         } else {
 508                 post_vsd_en = 0;
 509                 post_v_fac = 0x1000;
 510         }
 511
 512         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 513                 post_dsp_vact_st = screen->post_dsp_sty +
 514                     screen->mode.vsync_len + screen->mode.upper_margin;
 515                 post_dsp_vact_end = post_dsp_vact_st + screen->post_ysize;
 516
 517                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 518                                       screen->mode.upper_margin +
 519                                       y_res/2 +
 520                                       screen->mode.lower_margin +
 521                                       screen->mode.vsync_len +
 522                                       screen->mode.upper_margin + 1;
 523                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 524                                         screen->post_ysize/2;
 525         } else {
 526                 if (screen->y_mirror == 0) {
 527                         post_dsp_vact_st = screen->post_dsp_sty +
 528                             screen->mode.vsync_len +
 529                             screen->mode.upper_margin;
 530                         post_dsp_vact_end = post_dsp_vact_st +
 531                                 screen->post_ysize;
 532                 } else {
 533                         post_dsp_vact_end = v_total -
 534                                 screen->mode.lower_margin -
 535                             screen->post_dsp_sty;
 536                         post_dsp_vact_st = post_dsp_vact_end -
 537                                 screen->post_ysize;
 538                 }
 539                 post_dsp_vact_st_f1 = 0;
 540                 post_dsp_vact_end_f1 = 0;
 541         }
 542         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 543             screen->post_xsize, screen->post_ysize, screen->xpos);
 544         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 545             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 546         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 547         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 548             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 549         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 550
 551         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 552         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 553             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 554         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 555
 556         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 557         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 558             v_POST_VS_FACTOR_YRGB(post_v_fac);
 559         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 560
 561         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 562         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 563             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 564         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 565
 566         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 567         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 568         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 569         return 0;
 570 }
 571
 572 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 573 {
 574         struct lcdc_device *lcdc_dev =
 575             container_of(dev_drv, struct lcdc_device, driver);
 576         struct rk_lcdc_win *win;
 577         u32 colorkey_r, colorkey_g, colorkey_b;
 578         int i, key_val;
 579
 580         for (i = 0; i < 4; i++) {
 581                 win = dev_drv->win[i];
 582                 key_val = win->color_key_val;
 583                 colorkey_r = (key_val & 0xff) << 2;
 584                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 585                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 586                 /*color key dither 565/888->aaa */
 587                 key_val = colorkey_r | colorkey_g | colorkey_b;
 588                 switch (i) {
 589                 case 0:
 590                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 591                         break;
 592                 case 1:
 593                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 594                         break;
 595                 case 2:
 596                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 597                         break;
 598                 case 3:
 599                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 600                         break;
 601                 default:
 602                         pr_info("%s:un support win num:%d\n",
 603                                 __func__, i);
 604                         break;
 605                 }
 606         }
 607         return 0;
 608 }
 609
 610 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 611 {
 612         struct lcdc_device *lcdc_dev =
 613             container_of(dev_drv, struct lcdc_device, driver);
 614         struct rk_lcdc_win *win = dev_drv->win[win_id];
 615         struct alpha_config alpha_config;
 616         u32 mask, val;
 617         int ppixel_alpha = 0, global_alpha = 0, i;
 618         u32 src_alpha_ctl, dst_alpha_ctl;
 619
 620         for (i = 0; i < win->area_num; i++) {
 621                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 622                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 623         }
 624         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 625         alpha_config.src_global_alpha_val = win->g_alpha_val;
 626         win->alpha_mode = AB_SRC_OVER;
 627         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 628            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 629            global_alpha); */
 630         switch (win->alpha_mode) {
 631         case AB_USER_DEFINE:
 632                 break;
 633         case AB_CLEAR:
 634                 alpha_config.src_factor_mode = AA_ZERO;
 635                 alpha_config.dst_factor_mode = AA_ZERO;
 636                 break;
 637         case AB_SRC:
 638                 alpha_config.src_factor_mode = AA_ONE;
 639                 alpha_config.dst_factor_mode = AA_ZERO;
 640                 break;
 641         case AB_DST:
 642                 alpha_config.src_factor_mode = AA_ZERO;
 643                 alpha_config.dst_factor_mode = AA_ONE;
 644                 break;
 645         case AB_SRC_OVER:
 646                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 647                 if (global_alpha)
 648                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 649                 else
 650                         alpha_config.src_factor_mode = AA_ONE;
 651                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 652                 break;
 653         case AB_DST_OVER:
 654                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 655                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 656                 alpha_config.dst_factor_mode = AA_ONE;
 657                 break;
 658         case AB_SRC_IN:
 659                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 660                 alpha_config.src_factor_mode = AA_SRC;
 661                 alpha_config.dst_factor_mode = AA_ZERO;
 662                 break;
 663         case AB_DST_IN:
 664                 alpha_config.src_factor_mode = AA_ZERO;
 665                 alpha_config.dst_factor_mode = AA_SRC;
 666                 break;
 667         case AB_SRC_OUT:
 668                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 669                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 670                 alpha_config.dst_factor_mode = AA_ZERO;
 671                 break;
 672         case AB_DST_OUT:
 673                 alpha_config.src_factor_mode = AA_ZERO;
 674                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 675                 break;
 676         case AB_SRC_ATOP:
 677                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 678                 alpha_config.src_factor_mode = AA_SRC;
 679                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 680                 break;
 681         case AB_DST_ATOP:
 682                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 683                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 684                 alpha_config.dst_factor_mode = AA_SRC;
 685                 break;
 686         case XOR:
 687                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 688                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 689                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 690                 break;
 691         case AB_SRC_OVER_GLOBAL:
 692                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 693                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 694                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 695                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 696                 break;
 697         default:
 698                 pr_err("alpha mode error\n");
 699                 break;
 700         }
 701         if ((ppixel_alpha == 1) && (global_alpha == 1))
 702                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 703         else if (ppixel_alpha == 1)
 704                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 705         else if (global_alpha == 1)
 706                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 707         else
 708                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 709         alpha_config.src_alpha_mode = AA_STRAIGHT;
 710         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 711
 712         switch (win_id) {
 713         case 0:
 714                 src_alpha_ctl = 0x60;
 715                 dst_alpha_ctl = 0x64;
 716                 break;
 717         case 1:
 718                 src_alpha_ctl = 0xa0;
 719                 dst_alpha_ctl = 0xa4;
 720                 break;
 721         case 2:
 722                 src_alpha_ctl = 0xdc;
 723                 dst_alpha_ctl = 0xec;
 724                 break;
 725         case 3:
 726                 src_alpha_ctl = 0x12c;
 727                 dst_alpha_ctl = 0x13c;
 728                 break;
 729         case 4:
 730                 src_alpha_ctl = 0x160;
 731                 dst_alpha_ctl = 0x164;
 732                 break;
 733         }
 734         mask = m_WIN0_DST_FACTOR_M0;
 735         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 736         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 737         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 738             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 739             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 740             m_WIN0_SRC_GLOBAL_ALPHA;
 741         val = v_WIN0_SRC_ALPHA_EN(1) |
 742             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 743             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 744             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 745             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 746             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 747             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 748         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 749
 750         return 0;
 751 }
 752
 753 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 754 {
 755         struct rk_lcdc_win_area area_temp;
 756         int i, j;
 757
 758         for (i = 0; i < area_num; i++) {
 759                 for (j = i + 1; j < area_num; j++) {
 760                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 761                                 memcpy(&area_temp, &win->area[i],
 762                                        sizeof(struct rk_lcdc_win_area));
 763                                 memcpy(&win->area[i], &win->area[j],
 764                                        sizeof(struct rk_lcdc_win_area));
 765                                 memcpy(&win->area[j], &area_temp,
 766                                        sizeof(struct rk_lcdc_win_area));
 767                         }
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int __maybe_unused
 775         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 776 {
 777         struct rk_lcdc_win_area area_temp;
 778
 779         switch (area_num) {
 780         case 2:
 781                 area_temp = win->area[0];
 782                 win->area[0] = win->area[1];
 783                 win->area[1] = area_temp;
 784                 break;
 785         case 3:
 786                 area_temp = win->area[0];
 787                 win->area[0] = win->area[2];
 788                 win->area[2] = area_temp;
 789                 break;
 790         case 4:
 791                 area_temp = win->area[0];
 792                 win->area[0] = win->area[3];
 793                 win->area[3] = area_temp;
 794
 795                 area_temp = win->area[1];
 796                 win->area[1] = win->area[2];
 797                 win->area[2] = area_temp;
 798                 break;
 799         default:
 800                 pr_info("un supported area num!\n");
 801                 break;
 802         }
 803         return 0;
 804 }
 805
 806 static int rk3368_win_area_check_var(int win_id, int area_num,
 807                                      struct rk_lcdc_win_area *area_pre,
 808                                      struct rk_lcdc_win_area *area_now)
 809 {
 810         if ((area_pre->xpos > area_now->xpos) ||
 811             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 812              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 813                 area_now->state = 0;
 814                 pr_err("win[%d]:\n"
 815                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 816                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 817                        win_id,
 818                        area_num - 1, area_pre->xpos, area_pre->xsize,
 819                        area_pre->ypos, area_pre->ysize,
 820                        area_num, area_now->xpos, area_now->xsize,
 821                        area_now->ypos, area_now->ysize);
 822                 return -EINVAL;
 823         }
 824         return 0;
 825 }
 826
 827 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 828 {
 829         struct lcdc_device *lcdc_dev =
 830             container_of(dev_drv, struct lcdc_device, driver);
 831         u32 val, i;
 832
 833         for (i = 0; i < 100; i++) {
 834                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 835                 val &= m_DBG_IFBDC_IDLE;
 836                 if (val)
 837                         continue;
 838                 else
 839                         mdelay(10);
 840         };
 841         return val;
 842 }
 843
 844 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 845 {
 846         struct lcdc_device *lcdc_dev =
 847             container_of(dev_drv, struct lcdc_device, driver);
 848         struct rk_lcdc_win *win = dev_drv->win[win_id];
 849         u32 mask, val;
 850
 851         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 852             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 853             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 854         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 855             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 856             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 857             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 858             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 859             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 860         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 861
 862         mask = m_IFBDC_TILES_NUM;
 863         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 864         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 865
 866         mask = m_IFBDC_BASE_ADDR;
 867         val = v_IFBDC_BASE_ADDR(win->area[0].y_addr);
 868         lcdc_msk_reg(lcdc_dev, IFBDC_BASE_ADDR, mask, val);
 869
 870         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 871         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 872             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 873         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 874
 875         mask = m_IFBDC_CMP_INDEX_INIT;
 876         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 877         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 878
 879         mask = m_IFBDC_MB_VIR_WIDTH;
 880         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 881         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 882
 883         return 0;
 884 }
 885
 886 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 887 {
 888         struct lcdc_device *lcdc_dev =
 889             container_of(dev_drv, struct lcdc_device, driver);
 890         struct rk_lcdc_win *win = dev_drv->win[win_id];
 891         u8 fbdc_dsp_width_ratio;
 892         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 893         u16 fbdc_mb_width, fbdc_mb_height;
 894         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 895         u16 fbdc_cmp_index_init;
 896         u8 mb_w_size, mb_h_size;
 897         struct rk_screen *screen = dev_drv->cur_screen;
 898
 899         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 900                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 901                 return 0;
 902         }
 903
 904         switch (win->area[0].fmt_cfg) {
 905         case VOP_FORMAT_ARGB888:
 906                 fbdc_dsp_width_ratio = 0;
 907                 mb_w_size = 16;
 908                 break;
 909         case VOP_FORMAT_RGB888:
 910                 fbdc_dsp_width_ratio = 0;
 911                 mb_w_size = 16;
 912                 break;
 913         case VOP_FORMAT_RGB565:
 914                 fbdc_dsp_width_ratio = 1;
 915                 mb_w_size = 32;
 916                 break;
 917         default:
 918                 dev_err(lcdc_dev->dev,
 919                         "in fbdc mode,unsupport fmt:%d!\n",
 920                         win->area[0].fmt_cfg);
 921                 break;
 922         }
 923         mb_h_size = 4;
 924
 925         /*macro block xvir and yvir */
 926         if ((win->area[0].xvir % mb_w_size == 0) &&
 927             (win->area[0].yvir % mb_h_size == 0)) {
 928                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 929                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 930         } else {
 931                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 932                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 933                        win->area[0].xvir, win->area[0].yvir,
 934                        mb_w_size, mb_h_size);
 935         }
 936         /*macro block xact and yact */
 937         if ((win->area[0].xact % mb_w_size == 0) &&
 938             (win->area[0].yact % mb_h_size == 0)) {
 939                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 940                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 941         } else {
 942                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 943                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 944                        win->area[0].xact, win->area[0].yact,
 945                        mb_w_size, mb_h_size);
 946         }
 947         /*macro block xoff and yoff */
 948         if ((win->area[0].xoff % mb_w_size == 0) &&
 949             (win->area[0].yoff % mb_h_size == 0)) {
 950                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 951                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 952         } else {
 953                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 954                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 955                        win->area[0].xoff, win->area[0].yoff,
 956                        mb_w_size, mb_h_size);
 957         }
 958
 959         /*FBDC tiles */
 960         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 961
 962         /*
 963            switch (fbdc_rotation_mode)  {
 964            case FBDC_ROT_NONE:
 965            fbdc_cmp_index_init =
 966            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 967            break;
 968            case FBDC_X_MIRROR:
 969            fbdc_cmp_index_init =
 970            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 971            (fbdc_mb_width-1));
 972            break;
 973            case FBDC_Y_MIRROR:
 974            fbdc_cmp_index_init =
 975            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
 976            fbdc_mb_xst;
 977            break;
 978            case FBDC_ROT_180:
 979            fbdc_cmp_index_init =
 980            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
 981            (fbdc_mb_xst+(fbdc_mb_width-1));
 982            break;
 983            }
 984          */
 985         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
 986                 fbdc_cmp_index_init =
 987                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
 988                     (fbdc_mb_xst + (fbdc_mb_width - 1));
 989         } else {
 990                 fbdc_cmp_index_init =
 991                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
 992         }
 993         /*fbdc fmt maybe need to change*/
 994         win->area[0].fbdc_fmt_cfg = win->area[0].fbdc_data_format;
 995         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
 996         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
 997         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
 998         win->area[0].fbdc_mb_width = fbdc_mb_width;
 999         win->area[0].fbdc_mb_height = fbdc_mb_height;
1000         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1001         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1002         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1003         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1004
1005         return 0;
1006 }
1007
1008 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1009                                  struct rk_lcdc_win *win)
1010 {
1011         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1012         struct rk_screen *screen = dev_drv->cur_screen;
1013
1014         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1015                 switch (win->area[0].fmt_cfg) {
1016                 case VOP_FORMAT_ARGB888:
1017                 case VOP_FORMAT_RGB888:
1018                 case VOP_FORMAT_RGB565:
1019                         if ((screen->mode.xres < 1280) &&
1020                             (screen->mode.yres < 720)) {
1021                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1022                         } else {
1023                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1024                         }
1025                         break;
1026                 default:
1027                         break;
1028                 }
1029         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1030                 switch (win->area[0].fmt_cfg) {
1031                 case VOP_FORMAT_YCBCR420:
1032                         if ((win->id == 0) || (win->id == 1))
1033                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1034                         break;
1035                 default:
1036                         break;
1037                 }
1038         }
1039 }
1040
1041 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1042 {
1043         struct lcdc_device *lcdc_dev =
1044             container_of(dev_drv, struct lcdc_device, driver);
1045         struct rk_lcdc_win *win = dev_drv->win[win_id];
1046         unsigned int mask, val, off;
1047
1048         off = win_id * 0x40;
1049         /*if(win->win_lb_mode == 5)
1050            win->win_lb_mode = 4;
1051            for rk3288 to fix hw bug? */
1052
1053         if (win->state == 1) {
1054                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1055                 if (win->area[0].fbdc_en)
1056                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1057                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1058                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1059                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1060                 val = v_WIN0_EN(win->state) |
1061                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1062                     v_WIN0_FMT_10(win->fmt_10) |
1063                     v_WIN0_LB_MODE(win->win_lb_mode) |
1064                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1065                     v_WIN0_X_MIRROR(win->mirror_en) |
1066                     v_WIN0_Y_MIRROR(win->mirror_en) |
1067                     v_WIN0_CSC_MODE(win->csc_mode);
1068                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1069
1070                 mask = m_WIN0_BIC_COE_SEL |
1071                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1072                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1073                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1074                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1075                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1076                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1077                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1078                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1079                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1080                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1081                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1082                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1083                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1084                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1085                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1086                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1087                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1088                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1089                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1090                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1091                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1092                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1093                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1094                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1095                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1096                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1097                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1098                                 win->area[0].y_addr);
1099                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1100                                 win->area[0].uv_addr); */
1101                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1102                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1103                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1104
1105                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1106                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1107                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1108
1109                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1110                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1111                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1112
1113                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1114                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1115                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1116
1117                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1118                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1119                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1120                 if (win->alpha_en == 1) {
1121                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1122                 } else {
1123                         mask = m_WIN0_SRC_ALPHA_EN;
1124                         val = v_WIN0_SRC_ALPHA_EN(0);
1125                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1126                                      mask, val);
1127                 }
1128         } else {
1129                 mask = m_WIN0_EN;
1130                 val = v_WIN0_EN(win->state);
1131                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1132         }
1133         return 0;
1134 }
1135
1136 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1137 {
1138         struct lcdc_device *lcdc_dev =
1139             container_of(dev_drv, struct lcdc_device, driver);
1140         struct rk_lcdc_win *win = dev_drv->win[win_id];
1141         unsigned int mask, val, off;
1142
1143         off = (win_id - 2) * 0x50;
1144         rk3368_lcdc_area_xst(win, win->area_num);
1145
1146         if (win->state == 1) {
1147                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1148                 if (win->area[0].fbdc_en)
1149                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1150
1151                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1152                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1153                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1154                 /*area 0 */
1155                 if (win->area[0].state == 1) {
1156                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1157                             m_WIN2_RB_SWAP0;
1158                         val = v_WIN2_MST0_EN(win->area[0].state) |
1159                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1160                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1161                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1162
1163                         mask = m_WIN2_VIR_STRIDE0;
1164                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1165                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1166
1167                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1168                            win->area[0].y_addr); */
1169                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1170                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1171                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1172                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1173                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1174                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1175                 } else {
1176                         mask = m_WIN2_MST0_EN;
1177                         val = v_WIN2_MST0_EN(0);
1178                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1179                 }
1180                 /*area 1 */
1181                 if (win->area[1].state == 1) {
1182                         rk3368_win_area_check_var(win_id, 1,
1183                                                   &win->area[0], &win->area[1]);
1184
1185                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1186                             m_WIN2_RB_SWAP1;
1187                         val = v_WIN2_MST1_EN(win->area[1].state) |
1188                             v_WIN2_DATA_FMT0(win->area[1].fmt_cfg) |
1189                             v_WIN2_RB_SWAP0(win->area[1].swap_rb);
1190                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1191
1192                         mask = m_WIN2_VIR_STRIDE1;
1193                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1194                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1195
1196                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1197                            win->area[1].y_addr); */
1198                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1199                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1200                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1201                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1202                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1203                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1204                 } else {
1205                         mask = m_WIN2_MST1_EN;
1206                         val = v_WIN2_MST1_EN(0);
1207                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1208                 }
1209                 /*area 2 */
1210                 if (win->area[2].state == 1) {
1211                         rk3368_win_area_check_var(win_id, 2,
1212                                                   &win->area[1], &win->area[2]);
1213
1214                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1215                             m_WIN2_RB_SWAP2;
1216                         val = v_WIN2_MST2_EN(win->area[2].state) |
1217                             v_WIN2_DATA_FMT0(win->area[2].fmt_cfg) |
1218                             v_WIN2_RB_SWAP0(win->area[2].swap_rb);
1219                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1220
1221                         mask = m_WIN2_VIR_STRIDE2;
1222                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1223                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1224
1225                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1226                            win->area[2].y_addr); */
1227                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1228                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1229                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1230                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1231                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1232                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1233                 } else {
1234                         mask = m_WIN2_MST2_EN;
1235                         val = v_WIN2_MST2_EN(0);
1236                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1237                 }
1238                 /*area 3 */
1239                 if (win->area[3].state == 1) {
1240                         rk3368_win_area_check_var(win_id, 3,
1241                                                   &win->area[2], &win->area[3]);
1242
1243                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1244                             m_WIN2_RB_SWAP3;
1245                         val = v_WIN2_MST3_EN(win->area[3].state) |
1246                             v_WIN2_DATA_FMT0(win->area[3].fmt_cfg) |
1247                             v_WIN2_RB_SWAP0(win->area[3].swap_rb);
1248                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1249
1250                         mask = m_WIN2_VIR_STRIDE3;
1251                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1252                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1253
1254                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1255                            win->area[3].y_addr); */
1256                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1257                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1258                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1259                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1260                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1261                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1262                 } else {
1263                         mask = m_WIN2_MST3_EN;
1264                         val = v_WIN2_MST3_EN(0);
1265                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1266                 }
1267
1268                 if (win->alpha_en == 1) {
1269                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1270                 } else {
1271                         mask = m_WIN2_SRC_ALPHA_EN;
1272                         val = v_WIN2_SRC_ALPHA_EN(0);
1273                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1274                                      mask, val);
1275                 }
1276         } else {
1277                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1278                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1279                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1280                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1281                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1282         }
1283         return 0;
1284 }
1285
1286 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1287 {
1288         struct lcdc_device *lcdc_dev =
1289             container_of(dev_drv, struct lcdc_device, driver);
1290         struct rk_lcdc_win *win = dev_drv->win[win_id];
1291         unsigned int mask, val, hwc_size = 0;
1292
1293         if (win->state == 1) {
1294                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1295                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1296                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1297                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1298                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1299                     v_WIN0_CSC_MODE(win->csc_mode);
1300                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1301
1302                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1303                         hwc_size = 0;
1304                 else if ((win->area[0].xsize == 64) &&
1305                          (win->area[0].ysize == 64))
1306                         hwc_size = 1;
1307                 else if ((win->area[0].xsize == 96) &&
1308                          (win->area[0].ysize == 96))
1309                         hwc_size = 2;
1310                 else if ((win->area[0].xsize == 128) &&
1311                          (win->area[0].ysize == 128))
1312                         hwc_size = 3;
1313                 else
1314                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1315
1316                 mask = m_HWC_SIZE;
1317                 val = v_HWC_SIZE(hwc_size);
1318                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1319
1320                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1321                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1322                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1323                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1324
1325                 if (win->alpha_en == 1) {
1326                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1327                 } else {
1328                         mask = m_WIN2_SRC_ALPHA_EN;
1329                         val = v_WIN2_SRC_ALPHA_EN(0);
1330                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1331                 }
1332         } else {
1333                 mask = m_HWC_EN;
1334                 val = v_HWC_EN(win->state);
1335                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1336         }
1337         return 0;
1338 }
1339
1340 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1341                                          struct rk_lcdc_win *win)
1342 {
1343         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1344         int timeout;
1345         unsigned long flags;
1346
1347         spin_lock(&lcdc_dev->reg_lock);
1348         if (likely(lcdc_dev->clk_on)) {
1349                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1350                              v_STANDBY_EN(lcdc_dev->standby));
1351                 if ((win->id == 0) || (win->id == 1))
1352                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1353                 else if ((win->id == 2) || (win->id == 3))
1354                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1355                 else if (win->id == 4)
1356                         rk3368_hwc_reg_update(dev_drv, win->id);
1357                 /*rk3368_lcdc_post_cfg(dev_drv); */
1358                 lcdc_cfg_done(lcdc_dev);
1359         }
1360         spin_unlock(&lcdc_dev->reg_lock);
1361
1362         /*if (dev_drv->wait_fs) { */
1363         if (0) {
1364                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1365                 init_completion(&dev_drv->frame_done);
1366                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1367                 timeout =
1368                     wait_for_completion_timeout(&dev_drv->frame_done,
1369                                                 msecs_to_jiffies
1370                                                 (dev_drv->cur_screen->ft + 5));
1371                 if (!timeout && (!dev_drv->frame_done.done)) {
1372                         dev_warn(lcdc_dev->dev,
1373                                  "wait for new frame start time out!\n");
1374                         return -ETIMEDOUT;
1375                 }
1376         }
1377         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1378         return 0;
1379 }
1380
1381 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1382 {
1383         if (lcdc_dev->driver.iommu_enabled)
1384                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x330);
1385         else
1386                 memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x260);
1387         return 0;
1388 }
1389
1390 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1391 {
1392         u32 mask, val;
1393         struct lcdc_device *lcdc_dev =
1394             container_of(dev_drv, struct lcdc_device, driver);
1395         /*spin_lock(&lcdc_dev->reg_lock); */
1396         if (likely(lcdc_dev->clk_on)) {
1397                 mask = m_MMU_EN;
1398                 val = v_MMU_EN(1);
1399                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1400                 mask = m_AXI_MAX_OUTSTANDING_EN | m_AXI_OUTSTANDING_MAX_NUM;
1401                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1402                     v_AXI_MAX_OUTSTANDING_EN(1);
1403                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1404         }
1405         /*spin_unlock(&lcdc_dev->reg_lock); */
1406 #if defined(CONFIG_ROCKCHIP_IOMMU)
1407         if (dev_drv->iommu_enabled) {
1408                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1409                         lcdc_dev->iommu_status = 1;
1410                         rockchip_iovmm_activate(dev_drv->dev);
1411                 }
1412         }
1413 #endif
1414         return 0;
1415 }
1416
1417 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
1418 {
1419         int ret = 0, fps = 0;
1420         struct lcdc_device *lcdc_dev =
1421             container_of(dev_drv, struct lcdc_device, driver);
1422         struct rk_screen *screen = dev_drv->cur_screen;
1423 #ifdef CONFIG_RK_FPGA
1424         return 0;
1425 #endif
1426
1427         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1428         if (ret)
1429                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1430         lcdc_dev->pixclock =
1431             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1432         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1433
1434         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1435         screen->ft = 1000 / fps;
1436         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1437                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1438         return 0;
1439 }
1440
1441 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1442 {
1443         struct lcdc_device *lcdc_dev =
1444             container_of(dev_drv, struct lcdc_device, driver);
1445         struct rk_screen *screen = dev_drv->cur_screen;
1446         u16 hsync_len = screen->mode.hsync_len;
1447         u16 left_margin = screen->mode.left_margin;
1448         u16 right_margin = screen->mode.right_margin;
1449         u16 vsync_len = screen->mode.vsync_len;
1450         u16 upper_margin = screen->mode.upper_margin;
1451         u16 lower_margin = screen->mode.lower_margin;
1452         u16 x_res = screen->mode.xres;
1453         u16 y_res = screen->mode.yres;
1454         u32 mask, val;
1455         u16 h_total, v_total;
1456         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1457
1458         h_total = hsync_len + left_margin + x_res + right_margin;
1459         v_total = vsync_len + upper_margin + y_res + lower_margin;
1460
1461         screen->post_dsp_stx = x_res * (100 - screen->overscan.left) / 200;
1462         screen->post_dsp_sty = y_res * (100 - screen->overscan.top) / 200;
1463         screen->post_xsize = x_res *
1464             (screen->overscan.left + screen->overscan.right) / 200;
1465         screen->post_ysize = y_res *
1466             (screen->overscan.top + screen->overscan.bottom) / 200;
1467
1468         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1469         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1470         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1471
1472         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1473         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1474             v_DSP_HACT_ST(hsync_len + left_margin);
1475         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1476
1477         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1478                 /* First Field Timing */
1479                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1480                 val = v_DSP_VS_PW(vsync_len) |
1481                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1482                                       lower_margin) + y_res + 1);
1483                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1484
1485                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1486                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1487                     v_DSP_VACT_ST(vsync_len + upper_margin);
1488                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1489
1490                 /* Second Field Timing */
1491                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1492                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1493                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1494                     lower_margin;
1495                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1496                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1497
1498                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1499                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1500                     lower_margin + 1;
1501                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1502                     lower_margin + 1;
1503                 val =
1504                     v_DSP_VACT_END_F1(vact_end_f1) |
1505                     v_DSP_VAC_ST_F1(vact_st_f1);
1506                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1507
1508                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1509                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1510                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1511                 mask =
1512                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1513                     m_WIN0_CBR_DEFLICK;
1514                 val =
1515                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1516                     v_WIN0_CBR_DEFLICK(1);
1517                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1518
1519                 mask =
1520                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1521                     m_WIN1_CBR_DEFLICK;
1522                 val =
1523                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1524                     v_WIN1_CBR_DEFLICK(1);
1525                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1526
1527                 mask = m_WIN2_INTERLACE_READ;
1528                 val = v_WIN2_INTERLACE_READ(1);
1529                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1530
1531                 mask = m_WIN3_INTERLACE_READ;
1532                 val = v_WIN3_INTERLACE_READ(1);
1533                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1534
1535                 mask = m_HWC_INTERLACE_READ;
1536                 val = v_HWC_INTERLACE_READ(1);
1537                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1538
1539                 mask = m_DSP_LINE_FLAG0_NUM;
1540                 val =
1541                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2);
1542                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1543         } else {
1544                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1545                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1546                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1547
1548                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1549                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1550                     v_DSP_VACT_ST(vsync_len + upper_margin);
1551                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1552
1553                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1554                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1555                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1556
1557                 mask =
1558                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1559                     m_WIN0_CBR_DEFLICK;
1560                 val =
1561                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1562                     v_WIN0_CBR_DEFLICK(0);
1563                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1564
1565                 mask =
1566                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1567                     m_WIN1_CBR_DEFLICK;
1568                 val =
1569                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1570                     v_WIN1_CBR_DEFLICK(0);
1571                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1572
1573                 mask = m_WIN2_INTERLACE_READ;
1574                 val = v_WIN2_INTERLACE_READ(0);
1575                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1576
1577                 mask = m_WIN3_INTERLACE_READ;
1578                 val = v_WIN3_INTERLACE_READ(0);
1579                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1580
1581                 mask = m_HWC_INTERLACE_READ;
1582                 val = v_HWC_INTERLACE_READ(0);
1583                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1584
1585                 mask = m_DSP_LINE_FLAG0_NUM;
1586                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res);
1587                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1588         }
1589         rk3368_lcdc_post_cfg(dev_drv);
1590         return 0;
1591 }
1592
1593 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1594 {
1595         struct lcdc_device *lcdc_dev =
1596             container_of(dev_drv, struct lcdc_device, driver);
1597         u32 bcsh_ctrl;
1598
1599         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1600                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1601         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1602                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1603                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1604                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1605                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1606                 else            /* YUV2RGB */
1607                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1608                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1609                                      m_BCSH_R2Y_EN,
1610                                      v_BCSH_Y2R_EN(1) |
1611                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1612                                      v_BCSH_R2Y_EN(0));
1613         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1614                 /* bypass  --need check,if bcsh close? */
1615                 if (dev_drv->output_color == COLOR_RGB) {
1616                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1617                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1618                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1619                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1620                                              m_BCSH_R2Y_EN |
1621                                              m_BCSH_Y2R_EN,
1622                                              v_BCSH_R2Y_EN(1) |
1623                                              v_BCSH_Y2R_EN(1));
1624                         else
1625                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1626                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1627                                              v_BCSH_R2Y_EN(0) |
1628                                              v_BCSH_Y2R_EN(0));
1629                 } else          /* RGB2YUV */
1630                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1631                                      m_BCSH_R2Y_EN |
1632                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1633                                      v_BCSH_R2Y_EN(1) |
1634                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1635                                      v_BCSH_Y2R_EN(0));
1636         }
1637 }
1638
1639 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1640 {
1641         u16 face = 0;
1642         u16 dclk_ddr = 0;
1643         u32 v = 0;
1644         struct lcdc_device *lcdc_dev =
1645             container_of(dev_drv, struct lcdc_device, driver);
1646         struct rk_screen *screen = dev_drv->cur_screen;
1647         u32 mask, val;
1648
1649         spin_lock(&lcdc_dev->reg_lock);
1650         if (likely(lcdc_dev->clk_on)) {
1651                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1652                 if (!lcdc_dev->standby && !initscreen) {
1653                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1654                                      v_STANDBY_EN(1));
1655                         lcdc_cfg_done(lcdc_dev);
1656                         mdelay(50);
1657                 }
1658                 switch (screen->face) {
1659                 case OUT_P565:
1660                         face = OUT_P565;
1661                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1662                             m_DITHER_DOWN_SEL;
1663                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1664                             v_DITHER_DOWN_SEL(1);
1665                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1666                         break;
1667                 case OUT_P666:
1668                         face = OUT_P666;
1669                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1670                             m_DITHER_DOWN_SEL;
1671                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1672                             v_DITHER_DOWN_SEL(1);
1673                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1674                         break;
1675                 case OUT_D888_P565:
1676                         face = OUT_P888;
1677                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1678                             m_DITHER_DOWN_SEL;
1679                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1680                             v_DITHER_DOWN_SEL(1);
1681                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1682                         break;
1683                 case OUT_D888_P666:
1684                         face = OUT_P888;
1685                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1686                             m_DITHER_DOWN_SEL;
1687                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1688                             v_DITHER_DOWN_SEL(1);
1689                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1690                         break;
1691                 case OUT_P888:
1692                         face = OUT_P888;
1693                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1694                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1695                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1696                         break;
1697                 case OUT_YUV_420:
1698                         /*yuv420 output prefer yuv domain overlay */
1699                         face = OUT_YUV_420;
1700                         dclk_ddr = 1;
1701                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1702                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1703                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1704                         break;
1705                 default:
1706                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1707                         break;
1708                 }
1709                 switch (screen->type) {
1710                 case SCREEN_RGB:
1711                         mask = m_RGB_OUT_EN;
1712                         val = v_RGB_OUT_EN(1);
1713                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1714                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1715                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1716                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1717                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1718                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1719                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1720                         v = 1 << 15 | (1 << (15 + 16));
1721
1722                         break;
1723                 case SCREEN_LVDS:
1724                         mask = m_RGB_OUT_EN;
1725                         val = v_RGB_OUT_EN(1);
1726                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1727                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1728                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1729                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1730                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1731                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1732                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1733                         v = 0 << 15 | (1 << (15 + 16));
1734                         break;
1735                 case SCREEN_HDMI:
1736                         /*face = OUT_RGB_AAA;*/
1737                         dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1738                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1739                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1740                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1741                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1742                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1743                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1744                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1745                             v_HDMI_DEN_POL(screen->pin_den) |
1746                             v_HDMI_DCLK_POL(screen->pin_dclk);
1747                         break;
1748                 case SCREEN_MIPI:
1749                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1750                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1751                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1752                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1753                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1754                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1755                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1756                             v_MIPI_DEN_POL(screen->pin_den) |
1757                             v_MIPI_DCLK_POL(screen->pin_dclk);
1758                         break;
1759                 case SCREEN_DUAL_MIPI:
1760                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1761                                 m_RGB_OUT_EN;
1762                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1763                                 v_RGB_OUT_EN(0);
1764                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1765                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1766                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1767                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1768                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1769                             v_MIPI_DEN_POL(screen->pin_den) |
1770                             v_MIPI_DCLK_POL(screen->pin_dclk);
1771                         break;
1772                 case SCREEN_EDP:
1773                         face = OUT_P888;        /*RGB 888 output */
1774
1775                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1776                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1777                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1778                         /*because edp have to sent aaa fmt */
1779                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1780                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1781
1782                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1783                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1784                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1785                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1786                             v_EDP_DEN_POL(screen->pin_den) |
1787                             v_EDP_DCLK_POL(screen->pin_dclk);
1788                         break;
1789                 }
1790                 /*hsync vsync den dclk polo,dither */
1791                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1792 #ifndef CONFIG_RK_FPGA
1793                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1794                 move to  lvds driver*/
1795                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1796 #endif
1797                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1798                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1799                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1800                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1801                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1802                     v_DSP_BG_SWAP(screen->swap_gb) |
1803                     v_DSP_RB_SWAP(screen->swap_rb) |
1804                     v_DSP_RG_SWAP(screen->swap_rg) |
1805                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1806                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1807                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1808                     v_DSP_X_MIR_EN(screen->x_mirror) |
1809                     v_DSP_Y_MIR_EN(screen->y_mirror);
1810                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1811                 /*BG color */
1812                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1813                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1814                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1815                                 v_DSP_BG_RED(0x80);
1816                 else
1817                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1818                                 v_DSP_BG_RED(0);
1819                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1820                 dev_drv->output_color = screen->color_mode;
1821                 if (screen->dsp_lut == NULL)
1822                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1823                                      v_DSP_LUT_EN(0));
1824                 else
1825                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1826                                      v_DSP_LUT_EN(1));
1827                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1828                 rk3368_config_timing(dev_drv);
1829         }
1830         spin_unlock(&lcdc_dev->reg_lock);
1831         rk3368_lcdc_set_dclk(dev_drv);
1832         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1833             dev_drv->trsm_ops->enable)
1834                 dev_drv->trsm_ops->enable();
1835         if (screen->init)
1836                 screen->init();
1837         if (!lcdc_dev->standby)
1838                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1839         return 0;
1840 }
1841
1842
1843 /*enable layer,open:1,enable;0 disable*/
1844 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1845                                      unsigned int win_id, bool open)
1846 {
1847         spin_lock(&lcdc_dev->reg_lock);
1848         if (likely(lcdc_dev->clk_on) &&
1849             lcdc_dev->driver.win[win_id]->state != open) {
1850                 if (open) {
1851                         if (!lcdc_dev->atv_layer_cnt) {
1852                                 dev_info(lcdc_dev->dev,
1853                                          "wakeup from standby!\n");
1854                                 lcdc_dev->standby = 0;
1855                         }
1856                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1857                 } else {
1858                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1859                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1860                 }
1861                 lcdc_dev->driver.win[win_id]->state = open;
1862                 if (!open) {
1863                         /*rk3368_lcdc_reg_update(dev_drv);*/
1864                         rk3368_lcdc_layer_update_regs
1865                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1866                         lcdc_cfg_done(lcdc_dev);
1867                 }
1868                 /*if no layer used,disable lcdc */
1869                 if (!lcdc_dev->atv_layer_cnt) {
1870                         dev_info(lcdc_dev->dev,
1871                                  "no layer is used,go to standby!\n");
1872                         lcdc_dev->standby = 1;
1873                 }
1874         }
1875         spin_unlock(&lcdc_dev->reg_lock);
1876 }
1877
1878 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1879 {
1880         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1881                                                     struct lcdc_device, driver);
1882         u32 mask, val;
1883         /*struct rk_screen *screen = dev_drv->cur_screen; */
1884
1885         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1886             m_LINE_FLAG1_INTR_CLR;
1887         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1888             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1889         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1890
1891         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN | m_BUS_ERROR_INTR_EN;
1892         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1893             v_BUS_ERROR_INTR_EN(1);
1894         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1895
1896 #ifdef LCDC_IRQ_EMPTY_DEBUG
1897         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1898             m_WIN2_EMPTY_INTR_EN |
1899             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1900             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1901         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1902             v_WIN2_EMPTY_INTR_EN(1) |
1903             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1904             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1905         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1906 #endif
1907         return 0;
1908 }
1909
1910 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1911                             bool open)
1912 {
1913         struct lcdc_device *lcdc_dev =
1914             container_of(dev_drv, struct lcdc_device, driver);
1915 #if 0/*ndef CONFIG_RK_FPGA*/
1916         int sys_status =
1917             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
1918 #endif
1919         /*enable clk,when first layer open */
1920         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
1921                 /*rockchip_set_system_status(sys_status);*/
1922                 rk3368_lcdc_pre_init(dev_drv);
1923                 rk3368_lcdc_clk_enable(lcdc_dev);
1924 #if defined(CONFIG_ROCKCHIP_IOMMU)
1925                 if (dev_drv->iommu_enabled) {
1926                         if (!dev_drv->mmu_dev) {
1927                                 dev_drv->mmu_dev =
1928                                     rk_fb_get_sysmmu_device_by_compatible
1929                                     (dev_drv->mmu_dts_name);
1930                                 if (dev_drv->mmu_dev) {
1931                                         rk_fb_platform_set_sysmmu
1932                                             (dev_drv->mmu_dev, dev_drv->dev);
1933                                 } else {
1934                                         dev_err(dev_drv->dev,
1935                                                 "fail get rk iommu device\n");
1936                                         return -1;
1937                                 }
1938                         }
1939                         /*if (dev_drv->mmu_dev)
1940                            rockchip_iovmm_activate(dev_drv->dev); */
1941                 }
1942 #endif
1943                 rk3368_lcdc_reg_restore(lcdc_dev);
1944                 /*if (dev_drv->iommu_enabled)
1945                    rk3368_lcdc_mmu_en(dev_drv); */
1946                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
1947                         /*rk3368_lcdc_set_dclk(dev_drv); */
1948                         rk3368_lcdc_enable_irq(dev_drv);
1949                 } else {
1950                         rk3368_load_screen(dev_drv, 1);
1951                 }
1952                 if (dev_drv->bcsh.enable)
1953                         rk3368_lcdc_set_bcsh(dev_drv, 1);
1954                 spin_lock(&lcdc_dev->reg_lock);
1955                 if (dev_drv->cur_screen->dsp_lut)
1956                         rk3368_lcdc_set_lut(dev_drv,
1957                                             dev_drv->cur_screen->dsp_lut);
1958                 spin_unlock(&lcdc_dev->reg_lock);
1959         }
1960
1961         if (win_id < ARRAY_SIZE(lcdc_win))
1962                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
1963         else
1964                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
1965
1966
1967         /* when all layer closed,disable clk */
1968         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
1969            rk3368_lcdc_disable_irq(lcdc_dev);
1970            rk3368_lcdc_reg_update(dev_drv);
1971            #if defined(CONFIG_ROCKCHIP_IOMMU)
1972            if (dev_drv->iommu_enabled) {
1973            if (dev_drv->mmu_dev)
1974            rockchip_iovmm_deactivate(dev_drv->dev);
1975            }
1976            #endif
1977            rk3368_lcdc_clk_disable(lcdc_dev);
1978            #ifndef CONFIG_RK_FPGA
1979            rockchip_clear_system_status(sys_status);
1980            #endif
1981            } */
1982
1983         return 0;
1984 }
1985
1986 static int win_0_1_display(struct lcdc_device *lcdc_dev,
1987                            struct rk_lcdc_win *win)
1988 {
1989         u32 y_addr;
1990         u32 uv_addr;
1991         unsigned int off;
1992
1993         off = win->id * 0x40;
1994         /*win->smem_start + win->y_offset; */
1995         y_addr = win->area[0].smem_start + win->area[0].y_offset;
1996         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
1997         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
1998             lcdc_dev->id, win->id, y_addr, uv_addr);
1999         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2000             win->area[0].y_offset, win->area[0].c_offset);
2001         spin_lock(&lcdc_dev->reg_lock);
2002         if (likely(lcdc_dev->clk_on)) {
2003                 win->area[0].y_addr = y_addr;
2004                 win->area[0].uv_addr = uv_addr;
2005                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2006                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2007                 /*lcdc_cfg_done(lcdc_dev); */
2008         }
2009         spin_unlock(&lcdc_dev->reg_lock);
2010
2011         return 0;
2012 }
2013
2014 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2015                            struct rk_lcdc_win *win)
2016 {
2017         u32 i, y_addr;
2018         unsigned int off;
2019
2020         off = (win->id - 2) * 0x50;
2021         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2022         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2023
2024         spin_lock(&lcdc_dev->reg_lock);
2025         if (likely(lcdc_dev->clk_on)) {
2026                 for (i = 0; i < win->area_num; i++) {
2027                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2028                             i, win->area[i].y_addr, win->area[i].y_offset);
2029                         win->area[i].y_addr =
2030                             win->area[i].smem_start + win->area[i].y_offset;
2031                         }
2032                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2033                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2034                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2035                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2036         }
2037         spin_unlock(&lcdc_dev->reg_lock);
2038         return 0;
2039 }
2040
2041 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2042 {
2043         u32 y_addr;
2044
2045         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2046         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2047             lcdc_dev->id, __func__, y_addr);
2048         spin_lock(&lcdc_dev->reg_lock);
2049         if (likely(lcdc_dev->clk_on)) {
2050                 win->area[0].y_addr = y_addr;
2051                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2052         }
2053         spin_unlock(&lcdc_dev->reg_lock);
2054
2055         return 0;
2056 }
2057
2058 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2059 {
2060         struct lcdc_device *lcdc_dev =
2061             container_of(dev_drv, struct lcdc_device, driver);
2062         struct rk_lcdc_win *win = NULL;
2063         struct rk_screen *screen = dev_drv->cur_screen;
2064
2065 #if defined(WAIT_FOR_SYNC)
2066         int timeout;
2067         unsigned long flags;
2068 #endif
2069         win = dev_drv->win[win_id];
2070         if (!screen) {
2071                 dev_err(dev_drv->dev, "screen is null!\n");
2072                 return -ENOENT;
2073         }
2074         if (win_id == 0) {
2075                 win_0_1_display(lcdc_dev, win);
2076         } else if (win_id == 1) {
2077                 win_0_1_display(lcdc_dev, win);
2078         } else if (win_id == 2) {
2079                 win_2_3_display(lcdc_dev, win);
2080         } else if (win_id == 3) {
2081                 win_2_3_display(lcdc_dev, win);
2082         } else if (win_id == 4) {
2083                 hwc_display(lcdc_dev, win);
2084         } else {
2085                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2086                 return -EINVAL;
2087         }
2088
2089         /*this is the first frame of the system ,enable frame start interrupt */
2090         if ((dev_drv->first_frame)) {
2091                 dev_drv->first_frame = 0;
2092                 rk3368_lcdc_enable_irq(dev_drv);
2093         }
2094 #if defined(WAIT_FOR_SYNC)
2095         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2096         init_completion(&dev_drv->frame_done);
2097         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2098         timeout =
2099             wait_for_completion_timeout(&dev_drv->frame_done,
2100                                         msecs_to_jiffies(dev_drv->
2101                                                          cur_screen->ft + 5));
2102         if (!timeout && (!dev_drv->frame_done.done)) {
2103                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2104                 return -ETIMEDOUT;
2105         }
2106 #endif
2107         return 0;
2108 }
2109
2110 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2111 {
2112         u16 srcW;
2113         u16 srcH;
2114         u16 dstW;
2115         u16 dstH;
2116         u16 yrgb_srcW;
2117         u16 yrgb_srcH;
2118         u16 yrgb_dstW;
2119         u16 yrgb_dstH;
2120         u32 yrgb_vscalednmult;
2121         u32 yrgb_xscl_factor;
2122         u32 yrgb_yscl_factor;
2123         u8 yrgb_vsd_bil_gt2 = 0;
2124         u8 yrgb_vsd_bil_gt4 = 0;
2125
2126         u16 cbcr_srcW;
2127         u16 cbcr_srcH;
2128         u16 cbcr_dstW;
2129         u16 cbcr_dstH;
2130         u32 cbcr_vscalednmult;
2131         u32 cbcr_xscl_factor;
2132         u32 cbcr_yscl_factor;
2133         u8 cbcr_vsd_bil_gt2 = 0;
2134         u8 cbcr_vsd_bil_gt4 = 0;
2135         u8 yuv_fmt = 0;
2136
2137         srcW = win->area[0].xact;
2138         srcH = win->area[0].yact;
2139         dstW = win->area[0].xsize;
2140         dstH = win->area[0].ysize;
2141
2142         /*yrgb scl mode */
2143         yrgb_srcW = srcW;
2144         yrgb_srcH = srcH;
2145         yrgb_dstW = dstW;
2146         yrgb_dstH = dstH;
2147         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2148                 pr_err("ERROR: yrgb scale exceed 8,");
2149                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2150                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2151         }
2152         if (yrgb_srcW < yrgb_dstW)
2153                 win->yrgb_hor_scl_mode = SCALE_UP;
2154         else if (yrgb_srcW > yrgb_dstW)
2155                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2156         else
2157                 win->yrgb_hor_scl_mode = SCALE_NONE;
2158
2159         if (yrgb_srcH < yrgb_dstH)
2160                 win->yrgb_ver_scl_mode = SCALE_UP;
2161         else if (yrgb_srcH > yrgb_dstH)
2162                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2163         else
2164                 win->yrgb_ver_scl_mode = SCALE_NONE;
2165
2166         /*cbcr scl mode */
2167         switch (win->area[0].format) {
2168         case YUV422:
2169         case YUV422_A:
2170                 cbcr_srcW = srcW / 2;
2171                 cbcr_dstW = dstW;
2172                 cbcr_srcH = srcH;
2173                 cbcr_dstH = dstH;
2174                 yuv_fmt = 1;
2175                 break;
2176         case YUV420:
2177         case YUV420_A:
2178                 cbcr_srcW = srcW / 2;
2179                 cbcr_dstW = dstW;
2180                 cbcr_srcH = srcH / 2;
2181                 cbcr_dstH = dstH;
2182                 yuv_fmt = 1;
2183                 break;
2184         case YUV444:
2185         case YUV444_A:
2186                 cbcr_srcW = srcW;
2187                 cbcr_dstW = dstW;
2188                 cbcr_srcH = srcH;
2189                 cbcr_dstH = dstH;
2190                 yuv_fmt = 1;
2191                 break;
2192         default:
2193                 cbcr_srcW = 0;
2194                 cbcr_dstW = 0;
2195                 cbcr_srcH = 0;
2196                 cbcr_dstH = 0;
2197                 yuv_fmt = 0;
2198                 break;
2199         }
2200         if (yuv_fmt) {
2201                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2202                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2203                         pr_err("ERROR: cbcr scale exceed 8,");
2204                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2205                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2206                 }
2207         }
2208
2209         if (cbcr_srcW < cbcr_dstW)
2210                 win->cbr_hor_scl_mode = SCALE_UP;
2211         else if (cbcr_srcW > cbcr_dstW)
2212                 win->cbr_hor_scl_mode = SCALE_DOWN;
2213         else
2214                 win->cbr_hor_scl_mode = SCALE_NONE;
2215
2216         if (cbcr_srcH < cbcr_dstH)
2217                 win->cbr_ver_scl_mode = SCALE_UP;
2218         else if (cbcr_srcH > cbcr_dstH)
2219                 win->cbr_ver_scl_mode = SCALE_DOWN;
2220         else
2221                 win->cbr_ver_scl_mode = SCALE_NONE;
2222
2223         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2224             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2225             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2226             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2227             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2228             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2229             win->cbr_ver_scl_mode);*/
2230
2231         /*line buffer mode */
2232         if ((win->area[0].format == YUV422) ||
2233             (win->area[0].format == YUV420) ||
2234             (win->area[0].format == YUV422_A) ||
2235             (win->area[0].format == YUV420_A)) {
2236                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2237                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2238                             (cbcr_dstW == 0))
2239                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2240                                        cbcr_dstW);
2241                         else if (cbcr_dstW > 1280)
2242                                 win->win_lb_mode = LB_YUV_3840X5;
2243                         else
2244                                 win->win_lb_mode = LB_YUV_2560X8;
2245                 } else {        /*SCALE_UP or SCALE_NONE */
2246                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2247                             (cbcr_srcW == 0))
2248                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2249                                        cbcr_srcW);
2250                         else if (cbcr_srcW > 1280)
2251                                 win->win_lb_mode = LB_YUV_3840X5;
2252                         else
2253                                 win->win_lb_mode = LB_YUV_2560X8;
2254                 }
2255         } else {
2256                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2257                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2258                             (yrgb_dstW == 0))
2259                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2260                         else if (yrgb_dstW > 2560)
2261                                 win->win_lb_mode = LB_RGB_3840X2;
2262                         else if (yrgb_dstW > 1920)
2263                                 win->win_lb_mode = LB_RGB_2560X4;
2264                         else if (yrgb_dstW > 1280)
2265                                 win->win_lb_mode = LB_RGB_1920X5;
2266                         else
2267                                 win->win_lb_mode = LB_RGB_1280X8;
2268                 } else {        /*SCALE_UP or SCALE_NONE */
2269                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2270                             (yrgb_srcW == 0))
2271                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2272                         else if (yrgb_srcW > 2560)
2273                                 win->win_lb_mode = LB_RGB_3840X2;
2274                         else if (yrgb_srcW > 1920)
2275                                 win->win_lb_mode = LB_RGB_2560X4;
2276                         else if (yrgb_srcW > 1280)
2277                                 win->win_lb_mode = LB_RGB_1920X5;
2278                         else
2279                                 win->win_lb_mode = LB_RGB_1280X8;
2280                 }
2281         }
2282         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2283
2284         /*vsd/vsu scale ALGORITHM */
2285         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2286         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2287         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2288         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2289         switch (win->win_lb_mode) {
2290         case LB_YUV_3840X5:
2291         case LB_YUV_2560X8:
2292         case LB_RGB_1920X5:
2293         case LB_RGB_1280X8:
2294                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2295                 win->cbr_vsu_mode = SCALE_UP_BIC;
2296                 break;
2297         case LB_RGB_3840X2:
2298                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2299                         pr_err("ERROR : not allow yrgb ver scale\n");
2300                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2301                         pr_err("ERROR : not allow cbcr ver scale\n");
2302                 break;
2303         case LB_RGB_2560X4:
2304                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2305                 win->cbr_vsu_mode = SCALE_UP_BIL;
2306                 break;
2307         default:
2308                 pr_info("%s:un supported win_lb_mode:%d\n",
2309                         __func__, win->win_lb_mode);
2310                 break;
2311         }
2312         if (win->mirror_en == 1) {      /*interlace mode must bill */
2313                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2314         }
2315
2316         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2317             (win->area[0].fbdc_en == 1)) {
2318                 /*in this pattern,use bil mode,not support souble scd,
2319                 use avg mode, support double scd, but aclk should be
2320                 bigger than dclk,aclk>>dclk */
2321                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2322                         pr_err("ERROR : fbdc mode,not support y scale down:");
2323                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2324                                yrgb_srcH, yrgb_dstH);
2325                 }
2326         }
2327         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2328             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2329             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2330
2331         /*SCALE FACTOR */
2332
2333         /*(1.1)YRGB HOR SCALE FACTOR */
2334         switch (win->yrgb_hor_scl_mode) {
2335         case SCALE_NONE:
2336                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2337                 break;
2338         case SCALE_UP:
2339                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2340                 break;
2341         case SCALE_DOWN:
2342                 switch (win->yrgb_hsd_mode) {
2343                 case SCALE_DOWN_BIL:
2344                         yrgb_xscl_factor =
2345                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2346                         break;
2347                 case SCALE_DOWN_AVG:
2348                         yrgb_xscl_factor =
2349                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2350                         break;
2351                 default:
2352                         pr_info(
2353                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2354                                win->yrgb_hsd_mode);
2355                         break;
2356                 }
2357                 break;
2358         default:
2359                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2360                         __func__, win->yrgb_hor_scl_mode);
2361                 break;
2362         }                       /*win->yrgb_hor_scl_mode */
2363
2364         /*(1.2)YRGB VER SCALE FACTOR */
2365         switch (win->yrgb_ver_scl_mode) {
2366         case SCALE_NONE:
2367                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2368                 break;
2369         case SCALE_UP:
2370                 switch (win->yrgb_vsu_mode) {
2371                 case SCALE_UP_BIL:
2372                         yrgb_yscl_factor =
2373                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2374                         break;
2375                 case SCALE_UP_BIC:
2376                         if (yrgb_srcH < 3) {
2377                                 pr_err("yrgb_srcH should be");
2378                                 pr_err(" greater than 3 !!!\n");
2379                         }
2380                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2381                                                                 yrgb_dstH);
2382                         break;
2383                 default:
2384                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2385                                 __func__, win->yrgb_vsu_mode);
2386                         break;
2387                 }
2388                 break;
2389         case SCALE_DOWN:
2390                 switch (win->yrgb_vsd_mode) {
2391                 case SCALE_DOWN_BIL:
2392                         yrgb_vscalednmult =
2393                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2394                                                             yrgb_dstH);
2395                         yrgb_yscl_factor =
2396                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2397                                                            yrgb_vscalednmult);
2398                         if (yrgb_yscl_factor >= 0x2000) {
2399                                 pr_err("yrgb_yscl_factor should be ");
2400                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2401                                        yrgb_yscl_factor);
2402                         }
2403                         if (yrgb_vscalednmult == 4) {
2404                                 yrgb_vsd_bil_gt4 = 1;
2405                                 yrgb_vsd_bil_gt2 = 0;
2406                         } else if (yrgb_vscalednmult == 2) {
2407                                 yrgb_vsd_bil_gt4 = 0;
2408                                 yrgb_vsd_bil_gt2 = 1;
2409                         } else {
2410                                 yrgb_vsd_bil_gt4 = 0;
2411                                 yrgb_vsd_bil_gt2 = 0;
2412                         }
2413                         break;
2414                 case SCALE_DOWN_AVG:
2415                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2416                                                                  yrgb_dstH);
2417                         break;
2418                 default:
2419                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2420                                 __func__, win->yrgb_vsd_mode);
2421                         break;
2422                 }               /*win->yrgb_vsd_mode */
2423                 break;
2424         default:
2425                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2426                         __func__, win->yrgb_ver_scl_mode);
2427                 break;
2428         }
2429         win->scale_yrgb_x = yrgb_xscl_factor;
2430         win->scale_yrgb_y = yrgb_yscl_factor;
2431         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2432         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2433         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2434             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2435
2436         /*(2.1)CBCR HOR SCALE FACTOR */
2437         switch (win->cbr_hor_scl_mode) {
2438         case SCALE_NONE:
2439                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2440                 break;
2441         case SCALE_UP:
2442                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2443                 break;
2444         case SCALE_DOWN:
2445                 switch (win->cbr_hsd_mode) {
2446                 case SCALE_DOWN_BIL:
2447                         cbcr_xscl_factor =
2448                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2449                         break;
2450                 case SCALE_DOWN_AVG:
2451                         cbcr_xscl_factor =
2452                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2453                         break;
2454                 default:
2455                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2456                                 __func__, win->cbr_hsd_mode);
2457                         break;
2458                 }
2459                 break;
2460         default:
2461                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2462                         __func__, win->cbr_hor_scl_mode);
2463                 break;
2464         }                       /*win->cbr_hor_scl_mode */
2465
2466         /*(2.2)CBCR VER SCALE FACTOR */
2467         switch (win->cbr_ver_scl_mode) {
2468         case SCALE_NONE:
2469                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2470                 break;
2471         case SCALE_UP:
2472                 switch (win->cbr_vsu_mode) {
2473                 case SCALE_UP_BIL:
2474                         cbcr_yscl_factor =
2475                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2476                         break;
2477                 case SCALE_UP_BIC:
2478                         if (cbcr_srcH < 3) {
2479                                 pr_err("cbcr_srcH should be ");
2480                                 pr_err("greater than 3 !!!\n");
2481                         }
2482                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2483                                                                 cbcr_dstH);
2484                         break;
2485                 default:
2486                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2487                                 __func__, win->cbr_vsu_mode);
2488                         break;
2489                 }
2490                 break;
2491         case SCALE_DOWN:
2492                 switch (win->cbr_vsd_mode) {
2493                 case SCALE_DOWN_BIL:
2494                         cbcr_vscalednmult =
2495                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2496                                                             cbcr_dstH);
2497                         cbcr_yscl_factor =
2498                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2499                                                            cbcr_vscalednmult);
2500                         if (cbcr_yscl_factor >= 0x2000) {
2501                                 pr_err("cbcr_yscl_factor should be less ");
2502                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2503                                        cbcr_yscl_factor);
2504                         }
2505
2506                         if (cbcr_vscalednmult == 4) {
2507                                 cbcr_vsd_bil_gt4 = 1;
2508                                 cbcr_vsd_bil_gt2 = 0;
2509                         } else if (cbcr_vscalednmult == 2) {
2510                                 cbcr_vsd_bil_gt4 = 0;
2511                                 cbcr_vsd_bil_gt2 = 1;
2512                         } else {
2513                                 cbcr_vsd_bil_gt4 = 0;
2514                                 cbcr_vsd_bil_gt2 = 0;
2515                         }
2516                         break;
2517                 case SCALE_DOWN_AVG:
2518                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2519                                                                  cbcr_dstH);
2520                         break;
2521                 default:
2522                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2523                                 __func__, win->cbr_vsd_mode);
2524                         break;
2525                 }
2526                 break;
2527         default:
2528                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2529                         __func__, win->cbr_ver_scl_mode);
2530                 break;
2531         }
2532         win->scale_cbcr_x = cbcr_xscl_factor;
2533         win->scale_cbcr_y = cbcr_yscl_factor;
2534         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2535         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2536
2537         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2538             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2539         return 0;
2540 }
2541
2542 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2543                      struct rk_lcdc_win_area *area)
2544 {
2545         int pos;
2546
2547         if (screen->x_mirror && mirror_en)
2548                 pr_err("not support both win and global mirror\n");
2549
2550         if ((!mirror_en) && (!screen->x_mirror))
2551                 pos = area->xpos + screen->mode.left_margin +
2552                         screen->mode.hsync_len;
2553         else
2554                 pos = screen->mode.xres - area->xpos -
2555                         area->xsize + screen->mode.left_margin +
2556                         screen->mode.hsync_len;
2557
2558         return pos;
2559 }
2560
2561 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2562                      struct rk_lcdc_win_area *area)
2563 {
2564         int pos;
2565
2566         if (screen->y_mirror && mirror_en)
2567                 pr_err("not support both win and global mirror\n");
2568
2569         if ((!mirror_en) && (!screen->y_mirror))
2570                 pos = area->ypos + screen->mode.upper_margin +
2571                         screen->mode.vsync_len;
2572         else
2573                 pos = screen->mode.yres - area->ypos -
2574                         area->ysize + screen->mode.upper_margin +
2575                         screen->mode.vsync_len;
2576
2577         return pos;
2578 }
2579
2580 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2581                            struct rk_screen *screen, struct rk_lcdc_win *win)
2582 {
2583         u32 xact, yact, xvir, yvir, xpos, ypos;
2584         u8 fmt_cfg = 0, swap_rb;
2585         char fmt[9] = "NULL";
2586
2587         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2588         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2589
2590         spin_lock(&lcdc_dev->reg_lock);
2591         if (likely(lcdc_dev->clk_on)) {
2592                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2593                 switch (win->area[0].format) {
2594                 case ARGB888:
2595                         fmt_cfg = 0;
2596                         swap_rb = 0;
2597                         win->fmt_10 = 0;
2598                         break;
2599                 case XBGR888:
2600                 case ABGR888:
2601                         fmt_cfg = 0;
2602                         swap_rb = 1;
2603                         win->fmt_10 = 0;
2604                         break;
2605                 case RGB888:
2606                         fmt_cfg = 1;
2607                         swap_rb = 0;
2608                         win->fmt_10 = 0;
2609                         break;
2610                 case RGB565:
2611                         fmt_cfg = 2;
2612                         swap_rb = 0;
2613                         win->fmt_10 = 0;
2614                         break;
2615                 case YUV422:
2616                         fmt_cfg = 5;
2617                         swap_rb = 0;
2618                         win->fmt_10 = 0;
2619                         break;
2620                 case YUV420:
2621                         fmt_cfg = 4;
2622                         swap_rb = 0;
2623                         win->fmt_10 = 0;
2624                         break;
2625                 case YUV444:
2626                         fmt_cfg = 6;
2627                         swap_rb = 0;
2628                         win->fmt_10 = 0;
2629                         break;
2630                 case YUV422_A:
2631                         fmt_cfg = 5;
2632                         swap_rb = 0;
2633                         win->fmt_10 = 1;
2634                         break;
2635                 case YUV420_A:
2636                         fmt_cfg = 4;
2637                         swap_rb = 0;
2638                         win->fmt_10 = 1;
2639                         break;
2640                 case YUV444_A:
2641                         fmt_cfg = 6;
2642                         swap_rb = 0;
2643                         win->fmt_10 = 1;
2644                         break;
2645                 default:
2646                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2647                                 __func__);
2648                         break;
2649                 }
2650                 win->area[0].fmt_cfg = fmt_cfg;
2651                 win->area[0].swap_rb = swap_rb;
2652                 win->area[0].dsp_stx = xpos;
2653                 win->area[0].dsp_sty = ypos;
2654                 xact = win->area[0].xact;
2655                 yact = win->area[0].yact;
2656                 xvir = win->area[0].xvir;
2657                 yvir = win->area[0].yvir;
2658         }
2659         if (win->area[0].fbdc_en)
2660                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2661         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2662         spin_unlock(&lcdc_dev->reg_lock);
2663
2664         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2665             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2666             xact, yact, win->area[0].xsize);
2667         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2668             win->area[0].ysize, xvir, yvir, xpos, ypos);
2669
2670         return 0;
2671 }
2672
2673
2674 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2675                            struct rk_screen *screen, struct rk_lcdc_win *win)
2676 {
2677         int i;
2678         u8 fmt_cfg, swap_rb;
2679         char fmt[9] = "NULL";
2680
2681         if (win->mirror_en)
2682                 pr_err("win[%d] not support y mirror\n", win->id);
2683         spin_lock(&lcdc_dev->reg_lock);
2684         if (likely(lcdc_dev->clk_on)) {
2685                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2686                 for (i = 0; i < win->area_num; i++) {
2687                         switch (win->area[i].format) {
2688                         case ARGB888:
2689                                 fmt_cfg = 0;
2690                                 swap_rb = 0;
2691                                 break;
2692                         case XBGR888:
2693                         case ABGR888:
2694                                 fmt_cfg = 0;
2695                                 swap_rb = 1;
2696                                 break;
2697                         case RGB888:
2698                                 fmt_cfg = 1;
2699                                 swap_rb = 0;
2700                                 break;
2701                         case RGB565:
2702                                 fmt_cfg = 2;
2703                                 swap_rb = 0;
2704                                 break;
2705                         default:
2706                                 dev_err(lcdc_dev->driver.dev,
2707                                         "%s:un supported format!\n", __func__);
2708                                 break;
2709                         }
2710                         win->area[i].fmt_cfg = fmt_cfg;
2711                         win->area[i].swap_rb = swap_rb;
2712                         win->area[i].dsp_stx =
2713                                         dsp_x_pos(win->mirror_en, screen,
2714                                                   &win->area[i]);
2715                         win->area[i].dsp_sty =
2716                                         dsp_y_pos(win->mirror_en, screen,
2717                                                   &win->area[i]);
2718
2719                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2720                             get_format_string(win->area[i].format, fmt),
2721                             win->area[i].xsize, win->area[i].ysize,
2722                             win->area[i].xpos, win->area[i].ypos);
2723                 }
2724         }
2725         if (win->area[0].fbdc_en)
2726                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2727         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2728         spin_unlock(&lcdc_dev->reg_lock);
2729         return 0;
2730 }
2731
2732 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2733                        struct rk_screen *screen, struct rk_lcdc_win *win)
2734 {
2735         u32 xact, yact, xvir, yvir, xpos, ypos;
2736         u8 fmt_cfg = 0, swap_rb;
2737         char fmt[9] = "NULL";
2738
2739         xpos = win->area[0].xpos + screen->mode.left_margin +
2740             screen->mode.hsync_len;
2741         ypos = win->area[0].ypos + screen->mode.upper_margin +
2742             screen->mode.vsync_len;
2743
2744         spin_lock(&lcdc_dev->reg_lock);
2745         if (likely(lcdc_dev->clk_on)) {
2746                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2747                 switch (win->area[0].format) {
2748                 case ARGB888:
2749                         fmt_cfg = 0;
2750                         swap_rb = 0;
2751                         break;
2752                 case XBGR888:
2753                 case ABGR888:
2754                         fmt_cfg = 0;
2755                         swap_rb = 1;
2756                         break;
2757                 case RGB888:
2758                         fmt_cfg = 1;
2759                         swap_rb = 0;
2760                         break;
2761                 case RGB565:
2762                         fmt_cfg = 2;
2763                         swap_rb = 0;
2764                         break;
2765                 default:
2766                         dev_err(lcdc_dev->driver.dev,
2767                                 "%s:un supported format!\n", __func__);
2768                         break;
2769                 }
2770                 win->area[0].fmt_cfg = fmt_cfg;
2771                 win->area[0].swap_rb = swap_rb;
2772                 win->area[0].dsp_stx = xpos;
2773                 win->area[0].dsp_sty = ypos;
2774                 xact = win->area[0].xact;
2775                 yact = win->area[0].yact;
2776                 xvir = win->area[0].xvir;
2777                 yvir = win->area[0].yvir;
2778         }
2779         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2780         spin_unlock(&lcdc_dev->reg_lock);
2781
2782         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2783             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2784             xact, yact, win->area[0].xsize);
2785         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2786             win->area[0].ysize, xvir, yvir, xpos, ypos);
2787         return 0;
2788 }
2789
2790 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2791 {
2792         struct lcdc_device *lcdc_dev =
2793             container_of(dev_drv, struct lcdc_device, driver);
2794         struct rk_lcdc_win *win = NULL;
2795         struct rk_screen *screen = dev_drv->cur_screen;
2796
2797         win = dev_drv->win[win_id];
2798         switch (win_id) {
2799         case 0:
2800                 win_0_1_set_par(lcdc_dev, screen, win);
2801                 break;
2802         case 1:
2803                 win_0_1_set_par(lcdc_dev, screen, win);
2804                 break;
2805         case 2:
2806                 win_2_3_set_par(lcdc_dev, screen, win);
2807                 break;
2808         case 3:
2809                 win_2_3_set_par(lcdc_dev, screen, win);
2810                 break;
2811         case 4:
2812                 hwc_set_par(lcdc_dev, screen, win);
2813                 break;
2814         default:
2815                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2816                 break;
2817         }
2818         return 0;
2819 }
2820
2821 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2822                              unsigned long arg, int win_id)
2823 {
2824         struct lcdc_device *lcdc_dev =
2825             container_of(dev_drv, struct lcdc_device, driver);
2826         u32 panel_size[2];
2827         void __user *argp = (void __user *)arg;
2828         struct color_key_cfg clr_key_cfg;
2829
2830         switch (cmd) {
2831         case RK_FBIOGET_PANEL_SIZE:
2832                 panel_size[0] = lcdc_dev->screen->mode.xres;
2833                 panel_size[1] = lcdc_dev->screen->mode.yres;
2834                 if (copy_to_user(argp, panel_size, 8))
2835                         return -EFAULT;
2836                 break;
2837         case RK_FBIOPUT_COLOR_KEY_CFG:
2838                 if (copy_from_user(&clr_key_cfg, argp,
2839                                    sizeof(struct color_key_cfg)))
2840                         return -EFAULT;
2841                 rk3368_lcdc_clr_key_cfg(dev_drv);
2842                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2843                             clr_key_cfg.win0_color_key_cfg);
2844                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2845                             clr_key_cfg.win1_color_key_cfg);
2846                 break;
2847
2848         default:
2849                 break;
2850         }
2851         return 0;
2852 }
2853
2854 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2855 {
2856         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2857                                                     struct lcdc_device, driver);
2858         /*struct device_node *backlight;*/
2859
2860         if (lcdc_dev->backlight)
2861                 return 0;
2862 #if 0
2863         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
2864         if (backlight) {
2865                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
2866                 if (!lcdc_dev->backlight)
2867                         dev_info(lcdc_dev->dev, "No find backlight device\n");
2868         } else {
2869                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
2870         }
2871 #endif
2872         return 0;
2873 }
2874
2875 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
2876 {
2877         u32 reg;
2878         struct lcdc_device *lcdc_dev =
2879             container_of(dev_drv, struct lcdc_device, driver);
2880         if (dev_drv->suspend_flag)
2881                 return 0;
2882         /* close the backlight */
2883         /*rk3368_lcdc_get_backlight_device(dev_drv);
2884         if (lcdc_dev->backlight) {
2885                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
2886                 backlight_update_status(lcdc_dev->backlight);
2887         }*/
2888
2889         dev_drv->suspend_flag = 1;
2890         flush_kthread_worker(&dev_drv->update_regs_worker);
2891
2892         for (reg = MMU_DTE_ADDR; reg <= MMU_AUTO_GATING; reg += 4)
2893                 lcdc_readl_backup(lcdc_dev, reg);
2894         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
2895                 dev_drv->trsm_ops->disable();
2896
2897         spin_lock(&lcdc_dev->reg_lock);
2898         if (likely(lcdc_dev->clk_on)) {
2899                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2900                              v_DSP_BLANK_EN(1));
2901                 lcdc_msk_reg(lcdc_dev,
2902                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
2903                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
2904                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2905                              v_DSP_OUT_ZERO(1));
2906                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
2907                 lcdc_cfg_done(lcdc_dev);
2908
2909                 if (dev_drv->iommu_enabled) {
2910                         if (dev_drv->mmu_dev)
2911                                 rockchip_iovmm_deactivate(dev_drv->dev);
2912                 }
2913
2914                 spin_unlock(&lcdc_dev->reg_lock);
2915         } else {
2916                 spin_unlock(&lcdc_dev->reg_lock);
2917                 return 0;
2918         }
2919         rk3368_lcdc_clk_disable(lcdc_dev);
2920         rk_disp_pwr_disable(dev_drv);
2921         return 0;
2922 }
2923
2924 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
2925 {
2926         struct lcdc_device *lcdc_dev =
2927             container_of(dev_drv, struct lcdc_device, driver);
2928
2929         if (!dev_drv->suspend_flag)
2930                 return 0;
2931         rk_disp_pwr_enable(dev_drv);
2932         dev_drv->suspend_flag = 0;
2933
2934         if (1/*lcdc_dev->atv_layer_cnt*/) {
2935                 rk3368_lcdc_clk_enable(lcdc_dev);
2936                 rk3368_lcdc_reg_restore(lcdc_dev);
2937
2938                 spin_lock(&lcdc_dev->reg_lock);
2939                 if (dev_drv->cur_screen->dsp_lut)
2940                         rk3368_lcdc_set_lut(dev_drv,
2941                                             dev_drv->cur_screen->dsp_lut);
2942
2943                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
2944                              v_DSP_OUT_ZERO(0));
2945                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
2946                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
2947                              v_DSP_BLANK_EN(0));
2948                 lcdc_cfg_done(lcdc_dev);
2949
2950                 if (dev_drv->iommu_enabled) {
2951                         if (dev_drv->mmu_dev)
2952                                 rockchip_iovmm_activate(dev_drv->dev);
2953                 }
2954
2955                 spin_unlock(&lcdc_dev->reg_lock);
2956         }
2957
2958         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
2959                 dev_drv->trsm_ops->enable();
2960
2961         return 0;
2962 }
2963
2964 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
2965                              int win_id, int blank_mode)
2966 {
2967         switch (blank_mode) {
2968         case FB_BLANK_UNBLANK:
2969                 rk3368_lcdc_early_resume(dev_drv);
2970                 break;
2971         case FB_BLANK_NORMAL:
2972                 rk3368_lcdc_early_suspend(dev_drv);
2973                 break;
2974         default:
2975                 rk3368_lcdc_early_suspend(dev_drv);
2976                 break;
2977         }
2978
2979         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
2980
2981         return 0;
2982 }
2983
2984 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
2985 {
2986         return 0;
2987 }
2988
2989 /*overlay will be do at regupdate*/
2990 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
2991                                bool set)
2992 {
2993         struct lcdc_device *lcdc_dev =
2994             container_of(dev_drv, struct lcdc_device, driver);
2995         struct rk_lcdc_win *win = NULL;
2996         int i, ovl;
2997         unsigned int mask, val;
2998         int z_order_num = 0;
2999         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3000
3001         if (swap == 0) {
3002                 for (i = 0; i < 4; i++) {
3003                         win = dev_drv->win[i];
3004                         if (win->state == 1)
3005                                 z_order_num++;
3006                 }
3007                 for (i = 0; i < 4; i++) {
3008                         win = dev_drv->win[i];
3009                         if (win->state == 0)
3010                                 win->z_order = z_order_num++;
3011                         switch (win->z_order) {
3012                         case 0:
3013                                 layer0_sel = win->id;
3014                                 break;
3015                         case 1:
3016                                 layer1_sel = win->id;
3017                                 break;
3018                         case 2:
3019                                 layer2_sel = win->id;
3020                                 break;
3021                         case 3:
3022                                 layer3_sel = win->id;
3023                                 break;
3024                         default:
3025                                 break;
3026                         }
3027                 }
3028         } else {
3029                 layer0_sel = swap % 10;
3030                 layer1_sel = swap / 10 % 10;
3031                 layer2_sel = swap / 100 % 10;
3032                 layer3_sel = swap / 1000;
3033         }
3034
3035         spin_lock(&lcdc_dev->reg_lock);
3036         if (lcdc_dev->clk_on) {
3037                 if (set) {
3038                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3039                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3040                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3041                             v_DSP_LAYER1_SEL(layer1_sel) |
3042                             v_DSP_LAYER2_SEL(layer2_sel) |
3043                             v_DSP_LAYER3_SEL(layer3_sel);
3044                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3045                 } else {
3046                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3047                                                    m_DSP_LAYER0_SEL);
3048                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3049                                                    m_DSP_LAYER1_SEL);
3050                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3051                                                    m_DSP_LAYER2_SEL);
3052                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3053                                                    m_DSP_LAYER3_SEL);
3054                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3055                             layer1_sel * 10 + layer0_sel;
3056                 }
3057         } else {
3058                 ovl = -EPERM;
3059         }
3060         spin_unlock(&lcdc_dev->reg_lock);
3061
3062         return ovl;
3063 }
3064
3065 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3066 {
3067         if (!fmt)
3068                 return NULL;
3069
3070         switch (format) {
3071         case 0:
3072                 strcpy(fmt, "ARGB888");
3073                 break;
3074         case 1:
3075                 strcpy(fmt, "RGB888");
3076                 break;
3077         case 2:
3078                 strcpy(fmt, "RGB565");
3079                 break;
3080         case 4:
3081                 strcpy(fmt, "YCbCr420");
3082                 break;
3083         case 5:
3084                 strcpy(fmt, "YCbCr422");
3085                 break;
3086         case 6:
3087                 strcpy(fmt, "YCbCr444");
3088                 break;
3089         default:
3090                 strcpy(fmt, "invalid\n");
3091                 break;
3092         }
3093         return fmt;
3094 }
3095 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3096                                          char *buf, int win_id)
3097 {
3098         struct lcdc_device *lcdc_dev =
3099             container_of(dev_drv, struct lcdc_device, driver);
3100         struct rk_screen *screen = dev_drv->cur_screen;
3101         u16 hsync_len = screen->mode.hsync_len;
3102         u16 left_margin = screen->mode.left_margin;
3103         u16 vsync_len = screen->mode.vsync_len;
3104         u16 upper_margin = screen->mode.upper_margin;
3105         u32 h_pw_bp = hsync_len + left_margin;
3106         u32 v_pw_bp = vsync_len + upper_margin;
3107         u32 fmt_id;
3108         char format_w0[9] = "NULL";
3109         char format_w1[9] = "NULL";
3110         char format_w2_0[9] = "NULL";
3111         char format_w2_1[9] = "NULL";
3112         char format_w2_2[9] = "NULL";
3113         char format_w2_3[9] = "NULL";
3114         char format_w3_0[9] = "NULL";
3115         char format_w3_1[9] = "NULL";
3116         char format_w3_2[9] = "NULL";
3117         char format_w3_3[9] = "NULL";
3118         char dsp_buf[100];
3119         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3120         u32 y_factor, uv_factor;
3121         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3122         u8 w0_state, w1_state, w2_state, w3_state;
3123         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3124         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3125
3126         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3127         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3128         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3129         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3130         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3131         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3132
3133         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3134         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3135         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3136         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3137         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3138         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3139         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3140
3141         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3142         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3143         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3144         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3145         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3146         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3147         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3148         u32 dclk_freq;
3149         int size = 0;
3150
3151         dclk_freq = screen->mode.pixclock;
3152         /*rk3368_lcdc_reg_dump(dev_drv); */
3153
3154         spin_lock(&lcdc_dev->reg_lock);
3155         if (lcdc_dev->clk_on) {
3156                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3157                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3158                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3159                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3160                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3161                 /*WIN0 */
3162                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3163                 w0_state = win_ctrl & m_WIN0_EN;
3164                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3165                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3166                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3167                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3168                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3169                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3170                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3171                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3172                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3173                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3174                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3175                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3176                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3177                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3178                 if (w0_state) {
3179                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3180                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3181                 }
3182                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3183                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3184                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3185                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3186
3187                 /*WIN1 */
3188                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3189                 w1_state = win_ctrl & m_WIN1_EN;
3190                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3191                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3192                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3193                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3194                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3195                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3196                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3197                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3198                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3199                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3200                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3201                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3202                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3203                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3204                 if (w1_state) {
3205                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3206                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3207                 }
3208                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3209                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3210                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3211                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3212                 /*WIN2 */
3213                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3214                 w2_state = win_ctrl & m_WIN2_EN;
3215                 w2_0_state = (win_ctrl & m_WIN2_MST0_EN) >> 4;
3216                 w2_1_state = (win_ctrl & m_WIN2_MST1_EN) >> 5;
3217                 w2_2_state = (win_ctrl & m_WIN2_MST2_EN) >> 6;
3218                 w2_3_state = (win_ctrl & m_WIN2_MST3_EN) >> 7;
3219                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3220                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3221                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3222                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3223                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3224                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3225
3226                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3227                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3228                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3229                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3230                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3231                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3232                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3233                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3234
3235                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3236                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3237                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3238                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3239                 if (w2_0_state) {
3240                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3241                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3242                 }
3243                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3244                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3245                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3246                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3247                 if (w2_1_state) {
3248                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3249                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3250                 }
3251                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3252                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3253                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3254                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3255                 if (w2_2_state) {
3256                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3257                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3258                 }
3259                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3260                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3261                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3262                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3263                 if (w2_3_state) {
3264                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3265                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3266                 }
3267
3268                 /*WIN3 */
3269                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3270                 w3_state = win_ctrl & m_WIN3_EN;
3271                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3272                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 5;
3273                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 6;
3274                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 7;
3275                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3276                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3277                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3278                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3279                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3280                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3281                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3282                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3283                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3284                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3285                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3286                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3287                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3288                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3289                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3290                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3291                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3292                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3293                 if (w3_0_state) {
3294                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3295                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3296                 }
3297
3298                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3299                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3300                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3301                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3302                 if (w3_1_state) {
3303                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3304                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3305                 }
3306
3307                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3308                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3309                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3310                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3311                 if (w3_2_state) {
3312                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3313                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3314                 }
3315
3316                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3317                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3318                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3319                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3320                 if (w3_3_state) {
3321                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3322                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3323                 }
3324
3325         } else {
3326                 spin_unlock(&lcdc_dev->reg_lock);
3327                 return -EPERM;
3328         }
3329         spin_unlock(&lcdc_dev->reg_lock);
3330         size += snprintf(dsp_buf, 80,
3331                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3332                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3333         strcat(buf, dsp_buf);
3334         memset(dsp_buf, 0, sizeof(dsp_buf));
3335         /*win0*/
3336         size += snprintf(dsp_buf, 80,
3337                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3338                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3339         strcat(buf, dsp_buf);
3340         memset(dsp_buf, 0, sizeof(dsp_buf));
3341
3342         size += snprintf(dsp_buf, 80,
3343                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3344                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3345         strcat(buf, dsp_buf);
3346         memset(dsp_buf, 0, sizeof(dsp_buf));
3347
3348         size += snprintf(dsp_buf, 80,
3349                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3350                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3351         strcat(buf, dsp_buf);
3352         memset(dsp_buf, 0, sizeof(dsp_buf));
3353
3354         size += snprintf(dsp_buf, 80,
3355                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3356                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3357                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3358         strcat(buf, dsp_buf);
3359         memset(dsp_buf, 0, sizeof(dsp_buf));
3360
3361         /*win1*/
3362         size += snprintf(dsp_buf, 80,
3363                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3364                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3365         strcat(buf, dsp_buf);
3366         memset(dsp_buf, 0, sizeof(dsp_buf));
3367
3368         size += snprintf(dsp_buf, 80,
3369                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3370                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3371         strcat(buf, dsp_buf);
3372         memset(dsp_buf, 0, sizeof(dsp_buf));
3373
3374         size += snprintf(dsp_buf, 80,
3375                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3376                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3377         strcat(buf, dsp_buf);
3378         memset(dsp_buf, 0, sizeof(dsp_buf));
3379
3380         size += snprintf(dsp_buf, 80,
3381                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3382                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3383                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3384         strcat(buf, dsp_buf);
3385         memset(dsp_buf, 0, sizeof(dsp_buf));
3386
3387         /*win2*/
3388         size += snprintf(dsp_buf, 80,
3389                  "win2:\n  state:%d\n",
3390                  w2_state);
3391         strcat(buf, dsp_buf);
3392         memset(dsp_buf, 0, sizeof(dsp_buf));
3393         /*area 0*/
3394         size += snprintf(dsp_buf, 80,
3395                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3396                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3397         strcat(buf, dsp_buf);
3398         memset(dsp_buf, 0, sizeof(dsp_buf));
3399         size += snprintf(dsp_buf, 80,
3400                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3401                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3402                  lcdc_readl(lcdc_dev, WIN2_MST0));
3403         strcat(buf, dsp_buf);
3404         memset(dsp_buf, 0, sizeof(dsp_buf));
3405
3406         /*area 1*/
3407         size += snprintf(dsp_buf, 80,
3408                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3409                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3410         strcat(buf, dsp_buf);
3411         memset(dsp_buf, 0, sizeof(dsp_buf));
3412         size += snprintf(dsp_buf, 80,
3413                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3414                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3415                  lcdc_readl(lcdc_dev, WIN2_MST1));
3416         strcat(buf, dsp_buf);
3417         memset(dsp_buf, 0, sizeof(dsp_buf));
3418
3419         /*area 2*/
3420         size += snprintf(dsp_buf, 80,
3421                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3422                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3423         strcat(buf, dsp_buf);
3424         memset(dsp_buf, 0, sizeof(dsp_buf));
3425         size += snprintf(dsp_buf, 80,
3426                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3427                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3428                  lcdc_readl(lcdc_dev, WIN2_MST2));
3429         strcat(buf, dsp_buf);
3430         memset(dsp_buf, 0, sizeof(dsp_buf));
3431
3432         /*area 3*/
3433         size += snprintf(dsp_buf, 80,
3434                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3435                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3436         strcat(buf, dsp_buf);
3437         memset(dsp_buf, 0, sizeof(dsp_buf));
3438         size += snprintf(dsp_buf, 80,
3439                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3440                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3441                  lcdc_readl(lcdc_dev, WIN2_MST3));
3442         strcat(buf, dsp_buf);
3443         memset(dsp_buf, 0, sizeof(dsp_buf));
3444
3445         /*win3*/
3446         size += snprintf(dsp_buf, 80,
3447                  "win3:\n  state:%d\n",
3448                  w3_state);
3449         strcat(buf, dsp_buf);
3450         memset(dsp_buf, 0, sizeof(dsp_buf));
3451         /*area 0*/
3452         size += snprintf(dsp_buf, 80,
3453                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3454                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3455         strcat(buf, dsp_buf);
3456         memset(dsp_buf, 0, sizeof(dsp_buf));
3457         size += snprintf(dsp_buf, 80,
3458                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3459                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3460                  lcdc_readl(lcdc_dev, WIN3_MST0));
3461         strcat(buf, dsp_buf);
3462         memset(dsp_buf, 0, sizeof(dsp_buf));
3463
3464         /*area 1*/
3465         size += snprintf(dsp_buf, 80,
3466                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3467                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3468         strcat(buf, dsp_buf);
3469         memset(dsp_buf, 0, sizeof(dsp_buf));
3470         size += snprintf(dsp_buf, 80,
3471                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3472                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3473                  lcdc_readl(lcdc_dev, WIN3_MST1));
3474         strcat(buf, dsp_buf);
3475         memset(dsp_buf, 0, sizeof(dsp_buf));
3476
3477         /*area 2*/
3478         size += snprintf(dsp_buf, 80,
3479                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3480                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3481         strcat(buf, dsp_buf);
3482         memset(dsp_buf, 0, sizeof(dsp_buf));
3483         size += snprintf(dsp_buf, 80,
3484                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3485                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3486                  lcdc_readl(lcdc_dev, WIN3_MST2));
3487         strcat(buf, dsp_buf);
3488         memset(dsp_buf, 0, sizeof(dsp_buf));
3489
3490         /*area 3*/
3491         size += snprintf(dsp_buf, 80,
3492                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3493                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3494         strcat(buf, dsp_buf);
3495         memset(dsp_buf, 0, sizeof(dsp_buf));
3496         size += snprintf(dsp_buf, 80,
3497                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3498                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3499                  lcdc_readl(lcdc_dev, WIN3_MST3));
3500         strcat(buf, dsp_buf);
3501         memset(dsp_buf, 0, sizeof(dsp_buf));
3502
3503         return size;
3504 }
3505
3506 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3507                                bool set)
3508 {
3509         struct lcdc_device *lcdc_dev =
3510             container_of(dev_drv, struct lcdc_device, driver);
3511         struct rk_screen *screen = dev_drv->cur_screen;
3512         u64 ft = 0;
3513         u32 dotclk;
3514         int ret;
3515         u32 pixclock;
3516         u32 x_total, y_total;
3517
3518         if (set) {
3519                 if (fps == 0) {
3520                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3521                         return 0;
3522                 }
3523                 ft = div_u64(1000000000000llu, fps);
3524                 x_total =
3525                     screen->mode.upper_margin + screen->mode.lower_margin +
3526                     screen->mode.yres + screen->mode.vsync_len;
3527                 y_total =
3528                     screen->mode.left_margin + screen->mode.right_margin +
3529                     screen->mode.xres + screen->mode.hsync_len;
3530                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3531                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3532                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3533         }
3534
3535         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3536         lcdc_dev->pixclock = pixclock;
3537         dev_drv->pixclock = lcdc_dev->pixclock;
3538         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3539         screen->ft = 1000 / fps;        /*one frame time in ms */
3540
3541         if (set)
3542                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3543                          clk_get_rate(lcdc_dev->dclk), fps);
3544
3545         return fps;
3546 }
3547
3548 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3549 {
3550         mutex_lock(&dev_drv->fb_win_id_mutex);
3551         if (order == FB_DEFAULT_ORDER)
3552                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3553         dev_drv->fb4_win_id = order / 10000;
3554         dev_drv->fb3_win_id = (order / 1000) % 10;
3555         dev_drv->fb2_win_id = (order / 100) % 10;
3556         dev_drv->fb1_win_id = (order / 10) % 10;
3557         dev_drv->fb0_win_id = order % 10;
3558         mutex_unlock(&dev_drv->fb_win_id_mutex);
3559
3560         return 0;
3561 }
3562
3563 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3564                                   const char *id)
3565 {
3566         int win_id = 0;
3567
3568         mutex_lock(&dev_drv->fb_win_id_mutex);
3569         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3570                 win_id = dev_drv->fb0_win_id;
3571         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3572                 win_id = dev_drv->fb1_win_id;
3573         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3574                 win_id = dev_drv->fb2_win_id;
3575         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3576                 win_id = dev_drv->fb3_win_id;
3577         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3578                 win_id = dev_drv->fb4_win_id;
3579         mutex_unlock(&dev_drv->fb_win_id_mutex);
3580
3581         return win_id;
3582 }
3583
3584 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3585 {
3586         struct lcdc_device *lcdc_dev =
3587             container_of(dev_drv, struct lcdc_device, driver);
3588         int i;
3589         unsigned int mask, val;
3590         struct rk_lcdc_win *win = NULL;
3591
3592         spin_lock(&lcdc_dev->reg_lock);
3593         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3594                      v_STANDBY_EN(lcdc_dev->standby));
3595         for (i = 0; i < 4; i++) {
3596                 win = dev_drv->win[i];
3597                 if ((win->state == 0) && (win->last_state == 1)) {
3598                         switch (win->id) {
3599                         case 0:
3600                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3601                                    for rk3288 to fix hw bug? */
3602                                 mask = m_WIN0_EN;
3603                                 val = v_WIN0_EN(0);
3604                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3605                                 break;
3606                         case 1:
3607                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3608                                    for rk3288 to fix hw bug? */
3609                                 mask = m_WIN1_EN;
3610                                 val = v_WIN1_EN(0);
3611                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3612                                 break;
3613                         case 2:
3614                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3615                                     m_WIN2_MST1_EN |
3616                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3617                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3618                                     v_WIN2_MST1_EN(0) |
3619                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3620                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3621                                 break;
3622                         case 3:
3623                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3624                                     m_WIN3_MST1_EN |
3625                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3626                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3627                                     v_WIN3_MST1_EN(0) |
3628                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3629                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3630                                 break;
3631                         case 4:
3632                                 mask = m_HWC_EN;
3633                                 val = v_HWC_EN(0);
3634                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3635                                 break;
3636                         default:
3637                                 break;
3638                         }
3639                 }
3640                 win->last_state = win->state;
3641         }
3642         lcdc_cfg_done(lcdc_dev);
3643         spin_unlock(&lcdc_dev->reg_lock);
3644         return 0;
3645 }
3646
3647 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3648 {
3649         struct lcdc_device *lcdc_dev =
3650             container_of(dev_drv, struct lcdc_device, driver);
3651         spin_lock(&lcdc_dev->reg_lock);
3652         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3653                      v_DIRECT_PATH_EN(open));
3654         lcdc_cfg_done(lcdc_dev);
3655         spin_unlock(&lcdc_dev->reg_lock);
3656         return 0;
3657 }
3658
3659 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3660 {
3661         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3662                                                     struct lcdc_device, driver);
3663         spin_lock(&lcdc_dev->reg_lock);
3664         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3665                      v_DIRECT_PATCH_SEL(win_id));
3666         lcdc_cfg_done(lcdc_dev);
3667         spin_unlock(&lcdc_dev->reg_lock);
3668         return 0;
3669 }
3670
3671 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3672 {
3673         struct lcdc_device *lcdc_dev =
3674             container_of(dev_drv, struct lcdc_device, driver);
3675         int ovl;
3676
3677         spin_lock(&lcdc_dev->reg_lock);
3678         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3679         spin_unlock(&lcdc_dev->reg_lock);
3680         return ovl;
3681 }
3682
3683 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3684                                       int enable)
3685 {
3686         struct lcdc_device *lcdc_dev =
3687             container_of(dev_drv, struct lcdc_device, driver);
3688         if (enable)
3689                 enable_irq(lcdc_dev->irq);
3690         else
3691                 disable_irq(lcdc_dev->irq);
3692         return 0;
3693 }
3694
3695 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3696 {
3697         struct lcdc_device *lcdc_dev =
3698             container_of(dev_drv, struct lcdc_device, driver);
3699         u32 int_reg;
3700         int ret;
3701
3702         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3703                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3704                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3705                         lcdc_dev->driver.frame_time.last_framedone_t =
3706                             lcdc_dev->driver.frame_time.framedone_t;
3707                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3708                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3709                                      m_LINE_FLAG0_INTR_CLR,
3710                                      v_LINE_FLAG0_INTR_CLR(1));
3711                         ret = RK_LF_STATUS_FC;
3712                 } else {
3713                         ret = RK_LF_STATUS_FR;
3714                 }
3715         } else {
3716                 ret = RK_LF_STATUS_NC;
3717         }
3718
3719         return ret;
3720 }
3721
3722 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3723                                     unsigned int *dsp_addr)
3724 {
3725         struct lcdc_device *lcdc_dev =
3726             container_of(dev_drv, struct lcdc_device, driver);
3727         spin_lock(&lcdc_dev->reg_lock);
3728         if (lcdc_dev->clk_on) {
3729                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3730                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3731                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3732                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3733         }
3734         spin_unlock(&lcdc_dev->reg_lock);
3735         return 0;
3736 }
3737
3738 static struct lcdc_cabc_mode cabc_mode[4] = {
3739         /* pixel_num,8 stage_up, stage_down */
3740         {5, 282, 171, 300},     /*mode 1 */
3741         {10, 282, 171, 300},    /*mode 2 */
3742         {15, 282, 171, 300},    /*mode 3 */
3743         {20, 282, 171, 300},    /*mode 4 */
3744 };
3745
3746 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3747 {
3748         struct lcdc_device *lcdc_dev =
3749             container_of(dev_drv, struct lcdc_device, driver);
3750         struct rk_screen *screen = dev_drv->cur_screen;
3751         u32 total_pixel, calc_pixel, stage_up, stage_down;
3752         u32 pixel_num, global_su;
3753         u32 stage_up_rec, stage_down_rec, global_su_rec;
3754         u32 mask = 0, val = 0, cabc_en = 0;
3755
3756         dev_drv->cabc_mode = mode;
3757         cabc_en = (mode > 0) ? 1 : 0;
3758
3759         if (cabc_en == 0) {
3760                 spin_lock(&lcdc_dev->reg_lock);
3761                 if (lcdc_dev->clk_on) {
3762                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3763                                      m_CABC_EN, v_CABC_EN(0));
3764                         lcdc_cfg_done(lcdc_dev);
3765                 }
3766                 spin_unlock(&lcdc_dev->reg_lock);
3767                 return 0;
3768         }
3769
3770         total_pixel = screen->mode.xres * screen->mode.yres;
3771         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3772         calc_pixel = (total_pixel * pixel_num) / 1000;
3773         stage_up = cabc_mode[mode - 1].stage_up;
3774         stage_down = cabc_mode[mode - 1].stage_down;
3775         global_su = cabc_mode[mode - 1].global_su;
3776
3777         stage_up_rec = 256 * 256 / stage_up;
3778         stage_down_rec = 256 * 256 / stage_down;
3779         global_su_rec = 256 * 256 / global_su;
3780
3781         spin_lock(&lcdc_dev->reg_lock);
3782         if (lcdc_dev->clk_on) {
3783                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3784                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3785                         v_CABC_EN(cabc_en);
3786                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3787
3788                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3789                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(0);
3790                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3791
3792                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3793                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3794                 val = v_CABC_STAGE_UP(stage_up) |
3795                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3796                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3797                     v_CABC_GLOBAL_SU_REC(global_su_rec);
3798                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3799
3800                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3801                     m_CABC_GLOBAL_SU;
3802                 val = v_CABC_STAGE_DOWN(stage_down) |
3803                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3804                     v_CABC_GLOBAL_SU(global_su);
3805                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3806                 lcdc_cfg_done(lcdc_dev);
3807         }
3808         spin_unlock(&lcdc_dev->reg_lock);
3809
3810         return 0;
3811 }
3812
3813 /*
3814         a:[-30~0]:
3815             sin_hue = sin(a)*256 +0x100;
3816             cos_hue = cos(a)*256;
3817         a:[0~30]
3818             sin_hue = sin(a)*256;
3819             cos_hue = cos(a)*256;
3820 */
3821 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3822                                     bcsh_hue_mode mode)
3823 {
3824         struct lcdc_device *lcdc_dev =
3825             container_of(dev_drv, struct lcdc_device, driver);
3826         u32 val;
3827
3828         spin_lock(&lcdc_dev->reg_lock);
3829         if (lcdc_dev->clk_on) {
3830                 val = lcdc_readl(lcdc_dev, BCSH_H);
3831                 switch (mode) {
3832                 case H_SIN:
3833                         val &= m_BCSH_SIN_HUE;
3834                         break;
3835                 case H_COS:
3836                         val &= m_BCSH_COS_HUE;
3837                         val >>= 16;
3838                         break;
3839                 default:
3840                         break;
3841                 }
3842         }
3843         spin_unlock(&lcdc_dev->reg_lock);
3844
3845         return val;
3846 }
3847
3848 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3849                                     int sin_hue, int cos_hue)
3850 {
3851         struct lcdc_device *lcdc_dev =
3852             container_of(dev_drv, struct lcdc_device, driver);
3853         u32 mask, val;
3854
3855         spin_lock(&lcdc_dev->reg_lock);
3856         if (lcdc_dev->clk_on) {
3857                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
3858                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
3859                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
3860                 lcdc_cfg_done(lcdc_dev);
3861         }
3862         spin_unlock(&lcdc_dev->reg_lock);
3863
3864         return 0;
3865 }
3866
3867 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3868                                     bcsh_bcs_mode mode, int value)
3869 {
3870         struct lcdc_device *lcdc_dev =
3871             container_of(dev_drv, struct lcdc_device, driver);
3872         u32 mask, val;
3873
3874         spin_lock(&lcdc_dev->reg_lock);
3875         if (lcdc_dev->clk_on) {
3876                 switch (mode) {
3877                 case BRIGHTNESS:
3878                         /*from 0 to 255,typical is 128 */
3879                         if (value < 0x80)
3880                                 value += 0x80;
3881                         else if (value >= 0x80)
3882                                 value = value - 0x80;
3883                         mask = m_BCSH_BRIGHTNESS;
3884                         val = v_BCSH_BRIGHTNESS(value);
3885                         break;
3886                 case CONTRAST:
3887                         /*from 0 to 510,typical is 256 */
3888                         mask = m_BCSH_CONTRAST;
3889                         val = v_BCSH_CONTRAST(value);
3890                         break;
3891                 case SAT_CON:
3892                         /*from 0 to 1015,typical is 256 */
3893                         mask = m_BCSH_SAT_CON;
3894                         val = v_BCSH_SAT_CON(value);
3895                         break;
3896                 default:
3897                         break;
3898                 }
3899                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
3900                 lcdc_cfg_done(lcdc_dev);
3901         }
3902         spin_unlock(&lcdc_dev->reg_lock);
3903         return val;
3904 }
3905
3906 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
3907                                     bcsh_bcs_mode mode)
3908 {
3909         struct lcdc_device *lcdc_dev =
3910             container_of(dev_drv, struct lcdc_device, driver);
3911         u32 val;
3912
3913         spin_lock(&lcdc_dev->reg_lock);
3914         if (lcdc_dev->clk_on) {
3915                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
3916                 switch (mode) {
3917                 case BRIGHTNESS:
3918                         val &= m_BCSH_BRIGHTNESS;
3919                         if (val > 0x80)
3920                                 val -= 0x80;
3921                         else
3922                                 val += 0x80;
3923                         break;
3924                 case CONTRAST:
3925                         val &= m_BCSH_CONTRAST;
3926                         val >>= 8;
3927                         break;
3928                 case SAT_CON:
3929                         val &= m_BCSH_SAT_CON;
3930                         val >>= 20;
3931                         break;
3932                 default:
3933                         break;
3934                 }
3935         }
3936         spin_unlock(&lcdc_dev->reg_lock);
3937         return val;
3938 }
3939
3940 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
3941 {
3942         struct lcdc_device *lcdc_dev =
3943             container_of(dev_drv, struct lcdc_device, driver);
3944         u32 mask, val;
3945
3946         spin_lock(&lcdc_dev->reg_lock);
3947         if (lcdc_dev->clk_on) {
3948                 if (open) {
3949                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
3950                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
3951                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
3952                         dev_drv->bcsh.enable = 1;
3953                 } else {
3954                         mask = m_BCSH_EN;
3955                         val = v_BCSH_EN(0);
3956                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
3957                         dev_drv->bcsh.enable = 0;
3958                 }
3959                 rk3368_lcdc_bcsh_path_sel(dev_drv);
3960                 lcdc_cfg_done(lcdc_dev);
3961         }
3962         spin_unlock(&lcdc_dev->reg_lock);
3963         return 0;
3964 }
3965
3966 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
3967 {
3968         if (!enable || !dev_drv->bcsh.enable) {
3969                 rk3368_lcdc_open_bcsh(dev_drv, false);
3970                 return 0;
3971         }
3972
3973         if (dev_drv->bcsh.brightness <= 255 ||
3974             dev_drv->bcsh.contrast <= 510 ||
3975             dev_drv->bcsh.sat_con <= 1015 ||
3976             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
3977                 rk3368_lcdc_open_bcsh(dev_drv, true);
3978                 if (dev_drv->bcsh.brightness <= 255)
3979                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
3980                                                  dev_drv->bcsh.brightness);
3981                 if (dev_drv->bcsh.contrast <= 510)
3982                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
3983                                                  dev_drv->bcsh.contrast);
3984                 if (dev_drv->bcsh.sat_con <= 1015)
3985                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
3986                                                  dev_drv->bcsh.sat_con);
3987                 if (dev_drv->bcsh.sin_hue <= 511 &&
3988                     dev_drv->bcsh.cos_hue <= 511)
3989                         rk3368_lcdc_set_bcsh_hue(dev_drv,
3990                                                  dev_drv->bcsh.sin_hue,
3991                                                  dev_drv->bcsh.cos_hue);
3992         }
3993         return 0;
3994 }
3995
3996 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
3997 {
3998         struct lcdc_device *lcdc_dev =
3999             container_of(dev_drv, struct lcdc_device, driver);
4000
4001         if (enable) {
4002                 spin_lock(&lcdc_dev->reg_lock);
4003                 if (likely(lcdc_dev->clk_on)) {
4004                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4005                                      v_DSP_BLACK_EN(1));
4006                         lcdc_cfg_done(lcdc_dev);
4007                 }
4008                 spin_unlock(&lcdc_dev->reg_lock);
4009         } else {
4010                 spin_lock(&lcdc_dev->reg_lock);
4011                 if (likely(lcdc_dev->clk_on)) {
4012                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4013                                      v_DSP_BLACK_EN(0));
4014
4015                         lcdc_cfg_done(lcdc_dev);
4016                 }
4017                 spin_unlock(&lcdc_dev->reg_lock);
4018         }
4019
4020         return 0;
4021 }
4022
4023
4024 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4025                                        int enable)
4026 {
4027         struct lcdc_device *lcdc_dev =
4028             container_of(dev_drv, struct lcdc_device, driver);
4029
4030         rk3368_lcdc_get_backlight_device(dev_drv);
4031
4032         if (enable) {
4033                 /* close the backlight */
4034                 if (lcdc_dev->backlight) {
4035                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4036                         backlight_update_status(lcdc_dev->backlight);
4037                 }
4038                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4039                         dev_drv->trsm_ops->disable();
4040         } else {
4041                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4042                         dev_drv->trsm_ops->enable();
4043                 msleep(100);
4044                 /* open the backlight */
4045                 if (lcdc_dev->backlight) {
4046                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4047                         backlight_update_status(lcdc_dev->backlight);
4048                 }
4049         }
4050
4051         return 0;
4052 }
4053
4054 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4055         .open = rk3368_lcdc_open,
4056         .win_direct_en = rk3368_lcdc_win_direct_en,
4057         .load_screen = rk3368_load_screen,
4058         .set_par = rk3368_lcdc_set_par,
4059         .pan_display = rk3368_lcdc_pan_display,
4060         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4061         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4062         .blank = rk3368_lcdc_blank,
4063         .ioctl = rk3368_lcdc_ioctl,
4064         .suspend = rk3368_lcdc_early_suspend,
4065         .resume = rk3368_lcdc_early_resume,
4066         .get_win_state = rk3368_lcdc_get_win_state,
4067         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4068         .get_disp_info = rk3368_lcdc_get_disp_info,
4069         .fps_mgr = rk3368_lcdc_fps_mgr,
4070         .fb_get_win_id = rk3368_lcdc_get_win_id,
4071         .fb_win_remap = rk3368_fb_win_remap,
4072         .set_dsp_lut = rk3368_lcdc_set_lut,
4073         .poll_vblank = rk3368_lcdc_poll_vblank,
4074         .dpi_open = rk3368_lcdc_dpi_open,
4075         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4076         .dpi_status = rk3368_lcdc_dpi_status,
4077         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4078         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4079         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4080         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4081         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4082         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4083         .open_bcsh = rk3368_lcdc_open_bcsh,
4084         .dump_reg = rk3368_lcdc_reg_dump,
4085         .cfg_done = rk3368_lcdc_config_done,
4086         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4087         .dsp_black = rk3368_lcdc_dsp_black,
4088         .backlight_close = rk3368_lcdc_backlight_close,
4089         .mmu_en    = rk3368_lcdc_mmu_en,
4090 };
4091
4092 #ifdef LCDC_IRQ_EMPTY_DEBUG
4093 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4094                                  unsigned int intr_status)
4095 {
4096         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4097                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4098                              v_WIN0_EMPTY_INTR_CLR(1));
4099                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4100         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4101                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4102                              v_WIN1_EMPTY_INTR_CLR(1));
4103                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4104         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4105                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4106                              v_WIN2_EMPTY_INTR_CLR(1));
4107                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4108         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4109                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4110                              v_WIN3_EMPTY_INTR_CLR(1));
4111                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4112         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4113                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4114                              v_HWC_EMPTY_INTR_CLR(1));
4115                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4116         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4117                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4118                              v_POST_BUF_EMPTY_INTR_CLR(1));
4119                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4120         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4121                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4122                              v_PWM_GEN_INTR_CLR(1));
4123                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4124         }
4125         return 0;
4126 }
4127 #endif
4128
4129 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4130 {
4131         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4132         ktime_t timestamp = ktime_get();
4133         u32 intr_status;
4134
4135         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4136
4137         if (intr_status & m_FS_INTR_STS) {
4138                 timestamp = ktime_get();
4139                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4140                              v_FS_INTR_CLR(1));
4141                 /*if(lcdc_dev->driver.wait_fs){ */
4142                 if (0) {
4143                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4144                         complete(&(lcdc_dev->driver.frame_done));
4145                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4146                 }
4147 #ifdef CONFIG_DRM_ROCKCHIP
4148                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4149 #endif
4150                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4151                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4152
4153         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4154                 lcdc_dev->driver.frame_time.last_framedone_t =
4155                     lcdc_dev->driver.frame_time.framedone_t;
4156                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4157                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4158                              v_LINE_FLAG0_INTR_CLR(1));
4159         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4160                 /*line flag1 */
4161                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4162                              v_LINE_FLAG1_INTR_CLR(1));
4163         } else if (intr_status & m_FS_NEW_INTR_STS) {
4164                 /*new frame start */
4165                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4166                              v_FS_NEW_INTR_CLR(1));
4167         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4168                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4169                              v_BUS_ERROR_INTR_CLR(1));
4170                 dev_warn(lcdc_dev->dev, "bus error!");
4171         }
4172
4173         /* for win empty debug */
4174 #ifdef LCDC_IRQ_EMPTY_DEBUG
4175         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4176 #endif
4177         return IRQ_HANDLED;
4178 }
4179
4180 #if defined(CONFIG_PM)
4181 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4182 {
4183         return 0;
4184 }
4185
4186 static int rk3368_lcdc_resume(struct platform_device *pdev)
4187 {
4188         return 0;
4189 }
4190 #else
4191 #define rk3368_lcdc_suspend NULL
4192 #define rk3368_lcdc_resume  NULL
4193 #endif
4194
4195 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4196 {
4197         struct device_node *np = lcdc_dev->dev->of_node;
4198         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4199         int val;
4200
4201         if (of_property_read_u32(np, "rockchip,prop", &val))
4202                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4203         else
4204                 lcdc_dev->prop = val;
4205
4206         if (of_property_read_u32(np, "rockchip,mirror", &val))
4207                 dev_drv->rotate_mode = NO_MIRROR;
4208         else
4209                 dev_drv->rotate_mode = val;
4210
4211         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4212                 dev_drv->cabc_mode = 0; /* default set close cabc */
4213         else
4214                 dev_drv->cabc_mode = val;
4215
4216         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4217                 /*default set it as 3.xv power supply */
4218                 lcdc_dev->pwr18 = false;
4219         else
4220                 lcdc_dev->pwr18 = (val ? true : false);
4221
4222         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4223                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4224         else
4225                 dev_drv->fb_win_map = val;
4226
4227         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4228                 dev_drv->bcsh.enable = false;
4229         else
4230                 dev_drv->bcsh.enable = (val ? true : false);
4231
4232         if (of_property_read_u32(np, "rockchip,brightness", &val))
4233                 dev_drv->bcsh.brightness = 0xffff;
4234         else
4235                 dev_drv->bcsh.brightness = val;
4236
4237         if (of_property_read_u32(np, "rockchip,contrast", &val))
4238                 dev_drv->bcsh.contrast = 0xffff;
4239         else
4240                 dev_drv->bcsh.contrast = val;
4241
4242         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4243                 dev_drv->bcsh.sat_con = 0xffff;
4244         else
4245                 dev_drv->bcsh.sat_con = val;
4246
4247         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4248                 dev_drv->bcsh.sin_hue = 0xffff;
4249                 dev_drv->bcsh.cos_hue = 0xffff;
4250         } else {
4251                 dev_drv->bcsh.sin_hue = val & 0xff;
4252                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4253         }
4254
4255 #if defined(CONFIG_ROCKCHIP_IOMMU)
4256         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4257                 dev_drv->iommu_enabled = 0;
4258         else
4259                 dev_drv->iommu_enabled = val;
4260 #else
4261         dev_drv->iommu_enabled = 0;
4262 #endif
4263         return 0;
4264 }
4265
4266 static int rk3368_lcdc_probe(struct platform_device *pdev)
4267 {
4268         struct lcdc_device *lcdc_dev = NULL;
4269         struct rk_lcdc_driver *dev_drv;
4270         struct device *dev = &pdev->dev;
4271         struct resource *res;
4272         struct device_node *np = pdev->dev.of_node;
4273         int prop;
4274         int ret = 0;
4275
4276         /*if the primary lcdc has not registered ,the extend
4277            lcdc register later */
4278         of_property_read_u32(np, "rockchip,prop", &prop);
4279         if (prop == EXTEND) {
4280                 if (!is_prmry_rk_lcdc_registered())
4281                         return -EPROBE_DEFER;
4282         }
4283         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4284         if (!lcdc_dev) {
4285                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4286                 return -ENOMEM;
4287         }
4288         platform_set_drvdata(pdev, lcdc_dev);
4289         lcdc_dev->dev = dev;
4290         rk3368_lcdc_parse_dt(lcdc_dev);
4291         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4292         lcdc_dev->reg_phy_base = res->start;
4293         lcdc_dev->len = resource_size(res);
4294         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4295         if (IS_ERR(lcdc_dev->regs))
4296                 return PTR_ERR(lcdc_dev->regs);
4297         else
4298                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4299
4300         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4301         if (IS_ERR(lcdc_dev->regsbak))
4302                 return PTR_ERR(lcdc_dev->regsbak);
4303         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4304         lcdc_dev->grf_base =
4305                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4306         if (IS_ERR(lcdc_dev->grf_base)) {
4307                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4308                 return PTR_ERR(lcdc_dev->grf_base);
4309         }
4310         lcdc_dev->pmugrf_base =
4311                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmu");
4312         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4313                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4314                 return PTR_ERR(lcdc_dev->pmugrf_base);
4315         }
4316         lcdc_dev->id = 0;
4317         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4318         dev_drv = &lcdc_dev->driver;
4319         dev_drv->dev = dev;
4320         dev_drv->prop = prop;
4321         dev_drv->id = lcdc_dev->id;
4322         dev_drv->ops = &lcdc_drv_ops;
4323         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4324         spin_lock_init(&lcdc_dev->reg_lock);
4325
4326         lcdc_dev->irq = platform_get_irq(pdev, 0);
4327         if (lcdc_dev->irq < 0) {
4328                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4329                         lcdc_dev->id);
4330                 return -ENXIO;
4331         }
4332
4333         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4334                                IRQF_DISABLED | IRQF_SHARED,
4335                                dev_name(dev), lcdc_dev);
4336         if (ret) {
4337                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4338                         lcdc_dev->irq, ret);
4339                 return ret;
4340         }
4341
4342         if (dev_drv->iommu_enabled) {
4343                 if (lcdc_dev->id == 0) {
4344                         strcpy(dev_drv->mmu_dts_name,
4345                                VOPB_IOMMU_COMPATIBLE_NAME);
4346                 } else {
4347                         strcpy(dev_drv->mmu_dts_name,
4348                                VOPL_IOMMU_COMPATIBLE_NAME);
4349                 }
4350         }
4351
4352         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4353         if (ret < 0) {
4354                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4355                 return ret;
4356         }
4357         lcdc_dev->screen = dev_drv->screen0;
4358         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4359                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4360
4361         return 0;
4362 }
4363
4364 static int rk3368_lcdc_remove(struct platform_device *pdev)
4365 {
4366         return 0;
4367 }
4368
4369 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4370 {
4371         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4372
4373         if (0) {/*maybe lead to crash*/
4374                 rk3368_lcdc_deint(lcdc_dev);
4375                 rk_disp_pwr_disable(&lcdc_dev->driver);
4376         } else {
4377                 rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4378         }
4379 }
4380
4381 #if defined(CONFIG_OF)
4382 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4383         {.compatible = "rockchip,rk3368-lcdc",},
4384         {}
4385 };
4386 #endif
4387
4388 static struct platform_driver rk3368_lcdc_driver = {
4389         .probe = rk3368_lcdc_probe,
4390         .remove = rk3368_lcdc_remove,
4391         .driver = {
4392                    .name = "rk3368-lcdc",
4393                    .owner = THIS_MODULE,
4394                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4395                    },
4396         .suspend = rk3368_lcdc_suspend,
4397         .resume = rk3368_lcdc_resume,
4398         .shutdown = rk3368_lcdc_shutdown,
4399 };
4400
4401 static int __init rk3368_lcdc_module_init(void)
4402 {
4403         return platform_driver_register(&rk3368_lcdc_driver);
4404 }
4405
4406 static void __exit rk3368_lcdc_module_exit(void)
4407 {
4408         platform_driver_unregister(&rk3368_lcdc_driver);
4409 }
4410
4411 fs_initcall(rk3368_lcdc_module_init);
4412 module_exit(rk3368_lcdc_module_exit);