drivers/video/rockchip/lcdc/rk3368_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3368_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  *Author:hjc<hjc@rock-chips.com>
   6  *This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <linux/rockchip-iovmm.h>
  30 #include <asm/div64.h>
  31 #include <linux/uaccess.h>
  32 #include <linux/rockchip/cpu.h>
  33 #include <linux/rockchip/iomap.h>
  34 #include <linux/rockchip/grf.h>
  35 #include <linux/rockchip/common.h>
  36 #include <dt-bindings/clock/rk_system_status.h>
  37
  38 #include "rk3368_lcdc.h"
  39
  40 #if defined(CONFIG_HAS_EARLYSUSPEND)
  41 #include <linux/earlysuspend.h>
  42 #endif
  43 /*#define CONFIG_RK_FPGA 1*/
  44
  45 static int dbg_thresd;
  46 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  47
  48 #define DBG(level, x...) do {                   \
  49         if (unlikely(dbg_thresd >= level))      \
  50                 pr_info(x);\
  51         } while (0)
  52
  53 static struct rk_lcdc_win lcdc_win[] = {
  54         [0] = {
  55                .name = "win0",
  56                .id = 0,
  57                .support_3d = false,
  58                },
  59         [1] = {
  60                .name = "win1",
  61                .id = 1,
  62                .support_3d = false,
  63                },
  64         [2] = {
  65                .name = "win2",
  66                .id = 2,
  67                .support_3d = false,
  68                },
  69         [3] = {
  70                .name = "win3",
  71                .id = 3,
  72                .support_3d = false,
  73                },
  74         [4] = {
  75                .name = "hwc",
  76                .id = 4,
  77                .support_3d = false,
  78                }
  79 };
  80
  81 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable);
  82
  83 /*#define WAIT_FOR_SYNC 1*/
  84 u32 rk3368_get_hard_ware_vskiplines(u32 srch, u32 dsth)
  85 {
  86         u32 vscalednmult;
  87
  88         if (srch >= (u32) (4 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  89                 vscalednmult = 4;
  90         else if (srch >= (u32) (2 * dsth * MIN_SCALE_FACTOR_AFTER_VSKIP))
  91                 vscalednmult = 2;
  92         else
  93                 vscalednmult = 1;
  94
  95         return vscalednmult;
  96 }
  97
  98
  99 static int rk3368_set_cabc_lut(struct rk_lcdc_driver *dev_drv, int *cabc_lut)
 100 {
 101         int i;
 102         int __iomem *c;
 103         u32 v;
 104         struct lcdc_device *lcdc_dev =
 105             container_of(dev_drv, struct lcdc_device, driver);
 106
 107         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 108                      v_CABC_LUT_EN(0));
 109         lcdc_cfg_done(lcdc_dev);
 110         mdelay(25);
 111         for (i = 0; i < 256; i++) {
 112                 v = cabc_lut[i];
 113                 c = lcdc_dev->cabc_lut_addr_base + i;
 114                 writel_relaxed(v, c);
 115         }
 116         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
 117                      v_CABC_LUT_EN(1));
 118         return 0;
 119 }
 120
 121
 122 static int rk3368_lcdc_set_lut(struct rk_lcdc_driver *dev_drv, int *dsp_lut)
 123 {
 124         int i;
 125         int __iomem *c;
 126         u32 v;
 127         struct lcdc_device *lcdc_dev =
 128             container_of(dev_drv, struct lcdc_device, driver);
 129
 130         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 131                      v_DSP_LUT_EN(0));
 132         lcdc_cfg_done(lcdc_dev);
 133         mdelay(25);
 134         for (i = 0; i < 256; i++) {
 135                 v = dsp_lut[i];
 136                 c = lcdc_dev->dsp_lut_addr_base + i;
 137                 writel_relaxed(v, c);
 138         }
 139         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
 140                      v_DSP_LUT_EN(1));
 141
 142         return 0;
 143 }
 144
 145 static int rk3368_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 146 {
 147 #ifdef CONFIG_RK_FPGA
 148         lcdc_dev->clk_on = 1;
 149         return 0;
 150 #endif
 151         if (!lcdc_dev->clk_on) {
 152                 clk_prepare_enable(lcdc_dev->hclk);
 153                 clk_prepare_enable(lcdc_dev->dclk);
 154                 clk_prepare_enable(lcdc_dev->aclk);
 155                 /*clk_prepare_enable(lcdc_dev->pd);*/
 156                 spin_lock(&lcdc_dev->reg_lock);
 157                 lcdc_dev->clk_on = 1;
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         }
 160
 161         return 0;
 162 }
 163
 164 static int rk3368_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 165 {
 166 #ifdef CONFIG_RK_FPGA
 167         lcdc_dev->clk_on = 0;
 168         return 0;
 169 #endif
 170         if (lcdc_dev->clk_on) {
 171                 spin_lock(&lcdc_dev->reg_lock);
 172                 lcdc_dev->clk_on = 0;
 173                 spin_unlock(&lcdc_dev->reg_lock);
 174                 mdelay(25);
 175                 clk_disable_unprepare(lcdc_dev->dclk);
 176                 clk_disable_unprepare(lcdc_dev->hclk);
 177                 clk_disable_unprepare(lcdc_dev->aclk);
 178                 /*clk_disable_unprepare(lcdc_dev->pd);*/
 179         }
 180
 181         return 0;
 182 }
 183
 184 static int __maybe_unused
 185         rk3368_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 186 {
 187         u32 mask, val;
 188
 189         spin_lock(&lcdc_dev->reg_lock);
 190         if (likely(lcdc_dev->clk_on)) {
 191                 mask = m_FS_INTR_EN | m_FS_NEW_INTR_EN |
 192                     m_ADDR_SAME_INTR_EN | m_LINE_FLAG0_INTR_EN |
 193                     m_LINE_FLAG1_INTR_EN | m_BUS_ERROR_INTR_EN |
 194                     m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
 195                     m_WIN2_EMPTY_INTR_EN | m_WIN3_EMPTY_INTR_EN |
 196                     m_HWC_EMPTY_INTR_EN | m_POST_BUF_EMPTY_INTR_EN |
 197                     m_PWM_GEN_INTR_EN | m_DSP_HOLD_VALID_INTR_EN;
 198                 val = v_FS_INTR_EN(0) | v_FS_NEW_INTR_EN(0) |
 199                     v_ADDR_SAME_INTR_EN(0) |
 200                     v_LINE_FLAG0_INTR_EN(0) | v_LINE_FLAG1_INTR_EN(0) |
 201                     v_BUS_ERROR_INTR_EN(0) | v_WIN0_EMPTY_INTR_EN(0) |
 202                     v_WIN1_EMPTY_INTR_EN(0) | v_WIN2_EMPTY_INTR_EN(0) |
 203                     v_WIN3_EMPTY_INTR_EN(0) | v_HWC_EMPTY_INTR_EN(0) |
 204                     v_POST_BUF_EMPTY_INTR_EN(0) |
 205                     v_PWM_GEN_INTR_EN(0) | v_DSP_HOLD_VALID_INTR_EN(0);
 206                 lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
 207
 208                 mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR |
 209                     m_ADDR_SAME_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
 210                     m_LINE_FLAG1_INTR_CLR | m_BUS_ERROR_INTR_CLR |
 211                     m_WIN0_EMPTY_INTR_CLR | m_WIN1_EMPTY_INTR_CLR |
 212                     m_WIN2_EMPTY_INTR_CLR | m_WIN3_EMPTY_INTR_CLR |
 213                     m_HWC_EMPTY_INTR_CLR | m_POST_BUF_EMPTY_INTR_CLR |
 214                     m_PWM_GEN_INTR_CLR | m_DSP_HOLD_VALID_INTR_CLR;
 215                 val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
 216                     v_ADDR_SAME_INTR_CLR(1) |
 217                     v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1) |
 218                     v_BUS_ERROR_INTR_CLR(1) | v_WIN0_EMPTY_INTR_CLR(1) |
 219                     v_WIN1_EMPTY_INTR_CLR(1) | v_WIN2_EMPTY_INTR_CLR(1) |
 220                     v_WIN3_EMPTY_INTR_CLR(1) | v_HWC_EMPTY_INTR_CLR(1) |
 221                     v_POST_BUF_EMPTY_INTR_CLR(1) |
 222                     v_PWM_GEN_INTR_CLR(1) | v_DSP_HOLD_VALID_INTR_CLR(1);
 223                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
 224                 lcdc_cfg_done(lcdc_dev);
 225                 spin_unlock(&lcdc_dev->reg_lock);
 226         } else {
 227                 spin_unlock(&lcdc_dev->reg_lock);
 228         }
 229         mdelay(1);
 230         return 0;
 231 }
 232
 233 static int rk3368_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
 234 {
 235         struct lcdc_device *lcdc_dev =
 236             container_of(dev_drv, struct lcdc_device, driver);
 237         int *cbase = (int *)lcdc_dev->regs;
 238         int *regsbak = (int *)lcdc_dev->regsbak;
 239         int i, j, val;
 240         char dbg_message[30];
 241         char buf[10];
 242
 243         pr_info("lcd back up reg:\n");
 244         memset(dbg_message, 0, sizeof(dbg_message));
 245         memset(buf, 0, sizeof(buf));
 246         for (i = 0; i <= (0x200 >> 4); i++) {
 247                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 248                 for (j = 0; j < 4; j++) {
 249                         val = sprintf(buf, "%08x  ", *(regsbak + i * 4 + j));
 250                         strcat(dbg_message, buf);
 251                 }
 252                 pr_info("%s\n", dbg_message);
 253                 memset(dbg_message, 0, sizeof(dbg_message));
 254                 memset(buf, 0, sizeof(buf));
 255         }
 256
 257         pr_info("lcdc reg:\n");
 258         for (i = 0; i <= (0x200 >> 4); i++) {
 259                 val = sprintf(dbg_message, "0x%04x: ", i * 16);
 260                 for (j = 0; j < 4; j++) {
 261                         sprintf(buf, "%08x  ",
 262                                 readl_relaxed(cbase + i * 4 + j));
 263                         strcat(dbg_message, buf);
 264                 }
 265                 pr_info("%s\n", dbg_message);
 266                 memset(dbg_message, 0, sizeof(dbg_message));
 267                 memset(buf, 0, sizeof(buf));
 268         }
 269
 270         return 0;
 271 }
 272
 273 #define WIN_EN(id)              \
 274 static int win##id##_enable(struct lcdc_device *lcdc_dev, int en)       \
 275 { \
 276         u32 msk, val;                                                   \
 277         spin_lock(&lcdc_dev->reg_lock);                                 \
 278         msk =  m_WIN##id##_EN;                                          \
 279         val  =  v_WIN##id##_EN(en);                                     \
 280         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);              \
 281         lcdc_cfg_done(lcdc_dev);                                        \
 282         val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);            \
 283         while (val !=  (!!en))  {                                       \
 284                 val = lcdc_read_bit(lcdc_dev, WIN##id##_CTRL0, msk);    \
 285         }                                                               \
 286         spin_unlock(&lcdc_dev->reg_lock);                               \
 287         return 0;                                                       \
 288 }
 289
 290 WIN_EN(0);
 291 WIN_EN(1);
 292 WIN_EN(2);
 293 WIN_EN(3);
 294 /*enable/disable win directly*/
 295 static int rk3368_lcdc_win_direct_en(struct rk_lcdc_driver *drv,
 296                                      int win_id, int en)
 297 {
 298         struct lcdc_device *lcdc_dev =
 299             container_of(drv, struct lcdc_device, driver);
 300         if (win_id == 0)
 301                 win0_enable(lcdc_dev, en);
 302         else if (win_id == 1)
 303                 win1_enable(lcdc_dev, en);
 304         else if (win_id == 2)
 305                 win2_enable(lcdc_dev, en);
 306         else if (win_id == 3)
 307                 win3_enable(lcdc_dev, en);
 308         else
 309                 dev_err(lcdc_dev->dev, "invalid win number:%d\n", win_id);
 310         return 0;
 311 }
 312
 313 #define SET_WIN_ADDR(id) \
 314 static int set_win##id##_addr(struct lcdc_device *lcdc_dev, u32 addr) \
 315 {                                                       \
 316         u32 msk, val;                                   \
 317         spin_lock(&lcdc_dev->reg_lock);                 \
 318         lcdc_writel(lcdc_dev, WIN##id##_YRGB_MST, addr);        \
 319         msk =  m_WIN##id##_EN;                          \
 320         val  =  v_WIN0_EN(1);                           \
 321         lcdc_msk_reg(lcdc_dev, WIN##id##_CTRL0, msk, val);      \
 322         lcdc_cfg_done(lcdc_dev);                        \
 323         spin_unlock(&lcdc_dev->reg_lock);               \
 324         return 0;                                       \
 325 }
 326
 327 SET_WIN_ADDR(0);
 328 SET_WIN_ADDR(1);
 329 int rk3368_lcdc_direct_set_win_addr(struct rk_lcdc_driver *dev_drv,
 330                                     int win_id, u32 addr)
 331 {
 332         struct lcdc_device *lcdc_dev =
 333             container_of(dev_drv, struct lcdc_device, driver);
 334         if (win_id == 0)
 335                 set_win0_addr(lcdc_dev, addr);
 336         else
 337                 set_win1_addr(lcdc_dev, addr);
 338
 339         return 0;
 340 }
 341
 342 static void lcdc_read_reg_defalut_cfg(struct lcdc_device *lcdc_dev)
 343 {
 344         int reg = 0;
 345         u32 val = 0;
 346         struct rk_screen *screen = lcdc_dev->driver.cur_screen;
 347         u32 h_pw_bp = screen->mode.hsync_len + screen->mode.left_margin;
 348         u32 v_pw_bp = screen->mode.vsync_len + screen->mode.upper_margin;
 349         u32 st_x, st_y;
 350         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 351
 352         spin_lock(&lcdc_dev->reg_lock);
 353         for (reg = 0; reg < SCAN_LINE_NUM; reg += 4) {
 354                 val = lcdc_readl_backup(lcdc_dev, reg);
 355                 switch (reg) {
 356                 case WIN0_ACT_INFO:
 357                         win0->area[0].xact = (val & m_WIN0_ACT_WIDTH) + 1;
 358                         win0->area[0].yact =
 359                             ((val & m_WIN0_ACT_HEIGHT) >> 16) + 1;
 360                         break;
 361                 case WIN0_DSP_INFO:
 362                         win0->area[0].xsize = (val & m_WIN0_DSP_WIDTH) + 1;
 363                         win0->area[0].ysize =
 364                             ((val & m_WIN0_DSP_HEIGHT) >> 16) + 1;
 365                         break;
 366                 case WIN0_DSP_ST:
 367                         st_x = val & m_WIN0_DSP_XST;
 368                         st_y = (val & m_WIN0_DSP_YST) >> 16;
 369                         win0->area[0].xpos = st_x - h_pw_bp;
 370                         win0->area[0].ypos = st_y - v_pw_bp;
 371                         break;
 372                 case WIN0_CTRL0:
 373                         win0->state = val & m_WIN0_EN;
 374                         win0->area[0].fmt_cfg = (val & m_WIN0_DATA_FMT) >> 1;
 375                         win0->fmt_10 = (val & m_WIN0_FMT_10) >> 4;
 376                         win0->area[0].format = win0->area[0].fmt_cfg;
 377                         break;
 378                 case WIN0_VIR:
 379                         win0->area[0].y_vir_stride = val & m_WIN0_VIR_STRIDE;
 380                         win0->area[0].uv_vir_stride =
 381                             (val & m_WIN0_VIR_STRIDE_UV) >> 16;
 382                         if (win0->area[0].format == ARGB888)
 383                                 win0->area[0].xvir = win0->area[0].y_vir_stride;
 384                         else if (win0->area[0].format == RGB888)
 385                                 win0->area[0].xvir =
 386                                     win0->area[0].y_vir_stride * 4 / 3;
 387                         else if (win0->area[0].format == RGB565)
 388                                 win0->area[0].xvir =
 389                                     2 * win0->area[0].y_vir_stride;
 390                         else    /* YUV */
 391                                 win0->area[0].xvir =
 392                                     4 * win0->area[0].y_vir_stride;
 393                         break;
 394                 case WIN0_YRGB_MST:
 395                         win0->area[0].smem_start = val;
 396                         break;
 397                 case WIN0_CBR_MST:
 398                         win0->area[0].cbr_start = val;
 399                         break;
 400                 default:
 401                         break;
 402                 }
 403         }
 404         spin_unlock(&lcdc_dev->reg_lock);
 405 }
 406
 407 /********do basic init*********/
 408 static int rk3368_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 409 {
 410         u32 mask, val, v;
 411         struct lcdc_device *lcdc_dev =
 412             container_of(dev_drv, struct lcdc_device, driver);
 413         if (lcdc_dev->pre_init)
 414                 return 0;
 415
 416         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 417         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 418         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 419         /*lcdc_dev->pd = devm_clk_get(lcdc_dev->dev, "pd_lcdc");*/
 420
 421         if (/*IS_ERR(lcdc_dev->pd) || */(IS_ERR(lcdc_dev->aclk)) ||
 422             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 423                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 424                         lcdc_dev->id);
 425         }
 426
 427         rk_disp_pwr_enable(dev_drv);
 428         rk3368_lcdc_clk_enable(lcdc_dev);
 429
 430         /*backup reg config at uboot */
 431         lcdc_read_reg_defalut_cfg(lcdc_dev);
 432         if (lcdc_dev->pwr18 == 1) {
 433                 v = 0x00200020; /*bit5: 1,1.8v;0,3.3v*/
 434                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 435                                 PMUGRF_SOC_CON0_VOP, v);
 436         } else {
 437                 v = 0x00200000; /*bit5: 1,1.8v;0,3.3v*/
 438                 lcdc_grf_writel(lcdc_dev->pmugrf_base,
 439                                 PMUGRF_SOC_CON0_VOP, v);
 440         }
 441         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_0, 0x15110903);
 442         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE0_1, 0x00030911);
 443         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_0, 0x1a150b04);
 444         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE1_1, 0x00040b15);
 445         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_0, 0x15110903);
 446         lcdc_writel(lcdc_dev, CABC_GAUSS_LINE2_1, 0x00030911);
 447
 448         lcdc_writel(lcdc_dev, FRC_LOWER01_0, 0x12844821);
 449         lcdc_writel(lcdc_dev, FRC_LOWER01_1, 0x21488412);
 450         lcdc_writel(lcdc_dev, FRC_LOWER10_0, 0xa55a9696);
 451         lcdc_writel(lcdc_dev, FRC_LOWER10_1, 0x5aa56969);
 452         lcdc_writel(lcdc_dev, FRC_LOWER11_0, 0xdeb77deb);
 453         lcdc_writel(lcdc_dev, FRC_LOWER11_1, 0xed7bb7de);
 454
 455         mask = m_AUTO_GATING_EN;
 456         val = v_AUTO_GATING_EN(0);
 457         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 458         lcdc_cfg_done(lcdc_dev);
 459         /*disable win0 to workaround iommu pagefault */
 460         /*if (dev_drv->iommu_enabled) */
 461         /*      win0_enable(lcdc_dev, 0); */
 462         lcdc_dev->pre_init = true;
 463
 464         return 0;
 465 }
 466
 467 static void rk3368_lcdc_deint(struct lcdc_device *lcdc_dev)
 468 {
 469 }
 470
 471 static int rk3368_lcdc_post_cfg(struct rk_lcdc_driver *dev_drv)
 472 {
 473         struct lcdc_device *lcdc_dev =
 474             container_of(dev_drv, struct lcdc_device, driver);
 475         struct rk_screen *screen = dev_drv->cur_screen;
 476         u16 x_res = screen->mode.xres;
 477         u16 y_res = screen->mode.yres;
 478         u32 mask, val;
 479         u16 h_total, v_total;
 480         u16 post_hsd_en, post_vsd_en;
 481         u16 post_dsp_hact_st, post_dsp_hact_end;
 482         u16 post_dsp_vact_st, post_dsp_vact_end;
 483         u16 post_dsp_vact_st_f1, post_dsp_vact_end_f1;
 484         u16 post_h_fac, post_v_fac;
 485
 486         screen->post_dsp_stx = x_res * (100 - dev_drv->overscan.left) / 200;
 487         screen->post_dsp_sty = y_res * (100 - dev_drv->overscan.top) / 200;
 488         screen->post_xsize = x_res *
 489             (dev_drv->overscan.left + dev_drv->overscan.right) / 200;
 490         screen->post_ysize = y_res *
 491             (dev_drv->overscan.top + dev_drv->overscan.bottom) / 200;
 492
 493         h_total = screen->mode.hsync_len + screen->mode.left_margin +
 494             x_res + screen->mode.right_margin;
 495         v_total = screen->mode.vsync_len + screen->mode.upper_margin +
 496             y_res + screen->mode.lower_margin;
 497
 498         if (screen->post_dsp_stx + screen->post_xsize > x_res) {
 499                 dev_warn(lcdc_dev->dev, "post:stx[%d]+xsize[%d]>x_res[%d]\n",
 500                          screen->post_dsp_stx, screen->post_xsize, x_res);
 501                 screen->post_dsp_stx = x_res - screen->post_xsize;
 502         }
 503         if (screen->x_mirror == 0) {
 504                 post_dsp_hact_st = screen->post_dsp_stx +
 505                     screen->mode.hsync_len + screen->mode.left_margin;
 506                 post_dsp_hact_end = post_dsp_hact_st + screen->post_xsize;
 507         } else {
 508                 post_dsp_hact_end = h_total - screen->mode.right_margin -
 509                     screen->post_dsp_stx;
 510                 post_dsp_hact_st = post_dsp_hact_end - screen->post_xsize;
 511         }
 512         if ((screen->post_xsize < x_res) && (screen->post_xsize != 0)) {
 513                 post_hsd_en = 1;
 514                 post_h_fac =
 515                     GET_SCALE_FACTOR_BILI_DN(x_res, screen->post_xsize);
 516         } else {
 517                 post_hsd_en = 0;
 518                 post_h_fac = 0x1000;
 519         }
 520
 521         if (screen->post_dsp_sty + screen->post_ysize > y_res) {
 522                 dev_warn(lcdc_dev->dev, "post:sty[%d]+ysize[%d]> y_res[%d]\n",
 523                          screen->post_dsp_sty, screen->post_ysize, y_res);
 524                 screen->post_dsp_sty = y_res - screen->post_ysize;
 525         }
 526
 527         if ((screen->post_ysize < y_res) && (screen->post_ysize != 0)) {
 528                 post_vsd_en = 1;
 529                 post_v_fac = GET_SCALE_FACTOR_BILI_DN(y_res,
 530                                                       screen->post_ysize);
 531         } else {
 532                 post_vsd_en = 0;
 533                 post_v_fac = 0x1000;
 534         }
 535
 536         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 537                 post_dsp_vact_st = screen->post_dsp_sty / 2 +
 538                                         screen->mode.vsync_len +
 539                                         screen->mode.upper_margin;
 540                 post_dsp_vact_end = post_dsp_vact_st +
 541                                         screen->post_ysize / 2;
 542
 543                 post_dsp_vact_st_f1 = screen->mode.vsync_len +
 544                                       screen->mode.upper_margin +
 545                                       y_res/2 +
 546                                       screen->mode.lower_margin +
 547                                       screen->mode.vsync_len +
 548                                       screen->mode.upper_margin +
 549                                       screen->post_dsp_sty / 2 +
 550                                       1;
 551                 post_dsp_vact_end_f1 = post_dsp_vact_st_f1 +
 552                                         screen->post_ysize/2;
 553         } else {
 554                 if (screen->y_mirror == 0) {
 555                         post_dsp_vact_st = screen->post_dsp_sty +
 556                             screen->mode.vsync_len +
 557                             screen->mode.upper_margin;
 558                         post_dsp_vact_end = post_dsp_vact_st +
 559                                 screen->post_ysize;
 560                 } else {
 561                         post_dsp_vact_end = v_total -
 562                                 screen->mode.lower_margin -
 563                             screen->post_dsp_sty;
 564                         post_dsp_vact_st = post_dsp_vact_end -
 565                                 screen->post_ysize;
 566                 }
 567                 post_dsp_vact_st_f1 = 0;
 568                 post_dsp_vact_end_f1 = 0;
 569         }
 570         DBG(1, "post:xsize=%d,ysize=%d,xpos=%d",
 571             screen->post_xsize, screen->post_ysize, screen->xpos);
 572         DBG(1, ",ypos=%d,hsd_en=%d,h_fac=%d,vsd_en=%d,v_fac=%d\n",
 573             screen->ypos, post_hsd_en, post_h_fac, post_vsd_en, post_v_fac);
 574         mask = m_DSP_HACT_END_POST | m_DSP_HACT_ST_POST;
 575         val = v_DSP_HACT_END_POST(post_dsp_hact_end) |
 576             v_DSP_HACT_ST_POST(post_dsp_hact_st);
 577         lcdc_msk_reg(lcdc_dev, POST_DSP_HACT_INFO, mask, val);
 578
 579         mask = m_DSP_VACT_END_POST | m_DSP_VACT_ST_POST;
 580         val = v_DSP_VACT_END_POST(post_dsp_vact_end) |
 581             v_DSP_VACT_ST_POST(post_dsp_vact_st);
 582         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO, mask, val);
 583
 584         mask = m_POST_HS_FACTOR_YRGB | m_POST_VS_FACTOR_YRGB;
 585         val = v_POST_HS_FACTOR_YRGB(post_h_fac) |
 586             v_POST_VS_FACTOR_YRGB(post_v_fac);
 587         lcdc_msk_reg(lcdc_dev, POST_SCL_FACTOR_YRGB, mask, val);
 588
 589         mask = m_DSP_VACT_END_POST_F1 | m_DSP_VACT_ST_POST_F1;
 590         val = v_DSP_VACT_END_POST_F1(post_dsp_vact_end_f1) |
 591             v_DSP_VACT_ST_POST_F1(post_dsp_vact_st_f1);
 592         lcdc_msk_reg(lcdc_dev, POST_DSP_VACT_INFO_F1, mask, val);
 593
 594         mask = m_POST_HOR_SD_EN | m_POST_VER_SD_EN;
 595         val = v_POST_HOR_SD_EN(post_hsd_en) | v_POST_VER_SD_EN(post_vsd_en);
 596         lcdc_msk_reg(lcdc_dev, POST_SCL_CTRL, mask, val);
 597         return 0;
 598 }
 599
 600 static int rk3368_lcdc_clr_key_cfg(struct rk_lcdc_driver *dev_drv)
 601 {
 602         struct lcdc_device *lcdc_dev =
 603             container_of(dev_drv, struct lcdc_device, driver);
 604         struct rk_lcdc_win *win;
 605         u32 colorkey_r, colorkey_g, colorkey_b;
 606         int i, key_val;
 607
 608         for (i = 0; i < 4; i++) {
 609                 win = dev_drv->win[i];
 610                 key_val = win->color_key_val;
 611                 colorkey_r = (key_val & 0xff) << 2;
 612                 colorkey_g = ((key_val >> 8) & 0xff) << 12;
 613                 colorkey_b = ((key_val >> 16) & 0xff) << 22;
 614                 /*color key dither 565/888->aaa */
 615                 key_val = colorkey_r | colorkey_g | colorkey_b;
 616                 switch (i) {
 617                 case 0:
 618                         lcdc_writel(lcdc_dev, WIN0_COLOR_KEY, key_val);
 619                         break;
 620                 case 1:
 621                         lcdc_writel(lcdc_dev, WIN1_COLOR_KEY, key_val);
 622                         break;
 623                 case 2:
 624                         lcdc_writel(lcdc_dev, WIN2_COLOR_KEY, key_val);
 625                         break;
 626                 case 3:
 627                         lcdc_writel(lcdc_dev, WIN3_COLOR_KEY, key_val);
 628                         break;
 629                 default:
 630                         pr_info("%s:un support win num:%d\n",
 631                                 __func__, i);
 632                         break;
 633                 }
 634         }
 635         return 0;
 636 }
 637
 638 static int rk3368_lcdc_alpha_cfg(struct rk_lcdc_driver *dev_drv, int win_id)
 639 {
 640         struct lcdc_device *lcdc_dev =
 641             container_of(dev_drv, struct lcdc_device, driver);
 642         struct rk_lcdc_win *win = dev_drv->win[win_id];
 643         struct alpha_config alpha_config;
 644         u32 mask, val;
 645         int ppixel_alpha = 0, global_alpha = 0, i;
 646         u32 src_alpha_ctl, dst_alpha_ctl;
 647
 648         for (i = 0; i < win->area_num; i++) {
 649                 ppixel_alpha |= ((win->area[i].format == ARGB888) ||
 650                                  (win->area[i].format == FBDC_ARGB_888) ||
 651                                  (win->area[i].format == ABGR888)) ? 1 : 0;
 652         }
 653         global_alpha = (win->g_alpha_val == 0) ? 0 : 1;
 654         alpha_config.src_global_alpha_val = win->g_alpha_val;
 655         win->alpha_mode = AB_SRC_OVER;
 656         /*printk("%s,alpha_mode=%d,alpha_en=%d,ppixel_a=%d,gla_a=%d\n",
 657            __func__,win->alpha_mode,win->alpha_en,ppixel_alpha,
 658            global_alpha); */
 659         switch (win->alpha_mode) {
 660         case AB_USER_DEFINE:
 661                 break;
 662         case AB_CLEAR:
 663                 alpha_config.src_factor_mode = AA_ZERO;
 664                 alpha_config.dst_factor_mode = AA_ZERO;
 665                 break;
 666         case AB_SRC:
 667                 alpha_config.src_factor_mode = AA_ONE;
 668                 alpha_config.dst_factor_mode = AA_ZERO;
 669                 break;
 670         case AB_DST:
 671                 alpha_config.src_factor_mode = AA_ZERO;
 672                 alpha_config.dst_factor_mode = AA_ONE;
 673                 break;
 674         case AB_SRC_OVER:
 675                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 676                 if (global_alpha)
 677                         alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 678                 else
 679                         alpha_config.src_factor_mode = AA_ONE;
 680                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 681                 break;
 682         case AB_DST_OVER:
 683                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 684                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 685                 alpha_config.dst_factor_mode = AA_ONE;
 686                 break;
 687         case AB_SRC_IN:
 688                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 689                 alpha_config.src_factor_mode = AA_SRC;
 690                 alpha_config.dst_factor_mode = AA_ZERO;
 691                 break;
 692         case AB_DST_IN:
 693                 alpha_config.src_factor_mode = AA_ZERO;
 694                 alpha_config.dst_factor_mode = AA_SRC;
 695                 break;
 696         case AB_SRC_OUT:
 697                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 698                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 699                 alpha_config.dst_factor_mode = AA_ZERO;
 700                 break;
 701         case AB_DST_OUT:
 702                 alpha_config.src_factor_mode = AA_ZERO;
 703                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 704                 break;
 705         case AB_SRC_ATOP:
 706                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 707                 alpha_config.src_factor_mode = AA_SRC;
 708                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 709                 break;
 710         case AB_DST_ATOP:
 711                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 712                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 713                 alpha_config.dst_factor_mode = AA_SRC;
 714                 break;
 715         case XOR:
 716                 alpha_config.src_color_mode = AA_SRC_PRE_MUL;
 717                 alpha_config.src_factor_mode = AA_SRC_INVERSE;
 718                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 719                 break;
 720         case AB_SRC_OVER_GLOBAL:
 721                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 722                 alpha_config.src_color_mode = AA_SRC_NO_PRE_MUL;
 723                 alpha_config.src_factor_mode = AA_SRC_GLOBAL;
 724                 alpha_config.dst_factor_mode = AA_SRC_INVERSE;
 725                 break;
 726         default:
 727                 pr_err("alpha mode error\n");
 728                 break;
 729         }
 730         if ((ppixel_alpha == 1) && (global_alpha == 1))
 731                 alpha_config.src_global_alpha_mode = AA_PER_PIX_GLOBAL;
 732         else if (ppixel_alpha == 1)
 733                 alpha_config.src_global_alpha_mode = AA_PER_PIX;
 734         else if (global_alpha == 1)
 735                 alpha_config.src_global_alpha_mode = AA_GLOBAL;
 736         else
 737                 dev_warn(lcdc_dev->dev, "alpha_en should be 0\n");
 738         alpha_config.src_alpha_mode = AA_STRAIGHT;
 739         alpha_config.src_alpha_cal_m0 = AA_NO_SAT;
 740
 741         switch (win_id) {
 742         case 0:
 743                 src_alpha_ctl = 0x60;
 744                 dst_alpha_ctl = 0x64;
 745                 break;
 746         case 1:
 747                 src_alpha_ctl = 0xa0;
 748                 dst_alpha_ctl = 0xa4;
 749                 break;
 750         case 2:
 751                 src_alpha_ctl = 0xdc;
 752                 dst_alpha_ctl = 0xec;
 753                 break;
 754         case 3:
 755                 src_alpha_ctl = 0x12c;
 756                 dst_alpha_ctl = 0x13c;
 757                 break;
 758         case 4:
 759                 src_alpha_ctl = 0x160;
 760                 dst_alpha_ctl = 0x164;
 761                 break;
 762         }
 763         mask = m_WIN0_DST_FACTOR_M0;
 764         val = v_WIN0_DST_FACTOR_M0(alpha_config.dst_factor_mode);
 765         lcdc_msk_reg(lcdc_dev, dst_alpha_ctl, mask, val);
 766         mask = m_WIN0_SRC_ALPHA_EN | m_WIN0_SRC_COLOR_M0 |
 767             m_WIN0_SRC_ALPHA_M0 | m_WIN0_SRC_BLEND_M0 |
 768             m_WIN0_SRC_ALPHA_CAL_M0 | m_WIN0_SRC_FACTOR_M0 |
 769             m_WIN0_SRC_GLOBAL_ALPHA;
 770         val = v_WIN0_SRC_ALPHA_EN(1) |
 771             v_WIN0_SRC_COLOR_M0(alpha_config.src_color_mode) |
 772             v_WIN0_SRC_ALPHA_M0(alpha_config.src_alpha_mode) |
 773             v_WIN0_SRC_BLEND_M0(alpha_config.src_global_alpha_mode) |
 774             v_WIN0_SRC_ALPHA_CAL_M0(alpha_config.src_alpha_cal_m0) |
 775             v_WIN0_SRC_FACTOR_M0(alpha_config.src_factor_mode) |
 776             v_WIN0_SRC_GLOBAL_ALPHA(alpha_config.src_global_alpha_val);
 777         lcdc_msk_reg(lcdc_dev, src_alpha_ctl, mask, val);
 778
 779         return 0;
 780 }
 781
 782 static int rk3368_lcdc_area_xst(struct rk_lcdc_win *win, int area_num)
 783 {
 784         struct rk_lcdc_win_area area_temp;
 785         int i, j;
 786
 787         for (i = 0; i < area_num; i++) {
 788                 for (j = i + 1; j < area_num; j++) {
 789                         if (win->area[i].dsp_stx >  win->area[j].dsp_stx) {
 790                                 memcpy(&area_temp, &win->area[i],
 791                                        sizeof(struct rk_lcdc_win_area));
 792                                 memcpy(&win->area[i], &win->area[j],
 793                                        sizeof(struct rk_lcdc_win_area));
 794                                 memcpy(&win->area[j], &area_temp,
 795                                        sizeof(struct rk_lcdc_win_area));
 796                         }
 797                 }
 798         }
 799
 800         return 0;
 801 }
 802
 803 static int __maybe_unused
 804         rk3368_lcdc_area_swap(struct rk_lcdc_win *win, int area_num)
 805 {
 806         struct rk_lcdc_win_area area_temp;
 807
 808         switch (area_num) {
 809         case 2:
 810                 area_temp = win->area[0];
 811                 win->area[0] = win->area[1];
 812                 win->area[1] = area_temp;
 813                 break;
 814         case 3:
 815                 area_temp = win->area[0];
 816                 win->area[0] = win->area[2];
 817                 win->area[2] = area_temp;
 818                 break;
 819         case 4:
 820                 area_temp = win->area[0];
 821                 win->area[0] = win->area[3];
 822                 win->area[3] = area_temp;
 823
 824                 area_temp = win->area[1];
 825                 win->area[1] = win->area[2];
 826                 win->area[2] = area_temp;
 827                 break;
 828         default:
 829                 pr_info("un supported area num!\n");
 830                 break;
 831         }
 832         return 0;
 833 }
 834
 835 static int __maybe_unused
 836 rk3368_win_area_check_var(int win_id, int area_num,
 837                           struct rk_lcdc_win_area *area_pre,
 838                           struct rk_lcdc_win_area *area_now)
 839 {
 840         if ((area_pre->xpos > area_now->xpos) ||
 841             ((area_pre->xpos + area_pre->xsize > area_now->xpos) &&
 842              (area_pre->ypos + area_pre->ysize > area_now->ypos))) {
 843                 area_now->state = 0;
 844                 pr_err("win[%d]:\n"
 845                        "area_pre[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n"
 846                        "area_now[%d]:xpos[%d],xsize[%d],ypos[%d],ysize[%d]\n",
 847                        win_id,
 848                        area_num - 1, area_pre->xpos, area_pre->xsize,
 849                        area_pre->ypos, area_pre->ysize,
 850                        area_num, area_now->xpos, area_now->xsize,
 851                        area_now->ypos, area_now->ysize);
 852                 return -EINVAL;
 853         }
 854         return 0;
 855 }
 856
 857 static int __maybe_unused rk3368_get_fbdc_idle(struct rk_lcdc_driver *dev_drv)
 858 {
 859         struct lcdc_device *lcdc_dev =
 860             container_of(dev_drv, struct lcdc_device, driver);
 861         u32 val, i;
 862
 863         for (i = 0; i < 100; i++) {
 864                 val = lcdc_readl(lcdc_dev, IFBDC_DEBUG0);
 865                 val &= m_DBG_IFBDC_IDLE;
 866                 if (val)
 867                         continue;
 868                 else
 869                         mdelay(10);
 870         };
 871         return val;
 872 }
 873
 874 static int rk3368_fbdc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
 875 {
 876         struct lcdc_device *lcdc_dev =
 877             container_of(dev_drv, struct lcdc_device, driver);
 878         struct rk_lcdc_win *win = dev_drv->win[win_id];
 879         u32 mask, val;
 880
 881         mask = m_IFBDC_CTRL_FBDC_EN | m_IFBDC_CTRL_FBDC_COR_EN |
 882             m_IFBDC_CTRL_FBDC_WIN_SEL | m_IFBDC_CTRL_FBDC_ROTATION_MODE |
 883             m_IFBDC_CTRL_FBDC_FMT | m_IFBDC_CTRL_WIDTH_RATIO;
 884         val = v_IFBDC_CTRL_FBDC_EN(win->area[0].fbdc_en) |
 885             v_IFBDC_CTRL_FBDC_COR_EN(win->area[0].fbdc_cor_en) |
 886             v_IFBDC_CTRL_FBDC_WIN_SEL(win->id) |
 887             v_IFBDC_CTRL_FBDC_ROTATION_MODE(win->mirror_en << 1) |
 888             v_IFBDC_CTRL_FBDC_FMT(win->area[0].fbdc_fmt_cfg) |
 889             v_IFBDC_CTRL_WIDTH_RATIO(win->area[0].fbdc_dsp_width_ratio);
 890         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
 891
 892         mask = m_IFBDC_TILES_NUM;
 893         val = v_IFBDC_TILES_NUM(win->area[0].fbdc_num_tiles);
 894         lcdc_msk_reg(lcdc_dev, IFBDC_TILES_NUM, mask, val);
 895
 896         mask = m_IFBDC_MB_SIZE_WIDTH | m_IFBDC_MB_SIZE_HEIGHT;
 897         val = v_IFBDC_MB_SIZE_WIDTH(win->area[0].fbdc_mb_width) |
 898             v_IFBDC_MB_SIZE_HEIGHT(win->area[0].fbdc_mb_height);
 899         lcdc_msk_reg(lcdc_dev, IFBDC_MB_SIZE, mask, val);
 900
 901         mask = m_IFBDC_CMP_INDEX_INIT;
 902         val = v_IFBDC_CMP_INDEX_INIT(win->area[0].fbdc_cmp_index_init);
 903         lcdc_msk_reg(lcdc_dev, IFBDC_CMP_INDEX_INIT, mask, val);
 904
 905         mask = m_IFBDC_MB_VIR_WIDTH;
 906         val = v_IFBDC_MB_VIR_WIDTH(win->area[0].fbdc_mb_vir_width);
 907         lcdc_msk_reg(lcdc_dev, IFBDC_MB_VIR_WIDTH, mask, val);
 908
 909         return 0;
 910 }
 911
 912 static int rk3368_init_fbdc_config(struct rk_lcdc_driver *dev_drv, int win_id)
 913 {
 914         struct lcdc_device *lcdc_dev =
 915             container_of(dev_drv, struct lcdc_device, driver);
 916         struct rk_lcdc_win *win = dev_drv->win[win_id];
 917         u8 fbdc_dsp_width_ratio;
 918         u16 fbdc_mb_vir_width, fbdc_mb_vir_height;
 919         u16 fbdc_mb_width, fbdc_mb_height;
 920         u16 fbdc_mb_xst, fbdc_mb_yst, fbdc_num_tiles;
 921         u16 fbdc_cmp_index_init;
 922         u8 mb_w_size, mb_h_size;
 923         struct rk_screen *screen = dev_drv->cur_screen;
 924
 925         if (screen->mode.flag == FB_VMODE_INTERLACED) {
 926                 dev_err(lcdc_dev->dev, "unsupport fbdc+interlace!\n");
 927                 return 0;
 928         }
 929
 930         switch (win->area[0].fmt_cfg) {
 931         case VOP_FORMAT_ARGB888:
 932                 fbdc_dsp_width_ratio = 0;
 933                 mb_w_size = 16;
 934                 break;
 935         case VOP_FORMAT_RGB888:
 936                 fbdc_dsp_width_ratio = 0;
 937                 mb_w_size = 16;
 938                 break;
 939         case VOP_FORMAT_RGB565:
 940                 fbdc_dsp_width_ratio = 1;
 941                 mb_w_size = 32;
 942                 break;
 943         default:
 944                 dev_err(lcdc_dev->dev,
 945                         "in fbdc mode,unsupport fmt:%d!\n",
 946                         win->area[0].fmt_cfg);
 947                 break;
 948         }
 949         mb_h_size = 4;
 950
 951         /*macro block xvir and yvir */
 952         if ((win->area[0].xvir % mb_w_size == 0) &&
 953             (win->area[0].yvir % mb_h_size == 0)) {
 954                 fbdc_mb_vir_width = win->area[0].xvir / mb_w_size;
 955                 fbdc_mb_vir_height = win->area[0].yvir / mb_h_size;
 956         } else {
 957                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 958                 pr_err("xvir[%d]/yvir[%d] should %d/%d pix align!\n",
 959                        win->area[0].xvir, win->area[0].yvir,
 960                        mb_w_size, mb_h_size);
 961         }
 962         /*macro block xact and yact */
 963         if ((win->area[0].xact % mb_w_size == 0) &&
 964             (win->area[0].yact % mb_h_size == 0)) {
 965                 fbdc_mb_width = win->area[0].xact / mb_w_size;
 966                 fbdc_mb_height = win->area[0].yact / mb_h_size;
 967         } else {
 968                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 969                 pr_err("xact[%d]/yact[%d] should %d/%d pix align!\n",
 970                        win->area[0].xact, win->area[0].yact,
 971                        mb_w_size, mb_h_size);
 972         }
 973         /*macro block xoff and yoff */
 974         if ((win->area[0].xoff % mb_w_size == 0) &&
 975             (win->area[0].yoff % mb_h_size == 0)) {
 976                 fbdc_mb_xst = win->area[0].xoff / mb_w_size;
 977                 fbdc_mb_yst = win->area[0].yoff / mb_h_size;
 978         } else {
 979                 pr_err("fbdc fmt[%d]:", win->area[0].fmt_cfg);
 980                 pr_err("xoff[%d]/yoff[%d] should %d/%d pix align!\n",
 981                        win->area[0].xoff, win->area[0].yoff,
 982                        mb_w_size, mb_h_size);
 983         }
 984
 985         /*FBDC tiles */
 986         fbdc_num_tiles = fbdc_mb_vir_width * fbdc_mb_vir_height;
 987
 988         /*
 989            switch (fbdc_rotation_mode)  {
 990            case FBDC_ROT_NONE:
 991            fbdc_cmp_index_init =
 992            (fbdc_mb_yst*fbdc_mb_vir_width) +  fbdc_mb_xst;
 993            break;
 994            case FBDC_X_MIRROR:
 995            fbdc_cmp_index_init =
 996            (fbdc_mb_yst*fbdc_mb_vir_width) + (fbdc_mb_xst+
 997            (fbdc_mb_width-1));
 998            break;
 999            case FBDC_Y_MIRROR:
1000            fbdc_cmp_index_init =
1001            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width)  +
1002            fbdc_mb_xst;
1003            break;
1004            case FBDC_ROT_180:
1005            fbdc_cmp_index_init =
1006            ((fbdc_mb_yst+(fbdc_mb_height-1))*fbdc_mb_vir_width) +
1007            (fbdc_mb_xst+(fbdc_mb_width-1));
1008            break;
1009            }
1010          */
1011         if ((win->mirror_en) && ((win_id == 2) || (win_id == 3))) {
1012                 fbdc_cmp_index_init =
1013                     ((fbdc_mb_yst + (fbdc_mb_height - 1)) * fbdc_mb_vir_width) +
1014                     (fbdc_mb_xst + (fbdc_mb_width - 1));
1015         } else {
1016                 fbdc_cmp_index_init =
1017                     (fbdc_mb_yst * fbdc_mb_vir_width) + fbdc_mb_xst;
1018         }
1019         /*fbdc fmt maybe need to change*/
1020         win->area[0].fbdc_dsp_width_ratio = fbdc_dsp_width_ratio;
1021         win->area[0].fbdc_mb_vir_width = fbdc_mb_vir_width;
1022         win->area[0].fbdc_mb_vir_height = fbdc_mb_vir_height;
1023         win->area[0].fbdc_mb_width = fbdc_mb_width;
1024         win->area[0].fbdc_mb_height = fbdc_mb_height;
1025         win->area[0].fbdc_mb_xst = fbdc_mb_xst;
1026         win->area[0].fbdc_mb_yst = fbdc_mb_yst;
1027         win->area[0].fbdc_num_tiles = fbdc_num_tiles;
1028         win->area[0].fbdc_cmp_index_init = fbdc_cmp_index_init;
1029
1030         return 0;
1031 }
1032
1033 static void rk3368_lcdc_csc_mode(struct lcdc_device *lcdc_dev,
1034                                  struct rk_lcdc_win *win)
1035 {
1036         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1037         struct rk_screen *screen = dev_drv->cur_screen;
1038
1039         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1040                 switch (win->area[0].fmt_cfg) {
1041                 case VOP_FORMAT_ARGB888:
1042                 case VOP_FORMAT_RGB888:
1043                 case VOP_FORMAT_RGB565:
1044                         if ((screen->mode.xres < 1280) &&
1045                             (screen->mode.yres < 720)) {
1046                                 win->csc_mode = VOP_R2Y_CSC_BT601;
1047                         } else {
1048                                 win->csc_mode = VOP_R2Y_CSC_BT709;
1049                         }
1050                         break;
1051                 default:
1052                         break;
1053                 }
1054         } else if (dev_drv->overlay_mode == VOP_RGB_DOMAIN) {
1055                 switch (win->area[0].fmt_cfg) {
1056                 case VOP_FORMAT_YCBCR420:
1057                         if ((win->id == 0) || (win->id == 1))
1058                                 win->csc_mode = VOP_Y2R_CSC_MPEG;
1059                         break;
1060                 default:
1061                         break;
1062                 }
1063         }
1064 }
1065
1066 static int rk3368_win_0_1_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1067 {
1068         struct lcdc_device *lcdc_dev =
1069             container_of(dev_drv, struct lcdc_device, driver);
1070         struct rk_lcdc_win *win = dev_drv->win[win_id];
1071         unsigned int mask, val, off;
1072
1073         off = win_id * 0x40;
1074         /*if(win->win_lb_mode == 5)
1075            win->win_lb_mode = 4;
1076            for rk3288 to fix hw bug? */
1077
1078         if (win->state == 1) {
1079                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1080                 if (win->area[0].fbdc_en) {
1081                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1082                 } else {
1083                         mask = m_IFBDC_CTRL_FBDC_EN;
1084                         val = v_IFBDC_CTRL_FBDC_EN(0);
1085                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1086                 }
1087                 mask = m_WIN0_EN | m_WIN0_DATA_FMT | m_WIN0_FMT_10 |
1088                     m_WIN0_LB_MODE | m_WIN0_RB_SWAP | m_WIN0_X_MIRROR |
1089                     m_WIN0_Y_MIRROR | m_WIN0_CSC_MODE;
1090                 val = v_WIN0_EN(win->state) |
1091                     v_WIN0_DATA_FMT(win->area[0].fmt_cfg) |
1092                     v_WIN0_FMT_10(win->fmt_10) |
1093                     v_WIN0_LB_MODE(win->win_lb_mode) |
1094                     v_WIN0_RB_SWAP(win->area[0].swap_rb) |
1095                     v_WIN0_X_MIRROR(win->mirror_en) |
1096                     v_WIN0_Y_MIRROR(win->mirror_en) |
1097                     v_WIN0_CSC_MODE(win->csc_mode);
1098                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1099
1100                 mask = m_WIN0_BIC_COE_SEL |
1101                     m_WIN0_VSD_YRGB_GT4 | m_WIN0_VSD_YRGB_GT2 |
1102                     m_WIN0_VSD_CBR_GT4 | m_WIN0_VSD_CBR_GT2 |
1103                     m_WIN0_YRGB_HOR_SCL_MODE | m_WIN0_YRGB_VER_SCL_MODE |
1104                     m_WIN0_YRGB_HSD_MODE | m_WIN0_YRGB_VSU_MODE |
1105                     m_WIN0_YRGB_VSD_MODE | m_WIN0_CBR_HOR_SCL_MODE |
1106                     m_WIN0_CBR_VER_SCL_MODE | m_WIN0_CBR_HSD_MODE |
1107                     m_WIN0_CBR_VSU_MODE | m_WIN0_CBR_VSD_MODE;
1108                 val = v_WIN0_BIC_COE_SEL(win->bic_coe_el) |
1109                     v_WIN0_VSD_YRGB_GT4(win->vsd_yrgb_gt4) |
1110                     v_WIN0_VSD_YRGB_GT2(win->vsd_yrgb_gt2) |
1111                     v_WIN0_VSD_CBR_GT4(win->vsd_cbr_gt4) |
1112                     v_WIN0_VSD_CBR_GT2(win->vsd_cbr_gt2) |
1113                     v_WIN0_YRGB_HOR_SCL_MODE(win->yrgb_hor_scl_mode) |
1114                     v_WIN0_YRGB_VER_SCL_MODE(win->yrgb_ver_scl_mode) |
1115                     v_WIN0_YRGB_HSD_MODE(win->yrgb_hsd_mode) |
1116                     v_WIN0_YRGB_VSU_MODE(win->yrgb_vsu_mode) |
1117                     v_WIN0_YRGB_VSD_MODE(win->yrgb_vsd_mode) |
1118                     v_WIN0_CBR_HOR_SCL_MODE(win->cbr_hor_scl_mode) |
1119                     v_WIN0_CBR_VER_SCL_MODE(win->cbr_ver_scl_mode) |
1120                     v_WIN0_CBR_HSD_MODE(win->cbr_hsd_mode) |
1121                     v_WIN0_CBR_VSU_MODE(win->cbr_vsu_mode) |
1122                     v_WIN0_CBR_VSD_MODE(win->cbr_vsd_mode);
1123                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL1 + off, mask, val);
1124                 val = v_WIN0_VIR_STRIDE(win->area[0].y_vir_stride) |
1125                     v_WIN0_VIR_STRIDE_UV(win->area[0].uv_vir_stride);
1126                 lcdc_writel(lcdc_dev, WIN0_VIR + off, val);
1127                 /*lcdc_writel(lcdc_dev, WIN0_YRGB_MST+off,
1128                                 win->area[0].y_addr);
1129                    lcdc_writel(lcdc_dev, WIN0_CBR_MST+off,
1130                                 win->area[0].uv_addr); */
1131                 val = v_WIN0_ACT_WIDTH(win->area[0].xact) |
1132                     v_WIN0_ACT_HEIGHT(win->area[0].yact);
1133                 lcdc_writel(lcdc_dev, WIN0_ACT_INFO + off, val);
1134
1135                 val = v_WIN0_DSP_WIDTH(win->area[0].xsize) |
1136                     v_WIN0_DSP_HEIGHT(win->area[0].ysize);
1137                 lcdc_writel(lcdc_dev, WIN0_DSP_INFO + off, val);
1138
1139                 val = v_WIN0_DSP_XST(win->area[0].dsp_stx) |
1140                     v_WIN0_DSP_YST(win->area[0].dsp_sty);
1141                 lcdc_writel(lcdc_dev, WIN0_DSP_ST + off, val);
1142
1143                 val = v_WIN0_HS_FACTOR_YRGB(win->scale_yrgb_x) |
1144                     v_WIN0_VS_FACTOR_YRGB(win->scale_yrgb_y);
1145                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB + off, val);
1146
1147                 val = v_WIN0_HS_FACTOR_CBR(win->scale_cbcr_x) |
1148                     v_WIN0_VS_FACTOR_CBR(win->scale_cbcr_y);
1149                 lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR + off, val);
1150                 if (win->alpha_en == 1) {
1151                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1152                 } else {
1153                         mask = m_WIN0_SRC_ALPHA_EN;
1154                         val = v_WIN0_SRC_ALPHA_EN(0);
1155                         lcdc_msk_reg(lcdc_dev, WIN0_SRC_ALPHA_CTRL + off,
1156                                      mask, val);
1157                 }
1158         } else {
1159                 mask = m_WIN0_EN;
1160                 val = v_WIN0_EN(win->state);
1161                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0 + off, mask, val);
1162         }
1163         return 0;
1164 }
1165
1166 static int rk3368_win_2_3_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1167 {
1168         struct lcdc_device *lcdc_dev =
1169             container_of(dev_drv, struct lcdc_device, driver);
1170         struct rk_lcdc_win *win = dev_drv->win[win_id];
1171         unsigned int mask, val, off;
1172
1173         off = (win_id - 2) * 0x50;
1174         rk3368_lcdc_area_xst(win, win->area_num);
1175
1176         if (win->state == 1) {
1177                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1178                 if (win->area[0].fbdc_en) {
1179                         rk3368_fbdc_reg_update(&lcdc_dev->driver, win_id);
1180                 } else {
1181                         mask = m_IFBDC_CTRL_FBDC_EN;
1182                         val = v_IFBDC_CTRL_FBDC_EN(0);
1183                         lcdc_msk_reg(lcdc_dev, IFBDC_CTRL, mask, val);
1184                 }
1185
1186                 mask = m_WIN2_EN | m_WIN2_CSC_MODE;
1187                 val = v_WIN2_EN(1) | v_WIN1_CSC_MODE(win->csc_mode);
1188                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1189                 /*area 0 */
1190                 if (win->area[0].state == 1) {
1191                         mask = m_WIN2_MST0_EN | m_WIN2_DATA_FMT0 |
1192                             m_WIN2_RB_SWAP0;
1193                         val = v_WIN2_MST0_EN(win->area[0].state) |
1194                             v_WIN2_DATA_FMT0(win->area[0].fmt_cfg) |
1195                             v_WIN2_RB_SWAP0(win->area[0].swap_rb);
1196                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1197
1198                         mask = m_WIN2_VIR_STRIDE0;
1199                         val = v_WIN2_VIR_STRIDE0(win->area[0].y_vir_stride);
1200                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1201
1202                         /*lcdc_writel(lcdc_dev,WIN2_MST0+off,
1203                            win->area[0].y_addr); */
1204                         val = v_WIN2_DSP_WIDTH0(win->area[0].xsize) |
1205                             v_WIN2_DSP_HEIGHT0(win->area[0].ysize);
1206                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO0 + off, val);
1207                         val = v_WIN2_DSP_XST0(win->area[0].dsp_stx) |
1208                             v_WIN2_DSP_YST0(win->area[0].dsp_sty);
1209                         lcdc_writel(lcdc_dev, WIN2_DSP_ST0 + off, val);
1210                 } else {
1211                         mask = m_WIN2_MST0_EN;
1212                         val = v_WIN2_MST0_EN(0);
1213                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1214                 }
1215                 /*area 1 */
1216                 if (win->area[1].state == 1) {
1217                         /*rk3368_win_area_check_var(win_id, 1,
1218                                                   &win->area[0], &win->area[1]);
1219                         */
1220
1221                         mask = m_WIN2_MST1_EN | m_WIN2_DATA_FMT1 |
1222                             m_WIN2_RB_SWAP1;
1223                         val = v_WIN2_MST1_EN(win->area[1].state) |
1224                             v_WIN2_DATA_FMT1(win->area[1].fmt_cfg) |
1225                             v_WIN2_RB_SWAP1(win->area[1].swap_rb);
1226                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1227
1228                         mask = m_WIN2_VIR_STRIDE1;
1229                         val = v_WIN2_VIR_STRIDE1(win->area[1].y_vir_stride);
1230                         lcdc_msk_reg(lcdc_dev, WIN2_VIR0_1 + off, mask, val);
1231
1232                         /*lcdc_writel(lcdc_dev,WIN2_MST1+off,
1233                            win->area[1].y_addr); */
1234                         val = v_WIN2_DSP_WIDTH1(win->area[1].xsize) |
1235                             v_WIN2_DSP_HEIGHT1(win->area[1].ysize);
1236                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO1 + off, val);
1237                         val = v_WIN2_DSP_XST1(win->area[1].dsp_stx) |
1238                             v_WIN2_DSP_YST1(win->area[1].dsp_sty);
1239                         lcdc_writel(lcdc_dev, WIN2_DSP_ST1 + off, val);
1240                 } else {
1241                         mask = m_WIN2_MST1_EN;
1242                         val = v_WIN2_MST1_EN(0);
1243                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1244                 }
1245                 /*area 2 */
1246                 if (win->area[2].state == 1) {
1247                         /*rk3368_win_area_check_var(win_id, 2,
1248                                                   &win->area[1], &win->area[2]);
1249                         */
1250
1251                         mask = m_WIN2_MST2_EN | m_WIN2_DATA_FMT2 |
1252                             m_WIN2_RB_SWAP2;
1253                         val = v_WIN2_MST2_EN(win->area[2].state) |
1254                             v_WIN2_DATA_FMT2(win->area[2].fmt_cfg) |
1255                             v_WIN2_RB_SWAP2(win->area[2].swap_rb);
1256                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1257
1258                         mask = m_WIN2_VIR_STRIDE2;
1259                         val = v_WIN2_VIR_STRIDE2(win->area[2].y_vir_stride);
1260                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1261
1262                         /*lcdc_writel(lcdc_dev,WIN2_MST2+off,
1263                            win->area[2].y_addr); */
1264                         val = v_WIN2_DSP_WIDTH2(win->area[2].xsize) |
1265                             v_WIN2_DSP_HEIGHT2(win->area[2].ysize);
1266                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO2 + off, val);
1267                         val = v_WIN2_DSP_XST2(win->area[2].dsp_stx) |
1268                             v_WIN2_DSP_YST2(win->area[2].dsp_sty);
1269                         lcdc_writel(lcdc_dev, WIN2_DSP_ST2 + off, val);
1270                 } else {
1271                         mask = m_WIN2_MST2_EN;
1272                         val = v_WIN2_MST2_EN(0);
1273                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1274                 }
1275                 /*area 3 */
1276                 if (win->area[3].state == 1) {
1277                         /*rk3368_win_area_check_var(win_id, 3,
1278                                                   &win->area[2], &win->area[3]);
1279                         */
1280
1281                         mask = m_WIN2_MST3_EN | m_WIN2_DATA_FMT3 |
1282                             m_WIN2_RB_SWAP3;
1283                         val = v_WIN2_MST3_EN(win->area[3].state) |
1284                             v_WIN2_DATA_FMT3(win->area[3].fmt_cfg) |
1285                             v_WIN2_RB_SWAP3(win->area[3].swap_rb);
1286                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1287
1288                         mask = m_WIN2_VIR_STRIDE3;
1289                         val = v_WIN2_VIR_STRIDE3(win->area[3].y_vir_stride);
1290                         lcdc_msk_reg(lcdc_dev, WIN2_VIR2_3 + off, mask, val);
1291
1292                         /*lcdc_writel(lcdc_dev,WIN2_MST3+off,
1293                            win->area[3].y_addr); */
1294                         val = v_WIN2_DSP_WIDTH3(win->area[3].xsize) |
1295                             v_WIN2_DSP_HEIGHT3(win->area[3].ysize);
1296                         lcdc_writel(lcdc_dev, WIN2_DSP_INFO3 + off, val);
1297                         val = v_WIN2_DSP_XST3(win->area[3].dsp_stx) |
1298                             v_WIN2_DSP_YST3(win->area[3].dsp_sty);
1299                         lcdc_writel(lcdc_dev, WIN2_DSP_ST3 + off, val);
1300                 } else {
1301                         mask = m_WIN2_MST3_EN;
1302                         val = v_WIN2_MST3_EN(0);
1303                         lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1304                 }
1305
1306                 if (win->alpha_en == 1) {
1307                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1308                 } else {
1309                         mask = m_WIN2_SRC_ALPHA_EN;
1310                         val = v_WIN2_SRC_ALPHA_EN(0);
1311                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL + off,
1312                                      mask, val);
1313                 }
1314         } else {
1315                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
1316                     m_WIN2_MST0_EN | m_WIN2_MST2_EN | m_WIN2_MST3_EN;
1317                 val = v_WIN2_EN(win->state) | v_WIN2_MST0_EN(0) |
1318                     v_WIN2_MST1_EN(0) | v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
1319                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0 + off, mask, val);
1320         }
1321         return 0;
1322 }
1323
1324 static int rk3368_hwc_reg_update(struct rk_lcdc_driver *dev_drv, int win_id)
1325 {
1326         struct lcdc_device *lcdc_dev =
1327             container_of(dev_drv, struct lcdc_device, driver);
1328         struct rk_lcdc_win *win = dev_drv->win[win_id];
1329         unsigned int mask, val, hwc_size = 0;
1330
1331         if (win->state == 1) {
1332                 rk3368_lcdc_csc_mode(lcdc_dev, win);
1333                 mask = m_HWC_EN | m_HWC_DATA_FMT |
1334                     m_HWC_RB_SWAP | m_WIN0_CSC_MODE;
1335                 val = v_HWC_EN(1) | v_HWC_DATA_FMT(win->area[0].fmt_cfg) |
1336                     v_HWC_RB_SWAP(win->area[0].swap_rb) |
1337                     v_WIN0_CSC_MODE(win->csc_mode);
1338                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1339
1340                 if ((win->area[0].xsize == 32) && (win->area[0].ysize == 32))
1341                         hwc_size = 0;
1342                 else if ((win->area[0].xsize == 64) &&
1343                          (win->area[0].ysize == 64))
1344                         hwc_size = 1;
1345                 else if ((win->area[0].xsize == 96) &&
1346                          (win->area[0].ysize == 96))
1347                         hwc_size = 2;
1348                 else if ((win->area[0].xsize == 128) &&
1349                          (win->area[0].ysize == 128))
1350                         hwc_size = 3;
1351                 else
1352                         dev_err(lcdc_dev->dev, "un supported hwc size!\n");
1353
1354                 mask = m_HWC_SIZE;
1355                 val = v_HWC_SIZE(hwc_size);
1356                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1357
1358                 mask = m_HWC_DSP_XST | m_HWC_DSP_YST;
1359                 val = v_HWC_DSP_XST(win->area[0].dsp_stx) |
1360                     v_HWC_DSP_YST(win->area[0].dsp_sty);
1361                 lcdc_msk_reg(lcdc_dev, HWC_DSP_ST, mask, val);
1362
1363                 if (win->alpha_en == 1) {
1364                         rk3368_lcdc_alpha_cfg(dev_drv, win_id);
1365                 } else {
1366                         mask = m_WIN2_SRC_ALPHA_EN;
1367                         val = v_WIN2_SRC_ALPHA_EN(0);
1368                         lcdc_msk_reg(lcdc_dev, WIN2_SRC_ALPHA_CTRL, mask, val);
1369                 }
1370         } else {
1371                 mask = m_HWC_EN;
1372                 val = v_HWC_EN(win->state);
1373                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1374         }
1375         return 0;
1376 }
1377
1378 static int rk3368_lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
1379                                          struct rk_lcdc_win *win)
1380 {
1381         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
1382         int timeout;
1383         unsigned long flags;
1384
1385         spin_lock(&lcdc_dev->reg_lock);
1386         if (likely(lcdc_dev->clk_on)) {
1387                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1388                              v_STANDBY_EN(lcdc_dev->standby));
1389                 if ((win->id == 0) || (win->id == 1))
1390                         rk3368_win_0_1_reg_update(dev_drv, win->id);
1391                 else if ((win->id == 2) || (win->id == 3))
1392                         rk3368_win_2_3_reg_update(dev_drv, win->id);
1393                 else if (win->id == 4)
1394                         rk3368_hwc_reg_update(dev_drv, win->id);
1395                 /*rk3368_lcdc_post_cfg(dev_drv); */
1396                 lcdc_cfg_done(lcdc_dev);
1397         }
1398         spin_unlock(&lcdc_dev->reg_lock);
1399
1400         /*if (dev_drv->wait_fs) { */
1401         if (0) {
1402                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
1403                 init_completion(&dev_drv->frame_done);
1404                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
1405                 timeout =
1406                     wait_for_completion_timeout(&dev_drv->frame_done,
1407                                                 msecs_to_jiffies
1408                                                 (dev_drv->cur_screen->ft + 5));
1409                 if (!timeout && (!dev_drv->frame_done.done)) {
1410                         dev_warn(lcdc_dev->dev,
1411                                  "wait for new frame start time out!\n");
1412                         return -ETIMEDOUT;
1413                 }
1414         }
1415         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
1416         return 0;
1417 }
1418
1419 static int rk3368_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
1420 {
1421         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0x270);
1422         return 0;
1423 }
1424
1425 static int __maybe_unused rk3368_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
1426 {
1427         u32 mask, val;
1428         struct lcdc_device *lcdc_dev =
1429             container_of(dev_drv, struct lcdc_device, driver);
1430
1431 #if defined(CONFIG_ROCKCHIP_IOMMU)
1432         if (dev_drv->iommu_enabled) {
1433                 if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1434                         if (likely(lcdc_dev->clk_on)) {
1435                                 mask = m_MMU_EN;
1436                                 val = v_MMU_EN(1);
1437                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1438                                 mask = m_AXI_MAX_OUTSTANDING_EN |
1439                                         m_AXI_OUTSTANDING_MAX_NUM;
1440                                 val = v_AXI_OUTSTANDING_MAX_NUM(31) |
1441                                         v_AXI_MAX_OUTSTANDING_EN(1);
1442                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL1, mask, val);
1443                         }
1444                         lcdc_dev->iommu_status = 1;
1445                         rockchip_iovmm_activate(dev_drv->dev);
1446                 }
1447         }
1448 #endif
1449         return 0;
1450 }
1451
1452 static int rk3368_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv, int reset_rate)
1453 {
1454         int ret = 0, fps = 0;
1455         struct lcdc_device *lcdc_dev =
1456             container_of(dev_drv, struct lcdc_device, driver);
1457         struct rk_screen *screen = dev_drv->cur_screen;
1458 #ifdef CONFIG_RK_FPGA
1459         return 0;
1460 #endif
1461         if (reset_rate)
1462                 ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);/*set pll */
1463         if (ret)
1464                 dev_err(dev_drv->dev, "set lcdc%d dclk failed\n", lcdc_dev->id);
1465         lcdc_dev->pixclock =
1466             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1467         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
1468
1469         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
1470         screen->ft = 1000 / fps;
1471         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
1472                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
1473         return 0;
1474 }
1475
1476 static int rk3368_config_timing(struct rk_lcdc_driver *dev_drv)
1477 {
1478         struct lcdc_device *lcdc_dev =
1479             container_of(dev_drv, struct lcdc_device, driver);
1480         struct rk_screen *screen = dev_drv->cur_screen;
1481         u16 hsync_len = screen->mode.hsync_len;
1482         u16 left_margin = screen->mode.left_margin;
1483         u16 right_margin = screen->mode.right_margin;
1484         u16 vsync_len = screen->mode.vsync_len;
1485         u16 upper_margin = screen->mode.upper_margin;
1486         u16 lower_margin = screen->mode.lower_margin;
1487         u16 x_res = screen->mode.xres;
1488         u16 y_res = screen->mode.yres;
1489         u32 mask, val;
1490         u16 h_total, v_total;
1491         u16 vact_end_f1, vact_st_f1, vs_end_f1, vs_st_f1;
1492
1493         h_total = hsync_len + left_margin + x_res + right_margin;
1494         v_total = vsync_len + upper_margin + y_res + lower_margin;
1495
1496         mask = m_DSP_HS_PW | m_DSP_HTOTAL;
1497         val = v_DSP_HS_PW(hsync_len) | v_DSP_HTOTAL(h_total);
1498         lcdc_msk_reg(lcdc_dev, DSP_HTOTAL_HS_END, mask, val);
1499
1500         mask = m_DSP_HACT_END | m_DSP_HACT_ST;
1501         val = v_DSP_HACT_END(hsync_len + left_margin + x_res) |
1502             v_DSP_HACT_ST(hsync_len + left_margin);
1503         lcdc_msk_reg(lcdc_dev, DSP_HACT_ST_END, mask, val);
1504
1505         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
1506                 /* First Field Timing */
1507                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1508                 val = v_DSP_VS_PW(vsync_len) |
1509                     v_DSP_VTOTAL(2 * (vsync_len + upper_margin +
1510                                       lower_margin) + y_res + 1);
1511                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1512
1513                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1514                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res / 2) |
1515                     v_DSP_VACT_ST(vsync_len + upper_margin);
1516                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1517
1518                 /* Second Field Timing */
1519                 mask = m_DSP_VS_ST_F1 | m_DSP_VS_END_F1;
1520                 vs_st_f1 = vsync_len + upper_margin + y_res / 2 + lower_margin;
1521                 vs_end_f1 = 2 * vsync_len + upper_margin + y_res / 2 +
1522                     lower_margin;
1523                 val = v_DSP_VS_ST_F1(vs_st_f1) | v_DSP_VS_END_F1(vs_end_f1);
1524                 lcdc_msk_reg(lcdc_dev, DSP_VS_ST_END_F1, mask, val);
1525
1526                 mask = m_DSP_VACT_END_F1 | m_DSP_VAC_ST_F1;
1527                 vact_end_f1 = 2 * (vsync_len + upper_margin) + y_res +
1528                     lower_margin + 1;
1529                 vact_st_f1 = 2 * (vsync_len + upper_margin) + y_res / 2 +
1530                     lower_margin + 1;
1531                 val =
1532                     v_DSP_VACT_END_F1(vact_end_f1) |
1533                     v_DSP_VAC_ST_F1(vact_st_f1);
1534                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END_F1, mask, val);
1535
1536                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1537                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1538                              v_DSP_INTERLACE(1) | v_DSP_FIELD_POL(0));
1539                 mask =
1540                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1541                     m_WIN0_CBR_DEFLICK;
1542                 val =
1543                     v_WIN0_INTERLACE_READ(1) | v_WIN0_YRGB_DEFLICK(1) |
1544                     v_WIN0_CBR_DEFLICK(1);
1545                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1546
1547                 mask =
1548                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1549                     m_WIN1_CBR_DEFLICK;
1550                 val =
1551                     v_WIN1_INTERLACE_READ(1) | v_WIN1_YRGB_DEFLICK(1) |
1552                     v_WIN1_CBR_DEFLICK(1);
1553                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1554
1555                 mask = m_WIN2_INTERLACE_READ;
1556                 val = v_WIN2_INTERLACE_READ(1);
1557                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1558
1559                 mask = m_WIN3_INTERLACE_READ;
1560                 val = v_WIN3_INTERLACE_READ(1);
1561                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1562
1563                 mask = m_HWC_INTERLACE_READ;
1564                 val = v_HWC_INTERLACE_READ(1);
1565                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1566
1567                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1568                 val =
1569                     v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res / 2) |
1570                     v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res / 2);
1571                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1572         } else {
1573                 mask = m_DSP_VS_PW | m_DSP_VTOTAL;
1574                 val = v_DSP_VS_PW(vsync_len) | v_DSP_VTOTAL(v_total);
1575                 lcdc_msk_reg(lcdc_dev, DSP_VTOTAL_VS_END, mask, val);
1576
1577                 mask = m_DSP_VACT_END | m_DSP_VACT_ST;
1578                 val = v_DSP_VACT_END(vsync_len + upper_margin + y_res) |
1579                     v_DSP_VACT_ST(vsync_len + upper_margin);
1580                 lcdc_msk_reg(lcdc_dev, DSP_VACT_ST_END, mask, val);
1581
1582                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
1583                              m_DSP_INTERLACE | m_DSP_FIELD_POL,
1584                              v_DSP_INTERLACE(0) | v_DSP_FIELD_POL(0));
1585
1586                 mask =
1587                     m_WIN0_INTERLACE_READ | m_WIN0_YRGB_DEFLICK |
1588                     m_WIN0_CBR_DEFLICK;
1589                 val =
1590                     v_WIN0_INTERLACE_READ(0) | v_WIN0_YRGB_DEFLICK(0) |
1591                     v_WIN0_CBR_DEFLICK(0);
1592                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1593
1594                 mask =
1595                     m_WIN1_INTERLACE_READ | m_WIN1_YRGB_DEFLICK |
1596                     m_WIN1_CBR_DEFLICK;
1597                 val =
1598                     v_WIN1_INTERLACE_READ(0) | v_WIN1_YRGB_DEFLICK(0) |
1599                     v_WIN1_CBR_DEFLICK(0);
1600                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
1601
1602                 mask = m_WIN2_INTERLACE_READ;
1603                 val = v_WIN2_INTERLACE_READ(0);
1604                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
1605
1606                 mask = m_WIN3_INTERLACE_READ;
1607                 val = v_WIN3_INTERLACE_READ(0);
1608                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
1609
1610                 mask = m_HWC_INTERLACE_READ;
1611                 val = v_HWC_INTERLACE_READ(0);
1612                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
1613
1614                 mask = m_DSP_LINE_FLAG0_NUM | m_DSP_LINE_FLAG1_NUM;
1615                 val = v_DSP_LINE_FLAG0_NUM(vsync_len + upper_margin + y_res) |
1616                         v_DSP_LINE_FLAG1_NUM(vsync_len + upper_margin + y_res);
1617                 lcdc_msk_reg(lcdc_dev, LINE_FLAG, mask, val);
1618         }
1619         rk3368_lcdc_post_cfg(dev_drv);
1620         return 0;
1621 }
1622
1623 static void rk3368_lcdc_bcsh_path_sel(struct rk_lcdc_driver *dev_drv)
1624 {
1625         struct lcdc_device *lcdc_dev =
1626             container_of(dev_drv, struct lcdc_device, driver);
1627         u32 bcsh_ctrl;
1628
1629         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_OVERLAY_MODE,
1630                      v_OVERLAY_MODE(dev_drv->overlay_mode));
1631         if (dev_drv->overlay_mode == VOP_YUV_DOMAIN) {
1632                 if (dev_drv->output_color == COLOR_YCBCR)       /* bypass */
1633                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1634                                      m_BCSH_Y2R_EN | m_BCSH_R2Y_EN,
1635                                      v_BCSH_Y2R_EN(0) | v_BCSH_R2Y_EN(0));
1636                 else            /* YUV2RGB */
1637                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1638                                      m_BCSH_Y2R_EN | m_BCSH_Y2R_CSC_MODE |
1639                                      m_BCSH_R2Y_EN,
1640                                      v_BCSH_Y2R_EN(1) |
1641                                      v_BCSH_Y2R_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1642                                      v_BCSH_R2Y_EN(0));
1643         } else {                /* overlay_mode=VOP_RGB_DOMAIN */
1644                 /* bypass  --need check,if bcsh close? */
1645                 if (dev_drv->output_color == COLOR_RGB) {
1646                         bcsh_ctrl = lcdc_readl(lcdc_dev, BCSH_CTRL);
1647                         if (((bcsh_ctrl & m_BCSH_EN) == 1) ||
1648                             (dev_drv->bcsh.enable == 1))/*bcsh enabled */
1649                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1650                                              m_BCSH_R2Y_EN |
1651                                              m_BCSH_Y2R_EN,
1652                                              v_BCSH_R2Y_EN(1) |
1653                                              v_BCSH_Y2R_EN(1));
1654                         else
1655                                 lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1656                                              m_BCSH_R2Y_EN | m_BCSH_Y2R_EN,
1657                                              v_BCSH_R2Y_EN(0) |
1658                                              v_BCSH_Y2R_EN(0));
1659                 } else          /* RGB2YUV */
1660                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL,
1661                                      m_BCSH_R2Y_EN |
1662                                      m_BCSH_R2Y_CSC_MODE | m_BCSH_Y2R_EN,
1663                                      v_BCSH_R2Y_EN(1) |
1664                                      v_BCSH_R2Y_CSC_MODE(VOP_Y2R_CSC_MPEG) |
1665                                      v_BCSH_Y2R_EN(0));
1666         }
1667 }
1668
1669 static int rk3368_get_dspbuf_info(struct rk_lcdc_driver *dev_drv, u16 *xact,
1670                                   u16 *yact, int *format, u32 *dsp_addr)
1671 {
1672         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1673                                                     struct lcdc_device, driver);
1674         u32 val;
1675
1676         spin_lock(&lcdc_dev->reg_lock);
1677
1678         val = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
1679         *xact = (val & m_WIN0_ACT_WIDTH) + 1;
1680         *yact = ((val & m_WIN0_ACT_HEIGHT)>>16) + 1;
1681
1682         val = lcdc_readl(lcdc_dev, WIN0_CTRL0);
1683         *format = (val & m_WIN0_DATA_FMT) >> 1;
1684         *dsp_addr = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1685
1686         spin_unlock(&lcdc_dev->reg_lock);
1687
1688         return 0;
1689 }
1690
1691 static int rk3368_post_dspbuf(struct rk_lcdc_driver *dev_drv, u32 rgb_mst,
1692                               int format, u16 xact, u16 yact, u16 xvir)
1693 {
1694         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1695                                                     struct lcdc_device, driver);
1696         u32 val, mask;
1697         int swap = (format == RGB888) ? 1 : 0;
1698
1699         mask = m_WIN0_DATA_FMT | m_WIN0_RB_SWAP;
1700         val = v_WIN0_DATA_FMT(format) | v_WIN0_RB_SWAP(swap);
1701         lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
1702
1703         lcdc_msk_reg(lcdc_dev, WIN0_VIR, m_WIN0_VIR_STRIDE,
1704                         v_WIN0_VIR_STRIDE(xvir));
1705         lcdc_writel(lcdc_dev, WIN0_ACT_INFO, v_WIN0_ACT_WIDTH(xact) |
1706                     v_WIN0_ACT_HEIGHT(yact));
1707
1708         lcdc_writel(lcdc_dev, WIN0_YRGB_MST, rgb_mst);
1709
1710         lcdc_cfg_done(lcdc_dev);
1711
1712         return 0;
1713 }
1714
1715
1716 static int rk3368_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
1717 {
1718         u16 face = 0;
1719         u16 dclk_ddr = 0;
1720         u32 v = 0;
1721         struct lcdc_device *lcdc_dev =
1722             container_of(dev_drv, struct lcdc_device, driver);
1723         struct rk_screen *screen = dev_drv->cur_screen;
1724         u32 mask, val;
1725
1726         spin_lock(&lcdc_dev->reg_lock);
1727         if (likely(lcdc_dev->clk_on)) {
1728                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1729                 if (!lcdc_dev->standby && !initscreen) {
1730                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
1731                                      v_STANDBY_EN(1));
1732                         lcdc_cfg_done(lcdc_dev);
1733                         mdelay(50);
1734                 }
1735                 switch (screen->face) {
1736                 case OUT_P565:
1737                         face = OUT_P565;
1738                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1739                             m_DITHER_DOWN_SEL;
1740                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1741                             v_DITHER_DOWN_SEL(1);
1742                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1743                         break;
1744                 case OUT_P666:
1745                         face = OUT_P666;
1746                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1747                             m_DITHER_DOWN_SEL;
1748                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1749                             v_DITHER_DOWN_SEL(1);
1750                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1751                         break;
1752                 case OUT_D888_P565:
1753                         face = OUT_P888;
1754                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1755                             m_DITHER_DOWN_SEL;
1756                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(0) |
1757                             v_DITHER_DOWN_SEL(1);
1758                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1759                         break;
1760                 case OUT_D888_P666:
1761                         face = OUT_P888;
1762                         mask = m_DITHER_DOWN_EN | m_DITHER_DOWN_MODE |
1763                             m_DITHER_DOWN_SEL;
1764                         val = v_DITHER_DOWN_EN(1) | v_DITHER_DOWN_MODE(1) |
1765                             v_DITHER_DOWN_SEL(1);
1766                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1767                         break;
1768                 case OUT_P888:
1769                         face = OUT_P888;
1770                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1771                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1772                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1773                         break;
1774                 case OUT_YUV_420:
1775                         /*yuv420 output prefer yuv domain overlay */
1776                         face = OUT_YUV_420;
1777                         dclk_ddr = 1;
1778                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1779                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1780                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1781                         break;
1782                 default:
1783                         dev_err(lcdc_dev->dev, "un supported interface!\n");
1784                         break;
1785                 }
1786                 switch (screen->type) {
1787                 case SCREEN_RGB:
1788                         mask = m_RGB_OUT_EN;
1789                         val = v_RGB_OUT_EN(1);
1790                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1791                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1792                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1793                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1794                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1795                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1796                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1797                         v = 1 << 15 | (1 << (15 + 16));
1798
1799                         break;
1800                 case SCREEN_LVDS:
1801                         mask = m_RGB_OUT_EN;
1802                         val = v_RGB_OUT_EN(1);
1803                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1804                         mask = m_RGB_LVDS_HSYNC_POL | m_RGB_LVDS_VSYNC_POL |
1805                             m_RGB_LVDS_DEN_POL | m_RGB_LVDS_DCLK_POL;
1806                         val = v_RGB_LVDS_HSYNC_POL(screen->pin_hsync) |
1807                             v_RGB_LVDS_VSYNC_POL(screen->pin_vsync) |
1808                             v_RGB_LVDS_DEN_POL(screen->pin_den) |
1809                             v_RGB_LVDS_DCLK_POL(screen->pin_dclk);
1810                         v = 0 << 15 | (1 << (15 + 16));
1811                         break;
1812                 case SCREEN_HDMI:
1813                         /*face = OUT_RGB_AAA;*/
1814                         if (screen->color_mode == COLOR_RGB)
1815                                 dev_drv->overlay_mode = VOP_RGB_DOMAIN;
1816                         else
1817                                 dev_drv->overlay_mode = VOP_YUV_DOMAIN;
1818                         mask = m_HDMI_OUT_EN  | m_RGB_OUT_EN;
1819                         val = v_HDMI_OUT_EN(1) | v_RGB_OUT_EN(0);
1820                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1821                         mask = m_HDMI_HSYNC_POL | m_HDMI_VSYNC_POL |
1822                             m_HDMI_DEN_POL | m_HDMI_DCLK_POL;
1823                         val = v_HDMI_HSYNC_POL(screen->pin_hsync) |
1824                             v_HDMI_VSYNC_POL(screen->pin_vsync) |
1825                             v_HDMI_DEN_POL(screen->pin_den) |
1826                             v_HDMI_DCLK_POL(screen->pin_dclk);
1827                         break;
1828                 case SCREEN_MIPI:
1829                         mask = m_MIPI_OUT_EN  | m_RGB_OUT_EN;
1830                         val = v_MIPI_OUT_EN(1) | v_RGB_OUT_EN(0);
1831                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1832                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1833                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1834                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1835                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1836                             v_MIPI_DEN_POL(screen->pin_den) |
1837                             v_MIPI_DCLK_POL(screen->pin_dclk);
1838                         break;
1839                 case SCREEN_DUAL_MIPI:
1840                         mask = m_MIPI_OUT_EN | m_DOUB_CHANNEL_EN  |
1841                                 m_RGB_OUT_EN;
1842                         val = v_MIPI_OUT_EN(1) | v_DOUB_CHANNEL_EN(1) |
1843                                 v_RGB_OUT_EN(0);
1844                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1845                         mask = m_MIPI_HSYNC_POL | m_MIPI_VSYNC_POL |
1846                             m_MIPI_DEN_POL | m_MIPI_DCLK_POL;
1847                         val = v_MIPI_HSYNC_POL(screen->pin_hsync) |
1848                             v_MIPI_VSYNC_POL(screen->pin_vsync) |
1849                             v_MIPI_DEN_POL(screen->pin_den) |
1850                             v_MIPI_DCLK_POL(screen->pin_dclk);
1851                         break;
1852                 case SCREEN_EDP:
1853                         face = OUT_P888;        /*RGB 888 output */
1854
1855                         mask = m_EDP_OUT_EN | m_RGB_OUT_EN;
1856                         val = v_EDP_OUT_EN(1) | v_RGB_OUT_EN(0);
1857                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
1858                         /*because edp have to sent aaa fmt */
1859                         mask = m_DITHER_DOWN_EN | m_DITHER_UP_EN;
1860                         val = v_DITHER_DOWN_EN(0) | v_DITHER_UP_EN(0);
1861
1862                         mask |= m_EDP_HSYNC_POL | m_EDP_VSYNC_POL |
1863                             m_EDP_DEN_POL | m_EDP_DCLK_POL;
1864                         val |= v_EDP_HSYNC_POL(screen->pin_hsync) |
1865                             v_EDP_VSYNC_POL(screen->pin_vsync) |
1866                             v_EDP_DEN_POL(screen->pin_den) |
1867                             v_EDP_DCLK_POL(screen->pin_dclk);
1868                         break;
1869                 }
1870                 /*hsync vsync den dclk polo,dither */
1871                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
1872 #ifndef CONFIG_RK_FPGA
1873                 /*writel_relaxed(v, RK_GRF_VIRT + rk3368_GRF_SOC_CON7);
1874                 move to  lvds driver*/
1875                 /*GRF_SOC_CON7 bit[15]:0->dsi/lvds mode,1->ttl mode */
1876 #endif
1877                 mask = m_DSP_OUT_MODE | m_DSP_DCLK_DDR | m_DSP_BG_SWAP |
1878                     m_DSP_RB_SWAP | m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
1879                     m_DSP_DUMMY_SWAP | m_DSP_OUT_ZERO | m_DSP_BLANK_EN |
1880                     m_DSP_BLACK_EN | m_DSP_X_MIR_EN | m_DSP_Y_MIR_EN;
1881                 val = v_DSP_OUT_MODE(face) | v_DSP_DCLK_DDR(dclk_ddr) |
1882                     v_DSP_BG_SWAP(screen->swap_gb) |
1883                     v_DSP_RB_SWAP(screen->swap_rb) |
1884                     v_DSP_RG_SWAP(screen->swap_rg) |
1885                     v_DSP_DELTA_SWAP(screen->swap_delta) |
1886                     v_DSP_DUMMY_SWAP(screen->swap_dumy) | v_DSP_OUT_ZERO(0) |
1887                     v_DSP_BLANK_EN(0) | v_DSP_BLACK_EN(0) |
1888                     v_DSP_X_MIR_EN(screen->x_mirror) |
1889                     v_DSP_Y_MIR_EN(screen->y_mirror);
1890                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
1891                 /*BG color */
1892                 mask = m_DSP_BG_BLUE | m_DSP_BG_GREEN | m_DSP_BG_RED;
1893                 if (dev_drv->overlay_mode == VOP_YUV_DOMAIN)
1894                         val = v_DSP_BG_BLUE(0x80) | v_DSP_BG_GREEN(0x10) |
1895                                 v_DSP_BG_RED(0x80);
1896                 else
1897                         val = v_DSP_BG_BLUE(0) | v_DSP_BG_GREEN(0) |
1898                                 v_DSP_BG_RED(0);
1899                 lcdc_msk_reg(lcdc_dev, DSP_BG, mask, val);
1900                 dev_drv->output_color = screen->color_mode;
1901                 if (screen->dsp_lut == NULL)
1902                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1903                                      v_DSP_LUT_EN(0));
1904                 else
1905                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_LUT_EN,
1906                                      v_DSP_LUT_EN(1));
1907                 if (screen->cabc_lut == NULL) {
1908                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0, m_CABC_EN,
1909                                      v_CABC_EN(0));
1910                 } else {
1911                         lcdc_msk_reg(lcdc_dev, CABC_CTRL1, m_CABC_LUT_EN,
1912                                      v_CABC_LUT_EN(1));
1913                 }
1914                 rk3368_lcdc_bcsh_path_sel(dev_drv);
1915                 rk3368_config_timing(dev_drv);
1916         }
1917         spin_unlock(&lcdc_dev->reg_lock);
1918         rk3368_lcdc_set_dclk(dev_drv, 1);
1919         if (screen->type != SCREEN_HDMI && dev_drv->trsm_ops &&
1920             dev_drv->trsm_ops->enable)
1921                 dev_drv->trsm_ops->enable();
1922         if (screen->init)
1923                 screen->init();
1924         if (!lcdc_dev->standby)
1925                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
1926         return 0;
1927 }
1928
1929
1930 /*enable layer,open:1,enable;0 disable*/
1931 static void rk3368_lcdc_layer_enable(struct lcdc_device *lcdc_dev,
1932                                      unsigned int win_id, bool open)
1933 {
1934         spin_lock(&lcdc_dev->reg_lock);
1935         if (likely(lcdc_dev->clk_on) &&
1936             lcdc_dev->driver.win[win_id]->state != open) {
1937                 if (open) {
1938                         if (!lcdc_dev->atv_layer_cnt) {
1939                                 dev_info(lcdc_dev->dev,
1940                                          "wakeup from standby!\n");
1941                                 lcdc_dev->standby = 0;
1942                         }
1943                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
1944                 } else {
1945                         if (lcdc_dev->atv_layer_cnt & (1 << win_id))
1946                                 lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
1947                 }
1948                 lcdc_dev->driver.win[win_id]->state = open;
1949                 if (!open) {
1950                         /*rk3368_lcdc_reg_update(dev_drv);*/
1951                         rk3368_lcdc_layer_update_regs
1952                         (lcdc_dev, lcdc_dev->driver.win[win_id]);
1953                         lcdc_cfg_done(lcdc_dev);
1954                 }
1955                 /*if no layer used,disable lcdc */
1956                 if (!lcdc_dev->atv_layer_cnt) {
1957                         dev_info(lcdc_dev->dev,
1958                                  "no layer is used,go to standby!\n");
1959                         lcdc_dev->standby = 1;
1960                 }
1961         }
1962         spin_unlock(&lcdc_dev->reg_lock);
1963 }
1964
1965 static int rk3368_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
1966 {
1967         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1968                                                     struct lcdc_device, driver);
1969         u32 mask, val;
1970         /*struct rk_screen *screen = dev_drv->cur_screen; */
1971
1972         mask = m_FS_INTR_CLR | m_FS_NEW_INTR_CLR | m_LINE_FLAG0_INTR_CLR |
1973             m_LINE_FLAG1_INTR_CLR;
1974         val = v_FS_INTR_CLR(1) | v_FS_NEW_INTR_CLR(1) |
1975             v_LINE_FLAG0_INTR_CLR(1) | v_LINE_FLAG1_INTR_CLR(1);
1976         lcdc_msk_reg(lcdc_dev, INTR_CLEAR, mask, val);
1977
1978         mask = m_FS_INTR_EN | m_LINE_FLAG0_INTR_EN |
1979                 m_BUS_ERROR_INTR_EN | m_LINE_FLAG1_INTR_EN;
1980         val = v_FS_INTR_EN(1) | v_LINE_FLAG0_INTR_EN(1) |
1981             v_BUS_ERROR_INTR_EN(1) | v_LINE_FLAG1_INTR_EN(0);
1982         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1983
1984 #ifdef LCDC_IRQ_EMPTY_DEBUG
1985         mask = m_WIN0_EMPTY_INTR_EN | m_WIN1_EMPTY_INTR_EN |
1986             m_WIN2_EMPTY_INTR_EN |
1987             m_WIN3_EMPTY_INTR_EN | m_HWC_EMPTY_INTR_EN |
1988             m_POST_BUF_EMPTY_INTR_EN | m_PWM_GEN_INTR_EN;
1989         val = v_WIN0_EMPTY_INTR_EN(1) | v_WIN1_EMPTY_INTR_EN(1) |
1990             v_WIN2_EMPTY_INTR_EN(1) |
1991             v_WIN3_EMPTY_INTR_EN(1) | v_HWC_EMPTY_INTR_EN(1) |
1992             v_POST_BUF_EMPTY_INTR_EN(1) | v_PWM_GEN_INTR_EN(1);
1993         lcdc_msk_reg(lcdc_dev, INTR_EN, mask, val);
1994 #endif
1995         return 0;
1996 }
1997
1998 static int rk3368_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
1999                             bool open)
2000 {
2001         struct lcdc_device *lcdc_dev =
2002             container_of(dev_drv, struct lcdc_device, driver);
2003 #if 0/*ndef CONFIG_RK_FPGA*/
2004         int sys_status =
2005             (dev_drv->id == 0) ? SYS_STATUS_LCDC0 : SYS_STATUS_LCDC1;
2006 #endif
2007         /*enable clk,when first layer open */
2008         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
2009                 /*rockchip_set_system_status(sys_status);*/
2010                 rk3368_lcdc_pre_init(dev_drv);
2011                 rk3368_lcdc_clk_enable(lcdc_dev);
2012 #if defined(CONFIG_ROCKCHIP_IOMMU)
2013                 if (dev_drv->iommu_enabled) {
2014                         if (!dev_drv->mmu_dev) {
2015                                 dev_drv->mmu_dev =
2016                                     rk_fb_get_sysmmu_device_by_compatible
2017                                     (dev_drv->mmu_dts_name);
2018                                 if (dev_drv->mmu_dev) {
2019                                         rk_fb_platform_set_sysmmu
2020                                             (dev_drv->mmu_dev, dev_drv->dev);
2021                                 } else {
2022                                         dev_err(dev_drv->dev,
2023                                                 "fail get rk iommu device\n");
2024                                         return -1;
2025                                 }
2026                         }
2027                         /*if (dev_drv->mmu_dev)
2028                            rockchip_iovmm_activate(dev_drv->dev); */
2029                 }
2030 #endif
2031                 rk3368_lcdc_reg_restore(lcdc_dev);
2032                 /*if (dev_drv->iommu_enabled)
2033                    rk3368_lcdc_mmu_en(dev_drv); */
2034                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
2035                         rk3368_lcdc_set_dclk(dev_drv, 0);
2036                         rk3368_lcdc_enable_irq(dev_drv);
2037                 } else {
2038                         rk3368_load_screen(dev_drv, 1);
2039                 }
2040                 if (dev_drv->bcsh.enable)
2041                         rk3368_lcdc_set_bcsh(dev_drv, 1);
2042                 spin_lock(&lcdc_dev->reg_lock);
2043                 if (dev_drv->cur_screen->dsp_lut)
2044                         rk3368_lcdc_set_lut(dev_drv,
2045                                             dev_drv->cur_screen->dsp_lut);
2046                 if (dev_drv->cur_screen->cabc_lut)
2047                         rk3368_set_cabc_lut(dev_drv,
2048                                             dev_drv->cur_screen->cabc_lut);
2049                 spin_unlock(&lcdc_dev->reg_lock);
2050         }
2051
2052         if (win_id < ARRAY_SIZE(lcdc_win))
2053                 rk3368_lcdc_layer_enable(lcdc_dev, win_id, open);
2054         else
2055                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
2056
2057
2058         /* when all layer closed,disable clk */
2059         /*if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
2060            rk3368_lcdc_disable_irq(lcdc_dev);
2061            rk3368_lcdc_reg_update(dev_drv);
2062            #if defined(CONFIG_ROCKCHIP_IOMMU)
2063            if (dev_drv->iommu_enabled) {
2064            if (dev_drv->mmu_dev)
2065            rockchip_iovmm_deactivate(dev_drv->dev);
2066            }
2067            #endif
2068            rk3368_lcdc_clk_disable(lcdc_dev);
2069            #ifndef CONFIG_RK_FPGA
2070            rockchip_clear_system_status(sys_status);
2071            #endif
2072            } */
2073
2074         return 0;
2075 }
2076
2077 static int win_0_1_display(struct lcdc_device *lcdc_dev,
2078                            struct rk_lcdc_win *win)
2079 {
2080         u32 y_addr;
2081         u32 uv_addr;
2082         unsigned int off;
2083
2084         off = win->id * 0x40;
2085         /*win->smem_start + win->y_offset; */
2086         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2087         uv_addr = win->area[0].cbr_start + win->area[0].c_offset;
2088         DBG(2, "lcdc[%d]:win[%d]>>:y_addr:0x%x>>uv_addr:0x%x",
2089             lcdc_dev->id, win->id, y_addr, uv_addr);
2090         DBG(2, ">>y_offset:0x%x>>c_offset=0x%x\n",
2091             win->area[0].y_offset, win->area[0].c_offset);
2092         spin_lock(&lcdc_dev->reg_lock);
2093         if (likely(lcdc_dev->clk_on)) {
2094                 win->area[0].y_addr = y_addr;
2095                 win->area[0].uv_addr = uv_addr;
2096                 lcdc_writel(lcdc_dev, WIN0_YRGB_MST + off, win->area[0].y_addr);
2097                 lcdc_writel(lcdc_dev, WIN0_CBR_MST + off, win->area[0].uv_addr);
2098                 if (win->area[0].fbdc_en == 1)
2099                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2100                                         win->area[0].y_addr);
2101         }
2102         spin_unlock(&lcdc_dev->reg_lock);
2103
2104         return 0;
2105 }
2106
2107 static int win_2_3_display(struct lcdc_device *lcdc_dev,
2108                            struct rk_lcdc_win *win)
2109 {
2110         u32 i, y_addr;
2111         unsigned int off;
2112
2113         off = (win->id - 2) * 0x50;
2114         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2115         DBG(2, "lcdc[%d]:win[%d]:", lcdc_dev->id, win->id);
2116
2117         spin_lock(&lcdc_dev->reg_lock);
2118         if (likely(lcdc_dev->clk_on)) {
2119                 for (i = 0; i < win->area_num; i++) {
2120                         DBG(2, "area[%d]:yaddr:0x%x>>offset:0x%x>>\n",
2121                             i, win->area[i].y_addr, win->area[i].y_offset);
2122                         win->area[i].y_addr =
2123                             win->area[i].smem_start + win->area[i].y_offset;
2124                         }
2125                 lcdc_writel(lcdc_dev, WIN2_MST0 + off, win->area[0].y_addr);
2126                 lcdc_writel(lcdc_dev, WIN2_MST1 + off, win->area[1].y_addr);
2127                 lcdc_writel(lcdc_dev, WIN2_MST2 + off, win->area[2].y_addr);
2128                 lcdc_writel(lcdc_dev, WIN2_MST3 + off, win->area[3].y_addr);
2129                 if (win->area[0].fbdc_en == 1)
2130                         lcdc_writel(lcdc_dev, IFBDC_BASE_ADDR,
2131                                         win->area[0].y_addr);
2132         }
2133         spin_unlock(&lcdc_dev->reg_lock);
2134         return 0;
2135 }
2136
2137 static int hwc_display(struct lcdc_device *lcdc_dev, struct rk_lcdc_win *win)
2138 {
2139         u32 y_addr;
2140
2141         y_addr = win->area[0].smem_start + win->area[0].y_offset;
2142         DBG(2, "lcdc[%d]:hwc>>%s>>y_addr:0x%x>>\n",
2143             lcdc_dev->id, __func__, y_addr);
2144         spin_lock(&lcdc_dev->reg_lock);
2145         if (likely(lcdc_dev->clk_on)) {
2146                 win->area[0].y_addr = y_addr;
2147                 lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
2148         }
2149         spin_unlock(&lcdc_dev->reg_lock);
2150
2151         return 0;
2152 }
2153
2154 static int rk3368_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
2155 {
2156         struct lcdc_device *lcdc_dev =
2157             container_of(dev_drv, struct lcdc_device, driver);
2158         struct rk_lcdc_win *win = NULL;
2159         struct rk_screen *screen = dev_drv->cur_screen;
2160
2161 #if defined(WAIT_FOR_SYNC)
2162         int timeout;
2163         unsigned long flags;
2164 #endif
2165         win = dev_drv->win[win_id];
2166         if (!screen) {
2167                 dev_err(dev_drv->dev, "screen is null!\n");
2168                 return -ENOENT;
2169         }
2170         if (win_id == 0) {
2171                 win_0_1_display(lcdc_dev, win);
2172         } else if (win_id == 1) {
2173                 win_0_1_display(lcdc_dev, win);
2174         } else if (win_id == 2) {
2175                 win_2_3_display(lcdc_dev, win);
2176         } else if (win_id == 3) {
2177                 win_2_3_display(lcdc_dev, win);
2178         } else if (win_id == 4) {
2179                 hwc_display(lcdc_dev, win);
2180         } else {
2181                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
2182                 return -EINVAL;
2183         }
2184
2185         /*this is the first frame of the system ,enable frame start interrupt */
2186         if ((dev_drv->first_frame)) {
2187                 dev_drv->first_frame = 0;
2188                 rk3368_lcdc_enable_irq(dev_drv);
2189         }
2190 #if defined(WAIT_FOR_SYNC)
2191         spin_lock_irqsave(&dev_drv->cpl_lock, flags);
2192         init_completion(&dev_drv->frame_done);
2193         spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
2194         timeout =
2195             wait_for_completion_timeout(&dev_drv->frame_done,
2196                                         msecs_to_jiffies(dev_drv->
2197                                                          cur_screen->ft + 5));
2198         if (!timeout && (!dev_drv->frame_done.done)) {
2199                 dev_info(dev_drv->dev, "wait for new frame start time out!\n");
2200                 return -ETIMEDOUT;
2201         }
2202 #endif
2203         return 0;
2204 }
2205
2206 static int rk3368_lcdc_cal_scl_fac(struct rk_lcdc_win *win)
2207 {
2208         u16 srcW;
2209         u16 srcH;
2210         u16 dstW;
2211         u16 dstH;
2212         u16 yrgb_srcW;
2213         u16 yrgb_srcH;
2214         u16 yrgb_dstW;
2215         u16 yrgb_dstH;
2216         u32 yrgb_vscalednmult;
2217         u32 yrgb_xscl_factor;
2218         u32 yrgb_yscl_factor;
2219         u8 yrgb_vsd_bil_gt2 = 0;
2220         u8 yrgb_vsd_bil_gt4 = 0;
2221
2222         u16 cbcr_srcW;
2223         u16 cbcr_srcH;
2224         u16 cbcr_dstW;
2225         u16 cbcr_dstH;
2226         u32 cbcr_vscalednmult;
2227         u32 cbcr_xscl_factor;
2228         u32 cbcr_yscl_factor;
2229         u8 cbcr_vsd_bil_gt2 = 0;
2230         u8 cbcr_vsd_bil_gt4 = 0;
2231         u8 yuv_fmt = 0;
2232
2233         srcW = win->area[0].xact;
2234         srcH = win->area[0].yact;
2235         dstW = win->area[0].xsize;
2236         dstH = win->area[0].ysize;
2237
2238         /*yrgb scl mode */
2239         yrgb_srcW = srcW;
2240         yrgb_srcH = srcH;
2241         yrgb_dstW = dstW;
2242         yrgb_dstH = dstH;
2243         if ((yrgb_dstW * 8 <= yrgb_srcW) || (yrgb_dstH * 8 <= yrgb_srcH)) {
2244                 pr_err("ERROR: yrgb scale exceed 8,");
2245                 pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n",
2246                        yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH);
2247         }
2248         if (yrgb_srcW < yrgb_dstW)
2249                 win->yrgb_hor_scl_mode = SCALE_UP;
2250         else if (yrgb_srcW > yrgb_dstW)
2251                 win->yrgb_hor_scl_mode = SCALE_DOWN;
2252         else
2253                 win->yrgb_hor_scl_mode = SCALE_NONE;
2254
2255         if (yrgb_srcH < yrgb_dstH)
2256                 win->yrgb_ver_scl_mode = SCALE_UP;
2257         else if (yrgb_srcH > yrgb_dstH)
2258                 win->yrgb_ver_scl_mode = SCALE_DOWN;
2259         else
2260                 win->yrgb_ver_scl_mode = SCALE_NONE;
2261
2262         /*cbcr scl mode */
2263         switch (win->area[0].format) {
2264         case YUV422:
2265         case YUV422_A:
2266                 cbcr_srcW = srcW / 2;
2267                 cbcr_dstW = dstW;
2268                 cbcr_srcH = srcH;
2269                 cbcr_dstH = dstH;
2270                 yuv_fmt = 1;
2271                 break;
2272         case YUV420:
2273         case YUV420_A:
2274                 cbcr_srcW = srcW / 2;
2275                 cbcr_dstW = dstW;
2276                 cbcr_srcH = srcH / 2;
2277                 cbcr_dstH = dstH;
2278                 yuv_fmt = 1;
2279                 break;
2280         case YUV444:
2281         case YUV444_A:
2282                 cbcr_srcW = srcW;
2283                 cbcr_dstW = dstW;
2284                 cbcr_srcH = srcH;
2285                 cbcr_dstH = dstH;
2286                 yuv_fmt = 1;
2287                 break;
2288         default:
2289                 cbcr_srcW = 0;
2290                 cbcr_dstW = 0;
2291                 cbcr_srcH = 0;
2292                 cbcr_dstH = 0;
2293                 yuv_fmt = 0;
2294                 break;
2295         }
2296         if (yuv_fmt) {
2297                 if ((cbcr_dstW * 8 <= cbcr_srcW) ||
2298                     (cbcr_dstH * 8 <= cbcr_srcH)) {
2299                         pr_err("ERROR: cbcr scale exceed 8,");
2300                         pr_err("srcW=%d,srcH=%d,dstW=%d,dstH=%d\n", cbcr_srcW,
2301                                cbcr_srcH, cbcr_dstW, cbcr_dstH);
2302                 }
2303         }
2304
2305         if (cbcr_srcW < cbcr_dstW)
2306                 win->cbr_hor_scl_mode = SCALE_UP;
2307         else if (cbcr_srcW > cbcr_dstW)
2308                 win->cbr_hor_scl_mode = SCALE_DOWN;
2309         else
2310                 win->cbr_hor_scl_mode = SCALE_NONE;
2311
2312         if (cbcr_srcH < cbcr_dstH)
2313                 win->cbr_ver_scl_mode = SCALE_UP;
2314         else if (cbcr_srcH > cbcr_dstH)
2315                 win->cbr_ver_scl_mode = SCALE_DOWN;
2316         else
2317                 win->cbr_ver_scl_mode = SCALE_NONE;
2318
2319         /*DBG(1, "srcW:%d>>srcH:%d>>dstW:%d>>dstH:%d>>\n"
2320             "yrgb:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n"
2321             "cbcr:src:W=%d>>H=%d,dst:W=%d>>H=%d,H_mode=%d,V_mode=%d\n", srcW,
2322             srcH, dstW, dstH, yrgb_srcW, yrgb_srcH, yrgb_dstW, yrgb_dstH,
2323             win->yrgb_hor_scl_mode, win->yrgb_ver_scl_mode, cbcr_srcW,
2324             cbcr_srcH, cbcr_dstW, cbcr_dstH, win->cbr_hor_scl_mode,
2325             win->cbr_ver_scl_mode);*/
2326
2327         /*line buffer mode */
2328         if ((win->area[0].format == YUV422) ||
2329             (win->area[0].format == YUV420) ||
2330             (win->area[0].format == YUV422_A) ||
2331             (win->area[0].format == YUV420_A)) {
2332                 if (win->cbr_hor_scl_mode == SCALE_DOWN) {
2333                         if ((cbcr_dstW > VOP_INPUT_MAX_WIDTH / 2) ||
2334                             (cbcr_dstW == 0))
2335                                 pr_err("ERROR cbcr_dstW = %d,exceeds 2048\n",
2336                                        cbcr_dstW);
2337                         else if (cbcr_dstW > 1280)
2338                                 win->win_lb_mode = LB_YUV_3840X5;
2339                         else
2340                                 win->win_lb_mode = LB_YUV_2560X8;
2341                 } else {        /*SCALE_UP or SCALE_NONE */
2342                         if ((cbcr_srcW > VOP_INPUT_MAX_WIDTH / 2) ||
2343                             (cbcr_srcW == 0))
2344                                 pr_err("ERROR cbcr_srcW = %d,exceeds 2048\n",
2345                                        cbcr_srcW);
2346                         else if (cbcr_srcW > 1280)
2347                                 win->win_lb_mode = LB_YUV_3840X5;
2348                         else
2349                                 win->win_lb_mode = LB_YUV_2560X8;
2350                 }
2351         } else {
2352                 if (win->yrgb_hor_scl_mode == SCALE_DOWN) {
2353                         if ((yrgb_dstW > VOP_INPUT_MAX_WIDTH) ||
2354                             (yrgb_dstW == 0))
2355                                 pr_err("ERROR yrgb_dstW = %d\n", yrgb_dstW);
2356                         else if (yrgb_dstW > 2560)
2357                                 win->win_lb_mode = LB_RGB_3840X2;
2358                         else if (yrgb_dstW > 1920)
2359                                 win->win_lb_mode = LB_RGB_2560X4;
2360                         else if (yrgb_dstW > 1280)
2361                                 win->win_lb_mode = LB_RGB_1920X5;
2362                         else
2363                                 win->win_lb_mode = LB_RGB_1280X8;
2364                 } else {        /*SCALE_UP or SCALE_NONE */
2365                         if ((yrgb_srcW > VOP_INPUT_MAX_WIDTH) ||
2366                             (yrgb_srcW == 0))
2367                                 pr_err("ERROR yrgb_srcW = %d\n", yrgb_srcW);
2368                         else if (yrgb_srcW > 2560)
2369                                 win->win_lb_mode = LB_RGB_3840X2;
2370                         else if (yrgb_srcW > 1920)
2371                                 win->win_lb_mode = LB_RGB_2560X4;
2372                         else if (yrgb_srcW > 1280)
2373                                 win->win_lb_mode = LB_RGB_1920X5;
2374                         else
2375                                 win->win_lb_mode = LB_RGB_1280X8;
2376                 }
2377         }
2378         DBG(1, "win->win_lb_mode = %d;\n", win->win_lb_mode);
2379
2380         /*vsd/vsu scale ALGORITHM */
2381         win->yrgb_hsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2382         win->cbr_hsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2383         win->yrgb_vsd_mode = SCALE_DOWN_BIL;    /*not to specify */
2384         win->cbr_vsd_mode = SCALE_DOWN_BIL;     /*not to specify */
2385         switch (win->win_lb_mode) {
2386         case LB_YUV_3840X5:
2387         case LB_YUV_2560X8:
2388         case LB_RGB_1920X5:
2389         case LB_RGB_1280X8:
2390                 win->yrgb_vsu_mode = SCALE_UP_BIC;
2391                 win->cbr_vsu_mode = SCALE_UP_BIC;
2392                 break;
2393         case LB_RGB_3840X2:
2394                 if (win->yrgb_ver_scl_mode != SCALE_NONE)
2395                         pr_err("ERROR : not allow yrgb ver scale\n");
2396                 if (win->cbr_ver_scl_mode != SCALE_NONE)
2397                         pr_err("ERROR : not allow cbcr ver scale\n");
2398                 break;
2399         case LB_RGB_2560X4:
2400                 win->yrgb_vsu_mode = SCALE_UP_BIL;
2401                 win->cbr_vsu_mode = SCALE_UP_BIL;
2402                 break;
2403         default:
2404                 pr_info("%s:un supported win_lb_mode:%d\n",
2405                         __func__, win->win_lb_mode);
2406                 break;
2407         }
2408         if (win->mirror_en == 1) {      /*interlace mode must bill */
2409                 win->yrgb_vsd_mode = SCALE_DOWN_BIL;
2410         }
2411
2412         if ((win->yrgb_ver_scl_mode == SCALE_DOWN) &&
2413             (win->area[0].fbdc_en == 1)) {
2414                 /*in this pattern,use bil mode,not support souble scd,
2415                 use avg mode, support double scd, but aclk should be
2416                 bigger than dclk,aclk>>dclk */
2417                 if (yrgb_srcH >= 2 * yrgb_dstH) {
2418                         pr_err("ERROR : fbdc mode,not support y scale down:");
2419                         pr_err("srcH[%d] > 2 *dstH[%d]\n",
2420                                yrgb_srcH, yrgb_dstH);
2421                 }
2422         }
2423         DBG(1, "yrgb:hsd=%d,vsd=%d,vsu=%d;cbcr:hsd=%d,vsd=%d,vsu=%d\n",
2424             win->yrgb_hsd_mode, win->yrgb_vsd_mode, win->yrgb_vsu_mode,
2425             win->cbr_hsd_mode, win->cbr_vsd_mode, win->cbr_vsu_mode);
2426
2427         /*SCALE FACTOR */
2428
2429         /*(1.1)YRGB HOR SCALE FACTOR */
2430         switch (win->yrgb_hor_scl_mode) {
2431         case SCALE_NONE:
2432                 yrgb_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2433                 break;
2434         case SCALE_UP:
2435                 yrgb_xscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcW, yrgb_dstW);
2436                 break;
2437         case SCALE_DOWN:
2438                 switch (win->yrgb_hsd_mode) {
2439                 case SCALE_DOWN_BIL:
2440                         yrgb_xscl_factor =
2441                             GET_SCALE_FACTOR_BILI_DN(yrgb_srcW, yrgb_dstW);
2442                         break;
2443                 case SCALE_DOWN_AVG:
2444                         yrgb_xscl_factor =
2445                             GET_SCALE_FACTOR_AVRG(yrgb_srcW, yrgb_dstW);
2446                         break;
2447                 default:
2448                         pr_info(
2449                                 "%s:un supported yrgb_hsd_mode:%d\n", __func__,
2450                                win->yrgb_hsd_mode);
2451                         break;
2452                 }
2453                 break;
2454         default:
2455                 pr_info("%s:un supported yrgb_hor_scl_mode:%d\n",
2456                         __func__, win->yrgb_hor_scl_mode);
2457                 break;
2458         }                       /*win->yrgb_hor_scl_mode */
2459
2460         /*(1.2)YRGB VER SCALE FACTOR */
2461         switch (win->yrgb_ver_scl_mode) {
2462         case SCALE_NONE:
2463                 yrgb_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2464                 break;
2465         case SCALE_UP:
2466                 switch (win->yrgb_vsu_mode) {
2467                 case SCALE_UP_BIL:
2468                         yrgb_yscl_factor =
2469                             GET_SCALE_FACTOR_BILI_UP(yrgb_srcH, yrgb_dstH);
2470                         break;
2471                 case SCALE_UP_BIC:
2472                         if (yrgb_srcH < 3) {
2473                                 pr_err("yrgb_srcH should be");
2474                                 pr_err(" greater than 3 !!!\n");
2475                         }
2476                         yrgb_yscl_factor = GET_SCALE_FACTOR_BIC(yrgb_srcH,
2477                                                                 yrgb_dstH);
2478                         break;
2479                 default:
2480                         pr_info("%s:un support yrgb_vsu_mode:%d\n",
2481                                 __func__, win->yrgb_vsu_mode);
2482                         break;
2483                 }
2484                 break;
2485         case SCALE_DOWN:
2486                 switch (win->yrgb_vsd_mode) {
2487                 case SCALE_DOWN_BIL:
2488                         yrgb_vscalednmult =
2489                             rk3368_get_hard_ware_vskiplines(yrgb_srcH,
2490                                                             yrgb_dstH);
2491                         yrgb_yscl_factor =
2492                             GET_SCALE_FACTOR_BILI_DN_VSKIP(yrgb_srcH, yrgb_dstH,
2493                                                            yrgb_vscalednmult);
2494                         if (yrgb_yscl_factor >= 0x2000) {
2495                                 pr_err("yrgb_yscl_factor should be ");
2496                                 pr_err("less than 0x2000,yrgb_yscl_factor=%4x;\n",
2497                                        yrgb_yscl_factor);
2498                         }
2499                         if (yrgb_vscalednmult == 4) {
2500                                 yrgb_vsd_bil_gt4 = 1;
2501                                 yrgb_vsd_bil_gt2 = 0;
2502                         } else if (yrgb_vscalednmult == 2) {
2503                                 yrgb_vsd_bil_gt4 = 0;
2504                                 yrgb_vsd_bil_gt2 = 1;
2505                         } else {
2506                                 yrgb_vsd_bil_gt4 = 0;
2507                                 yrgb_vsd_bil_gt2 = 0;
2508                         }
2509                         break;
2510                 case SCALE_DOWN_AVG:
2511                         yrgb_yscl_factor = GET_SCALE_FACTOR_AVRG(yrgb_srcH,
2512                                                                  yrgb_dstH);
2513                         break;
2514                 default:
2515                         pr_info("%s:un support yrgb_vsd_mode:%d\n",
2516                                 __func__, win->yrgb_vsd_mode);
2517                         break;
2518                 }               /*win->yrgb_vsd_mode */
2519                 break;
2520         default:
2521                 pr_info("%s:un supported yrgb_ver_scl_mode:%d\n",
2522                         __func__, win->yrgb_ver_scl_mode);
2523                 break;
2524         }
2525         win->scale_yrgb_x = yrgb_xscl_factor;
2526         win->scale_yrgb_y = yrgb_yscl_factor;
2527         win->vsd_yrgb_gt4 = yrgb_vsd_bil_gt4;
2528         win->vsd_yrgb_gt2 = yrgb_vsd_bil_gt2;
2529         DBG(1, "yrgb:h_fac=%d, v_fac=%d,gt4=%d, gt2=%d\n", yrgb_xscl_factor,
2530             yrgb_yscl_factor, yrgb_vsd_bil_gt4, yrgb_vsd_bil_gt2);
2531
2532         /*(2.1)CBCR HOR SCALE FACTOR */
2533         switch (win->cbr_hor_scl_mode) {
2534         case SCALE_NONE:
2535                 cbcr_xscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2536                 break;
2537         case SCALE_UP:
2538                 cbcr_xscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcW, cbcr_dstW);
2539                 break;
2540         case SCALE_DOWN:
2541                 switch (win->cbr_hsd_mode) {
2542                 case SCALE_DOWN_BIL:
2543                         cbcr_xscl_factor =
2544                             GET_SCALE_FACTOR_BILI_DN(cbcr_srcW, cbcr_dstW);
2545                         break;
2546                 case SCALE_DOWN_AVG:
2547                         cbcr_xscl_factor =
2548                             GET_SCALE_FACTOR_AVRG(cbcr_srcW, cbcr_dstW);
2549                         break;
2550                 default:
2551                         pr_info("%s:un support cbr_hsd_mode:%d\n",
2552                                 __func__, win->cbr_hsd_mode);
2553                         break;
2554                 }
2555                 break;
2556         default:
2557                 pr_info("%s:un supported cbr_hor_scl_mode:%d\n",
2558                         __func__, win->cbr_hor_scl_mode);
2559                 break;
2560         }                       /*win->cbr_hor_scl_mode */
2561
2562         /*(2.2)CBCR VER SCALE FACTOR */
2563         switch (win->cbr_ver_scl_mode) {
2564         case SCALE_NONE:
2565                 cbcr_yscl_factor = (1 << SCALE_FACTOR_DEFAULT_FIXPOINT_SHIFT);
2566                 break;
2567         case SCALE_UP:
2568                 switch (win->cbr_vsu_mode) {
2569                 case SCALE_UP_BIL:
2570                         cbcr_yscl_factor =
2571                             GET_SCALE_FACTOR_BILI_UP(cbcr_srcH, cbcr_dstH);
2572                         break;
2573                 case SCALE_UP_BIC:
2574                         if (cbcr_srcH < 3) {
2575                                 pr_err("cbcr_srcH should be ");
2576                                 pr_err("greater than 3 !!!\n");
2577                         }
2578                         cbcr_yscl_factor = GET_SCALE_FACTOR_BIC(cbcr_srcH,
2579                                                                 cbcr_dstH);
2580                         break;
2581                 default:
2582                         pr_info("%s:un support cbr_vsu_mode:%d\n",
2583                                 __func__, win->cbr_vsu_mode);
2584                         break;
2585                 }
2586                 break;
2587         case SCALE_DOWN:
2588                 switch (win->cbr_vsd_mode) {
2589                 case SCALE_DOWN_BIL:
2590                         cbcr_vscalednmult =
2591                             rk3368_get_hard_ware_vskiplines(cbcr_srcH,
2592                                                             cbcr_dstH);
2593                         cbcr_yscl_factor =
2594                             GET_SCALE_FACTOR_BILI_DN_VSKIP(cbcr_srcH, cbcr_dstH,
2595                                                            cbcr_vscalednmult);
2596                         if (cbcr_yscl_factor >= 0x2000) {
2597                                 pr_err("cbcr_yscl_factor should be less ");
2598                                 pr_err("than 0x2000,cbcr_yscl_factor=%4x;\n",
2599                                        cbcr_yscl_factor);
2600                         }
2601
2602                         if (cbcr_vscalednmult == 4) {
2603                                 cbcr_vsd_bil_gt4 = 1;
2604                                 cbcr_vsd_bil_gt2 = 0;
2605                         } else if (cbcr_vscalednmult == 2) {
2606                                 cbcr_vsd_bil_gt4 = 0;
2607                                 cbcr_vsd_bil_gt2 = 1;
2608                         } else {
2609                                 cbcr_vsd_bil_gt4 = 0;
2610                                 cbcr_vsd_bil_gt2 = 0;
2611                         }
2612                         break;
2613                 case SCALE_DOWN_AVG:
2614                         cbcr_yscl_factor = GET_SCALE_FACTOR_AVRG(cbcr_srcH,
2615                                                                  cbcr_dstH);
2616                         break;
2617                 default:
2618                         pr_info("%s:un support cbr_vsd_mode:%d\n",
2619                                 __func__, win->cbr_vsd_mode);
2620                         break;
2621                 }
2622                 break;
2623         default:
2624                 pr_info("%s:un supported cbr_ver_scl_mode:%d\n",
2625                         __func__, win->cbr_ver_scl_mode);
2626                 break;
2627         }
2628         win->scale_cbcr_x = cbcr_xscl_factor;
2629         win->scale_cbcr_y = cbcr_yscl_factor;
2630         win->vsd_cbr_gt4 = cbcr_vsd_bil_gt4;
2631         win->vsd_cbr_gt2 = cbcr_vsd_bil_gt2;
2632
2633         DBG(1, "cbcr:h_fac=%d,v_fac=%d,gt4=%d,gt2=%d\n", cbcr_xscl_factor,
2634             cbcr_yscl_factor, cbcr_vsd_bil_gt4, cbcr_vsd_bil_gt2);
2635         return 0;
2636 }
2637
2638 static int dsp_x_pos(int mirror_en, struct rk_screen *screen,
2639                      struct rk_lcdc_win_area *area)
2640 {
2641         int pos;
2642
2643         if (screen->x_mirror && mirror_en)
2644                 pr_err("not support both win and global mirror\n");
2645
2646         if ((!mirror_en) && (!screen->x_mirror))
2647                 pos = area->xpos + screen->mode.left_margin +
2648                         screen->mode.hsync_len;
2649         else
2650                 pos = screen->mode.xres - area->xpos -
2651                         area->xsize + screen->mode.left_margin +
2652                         screen->mode.hsync_len;
2653
2654         return pos;
2655 }
2656
2657 static int dsp_y_pos(int mirror_en, struct rk_screen *screen,
2658                      struct rk_lcdc_win_area *area)
2659 {
2660         int pos;
2661
2662         if (screen->y_mirror && mirror_en)
2663                 pr_err("not support both win and global mirror\n");
2664         if (screen->mode.vmode == FB_VMODE_NONINTERLACED) {
2665                 if ((!mirror_en) && (!screen->y_mirror))
2666                         pos = area->ypos + screen->mode.upper_margin +
2667                                 screen->mode.vsync_len;
2668                 else
2669                         pos = screen->mode.yres - area->ypos -
2670                                 area->ysize + screen->mode.upper_margin +
2671                                 screen->mode.vsync_len;
2672         } else if (screen->mode.vmode == FB_VMODE_INTERLACED) {
2673                 pos = area->ypos / 2 + screen->mode.upper_margin +
2674                         screen->mode.vsync_len;
2675                 area->ysize /= 2;
2676         }
2677
2678         return pos;
2679 }
2680
2681 static int win_0_1_set_par(struct lcdc_device *lcdc_dev,
2682                            struct rk_screen *screen, struct rk_lcdc_win *win)
2683 {
2684         u32 xact, yact, xvir, yvir, xpos, ypos;
2685         u8 fmt_cfg = 0, swap_rb;
2686         char fmt[9] = "NULL";
2687
2688         xpos = dsp_x_pos(win->mirror_en, screen, &win->area[0]);
2689         ypos = dsp_y_pos(win->mirror_en, screen, &win->area[0]);
2690
2691         spin_lock(&lcdc_dev->reg_lock);
2692         if (likely(lcdc_dev->clk_on)) {
2693                 rk3368_lcdc_cal_scl_fac(win);   /*fac,lb,gt2,gt4 */
2694                 switch (win->area[0].format) {
2695                 case FBDC_RGB_565:
2696                         fmt_cfg = 2;
2697                         swap_rb = 0;
2698                         win->fmt_10 = 0;
2699                         win->area[0].fbdc_fmt_cfg = 0x05;
2700                         break;
2701                 case FBDC_ARGB_888:
2702                         fmt_cfg = 0;
2703                         swap_rb = 0;
2704                         win->fmt_10 = 0;
2705                         win->area[0].fbdc_fmt_cfg = 0x0c;
2706                         break;
2707                 case FBDC_RGBX_888:
2708                         fmt_cfg = 0;
2709                         swap_rb = 0;
2710                         win->fmt_10 = 0;
2711                         win->area[0].fbdc_fmt_cfg = 0x3a;
2712                         break;
2713                 case ARGB888:
2714                         fmt_cfg = 0;
2715                         swap_rb = 0;
2716                         win->fmt_10 = 0;
2717                         break;
2718                 case XBGR888:
2719                 case ABGR888:
2720                         fmt_cfg = 0;
2721                         swap_rb = 1;
2722                         win->fmt_10 = 0;
2723                         break;
2724                 case RGB888:
2725                         fmt_cfg = 1;
2726                         swap_rb = 0;
2727                         win->fmt_10 = 0;
2728                         break;
2729                 case RGB565:
2730                         fmt_cfg = 2;
2731                         swap_rb = 0;
2732                         win->fmt_10 = 0;
2733                         break;
2734                 case YUV422:
2735                         fmt_cfg = 5;
2736                         swap_rb = 0;
2737                         win->fmt_10 = 0;
2738                         break;
2739                 case YUV420:
2740                         fmt_cfg = 4;
2741                         swap_rb = 0;
2742                         win->fmt_10 = 0;
2743                         break;
2744                 case YUV444:
2745                         fmt_cfg = 6;
2746                         swap_rb = 0;
2747                         win->fmt_10 = 0;
2748                         break;
2749                 case YUV422_A:
2750                         fmt_cfg = 5;
2751                         swap_rb = 0;
2752                         win->fmt_10 = 1;
2753                         break;
2754                 case YUV420_A:
2755                         fmt_cfg = 4;
2756                         swap_rb = 0;
2757                         win->fmt_10 = 1;
2758                         break;
2759                 case YUV444_A:
2760                         fmt_cfg = 6;
2761                         swap_rb = 0;
2762                         win->fmt_10 = 1;
2763                         break;
2764                 default:
2765                         dev_err(lcdc_dev->driver.dev, "%s:unsupport format!\n",
2766                                 __func__);
2767                         break;
2768                 }
2769                 win->area[0].fmt_cfg = fmt_cfg;
2770                 win->area[0].swap_rb = swap_rb;
2771                 win->area[0].dsp_stx = xpos;
2772                 win->area[0].dsp_sty = ypos;
2773                 xact = win->area[0].xact;
2774                 yact = win->area[0].yact;
2775                 xvir = win->area[0].xvir;
2776                 yvir = win->area[0].yvir;
2777         }
2778         if (win->area[0].fbdc_en)
2779                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2780         rk3368_win_0_1_reg_update(&lcdc_dev->driver, win->id);
2781         spin_unlock(&lcdc_dev->reg_lock);
2782
2783         DBG(1, "lcdc[%d]:win[%d]\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2784             lcdc_dev->id, win->id, get_format_string(win->area[0].format, fmt),
2785             xact, yact, win->area[0].xsize);
2786         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2787             win->area[0].ysize, xvir, yvir, xpos, ypos);
2788
2789         return 0;
2790 }
2791
2792
2793 static int win_2_3_set_par(struct lcdc_device *lcdc_dev,
2794                            struct rk_screen *screen, struct rk_lcdc_win *win)
2795 {
2796         int i;
2797         u8 fmt_cfg, swap_rb;
2798         char fmt[9] = "NULL";
2799
2800         if (win->mirror_en)
2801                 pr_err("win[%d] not support y mirror\n", win->id);
2802         spin_lock(&lcdc_dev->reg_lock);
2803         if (likely(lcdc_dev->clk_on)) {
2804                 DBG(2, "lcdc[%d]:win[%d]>>\n>\n", lcdc_dev->id, win->id);
2805                 for (i = 0; i < win->area_num; i++) {
2806                         switch (win->area[i].format) {
2807                         case FBDC_RGB_565:
2808                                 fmt_cfg = 2;
2809                                 swap_rb = 0;
2810                                 win->fmt_10 = 0;
2811                                 win->area[0].fbdc_fmt_cfg = 0x05;
2812                                 break;
2813                         case FBDC_ARGB_888:
2814                                 fmt_cfg = 0;
2815                                 swap_rb = 0;
2816                                 win->fmt_10 = 0;
2817                                 win->area[0].fbdc_fmt_cfg = 0x0c;
2818                                 break;
2819                         case FBDC_RGBX_888:
2820                                 fmt_cfg = 0;
2821                                 swap_rb = 0;
2822                                 win->fmt_10 = 0;
2823                                 win->area[0].fbdc_fmt_cfg = 0x3a;
2824                                 break;
2825                         case ARGB888:
2826                                 fmt_cfg = 0;
2827                                 swap_rb = 0;
2828                                 break;
2829                         case XBGR888:
2830                         case ABGR888:
2831                                 fmt_cfg = 0;
2832                                 swap_rb = 1;
2833                                 break;
2834                         case RGB888:
2835                                 fmt_cfg = 1;
2836                                 swap_rb = 0;
2837                                 break;
2838                         case RGB565:
2839                                 fmt_cfg = 2;
2840                                 swap_rb = 0;
2841                                 break;
2842                         default:
2843                                 dev_err(lcdc_dev->driver.dev,
2844                                         "%s:un supported format!\n", __func__);
2845                                 break;
2846                         }
2847                         win->area[i].fmt_cfg = fmt_cfg;
2848                         win->area[i].swap_rb = swap_rb;
2849                         win->area[i].dsp_stx =
2850                                         dsp_x_pos(win->mirror_en, screen,
2851                                                   &win->area[i]);
2852                         win->area[i].dsp_sty =
2853                                         dsp_y_pos(win->mirror_en, screen,
2854                                                   &win->area[i]);
2855
2856                         DBG(2, "fmt:%s:xsize:%d>>ysize:%d>>xpos:%d>>ypos:%d\n",
2857                             get_format_string(win->area[i].format, fmt),
2858                             win->area[i].xsize, win->area[i].ysize,
2859                             win->area[i].xpos, win->area[i].ypos);
2860                 }
2861         }
2862         if (win->area[0].fbdc_en)
2863                 rk3368_init_fbdc_config(&lcdc_dev->driver, win->id);
2864         rk3368_win_2_3_reg_update(&lcdc_dev->driver, win->id);
2865         spin_unlock(&lcdc_dev->reg_lock);
2866         return 0;
2867 }
2868
2869 static int hwc_set_par(struct lcdc_device *lcdc_dev,
2870                        struct rk_screen *screen, struct rk_lcdc_win *win)
2871 {
2872         u32 xact, yact, xvir, yvir, xpos, ypos;
2873         u8 fmt_cfg = 0, swap_rb;
2874         char fmt[9] = "NULL";
2875
2876         xpos = win->area[0].xpos + screen->mode.left_margin +
2877             screen->mode.hsync_len;
2878         ypos = win->area[0].ypos + screen->mode.upper_margin +
2879             screen->mode.vsync_len;
2880
2881         spin_lock(&lcdc_dev->reg_lock);
2882         if (likely(lcdc_dev->clk_on)) {
2883                 /*rk3368_lcdc_cal_scl_fac(win); *//*fac,lb,gt2,gt4 */
2884                 switch (win->area[0].format) {
2885                 case ARGB888:
2886                         fmt_cfg = 0;
2887                         swap_rb = 0;
2888                         break;
2889                 case XBGR888:
2890                 case ABGR888:
2891                         fmt_cfg = 0;
2892                         swap_rb = 1;
2893                         break;
2894                 case RGB888:
2895                         fmt_cfg = 1;
2896                         swap_rb = 0;
2897                         break;
2898                 case RGB565:
2899                         fmt_cfg = 2;
2900                         swap_rb = 0;
2901                         break;
2902                 default:
2903                         dev_err(lcdc_dev->driver.dev,
2904                                 "%s:un supported format!\n", __func__);
2905                         break;
2906                 }
2907                 win->area[0].fmt_cfg = fmt_cfg;
2908                 win->area[0].swap_rb = swap_rb;
2909                 win->area[0].dsp_stx = xpos;
2910                 win->area[0].dsp_sty = ypos;
2911                 xact = win->area[0].xact;
2912                 yact = win->area[0].yact;
2913                 xvir = win->area[0].xvir;
2914                 yvir = win->area[0].yvir;
2915         }
2916         rk3368_hwc_reg_update(&lcdc_dev->driver, 4);
2917         spin_unlock(&lcdc_dev->reg_lock);
2918
2919         DBG(1, "lcdc[%d]:hwc>>%s\n>>format:%s>>>xact:%d>>yact:%d>>xsize:%d",
2920             lcdc_dev->id, __func__, get_format_string(win->area[0].format, fmt),
2921             xact, yact, win->area[0].xsize);
2922         DBG(1, ">>ysize:%d>>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n",
2923             win->area[0].ysize, xvir, yvir, xpos, ypos);
2924         return 0;
2925 }
2926
2927 static int rk3368_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
2928 {
2929         struct lcdc_device *lcdc_dev =
2930             container_of(dev_drv, struct lcdc_device, driver);
2931         struct rk_lcdc_win *win = NULL;
2932         struct rk_screen *screen = dev_drv->cur_screen;
2933
2934         win = dev_drv->win[win_id];
2935         switch (win_id) {
2936         case 0:
2937                 win_0_1_set_par(lcdc_dev, screen, win);
2938                 break;
2939         case 1:
2940                 win_0_1_set_par(lcdc_dev, screen, win);
2941                 break;
2942         case 2:
2943                 win_2_3_set_par(lcdc_dev, screen, win);
2944                 break;
2945         case 3:
2946                 win_2_3_set_par(lcdc_dev, screen, win);
2947                 break;
2948         case 4:
2949                 hwc_set_par(lcdc_dev, screen, win);
2950                 break;
2951         default:
2952                 dev_err(dev_drv->dev, "unsupported win number:%d\n", win_id);
2953                 break;
2954         }
2955         return 0;
2956 }
2957
2958 static int rk3368_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
2959                              unsigned long arg, int win_id)
2960 {
2961         struct lcdc_device *lcdc_dev =
2962             container_of(dev_drv, struct lcdc_device, driver);
2963         u32 panel_size[2];
2964         void __user *argp = (void __user *)arg;
2965         struct color_key_cfg clr_key_cfg;
2966
2967         switch (cmd) {
2968         case RK_FBIOGET_PANEL_SIZE:
2969                 panel_size[0] = lcdc_dev->screen->mode.xres;
2970                 panel_size[1] = lcdc_dev->screen->mode.yres;
2971                 if (copy_to_user(argp, panel_size, 8))
2972                         return -EFAULT;
2973                 break;
2974         case RK_FBIOPUT_COLOR_KEY_CFG:
2975                 if (copy_from_user(&clr_key_cfg, argp,
2976                                    sizeof(struct color_key_cfg)))
2977                         return -EFAULT;
2978                 rk3368_lcdc_clr_key_cfg(dev_drv);
2979                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
2980                             clr_key_cfg.win0_color_key_cfg);
2981                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
2982                             clr_key_cfg.win1_color_key_cfg);
2983                 break;
2984
2985         default:
2986                 break;
2987         }
2988         return 0;
2989 }
2990
2991 static int rk3368_lcdc_get_backlight_device(struct rk_lcdc_driver *dev_drv)
2992 {
2993         struct lcdc_device *lcdc_dev = container_of(dev_drv,
2994                                                     struct lcdc_device, driver);
2995         /*struct device_node *backlight;*/
2996
2997         if (lcdc_dev->backlight)
2998                 return 0;
2999 #if 0
3000         backlight = of_parse_phandle(lcdc_dev->dev->of_node, "backlight", 0);
3001         if (backlight) {
3002                 lcdc_dev->backlight = of_find_backlight_by_node(backlight);
3003                 if (!lcdc_dev->backlight)
3004                         dev_info(lcdc_dev->dev, "No find backlight device\n");
3005         } else {
3006                 dev_info(lcdc_dev->dev, "No find backlight device node\n");
3007         }
3008 #endif
3009         return 0;
3010 }
3011
3012 static int rk3368_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
3013 {
3014         struct lcdc_device *lcdc_dev =
3015             container_of(dev_drv, struct lcdc_device, driver);
3016         if (dev_drv->suspend_flag)
3017                 return 0;
3018         /* close the backlight */
3019         /*rk3368_lcdc_get_backlight_device(dev_drv);
3020         if (lcdc_dev->backlight) {
3021                 lcdc_dev->backlight->props.fb_blank = FB_BLANK_POWERDOWN;
3022                 backlight_update_status(lcdc_dev->backlight);
3023         }*/
3024
3025         dev_drv->suspend_flag = 1;
3026         flush_kthread_worker(&dev_drv->update_regs_worker);
3027
3028         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
3029                 dev_drv->trsm_ops->disable();
3030
3031         spin_lock(&lcdc_dev->reg_lock);
3032         if (likely(lcdc_dev->clk_on)) {
3033                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3034                              v_DSP_BLANK_EN(1));
3035                 lcdc_msk_reg(lcdc_dev,
3036                              INTR_CLEAR, m_FS_INTR_CLR | m_LINE_FLAG0_INTR_CLR,
3037                              v_FS_INTR_CLR(1) | v_LINE_FLAG0_INTR_CLR(1));
3038                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3039                              v_DSP_OUT_ZERO(1));
3040                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(1));
3041                 lcdc_cfg_done(lcdc_dev);
3042
3043                 if (dev_drv->iommu_enabled) {
3044                         if (dev_drv->mmu_dev)
3045                                 rockchip_iovmm_deactivate(dev_drv->dev);
3046                 }
3047
3048                 spin_unlock(&lcdc_dev->reg_lock);
3049         } else {
3050                 spin_unlock(&lcdc_dev->reg_lock);
3051                 return 0;
3052         }
3053         rk3368_lcdc_clk_disable(lcdc_dev);
3054         rk_disp_pwr_disable(dev_drv);
3055         return 0;
3056 }
3057
3058 static int rk3368_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
3059 {
3060         struct lcdc_device *lcdc_dev =
3061             container_of(dev_drv, struct lcdc_device, driver);
3062
3063         if (!dev_drv->suspend_flag)
3064                 return 0;
3065         rk_disp_pwr_enable(dev_drv);
3066         dev_drv->suspend_flag = 0;
3067
3068         if (1/*lcdc_dev->atv_layer_cnt*/) {
3069                 rk3368_lcdc_clk_enable(lcdc_dev);
3070                 rk3368_lcdc_reg_restore(lcdc_dev);
3071
3072                 spin_lock(&lcdc_dev->reg_lock);
3073                 if (dev_drv->cur_screen->dsp_lut)
3074                         rk3368_lcdc_set_lut(dev_drv,
3075                                             dev_drv->cur_screen->dsp_lut);
3076                 if (dev_drv->cur_screen->cabc_lut)
3077                         rk3368_set_cabc_lut(dev_drv,
3078                                             dev_drv->cur_screen->cabc_lut);
3079
3080                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_OUT_ZERO,
3081                              v_DSP_OUT_ZERO(0));
3082                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN, v_STANDBY_EN(0));
3083                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLANK_EN,
3084                              v_DSP_BLANK_EN(0));
3085                 lcdc_cfg_done(lcdc_dev);
3086
3087                 if (dev_drv->iommu_enabled) {
3088                         if (dev_drv->mmu_dev)
3089                                 rockchip_iovmm_activate(dev_drv->dev);
3090                 }
3091
3092                 spin_unlock(&lcdc_dev->reg_lock);
3093         }
3094
3095         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
3096                 dev_drv->trsm_ops->enable();
3097         return 0;
3098 }
3099
3100 static int rk3368_lcdc_blank(struct rk_lcdc_driver *dev_drv,
3101                              int win_id, int blank_mode)
3102 {
3103         switch (blank_mode) {
3104         case FB_BLANK_UNBLANK:
3105                 rk3368_lcdc_early_resume(dev_drv);
3106                 break;
3107         case FB_BLANK_NORMAL:
3108                 rk3368_lcdc_early_suspend(dev_drv);
3109                 break;
3110         default:
3111                 rk3368_lcdc_early_suspend(dev_drv);
3112                 break;
3113         }
3114
3115         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
3116
3117         return 0;
3118 }
3119
3120 static int rk3368_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv, int win_id)
3121 {
3122         return 0;
3123 }
3124
3125 /*overlay will be do at regupdate*/
3126 static int rk3368_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
3127                                bool set)
3128 {
3129         struct lcdc_device *lcdc_dev =
3130             container_of(dev_drv, struct lcdc_device, driver);
3131         struct rk_lcdc_win *win = NULL;
3132         int i, ovl;
3133         unsigned int mask, val;
3134         int z_order_num = 0;
3135         int layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3136
3137         if (swap == 0) {
3138                 for (i = 0; i < 4; i++) {
3139                         win = dev_drv->win[i];
3140                         if (win->state == 1)
3141                                 z_order_num++;
3142                 }
3143                 for (i = 0; i < 4; i++) {
3144                         win = dev_drv->win[i];
3145                         if (win->state == 0)
3146                                 win->z_order = z_order_num++;
3147                         switch (win->z_order) {
3148                         case 0:
3149                                 layer0_sel = win->id;
3150                                 break;
3151                         case 1:
3152                                 layer1_sel = win->id;
3153                                 break;
3154                         case 2:
3155                                 layer2_sel = win->id;
3156                                 break;
3157                         case 3:
3158                                 layer3_sel = win->id;
3159                                 break;
3160                         default:
3161                                 break;
3162                         }
3163                 }
3164         } else {
3165                 layer0_sel = swap % 10;
3166                 layer1_sel = swap / 10 % 10;
3167                 layer2_sel = swap / 100 % 10;
3168                 layer3_sel = swap / 1000;
3169         }
3170
3171         spin_lock(&lcdc_dev->reg_lock);
3172         if (lcdc_dev->clk_on) {
3173                 if (set) {
3174                         mask = m_DSP_LAYER0_SEL | m_DSP_LAYER1_SEL |
3175                             m_DSP_LAYER2_SEL | m_DSP_LAYER3_SEL;
3176                         val = v_DSP_LAYER0_SEL(layer0_sel) |
3177                             v_DSP_LAYER1_SEL(layer1_sel) |
3178                             v_DSP_LAYER2_SEL(layer2_sel) |
3179                             v_DSP_LAYER3_SEL(layer3_sel);
3180                         lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
3181                 } else {
3182                         layer0_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3183                                                    m_DSP_LAYER0_SEL);
3184                         layer1_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3185                                                    m_DSP_LAYER1_SEL);
3186                         layer2_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3187                                                    m_DSP_LAYER2_SEL);
3188                         layer3_sel = lcdc_read_bit(lcdc_dev, DSP_CTRL1,
3189                                                    m_DSP_LAYER3_SEL);
3190                         ovl = layer3_sel * 1000 + layer2_sel * 100 +
3191                             layer1_sel * 10 + layer0_sel;
3192                 }
3193         } else {
3194                 ovl = -EPERM;
3195         }
3196         spin_unlock(&lcdc_dev->reg_lock);
3197
3198         return ovl;
3199 }
3200
3201 static char *rk3368_lcdc_format_to_string(int format, char *fmt)
3202 {
3203         if (!fmt)
3204                 return NULL;
3205
3206         switch (format) {
3207         case 0:
3208                 strcpy(fmt, "ARGB888");
3209                 break;
3210         case 1:
3211                 strcpy(fmt, "RGB888");
3212                 break;
3213         case 2:
3214                 strcpy(fmt, "RGB565");
3215                 break;
3216         case 4:
3217                 strcpy(fmt, "YCbCr420");
3218                 break;
3219         case 5:
3220                 strcpy(fmt, "YCbCr422");
3221                 break;
3222         case 6:
3223                 strcpy(fmt, "YCbCr444");
3224                 break;
3225         default:
3226                 strcpy(fmt, "invalid\n");
3227                 break;
3228         }
3229         return fmt;
3230 }
3231 static ssize_t rk3368_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
3232                                          char *buf, int win_id)
3233 {
3234         struct lcdc_device *lcdc_dev =
3235             container_of(dev_drv, struct lcdc_device, driver);
3236         struct rk_screen *screen = dev_drv->cur_screen;
3237         u16 hsync_len = screen->mode.hsync_len;
3238         u16 left_margin = screen->mode.left_margin;
3239         u16 vsync_len = screen->mode.vsync_len;
3240         u16 upper_margin = screen->mode.upper_margin;
3241         u32 h_pw_bp = hsync_len + left_margin;
3242         u32 v_pw_bp = vsync_len + upper_margin;
3243         u32 fmt_id;
3244         char format_w0[9] = "NULL";
3245         char format_w1[9] = "NULL";
3246         char format_w2_0[9] = "NULL";
3247         char format_w2_1[9] = "NULL";
3248         char format_w2_2[9] = "NULL";
3249         char format_w2_3[9] = "NULL";
3250         char format_w3_0[9] = "NULL";
3251         char format_w3_1[9] = "NULL";
3252         char format_w3_2[9] = "NULL";
3253         char format_w3_3[9] = "NULL";
3254         char dsp_buf[100];
3255         u32 win_ctrl, zorder, vir_info, act_info, dsp_info, dsp_st;
3256         u32 y_factor, uv_factor;
3257         u8 layer0_sel, layer1_sel, layer2_sel, layer3_sel;
3258         u8 w0_state, w1_state, w2_state, w3_state;
3259         u8 w2_0_state, w2_1_state, w2_2_state, w2_3_state;
3260         u8 w3_0_state, w3_1_state, w3_2_state, w3_3_state;
3261
3262         u32 w0_vir_y, w0_vir_uv, w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y;
3263         u32 w0_st_x = h_pw_bp, w0_st_y = v_pw_bp;
3264         u32 w1_vir_y, w1_vir_uv, w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y;
3265         u32 w1_st_x = h_pw_bp, w1_st_y = v_pw_bp;
3266         u32 w0_y_h_fac, w0_y_v_fac, w0_uv_h_fac, w0_uv_v_fac;
3267         u32 w1_y_h_fac, w1_y_v_fac, w1_uv_h_fac, w1_uv_v_fac;
3268
3269         u32 w2_0_vir_y, w2_1_vir_y, w2_2_vir_y, w2_3_vir_y;
3270         u32 w2_0_dsp_x, w2_1_dsp_x, w2_2_dsp_x, w2_3_dsp_x;
3271         u32 w2_0_dsp_y, w2_1_dsp_y, w2_2_dsp_y, w2_3_dsp_y;
3272         u32 w2_0_st_x = h_pw_bp, w2_1_st_x = h_pw_bp;
3273         u32 w2_2_st_x = h_pw_bp, w2_3_st_x = h_pw_bp;
3274         u32 w2_0_st_y = v_pw_bp, w2_1_st_y = v_pw_bp;
3275         u32 w2_2_st_y = v_pw_bp, w2_3_st_y = v_pw_bp;
3276
3277         u32 w3_0_vir_y, w3_1_vir_y, w3_2_vir_y, w3_3_vir_y;
3278         u32 w3_0_dsp_x, w3_1_dsp_x, w3_2_dsp_x, w3_3_dsp_x;
3279         u32 w3_0_dsp_y, w3_1_dsp_y, w3_2_dsp_y, w3_3_dsp_y;
3280         u32 w3_0_st_x = h_pw_bp, w3_1_st_x = h_pw_bp;
3281         u32 w3_2_st_x = h_pw_bp, w3_3_st_x = h_pw_bp;
3282         u32 w3_0_st_y = v_pw_bp, w3_1_st_y = v_pw_bp;
3283         u32 w3_2_st_y = v_pw_bp, w3_3_st_y = v_pw_bp;
3284         u32 dclk_freq;
3285         int size = 0;
3286
3287         dclk_freq = screen->mode.pixclock;
3288         /*rk3368_lcdc_reg_dump(dev_drv); */
3289
3290         spin_lock(&lcdc_dev->reg_lock);
3291         if (lcdc_dev->clk_on) {
3292                 zorder = lcdc_readl(lcdc_dev, DSP_CTRL1);
3293                 layer0_sel = (zorder & m_DSP_LAYER0_SEL) >> 8;
3294                 layer1_sel = (zorder & m_DSP_LAYER1_SEL) >> 10;
3295                 layer2_sel = (zorder & m_DSP_LAYER2_SEL) >> 12;
3296                 layer3_sel = (zorder & m_DSP_LAYER3_SEL) >> 14;
3297                 /*WIN0 */
3298                 win_ctrl = lcdc_readl(lcdc_dev, WIN0_CTRL0);
3299                 w0_state = win_ctrl & m_WIN0_EN;
3300                 fmt_id = (win_ctrl & m_WIN0_DATA_FMT) >> 1;
3301                 rk3368_lcdc_format_to_string(fmt_id, format_w0);
3302                 vir_info = lcdc_readl(lcdc_dev, WIN0_VIR);
3303                 act_info = lcdc_readl(lcdc_dev, WIN0_ACT_INFO);
3304                 dsp_info = lcdc_readl(lcdc_dev, WIN0_DSP_INFO);
3305                 dsp_st = lcdc_readl(lcdc_dev, WIN0_DSP_ST);
3306                 y_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_YRGB);
3307                 uv_factor = lcdc_readl(lcdc_dev, WIN0_SCL_FACTOR_CBR);
3308                 w0_vir_y = vir_info & m_WIN0_VIR_STRIDE;
3309                 w0_vir_uv = (vir_info & m_WIN0_VIR_STRIDE_UV) >> 16;
3310                 w0_act_x = (act_info & m_WIN0_ACT_WIDTH) + 1;
3311                 w0_act_y = ((act_info & m_WIN0_ACT_HEIGHT) >> 16) + 1;
3312                 w0_dsp_x = (dsp_info & m_WIN0_DSP_WIDTH) + 1;
3313                 w0_dsp_y = ((dsp_info & m_WIN0_DSP_HEIGHT) >> 16) + 1;
3314                 if (w0_state) {
3315                         w0_st_x = dsp_st & m_WIN0_DSP_XST;
3316                         w0_st_y = (dsp_st & m_WIN0_DSP_YST) >> 16;
3317                 }
3318                 w0_y_h_fac = y_factor & m_WIN0_HS_FACTOR_YRGB;
3319                 w0_y_v_fac = (y_factor & m_WIN0_VS_FACTOR_YRGB) >> 16;
3320                 w0_uv_h_fac = uv_factor & m_WIN0_HS_FACTOR_CBR;
3321                 w0_uv_v_fac = (uv_factor & m_WIN0_VS_FACTOR_CBR) >> 16;
3322
3323                 /*WIN1 */
3324                 win_ctrl = lcdc_readl(lcdc_dev, WIN1_CTRL0);
3325                 w1_state = win_ctrl & m_WIN1_EN;
3326                 fmt_id = (win_ctrl & m_WIN1_DATA_FMT) >> 1;
3327                 rk3368_lcdc_format_to_string(fmt_id, format_w1);
3328                 vir_info = lcdc_readl(lcdc_dev, WIN1_VIR);
3329                 act_info = lcdc_readl(lcdc_dev, WIN1_ACT_INFO);
3330                 dsp_info = lcdc_readl(lcdc_dev, WIN1_DSP_INFO);
3331                 dsp_st = lcdc_readl(lcdc_dev, WIN1_DSP_ST);
3332                 y_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_YRGB);
3333                 uv_factor = lcdc_readl(lcdc_dev, WIN1_SCL_FACTOR_CBR);
3334                 w1_vir_y = vir_info & m_WIN1_VIR_STRIDE;
3335                 w1_vir_uv = (vir_info & m_WIN1_VIR_STRIDE_UV) >> 16;
3336                 w1_act_x = (act_info & m_WIN1_ACT_WIDTH) + 1;
3337                 w1_act_y = ((act_info & m_WIN1_ACT_HEIGHT) >> 16) + 1;
3338                 w1_dsp_x = (dsp_info & m_WIN1_DSP_WIDTH) + 1;
3339                 w1_dsp_y = ((dsp_info & m_WIN1_DSP_HEIGHT) >> 16) + 1;
3340                 if (w1_state) {
3341                         w1_st_x = dsp_st & m_WIN1_DSP_XST;
3342                         w1_st_y = (dsp_st & m_WIN1_DSP_YST) >> 16;
3343                 }
3344                 w1_y_h_fac = y_factor & m_WIN1_HS_FACTOR_YRGB;
3345                 w1_y_v_fac = (y_factor & m_WIN1_VS_FACTOR_YRGB) >> 16;
3346                 w1_uv_h_fac = uv_factor & m_WIN1_HS_FACTOR_CBR;
3347                 w1_uv_v_fac = (uv_factor & m_WIN1_VS_FACTOR_CBR) >> 16;
3348                 /*WIN2 */
3349                 win_ctrl = lcdc_readl(lcdc_dev, WIN2_CTRL0);
3350                 w2_state = win_ctrl & m_WIN2_EN;
3351                 w2_0_state = (win_ctrl & 0x10) >> 4;
3352                 w2_1_state = (win_ctrl & 0x100) >> 8;
3353                 w2_2_state = (win_ctrl & 0x1000) >> 12;
3354                 w2_3_state = (win_ctrl & 0x10000) >> 16;
3355                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR0_1);
3356                 w2_0_vir_y = vir_info & m_WIN2_VIR_STRIDE0;
3357                 w2_1_vir_y = (vir_info & m_WIN2_VIR_STRIDE1) >> 16;
3358                 vir_info = lcdc_readl(lcdc_dev, WIN2_VIR2_3);
3359                 w2_2_vir_y = vir_info & m_WIN2_VIR_STRIDE2;
3360                 w2_3_vir_y = (vir_info & m_WIN2_VIR_STRIDE3) >> 16;
3361
3362                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT0) >> 1;
3363                 rk3368_lcdc_format_to_string(fmt_id, format_w2_0);
3364                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT1) >> 1;
3365                 rk3368_lcdc_format_to_string(fmt_id, format_w2_1);
3366                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT2) >> 1;
3367                 rk3368_lcdc_format_to_string(fmt_id, format_w2_2);
3368                 fmt_id = (win_ctrl & m_WIN2_DATA_FMT3) >> 1;
3369                 rk3368_lcdc_format_to_string(fmt_id, format_w2_3);
3370
3371                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO0);
3372                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST0);
3373                 w2_0_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH0) + 1;
3374                 w2_0_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT0) >> 16) + 1;
3375                 if (w2_0_state) {
3376                         w2_0_st_x = dsp_st & m_WIN2_DSP_XST0;
3377                         w2_0_st_y = (dsp_st & m_WIN2_DSP_YST0) >> 16;
3378                 }
3379                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO1);
3380                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST1);
3381                 w2_1_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH1) + 1;
3382                 w2_1_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT1) >> 16) + 1;
3383                 if (w2_1_state) {
3384                         w2_1_st_x = dsp_st & m_WIN2_DSP_XST1;
3385                         w2_1_st_y = (dsp_st & m_WIN2_DSP_YST1) >> 16;
3386                 }
3387                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO2);
3388                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST2);
3389                 w2_2_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH2) + 1;
3390                 w2_2_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT2) >> 16) + 1;
3391                 if (w2_2_state) {
3392                         w2_2_st_x = dsp_st & m_WIN2_DSP_XST2;
3393                         w2_2_st_y = (dsp_st & m_WIN2_DSP_YST2) >> 16;
3394                 }
3395                 dsp_info = lcdc_readl(lcdc_dev, WIN2_DSP_INFO3);
3396                 dsp_st = lcdc_readl(lcdc_dev, WIN2_DSP_ST3);
3397                 w2_3_dsp_x = (dsp_info & m_WIN2_DSP_WIDTH3) + 1;
3398                 w2_3_dsp_y = ((dsp_info & m_WIN2_DSP_HEIGHT3) >> 16) + 1;
3399                 if (w2_3_state) {
3400                         w2_3_st_x = dsp_st & m_WIN2_DSP_XST3;
3401                         w2_3_st_y = (dsp_st & m_WIN2_DSP_YST3) >> 16;
3402                 }
3403
3404                 /*WIN3 */
3405                 win_ctrl = lcdc_readl(lcdc_dev, WIN3_CTRL0);
3406                 w3_state = win_ctrl & m_WIN3_EN;
3407                 w3_0_state = (win_ctrl & m_WIN3_MST0_EN) >> 4;
3408                 w3_1_state = (win_ctrl & m_WIN3_MST1_EN) >> 8;
3409                 w3_2_state = (win_ctrl & m_WIN3_MST2_EN) >> 12;
3410                 w3_3_state = (win_ctrl & m_WIN3_MST3_EN) >> 16;
3411                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR0_1);
3412                 w3_0_vir_y = vir_info & m_WIN3_VIR_STRIDE0;
3413                 w3_1_vir_y = (vir_info & m_WIN3_VIR_STRIDE1) >> 16;
3414                 vir_info = lcdc_readl(lcdc_dev, WIN3_VIR2_3);
3415                 w3_2_vir_y = vir_info & m_WIN3_VIR_STRIDE2;
3416                 w3_3_vir_y = (vir_info & m_WIN3_VIR_STRIDE3) >> 16;
3417                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT0) >> 1;
3418                 rk3368_lcdc_format_to_string(fmt_id, format_w3_0);
3419                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT1) >> 1;
3420                 rk3368_lcdc_format_to_string(fmt_id, format_w3_1);
3421                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT2) >> 1;
3422                 rk3368_lcdc_format_to_string(fmt_id, format_w3_2);
3423                 fmt_id = (win_ctrl & m_WIN3_DATA_FMT3) >> 1;
3424                 rk3368_lcdc_format_to_string(fmt_id, format_w3_3);
3425                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO0);
3426                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST0);
3427                 w3_0_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH0) + 1;
3428                 w3_0_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT0) >> 16) + 1;
3429                 if (w3_0_state) {
3430                         w3_0_st_x = dsp_st & m_WIN3_DSP_XST0;
3431                         w3_0_st_y = (dsp_st & m_WIN3_DSP_YST0) >> 16;
3432                 }
3433
3434                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO1);
3435                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST1);
3436                 w3_1_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH1) + 1;
3437                 w3_1_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT1) >> 16) + 1;
3438                 if (w3_1_state) {
3439                         w3_1_st_x = dsp_st & m_WIN3_DSP_XST1;
3440                         w3_1_st_y = (dsp_st & m_WIN3_DSP_YST1) >> 16;
3441                 }
3442
3443                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO2);
3444                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST2);
3445                 w3_2_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH2) + 1;
3446                 w3_2_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT2) >> 16) + 1;
3447                 if (w3_2_state) {
3448                         w3_2_st_x = dsp_st & m_WIN3_DSP_XST2;
3449                         w3_2_st_y = (dsp_st & m_WIN3_DSP_YST2) >> 16;
3450                 }
3451
3452                 dsp_info = lcdc_readl(lcdc_dev, WIN3_DSP_INFO3);
3453                 dsp_st = lcdc_readl(lcdc_dev, WIN3_DSP_ST3);
3454                 w3_3_dsp_x = (dsp_info & m_WIN3_DSP_WIDTH3) + 1;
3455                 w3_3_dsp_y = ((dsp_info & m_WIN3_DSP_HEIGHT3) >> 16) + 1;
3456                 if (w3_3_state) {
3457                         w3_3_st_x = dsp_st & m_WIN3_DSP_XST3;
3458                         w3_3_st_y = (dsp_st & m_WIN3_DSP_YST3) >> 16;
3459                 }
3460
3461         } else {
3462                 spin_unlock(&lcdc_dev->reg_lock);
3463                 return -EPERM;
3464         }
3465         spin_unlock(&lcdc_dev->reg_lock);
3466         size += snprintf(dsp_buf, 80,
3467                 "z-order:\n  win[%d]\n  win[%d]\n  win[%d]\n  win[%d]\n",
3468                 layer3_sel, layer2_sel, layer1_sel, layer0_sel);
3469         strcat(buf, dsp_buf);
3470         memset(dsp_buf, 0, sizeof(dsp_buf));
3471         /*win0*/
3472         size += snprintf(dsp_buf, 80,
3473                  "win0:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3474                  w0_state, format_w0, w0_vir_y, w0_vir_uv);
3475         strcat(buf, dsp_buf);
3476         memset(dsp_buf, 0, sizeof(dsp_buf));
3477
3478         size += snprintf(dsp_buf, 80,
3479                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3480                  w0_act_x, w0_act_y, w0_dsp_x, w0_dsp_y);
3481         strcat(buf, dsp_buf);
3482         memset(dsp_buf, 0, sizeof(dsp_buf));
3483
3484         size += snprintf(dsp_buf, 80,
3485                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3486                  w0_st_x-h_pw_bp, w0_st_y-v_pw_bp, w0_y_h_fac, w0_y_v_fac);
3487         strcat(buf, dsp_buf);
3488         memset(dsp_buf, 0, sizeof(dsp_buf));
3489
3490         size += snprintf(dsp_buf, 80,
3491                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3492                  w0_uv_h_fac, w0_uv_v_fac, lcdc_readl(lcdc_dev, WIN0_YRGB_MST),
3493                  lcdc_readl(lcdc_dev, WIN0_CBR_MST));
3494         strcat(buf, dsp_buf);
3495         memset(dsp_buf, 0, sizeof(dsp_buf));
3496
3497         /*win1*/
3498         size += snprintf(dsp_buf, 80,
3499                  "win1:\n  state:%d, fmt:%7s\n  y_vir:%4d, uv_vir:%4d,",
3500                  w1_state, format_w1, w1_vir_y, w1_vir_uv);
3501         strcat(buf, dsp_buf);
3502         memset(dsp_buf, 0, sizeof(dsp_buf));
3503
3504         size += snprintf(dsp_buf, 80,
3505                  " x_act  :%5d, y_act  :%5d, dsp_x   :%5d, dsp_y   :%5d\n",
3506                  w1_act_x, w1_act_y, w1_dsp_x, w1_dsp_y);
3507         strcat(buf, dsp_buf);
3508         memset(dsp_buf, 0, sizeof(dsp_buf));
3509
3510         size += snprintf(dsp_buf, 80,
3511                  "  x_st :%4d, y_st  :%4d, y_h_fac:%5d, y_v_fac:%5d, ",
3512                  w1_st_x-h_pw_bp, w1_st_y-v_pw_bp, w1_y_h_fac, w1_y_v_fac);
3513         strcat(buf, dsp_buf);
3514         memset(dsp_buf, 0, sizeof(dsp_buf));
3515
3516         size += snprintf(dsp_buf, 80,
3517                  "uv_h_fac:%5d, uv_v_fac:%5d\n  y_addr:0x%08x,    uv_addr:0x%08x\n",
3518                  w1_uv_h_fac, w1_uv_v_fac, lcdc_readl(lcdc_dev, WIN1_YRGB_MST),
3519                  lcdc_readl(lcdc_dev, WIN1_CBR_MST));
3520         strcat(buf, dsp_buf);
3521         memset(dsp_buf, 0, sizeof(dsp_buf));
3522
3523         /*win2*/
3524         size += snprintf(dsp_buf, 80,
3525                  "win2:\n  state:%d\n",
3526                  w2_state);
3527         strcat(buf, dsp_buf);
3528         memset(dsp_buf, 0, sizeof(dsp_buf));
3529         /*area 0*/
3530         size += snprintf(dsp_buf, 80,
3531                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3532                  w2_0_state, format_w2_0, w2_0_dsp_x, w2_0_dsp_y);
3533         strcat(buf, dsp_buf);
3534         memset(dsp_buf, 0, sizeof(dsp_buf));
3535         size += snprintf(dsp_buf, 80,
3536                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3537                  w2_0_st_x - h_pw_bp, w2_0_st_y - v_pw_bp,
3538                  lcdc_readl(lcdc_dev, WIN2_MST0));
3539         strcat(buf, dsp_buf);
3540         memset(dsp_buf, 0, sizeof(dsp_buf));
3541
3542         /*area 1*/
3543         size += snprintf(dsp_buf, 80,
3544                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3545                  w2_1_state, format_w2_1, w2_1_dsp_x, w2_1_dsp_y);
3546         strcat(buf, dsp_buf);
3547         memset(dsp_buf, 0, sizeof(dsp_buf));
3548         size += snprintf(dsp_buf, 80,
3549                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3550                  w2_1_st_x - h_pw_bp, w2_1_st_y - v_pw_bp,
3551                  lcdc_readl(lcdc_dev, WIN2_MST1));
3552         strcat(buf, dsp_buf);
3553         memset(dsp_buf, 0, sizeof(dsp_buf));
3554
3555         /*area 2*/
3556         size += snprintf(dsp_buf, 80,
3557                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3558                  w2_2_state, format_w2_2, w2_2_dsp_x, w2_2_dsp_y);
3559         strcat(buf, dsp_buf);
3560         memset(dsp_buf, 0, sizeof(dsp_buf));
3561         size += snprintf(dsp_buf, 80,
3562                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3563                  w2_2_st_x - h_pw_bp, w2_2_st_y - v_pw_bp,
3564                  lcdc_readl(lcdc_dev, WIN2_MST2));
3565         strcat(buf, dsp_buf);
3566         memset(dsp_buf, 0, sizeof(dsp_buf));
3567
3568         /*area 3*/
3569         size += snprintf(dsp_buf, 80,
3570                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3571                  w2_3_state, format_w2_3, w2_3_dsp_x, w2_3_dsp_y);
3572         strcat(buf, dsp_buf);
3573         memset(dsp_buf, 0, sizeof(dsp_buf));
3574         size += snprintf(dsp_buf, 80,
3575                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3576                  w2_3_st_x - h_pw_bp, w2_3_st_y - v_pw_bp,
3577                  lcdc_readl(lcdc_dev, WIN2_MST3));
3578         strcat(buf, dsp_buf);
3579         memset(dsp_buf, 0, sizeof(dsp_buf));
3580
3581         /*win3*/
3582         size += snprintf(dsp_buf, 80,
3583                  "win3:\n  state:%d\n",
3584                  w3_state);
3585         strcat(buf, dsp_buf);
3586         memset(dsp_buf, 0, sizeof(dsp_buf));
3587         /*area 0*/
3588         size += snprintf(dsp_buf, 80,
3589                  "  area0: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3590                  w3_0_state, format_w3_0, w3_0_dsp_x, w3_0_dsp_y);
3591         strcat(buf, dsp_buf);
3592         memset(dsp_buf, 0, sizeof(dsp_buf));
3593         size += snprintf(dsp_buf, 80,
3594                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3595                  w3_0_st_x - h_pw_bp, w3_0_st_y - v_pw_bp,
3596                  lcdc_readl(lcdc_dev, WIN3_MST0));
3597         strcat(buf, dsp_buf);
3598         memset(dsp_buf, 0, sizeof(dsp_buf));
3599
3600         /*area 1*/
3601         size += snprintf(dsp_buf, 80,
3602                  "  area1: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3603                  w3_1_state, format_w3_1, w3_1_dsp_x, w3_1_dsp_y);
3604         strcat(buf, dsp_buf);
3605         memset(dsp_buf, 0, sizeof(dsp_buf));
3606         size += snprintf(dsp_buf, 80,
3607                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3608                  w3_1_st_x - h_pw_bp, w3_1_st_y - v_pw_bp,
3609                  lcdc_readl(lcdc_dev, WIN3_MST1));
3610         strcat(buf, dsp_buf);
3611         memset(dsp_buf, 0, sizeof(dsp_buf));
3612
3613         /*area 2*/
3614         size += snprintf(dsp_buf, 80,
3615                  "  area2: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3616                  w3_2_state, format_w3_2, w3_2_dsp_x, w3_2_dsp_y);
3617         strcat(buf, dsp_buf);
3618         memset(dsp_buf, 0, sizeof(dsp_buf));
3619         size += snprintf(dsp_buf, 80,
3620                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3621                  w3_2_st_x - h_pw_bp, w3_2_st_y - v_pw_bp,
3622                  lcdc_readl(lcdc_dev, WIN3_MST2));
3623         strcat(buf, dsp_buf);
3624         memset(dsp_buf, 0, sizeof(dsp_buf));
3625
3626         /*area 3*/
3627         size += snprintf(dsp_buf, 80,
3628                  "  area3: state:%d, fmt:%7s, dsp_x:%4d, dsp_y:%4d,",
3629                  w3_3_state, format_w3_3, w3_3_dsp_x, w3_3_dsp_y);
3630         strcat(buf, dsp_buf);
3631         memset(dsp_buf, 0, sizeof(dsp_buf));
3632         size += snprintf(dsp_buf, 80,
3633                  " x_st:%4d, y_st:%4d, y_addr:0x%08x\n",
3634                  w3_3_st_x - h_pw_bp, w3_3_st_y - v_pw_bp,
3635                  lcdc_readl(lcdc_dev, WIN3_MST3));
3636         strcat(buf, dsp_buf);
3637         memset(dsp_buf, 0, sizeof(dsp_buf));
3638
3639         return size;
3640 }
3641
3642 static int rk3368_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
3643                                bool set)
3644 {
3645         struct lcdc_device *lcdc_dev =
3646             container_of(dev_drv, struct lcdc_device, driver);
3647         struct rk_screen *screen = dev_drv->cur_screen;
3648         u64 ft = 0;
3649         u32 dotclk;
3650         int ret;
3651         u32 pixclock;
3652         u32 x_total, y_total;
3653
3654         if (set) {
3655                 if (fps == 0) {
3656                         dev_info(dev_drv->dev, "unsupport set fps=0\n");
3657                         return 0;
3658                 }
3659                 ft = div_u64(1000000000000llu, fps);
3660                 x_total =
3661                     screen->mode.upper_margin + screen->mode.lower_margin +
3662                     screen->mode.yres + screen->mode.vsync_len;
3663                 y_total =
3664                     screen->mode.left_margin + screen->mode.right_margin +
3665                     screen->mode.xres + screen->mode.hsync_len;
3666                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
3667                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
3668                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
3669         }
3670
3671         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
3672         lcdc_dev->pixclock = pixclock;
3673         dev_drv->pixclock = lcdc_dev->pixclock;
3674         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
3675         screen->ft = 1000 / fps;        /*one frame time in ms */
3676
3677         if (set)
3678                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
3679                          clk_get_rate(lcdc_dev->dclk), fps);
3680
3681         return fps;
3682 }
3683
3684 static int rk3368_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
3685 {
3686         mutex_lock(&dev_drv->fb_win_id_mutex);
3687         if (order == FB_DEFAULT_ORDER)
3688                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3_FB4_HWC;
3689         dev_drv->fb4_win_id = order / 10000;
3690         dev_drv->fb3_win_id = (order / 1000) % 10;
3691         dev_drv->fb2_win_id = (order / 100) % 10;
3692         dev_drv->fb1_win_id = (order / 10) % 10;
3693         dev_drv->fb0_win_id = order % 10;
3694         mutex_unlock(&dev_drv->fb_win_id_mutex);
3695
3696         return 0;
3697 }
3698
3699 static int rk3368_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
3700                                   const char *id)
3701 {
3702         int win_id = 0;
3703
3704         mutex_lock(&dev_drv->fb_win_id_mutex);
3705         if (!strcmp(id, "fb0") || !strcmp(id, "fb5"))
3706                 win_id = dev_drv->fb0_win_id;
3707         else if (!strcmp(id, "fb1") || !strcmp(id, "fb6"))
3708                 win_id = dev_drv->fb1_win_id;
3709         else if (!strcmp(id, "fb2") || !strcmp(id, "fb7"))
3710                 win_id = dev_drv->fb2_win_id;
3711         else if (!strcmp(id, "fb3") || !strcmp(id, "fb8"))
3712                 win_id = dev_drv->fb3_win_id;
3713         else if (!strcmp(id, "fb4") || !strcmp(id, "fb9"))
3714                 win_id = dev_drv->fb4_win_id;
3715         mutex_unlock(&dev_drv->fb_win_id_mutex);
3716
3717         return win_id;
3718 }
3719
3720 static int rk3368_lcdc_config_done(struct rk_lcdc_driver *dev_drv)
3721 {
3722         struct lcdc_device *lcdc_dev =
3723             container_of(dev_drv, struct lcdc_device, driver);
3724         int i;
3725         unsigned int mask, val;
3726         struct rk_lcdc_win *win = NULL;
3727
3728         spin_lock(&lcdc_dev->reg_lock);
3729         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_STANDBY_EN,
3730                      v_STANDBY_EN(lcdc_dev->standby));
3731         for (i = 0; i < 4; i++) {
3732                 win = dev_drv->win[i];
3733                 if ((win->state == 0) && (win->last_state == 1)) {
3734                         switch (win->id) {
3735                         case 0:
3736                                 /*lcdc_writel(lcdc_dev,WIN0_CTRL1,0x0);
3737                                    for rk3288 to fix hw bug? */
3738                                 mask = m_WIN0_EN;
3739                                 val = v_WIN0_EN(0);
3740                                 lcdc_msk_reg(lcdc_dev, WIN0_CTRL0, mask, val);
3741                                 break;
3742                         case 1:
3743                                 /*lcdc_writel(lcdc_dev,WIN1_CTRL1,0x0);
3744                                    for rk3288 to fix hw bug? */
3745                                 mask = m_WIN1_EN;
3746                                 val = v_WIN1_EN(0);
3747                                 lcdc_msk_reg(lcdc_dev, WIN1_CTRL0, mask, val);
3748                                 break;
3749                         case 2:
3750                                 mask = m_WIN2_EN | m_WIN2_MST0_EN |
3751                                     m_WIN2_MST1_EN |
3752                                     m_WIN2_MST2_EN | m_WIN2_MST3_EN;
3753                                 val = v_WIN2_EN(0) | v_WIN2_MST0_EN(0) |
3754                                     v_WIN2_MST1_EN(0) |
3755                                     v_WIN2_MST2_EN(0) | v_WIN2_MST3_EN(0);
3756                                 lcdc_msk_reg(lcdc_dev, WIN2_CTRL0, mask, val);
3757                                 break;
3758                         case 3:
3759                                 mask = m_WIN3_EN | m_WIN3_MST0_EN |
3760                                     m_WIN3_MST1_EN |
3761                                     m_WIN3_MST2_EN | m_WIN3_MST3_EN;
3762                                 val = v_WIN3_EN(0) | v_WIN3_MST0_EN(0) |
3763                                     v_WIN3_MST1_EN(0) |
3764                                     v_WIN3_MST2_EN(0) | v_WIN3_MST3_EN(0);
3765                                 lcdc_msk_reg(lcdc_dev, WIN3_CTRL0, mask, val);
3766                                 break;
3767                         case 4:
3768                                 mask = m_HWC_EN;
3769                                 val = v_HWC_EN(0);
3770                                 lcdc_msk_reg(lcdc_dev, HWC_CTRL0, mask, val);
3771                                 break;
3772                         default:
3773                                 break;
3774                         }
3775                 }
3776                 win->last_state = win->state;
3777         }
3778         lcdc_cfg_done(lcdc_dev);
3779         spin_unlock(&lcdc_dev->reg_lock);
3780         return 0;
3781 }
3782
3783 static int rk3368_lcdc_dpi_open(struct rk_lcdc_driver *dev_drv, bool open)
3784 {
3785         struct lcdc_device *lcdc_dev =
3786             container_of(dev_drv, struct lcdc_device, driver);
3787         spin_lock(&lcdc_dev->reg_lock);
3788         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN,
3789                      v_DIRECT_PATH_EN(open));
3790         lcdc_cfg_done(lcdc_dev);
3791         spin_unlock(&lcdc_dev->reg_lock);
3792         return 0;
3793 }
3794
3795 static int rk3368_lcdc_dpi_win_sel(struct rk_lcdc_driver *dev_drv, int win_id)
3796 {
3797         struct lcdc_device *lcdc_dev = container_of(dev_drv,
3798                                                     struct lcdc_device, driver);
3799         spin_lock(&lcdc_dev->reg_lock);
3800         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_DIRECT_PATCH_SEL,
3801                      v_DIRECT_PATCH_SEL(win_id));
3802         lcdc_cfg_done(lcdc_dev);
3803         spin_unlock(&lcdc_dev->reg_lock);
3804         return 0;
3805 }
3806
3807 static int rk3368_lcdc_dpi_status(struct rk_lcdc_driver *dev_drv)
3808 {
3809         struct lcdc_device *lcdc_dev =
3810             container_of(dev_drv, struct lcdc_device, driver);
3811         int ovl;
3812
3813         spin_lock(&lcdc_dev->reg_lock);
3814         ovl = lcdc_read_bit(lcdc_dev, SYS_CTRL, m_DIRECT_PATH_EN);
3815         spin_unlock(&lcdc_dev->reg_lock);
3816         return ovl;
3817 }
3818
3819 static int rk3368_lcdc_set_irq_to_cpu(struct rk_lcdc_driver *dev_drv,
3820                                       int enable)
3821 {
3822         struct lcdc_device *lcdc_dev =
3823             container_of(dev_drv, struct lcdc_device, driver);
3824         if (enable)
3825                 enable_irq(lcdc_dev->irq);
3826         else
3827                 disable_irq(lcdc_dev->irq);
3828         return 0;
3829 }
3830
3831 int rk3368_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
3832 {
3833         struct lcdc_device *lcdc_dev =
3834             container_of(dev_drv, struct lcdc_device, driver);
3835         u32 int_reg;
3836         int ret;
3837
3838         if (lcdc_dev->clk_on && (!dev_drv->suspend_flag)) {
3839                 int_reg = lcdc_readl(lcdc_dev, INTR_STATUS);
3840                 if (int_reg & m_LINE_FLAG0_INTR_STS) {
3841                         lcdc_dev->driver.frame_time.last_framedone_t =
3842                             lcdc_dev->driver.frame_time.framedone_t;
3843                         lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
3844                         lcdc_msk_reg(lcdc_dev, INTR_CLEAR,
3845                                      m_LINE_FLAG0_INTR_CLR,
3846                                      v_LINE_FLAG0_INTR_CLR(1));
3847                         ret = RK_LF_STATUS_FC;
3848                 } else {
3849                         ret = RK_LF_STATUS_FR;
3850                 }
3851         } else {
3852                 ret = RK_LF_STATUS_NC;
3853         }
3854
3855         return ret;
3856 }
3857
3858 static int rk3368_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
3859                                     unsigned int *dsp_addr)
3860 {
3861         struct lcdc_device *lcdc_dev =
3862             container_of(dev_drv, struct lcdc_device, driver);
3863         spin_lock(&lcdc_dev->reg_lock);
3864         if (lcdc_dev->clk_on) {
3865                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
3866                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_YRGB_MST);
3867                 dsp_addr[2] = lcdc_readl(lcdc_dev, WIN2_MST0);
3868                 dsp_addr[3] = lcdc_readl(lcdc_dev, WIN3_MST0);
3869         }
3870         spin_unlock(&lcdc_dev->reg_lock);
3871         return 0;
3872 }
3873
3874 static struct lcdc_cabc_mode cabc_mode[4] = {
3875       /* calc,     up,     down,   global_limit   */
3876         {5,    256,  256,   256},  /*mode 1   0*/
3877         {5,    258,  253,   277},  /*mode 2   15%*/
3878         {5,    259,  252,   330},  /*mode 3   40%*/
3879         {5,    267,  244,   400},  /*mode 4   60%*/
3880 };
3881
3882 static int rk3368_lcdc_set_dsp_cabc(struct rk_lcdc_driver *dev_drv, int mode)
3883 {
3884         struct lcdc_device *lcdc_dev =
3885             container_of(dev_drv, struct lcdc_device, driver);
3886         struct rk_screen *screen = dev_drv->cur_screen;
3887         u32 total_pixel, calc_pixel, stage_up, stage_down;
3888         u32 pixel_num, global_su;
3889         u32 stage_up_rec, stage_down_rec, global_su_rec, gamma_global_su_rec;
3890         u32 mask = 0, val = 0, cabc_en = 0;
3891         int *cabc_lut = NULL;
3892
3893         if (!screen->cabc_lut) {
3894                 pr_err("screen cabc lut not config, so not open cabc\n");
3895                 return 0;
3896         } else {
3897                 cabc_lut = screen->cabc_lut;
3898         }
3899
3900         dev_drv->cabc_mode = mode;
3901         cabc_en = (mode > 0) ? 1 : 0;
3902
3903         if (cabc_en == 0) {
3904                 spin_lock(&lcdc_dev->reg_lock);
3905                 if (lcdc_dev->clk_on) {
3906                         lcdc_msk_reg(lcdc_dev, CABC_CTRL0,
3907                                      m_CABC_EN, v_CABC_EN(0));
3908                         lcdc_cfg_done(lcdc_dev);
3909                 }
3910                 spin_unlock(&lcdc_dev->reg_lock);
3911                 return 0;
3912         }
3913
3914         total_pixel = screen->mode.xres * screen->mode.yres;
3915         pixel_num = 1000 - (cabc_mode[mode - 1].pixel_num);
3916         calc_pixel = (total_pixel * pixel_num) / 1000;
3917         stage_up = cabc_mode[mode - 1].stage_up;
3918         stage_down = cabc_mode[mode - 1].stage_down;
3919         global_su = cabc_mode[mode - 1].global_su;
3920
3921         stage_up_rec = 256 * 256 / stage_up;
3922         stage_down_rec = 256 * 256 / stage_down;
3923         global_su_rec = (256 * 256 / global_su) - 1;
3924         gamma_global_su_rec = cabc_lut[global_su_rec];
3925
3926         spin_lock(&lcdc_dev->reg_lock);
3927         if (lcdc_dev->clk_on) {
3928                 mask = m_CABC_CALC_PIXEL_NUM | m_CABC_EN;
3929                 val = v_CABC_CALC_PIXEL_NUM(calc_pixel) |
3930                         v_CABC_EN(cabc_en);
3931                 lcdc_msk_reg(lcdc_dev, CABC_CTRL0, mask, val);
3932
3933                 mask = m_CABC_TOTAL_PIXEL_NUM | m_CABC_LUT_EN;
3934                 val = v_CABC_TOTAL_PIXEL_NUM(total_pixel) | v_CABC_LUT_EN(1);
3935                 lcdc_msk_reg(lcdc_dev, CABC_CTRL1, mask, val);
3936
3937                 mask = m_CABC_STAGE_UP | m_CABC_STAGE_UP_REC |
3938                     m_CABC_GLOBAL_SU_LIMIT_EN | m_CABC_GLOBAL_SU_REC;
3939                 val = v_CABC_STAGE_UP(stage_up) |
3940                     v_CABC_STAGE_UP_REC(stage_up_rec) |
3941                     v_CABC_GLOBAL_SU_LIMIT_EN(1) |
3942                     v_CABC_GLOBAL_SU_REC(gamma_global_su_rec);
3943                 lcdc_msk_reg(lcdc_dev, CABC_CTRL2, mask, val);
3944
3945                 mask = m_CABC_STAGE_DOWN | m_CABC_STAGE_DOWN_REC |
3946                     m_CABC_GLOBAL_SU;
3947                 val = v_CABC_STAGE_DOWN(stage_down) |
3948                     v_CABC_STAGE_DOWN_REC(stage_down_rec) |
3949                     v_CABC_GLOBAL_SU(global_su);
3950                 lcdc_msk_reg(lcdc_dev, CABC_CTRL3, mask, val);
3951                 lcdc_cfg_done(lcdc_dev);
3952         }
3953         spin_unlock(&lcdc_dev->reg_lock);
3954
3955         return 0;
3956 }
3957
3958 /*
3959         a:[-30~0]:
3960             sin_hue = sin(a)*256 +0x100;
3961             cos_hue = cos(a)*256;
3962         a:[0~30]
3963             sin_hue = sin(a)*256;
3964             cos_hue = cos(a)*256;
3965 */
3966 static int rk3368_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3967                                     bcsh_hue_mode mode)
3968 {
3969         struct lcdc_device *lcdc_dev =
3970             container_of(dev_drv, struct lcdc_device, driver);
3971         u32 val;
3972
3973         spin_lock(&lcdc_dev->reg_lock);
3974         if (lcdc_dev->clk_on) {
3975                 val = lcdc_readl(lcdc_dev, BCSH_H);
3976                 switch (mode) {
3977                 case H_SIN:
3978                         val &= m_BCSH_SIN_HUE;
3979                         break;
3980                 case H_COS:
3981                         val &= m_BCSH_COS_HUE;
3982                         val >>= 16;
3983                         break;
3984                 default:
3985                         break;
3986                 }
3987         }
3988         spin_unlock(&lcdc_dev->reg_lock);
3989
3990         return val;
3991 }
3992
3993 static int rk3368_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
3994                                     int sin_hue, int cos_hue)
3995 {
3996         struct lcdc_device *lcdc_dev =
3997             container_of(dev_drv, struct lcdc_device, driver);
3998         u32 mask, val;
3999
4000         spin_lock(&lcdc_dev->reg_lock);
4001         if (lcdc_dev->clk_on) {
4002                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
4003                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
4004                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
4005                 lcdc_cfg_done(lcdc_dev);
4006         }
4007         spin_unlock(&lcdc_dev->reg_lock);
4008
4009         return 0;
4010 }
4011
4012 static int rk3368_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4013                                     bcsh_bcs_mode mode, int value)
4014 {
4015         struct lcdc_device *lcdc_dev =
4016             container_of(dev_drv, struct lcdc_device, driver);
4017         u32 mask, val;
4018
4019         spin_lock(&lcdc_dev->reg_lock);
4020         if (lcdc_dev->clk_on) {
4021                 switch (mode) {
4022                 case BRIGHTNESS:
4023                         /*from 0 to 255,typical is 128 */
4024                         if (value < 0x80)
4025                                 value += 0x80;
4026                         else if (value >= 0x80)
4027                                 value = value - 0x80;
4028                         mask = m_BCSH_BRIGHTNESS;
4029                         val = v_BCSH_BRIGHTNESS(value);
4030                         break;
4031                 case CONTRAST:
4032                         /*from 0 to 510,typical is 256 */
4033                         mask = m_BCSH_CONTRAST;
4034                         val = v_BCSH_CONTRAST(value);
4035                         break;
4036                 case SAT_CON:
4037                         /*from 0 to 1015,typical is 256 */
4038                         mask = m_BCSH_SAT_CON;
4039                         val = v_BCSH_SAT_CON(value);
4040                         break;
4041                 default:
4042                         break;
4043                 }
4044                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
4045                 lcdc_cfg_done(lcdc_dev);
4046         }
4047         spin_unlock(&lcdc_dev->reg_lock);
4048         return val;
4049 }
4050
4051 static int rk3368_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
4052                                     bcsh_bcs_mode mode)
4053 {
4054         struct lcdc_device *lcdc_dev =
4055             container_of(dev_drv, struct lcdc_device, driver);
4056         u32 val;
4057
4058         spin_lock(&lcdc_dev->reg_lock);
4059         if (lcdc_dev->clk_on) {
4060                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
4061                 switch (mode) {
4062                 case BRIGHTNESS:
4063                         val &= m_BCSH_BRIGHTNESS;
4064                         if (val > 0x80)
4065                                 val -= 0x80;
4066                         else
4067                                 val += 0x80;
4068                         break;
4069                 case CONTRAST:
4070                         val &= m_BCSH_CONTRAST;
4071                         val >>= 8;
4072                         break;
4073                 case SAT_CON:
4074                         val &= m_BCSH_SAT_CON;
4075                         val >>= 20;
4076                         break;
4077                 default:
4078                         break;
4079                 }
4080         }
4081         spin_unlock(&lcdc_dev->reg_lock);
4082         return val;
4083 }
4084
4085 static int rk3368_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
4086 {
4087         struct lcdc_device *lcdc_dev =
4088             container_of(dev_drv, struct lcdc_device, driver);
4089         u32 mask, val;
4090
4091         spin_lock(&lcdc_dev->reg_lock);
4092         if (lcdc_dev->clk_on) {
4093                 if (open) {
4094                         lcdc_writel(lcdc_dev, BCSH_COLOR_BAR, 0x1);
4095                         lcdc_writel(lcdc_dev, BCSH_BCS, 0xd0010000);
4096                         lcdc_writel(lcdc_dev, BCSH_H, 0x01000000);
4097                         dev_drv->bcsh.enable = 1;
4098                 } else {
4099                         mask = m_BCSH_EN;
4100                         val = v_BCSH_EN(0);
4101                         lcdc_msk_reg(lcdc_dev, BCSH_COLOR_BAR, mask, val);
4102                         dev_drv->bcsh.enable = 0;
4103                 }
4104                 rk3368_lcdc_bcsh_path_sel(dev_drv);
4105                 lcdc_cfg_done(lcdc_dev);
4106         }
4107         spin_unlock(&lcdc_dev->reg_lock);
4108         return 0;
4109 }
4110
4111 static int rk3368_lcdc_set_bcsh(struct rk_lcdc_driver *dev_drv, bool enable)
4112 {
4113         if (!enable || !dev_drv->bcsh.enable) {
4114                 rk3368_lcdc_open_bcsh(dev_drv, false);
4115                 return 0;
4116         }
4117
4118         if (dev_drv->bcsh.brightness <= 255 ||
4119             dev_drv->bcsh.contrast <= 510 ||
4120             dev_drv->bcsh.sat_con <= 1015 ||
4121             (dev_drv->bcsh.sin_hue <= 511 && dev_drv->bcsh.cos_hue <= 511)) {
4122                 rk3368_lcdc_open_bcsh(dev_drv, true);
4123                 if (dev_drv->bcsh.brightness <= 255)
4124                         rk3368_lcdc_set_bcsh_bcs(dev_drv, BRIGHTNESS,
4125                                                  dev_drv->bcsh.brightness);
4126                 if (dev_drv->bcsh.contrast <= 510)
4127                         rk3368_lcdc_set_bcsh_bcs(dev_drv, CONTRAST,
4128                                                  dev_drv->bcsh.contrast);
4129                 if (dev_drv->bcsh.sat_con <= 1015)
4130                         rk3368_lcdc_set_bcsh_bcs(dev_drv, SAT_CON,
4131                                                  dev_drv->bcsh.sat_con);
4132                 if (dev_drv->bcsh.sin_hue <= 511 &&
4133                     dev_drv->bcsh.cos_hue <= 511)
4134                         rk3368_lcdc_set_bcsh_hue(dev_drv,
4135                                                  dev_drv->bcsh.sin_hue,
4136                                                  dev_drv->bcsh.cos_hue);
4137         }
4138         return 0;
4139 }
4140
4141 static int rk3368_lcdc_dsp_black(struct rk_lcdc_driver *dev_drv, int enable)
4142 {
4143         struct lcdc_device *lcdc_dev =
4144             container_of(dev_drv, struct lcdc_device, driver);
4145
4146         if (enable) {
4147                 spin_lock(&lcdc_dev->reg_lock);
4148                 if (likely(lcdc_dev->clk_on)) {
4149                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4150                                      v_DSP_BLACK_EN(1));
4151                         lcdc_cfg_done(lcdc_dev);
4152                 }
4153                 spin_unlock(&lcdc_dev->reg_lock);
4154         } else {
4155                 spin_lock(&lcdc_dev->reg_lock);
4156                 if (likely(lcdc_dev->clk_on)) {
4157                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_DSP_BLACK_EN,
4158                                      v_DSP_BLACK_EN(0));
4159
4160                         lcdc_cfg_done(lcdc_dev);
4161                 }
4162                 spin_unlock(&lcdc_dev->reg_lock);
4163         }
4164
4165         return 0;
4166 }
4167
4168
4169 static int rk3368_lcdc_backlight_close(struct rk_lcdc_driver *dev_drv,
4170                                        int enable)
4171 {
4172         struct lcdc_device *lcdc_dev =
4173             container_of(dev_drv, struct lcdc_device, driver);
4174
4175         rk3368_lcdc_get_backlight_device(dev_drv);
4176
4177         if (enable) {
4178                 /* close the backlight */
4179                 if (lcdc_dev->backlight) {
4180                         lcdc_dev->backlight->props.power = FB_BLANK_POWERDOWN;
4181                         backlight_update_status(lcdc_dev->backlight);
4182                 }
4183                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
4184                         dev_drv->trsm_ops->disable();
4185         } else {
4186                 if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
4187                         dev_drv->trsm_ops->enable();
4188                 msleep(100);
4189                 /* open the backlight */
4190                 if (lcdc_dev->backlight) {
4191                         lcdc_dev->backlight->props.power = FB_BLANK_UNBLANK;
4192                         backlight_update_status(lcdc_dev->backlight);
4193                 }
4194         }
4195
4196         return 0;
4197 }
4198
4199 static int rk3368_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
4200                                     struct overscan *overscan)
4201 {
4202         rk3368_lcdc_post_cfg(dev_drv);
4203
4204         return 0;
4205 }
4206
4207 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
4208         .open = rk3368_lcdc_open,
4209         .win_direct_en = rk3368_lcdc_win_direct_en,
4210         .load_screen = rk3368_load_screen,
4211         .get_dspbuf_info = rk3368_get_dspbuf_info,
4212         .post_dspbuf = rk3368_post_dspbuf,
4213         .set_par = rk3368_lcdc_set_par,
4214         .pan_display = rk3368_lcdc_pan_display,
4215         .direct_set_addr = rk3368_lcdc_direct_set_win_addr,
4216         /*.lcdc_reg_update = rk3368_lcdc_reg_update,*/
4217         .blank = rk3368_lcdc_blank,
4218         .ioctl = rk3368_lcdc_ioctl,
4219         .suspend = rk3368_lcdc_early_suspend,
4220         .resume = rk3368_lcdc_early_resume,
4221         .get_win_state = rk3368_lcdc_get_win_state,
4222         .ovl_mgr = rk3368_lcdc_ovl_mgr,
4223         .get_disp_info = rk3368_lcdc_get_disp_info,
4224         .fps_mgr = rk3368_lcdc_fps_mgr,
4225         .fb_get_win_id = rk3368_lcdc_get_win_id,
4226         .fb_win_remap = rk3368_fb_win_remap,
4227         .set_dsp_lut = rk3368_lcdc_set_lut,
4228         .set_cabc_lut = rk3368_set_cabc_lut,
4229         .poll_vblank = rk3368_lcdc_poll_vblank,
4230         .dpi_open = rk3368_lcdc_dpi_open,
4231         .dpi_win_sel = rk3368_lcdc_dpi_win_sel,
4232         .dpi_status = rk3368_lcdc_dpi_status,
4233         .get_dsp_addr = rk3368_lcdc_get_dsp_addr,
4234         .set_dsp_cabc = rk3368_lcdc_set_dsp_cabc,
4235         .set_dsp_bcsh_hue = rk3368_lcdc_set_bcsh_hue,
4236         .set_dsp_bcsh_bcs = rk3368_lcdc_set_bcsh_bcs,
4237         .get_dsp_bcsh_hue = rk3368_lcdc_get_bcsh_hue,
4238         .get_dsp_bcsh_bcs = rk3368_lcdc_get_bcsh_bcs,
4239         .open_bcsh = rk3368_lcdc_open_bcsh,
4240         .dump_reg = rk3368_lcdc_reg_dump,
4241         .cfg_done = rk3368_lcdc_config_done,
4242         .set_irq_to_cpu = rk3368_lcdc_set_irq_to_cpu,
4243         .dsp_black = rk3368_lcdc_dsp_black,
4244         .backlight_close = rk3368_lcdc_backlight_close,
4245         .mmu_en    = rk3368_lcdc_mmu_en,
4246         .set_overscan   = rk3368_lcdc_set_overscan,
4247 };
4248
4249 #ifdef LCDC_IRQ_EMPTY_DEBUG
4250 static int rk3368_lcdc_parse_irq(struct lcdc_device *lcdc_dev,
4251                                  unsigned int intr_status)
4252 {
4253         if (intr_status & m_WIN0_EMPTY_INTR_STS) {
4254                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN0_EMPTY_INTR_CLR,
4255                              v_WIN0_EMPTY_INTR_CLR(1));
4256                 dev_warn(lcdc_dev->dev, "win0 empty irq!");
4257         } else if (intr_status & m_WIN1_EMPTY_INTR_STS) {
4258                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN1_EMPTY_INTR_CLR,
4259                              v_WIN1_EMPTY_INTR_CLR(1));
4260                 dev_warn(lcdc_dev->dev, "win1 empty irq!");
4261         } else if (intr_status & m_WIN2_EMPTY_INTR_STS) {
4262                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN2_EMPTY_INTR_CLR,
4263                              v_WIN2_EMPTY_INTR_CLR(1));
4264                 dev_warn(lcdc_dev->dev, "win2 empty irq!");
4265         } else if (intr_status & m_WIN3_EMPTY_INTR_STS) {
4266                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_WIN3_EMPTY_INTR_CLR,
4267                              v_WIN3_EMPTY_INTR_CLR(1));
4268                 dev_warn(lcdc_dev->dev, "win3 empty irq!");
4269         } else if (intr_status & m_HWC_EMPTY_INTR_STS) {
4270                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_HWC_EMPTY_INTR_CLR,
4271                              v_HWC_EMPTY_INTR_CLR(1));
4272                 dev_warn(lcdc_dev->dev, "HWC empty irq!");
4273         } else if (intr_status & m_POST_BUF_EMPTY_INTR_STS) {
4274                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_POST_BUF_EMPTY_INTR_CLR,
4275                              v_POST_BUF_EMPTY_INTR_CLR(1));
4276                 dev_warn(lcdc_dev->dev, "post buf empty irq!");
4277         } else if (intr_status & m_PWM_GEN_INTR_STS) {
4278                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_PWM_GEN_INTR_CLR,
4279                              v_PWM_GEN_INTR_CLR(1));
4280                 dev_warn(lcdc_dev->dev, "PWM gen irq!");
4281         }
4282         return 0;
4283 }
4284 #endif
4285
4286 static irqreturn_t rk3368_lcdc_isr(int irq, void *dev_id)
4287 {
4288         struct lcdc_device *lcdc_dev = (struct lcdc_device *)dev_id;
4289         ktime_t timestamp = ktime_get();
4290         u32 intr_status;
4291
4292         intr_status = lcdc_readl(lcdc_dev, INTR_STATUS);
4293
4294         if (intr_status & m_FS_INTR_STS) {
4295                 timestamp = ktime_get();
4296                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_INTR_CLR,
4297                              v_FS_INTR_CLR(1));
4298                 /*if(lcdc_dev->driver.wait_fs){ */
4299                 if (0) {
4300                         spin_lock(&(lcdc_dev->driver.cpl_lock));
4301                         complete(&(lcdc_dev->driver.frame_done));
4302                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
4303                 }
4304 #ifdef CONFIG_DRM_ROCKCHIP
4305                 lcdc_dev->driver.irq_call_back(&lcdc_dev->driver);
4306 #endif
4307                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
4308                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
4309
4310         } else if (intr_status & m_LINE_FLAG0_INTR_STS) {
4311                 lcdc_dev->driver.frame_time.last_framedone_t =
4312                     lcdc_dev->driver.frame_time.framedone_t;
4313                 lcdc_dev->driver.frame_time.framedone_t = cpu_clock(0);
4314                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG0_INTR_CLR,
4315                              v_LINE_FLAG0_INTR_CLR(1));
4316         } else if (intr_status & m_LINE_FLAG1_INTR_STS) {
4317                 /*line flag1 */
4318                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_LINE_FLAG1_INTR_CLR,
4319                              v_LINE_FLAG1_INTR_CLR(1));
4320         } else if (intr_status & m_FS_NEW_INTR_STS) {
4321                 /*new frame start */
4322                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_FS_NEW_INTR_CLR,
4323                              v_FS_NEW_INTR_CLR(1));
4324         } else if (intr_status & m_BUS_ERROR_INTR_STS) {
4325                 lcdc_msk_reg(lcdc_dev, INTR_CLEAR, m_BUS_ERROR_INTR_CLR,
4326                              v_BUS_ERROR_INTR_CLR(1));
4327                 dev_warn(lcdc_dev->dev, "bus error!");
4328         }
4329
4330         /* for win empty debug */
4331 #ifdef LCDC_IRQ_EMPTY_DEBUG
4332         rk3368_lcdc_parse_irq(lcdc_dev, intr_status);
4333 #endif
4334         return IRQ_HANDLED;
4335 }
4336
4337 #if defined(CONFIG_PM)
4338 static int rk3368_lcdc_suspend(struct platform_device *pdev, pm_message_t state)
4339 {
4340         return 0;
4341 }
4342
4343 static int rk3368_lcdc_resume(struct platform_device *pdev)
4344 {
4345         return 0;
4346 }
4347 #else
4348 #define rk3368_lcdc_suspend NULL
4349 #define rk3368_lcdc_resume  NULL
4350 #endif
4351
4352 static int rk3368_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
4353 {
4354         struct device_node *np = lcdc_dev->dev->of_node;
4355         struct rk_lcdc_driver *dev_drv = &lcdc_dev->driver;
4356         int val;
4357
4358         if (of_property_read_u32(np, "rockchip,prop", &val))
4359                 lcdc_dev->prop = PRMRY; /*default set it as primary */
4360         else
4361                 lcdc_dev->prop = val;
4362
4363         if (of_property_read_u32(np, "rockchip,mirror", &val))
4364                 dev_drv->rotate_mode = NO_MIRROR;
4365         else
4366                 dev_drv->rotate_mode = val;
4367
4368         if (of_property_read_u32(np, "rockchip,cabc_mode", &val))
4369                 dev_drv->cabc_mode = 0; /* default set close cabc */
4370         else
4371                 dev_drv->cabc_mode = val;
4372
4373         if (of_property_read_u32(np, "rockchip,pwr18", &val))
4374                 /*default set it as 3.xv power supply */
4375                 lcdc_dev->pwr18 = false;
4376         else
4377                 lcdc_dev->pwr18 = (val ? true : false);
4378
4379         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
4380                 dev_drv->fb_win_map = FB_DEFAULT_ORDER;
4381         else
4382                 dev_drv->fb_win_map = val;
4383
4384         if (of_property_read_u32(np, "rockchip,bcsh-en", &val))
4385                 dev_drv->bcsh.enable = false;
4386         else
4387                 dev_drv->bcsh.enable = (val ? true : false);
4388
4389         if (of_property_read_u32(np, "rockchip,brightness", &val))
4390                 dev_drv->bcsh.brightness = 0xffff;
4391         else
4392                 dev_drv->bcsh.brightness = val;
4393
4394         if (of_property_read_u32(np, "rockchip,contrast", &val))
4395                 dev_drv->bcsh.contrast = 0xffff;
4396         else
4397                 dev_drv->bcsh.contrast = val;
4398
4399         if (of_property_read_u32(np, "rockchip,sat-con", &val))
4400                 dev_drv->bcsh.sat_con = 0xffff;
4401         else
4402                 dev_drv->bcsh.sat_con = val;
4403
4404         if (of_property_read_u32(np, "rockchip,hue", &val)) {
4405                 dev_drv->bcsh.sin_hue = 0xffff;
4406                 dev_drv->bcsh.cos_hue = 0xffff;
4407         } else {
4408                 dev_drv->bcsh.sin_hue = val & 0xff;
4409                 dev_drv->bcsh.cos_hue = (val >> 8) & 0xff;
4410         }
4411
4412 #if defined(CONFIG_ROCKCHIP_IOMMU)
4413         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
4414                 dev_drv->iommu_enabled = 0;
4415         else
4416                 dev_drv->iommu_enabled = val;
4417 #else
4418         dev_drv->iommu_enabled = 0;
4419 #endif
4420         return 0;
4421 }
4422
4423 static int rk3368_lcdc_probe(struct platform_device *pdev)
4424 {
4425         struct lcdc_device *lcdc_dev = NULL;
4426         struct rk_lcdc_driver *dev_drv;
4427         struct device *dev = &pdev->dev;
4428         struct resource *res;
4429         struct device_node *np = pdev->dev.of_node;
4430         int prop;
4431         int ret = 0;
4432
4433         /*if the primary lcdc has not registered ,the extend
4434            lcdc register later */
4435         of_property_read_u32(np, "rockchip,prop", &prop);
4436         if (prop == EXTEND) {
4437                 if (!is_prmry_rk_lcdc_registered())
4438                         return -EPROBE_DEFER;
4439         }
4440         lcdc_dev = devm_kzalloc(dev, sizeof(struct lcdc_device), GFP_KERNEL);
4441         if (!lcdc_dev) {
4442                 dev_err(&pdev->dev, "rk3368 lcdc device kmalloc fail!");
4443                 return -ENOMEM;
4444         }
4445         platform_set_drvdata(pdev, lcdc_dev);
4446         lcdc_dev->dev = dev;
4447         rk3368_lcdc_parse_dt(lcdc_dev);
4448         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4449         lcdc_dev->reg_phy_base = res->start;
4450         lcdc_dev->len = resource_size(res);
4451         lcdc_dev->regs = devm_ioremap_resource(dev, res);
4452         if (IS_ERR(lcdc_dev->regs))
4453                 return PTR_ERR(lcdc_dev->regs);
4454         else
4455                 dev_info(dev, "lcdc_dev->regs=0x%lx\n", (long)lcdc_dev->regs);
4456
4457         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
4458         if (IS_ERR(lcdc_dev->regsbak))
4459                 return PTR_ERR(lcdc_dev->regsbak);
4460         lcdc_dev->dsp_lut_addr_base = (lcdc_dev->regs + GAMMA_LUT_ADDR);
4461         lcdc_dev->cabc_lut_addr_base = (lcdc_dev->regs + CABC_GAMMA_LUT_ADDR);
4462         lcdc_dev->grf_base =
4463                 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
4464         if (IS_ERR(lcdc_dev->grf_base)) {
4465                 dev_err(&pdev->dev, "can't find lcdc grf property\n");
4466                 return PTR_ERR(lcdc_dev->grf_base);
4467         }
4468         lcdc_dev->pmugrf_base =
4469                 syscon_regmap_lookup_by_phandle(np, "rockchip,pmugrf");
4470         if (IS_ERR(lcdc_dev->pmugrf_base)) {
4471                 dev_err(&pdev->dev, "can't find lcdc pmu grf property\n");
4472                 return PTR_ERR(lcdc_dev->pmugrf_base);
4473         }
4474         lcdc_dev->id = 0;
4475         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
4476         dev_drv = &lcdc_dev->driver;
4477         dev_drv->dev = dev;
4478         dev_drv->prop = prop;
4479         dev_drv->id = lcdc_dev->id;
4480         dev_drv->ops = &lcdc_drv_ops;
4481         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
4482         spin_lock_init(&lcdc_dev->reg_lock);
4483
4484         lcdc_dev->irq = platform_get_irq(pdev, 0);
4485         if (lcdc_dev->irq < 0) {
4486                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
4487                         lcdc_dev->id);
4488                 return -ENXIO;
4489         }
4490
4491         ret = devm_request_irq(dev, lcdc_dev->irq, rk3368_lcdc_isr,
4492                                IRQF_DISABLED | IRQF_SHARED,
4493                                dev_name(dev), lcdc_dev);
4494         if (ret) {
4495                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
4496                         lcdc_dev->irq, ret);
4497                 return ret;
4498         }
4499
4500         if (dev_drv->iommu_enabled) {
4501                 if (lcdc_dev->id == 0) {
4502                         strcpy(dev_drv->mmu_dts_name,
4503                                VOPB_IOMMU_COMPATIBLE_NAME);
4504                 } else {
4505                         strcpy(dev_drv->mmu_dts_name,
4506                                VOPL_IOMMU_COMPATIBLE_NAME);
4507                 }
4508         }
4509
4510         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
4511         if (ret < 0) {
4512                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
4513                 return ret;
4514         }
4515         lcdc_dev->screen = dev_drv->screen0;
4516         dev_info(dev, "lcdc%d probe ok, iommu %s\n",
4517                  lcdc_dev->id, dev_drv->iommu_enabled ? "enabled" : "disabled");
4518
4519         return 0;
4520 }
4521
4522 static int rk3368_lcdc_remove(struct platform_device *pdev)
4523 {
4524         return 0;
4525 }
4526
4527 static void rk3368_lcdc_shutdown(struct platform_device *pdev)
4528 {
4529         struct lcdc_device *lcdc_dev = platform_get_drvdata(pdev);
4530
4531         rk3368_lcdc_early_suspend(&lcdc_dev->driver);
4532         rk3368_lcdc_deint(lcdc_dev);
4533 }
4534
4535 #if defined(CONFIG_OF)
4536 static const struct of_device_id rk3368_lcdc_dt_ids[] = {
4537         {.compatible = "rockchip,rk3368-lcdc",},
4538         {}
4539 };
4540 #endif
4541
4542 static struct platform_driver rk3368_lcdc_driver = {
4543         .probe = rk3368_lcdc_probe,
4544         .remove = rk3368_lcdc_remove,
4545         .driver = {
4546                    .name = "rk3368-lcdc",
4547                    .owner = THIS_MODULE,
4548                    .of_match_table = of_match_ptr(rk3368_lcdc_dt_ids),
4549                    },
4550         .suspend = rk3368_lcdc_suspend,
4551         .resume = rk3368_lcdc_resume,
4552         .shutdown = rk3368_lcdc_shutdown,
4553 };
4554
4555 static int __init rk3368_lcdc_module_init(void)
4556 {
4557         return platform_driver_register(&rk3368_lcdc_driver);
4558 }
4559
4560 static void __exit rk3368_lcdc_module_exit(void)
4561 {
4562         platform_driver_unregister(&rk3368_lcdc_driver);
4563 }
4564
4565 fs_initcall(rk3368_lcdc_module_init);
4566 module_exit(rk3368_lcdc_module_exit);