1 #ifndef _RGA_DRIVER_H_
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2 #define _RGA_DRIVER_H_
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4 #include <linux/mutex.h>
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6 #define RGA_BLIT_SYNC 0x5017
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7 #define RGA_BLIT_ASYNC 0x5018
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8 #define RGA_FLUSH 0x5019
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9 #define RGA_GET_RESULT 0x501a
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12 #define RGA_REG_CTRL_LEN 0x8 /* 8 */
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13 #define RGA_REG_CMD_LEN 0x1c /* 28 */
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14 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */
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16 #define RGA_OUT_OF_RESOURCES -10
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17 #define RGA_MALLOC_ERROR -11
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20 #define rgaIS_ERROR(status) (status < 0)
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21 #define rgaNO_ERROR(status) (status >= 0)
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22 #define rgaIS_SUCCESS(status) (status == 0)
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26 /* RGA process mode enum */
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30 color_palette_mode = 0x1,
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31 color_fill_mode = 0x2,
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32 line_point_drawing_mode = 0x3,
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33 blur_sharp_filter_mode = 0x4,
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34 pre_scaling_mode = 0x5,
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35 update_palette_table_mode = 0x6,
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36 update_patten_buff_mode = 0x7,
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42 rop_enable_mask = 0x2,
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43 dither_enable_mask = 0x8,
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44 fading_enable_mask = 0x10,
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45 PD_enbale_mask = 0x20,
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50 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */
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51 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */
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52 yuv2rgb_mode2 = 0x2, /* BT.709 */
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56 /* RGA rotate mode */
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59 rotate_mode0 = 0x0, /* no rotate */
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60 rotate_mode1 = 0x1, /* rotate */
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61 rotate_mode2 = 0x2, /* x_mirror */
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62 rotate_mode3 = 0x3, /* y_mirror */
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67 color_palette_mode0 = 0x0, /* 1K */
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68 color_palette_mode1 = 0x1, /* 2K */
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69 color_palette_mode2 = 0x2, /* 4K */
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70 color_palette_mode3 = 0x3, /* 8K */
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76 // Alpha Red Green Blue
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77 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888
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78 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888
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79 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888
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80 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888
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81 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565
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82 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551
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83 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444
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84 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888
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89 RK_FORMAT_RGBA_8888 = 0x0,
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90 RK_FORMAT_RGBX_8888 = 0x1,
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91 RK_FORMAT_RGB_888 = 0x2,
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92 RK_FORMAT_BGRA_8888 = 0x3,
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93 RK_FORMAT_RGB_565 = 0x4,
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94 RK_FORMAT_RGBA_5551 = 0x5,
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95 RK_FORMAT_RGBA_4444 = 0x6,
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96 RK_FORMAT_BGR_888 = 0x7,
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98 RK_FORMAT_YCbCr_422_SP = 0x8,
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99 RK_FORMAT_YCbCr_422_P = 0x9,
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100 RK_FORMAT_YCbCr_420_SP = 0xa,
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101 RK_FORMAT_YCbCr_420_P = 0xb,
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103 RK_FORMAT_YCrCb_422_SP = 0xc,
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104 RK_FORMAT_YCrCb_422_P = 0xd,
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105 RK_FORMAT_YCrCb_420_SP = 0xe,
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106 RK_FORMAT_YCrCb_420_P = 0xf,
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108 RK_FORMAT_BPP1 = 0x10,
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109 RK_FORMAT_BPP2 = 0x11,
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110 RK_FORMAT_BPP4 = 0x12,
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111 RK_FORMAT_BPP8 = 0x13,
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115 typedef struct rga_img_info_t
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117 unsigned int yrgb_addr; /* yrgb mem addr */
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118 unsigned int uv_addr; /* cb/cr mem addr */
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119 unsigned int v_addr; /* cr mem addr */
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120 unsigned int format; //definition by RK_FORMAT
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122 unsigned short act_w;
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123 unsigned short act_h;
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124 unsigned short x_offset;
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125 unsigned short y_offset;
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127 unsigned short vir_w;
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128 unsigned short vir_h;
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130 unsigned short endian_mode; //for BPP
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131 unsigned short alpha_swap;
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136 typedef struct mdp_img_act
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138 unsigned short w; // width
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139 unsigned short h; // height
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140 short x_off; // x offset for the vir
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141 short y_off; // y offset for the vir
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147 typedef struct RANGE
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149 unsigned short min;
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150 unsigned short max;
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154 typedef struct POINT
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161 typedef struct RECT
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163 unsigned short xmin;
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164 unsigned short xmax; // width - 1
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165 unsigned short ymin;
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166 unsigned short ymax; // height - 1
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180 unsigned char mmu_en;
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181 uint32_t base_addr;
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182 uint32_t mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size*/
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188 typedef struct COLOR_FILL
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199 //u8 cp_gr_saturation;
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203 typedef struct FADING
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213 typedef struct line_draw_t
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215 POINT start_point; /* LineDraw_start_point */
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216 POINT end_point; /* LineDraw_end_point */
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217 uint32_t color; /* LineDraw_color */
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218 uint32_t flag; /* (enum) LineDrawing mode sel */
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219 uint32_t line_width; /* range 1~16 */
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226 uint8_t render_mode; /* (enum) process mode sel */
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228 rga_img_info_t src; /* src image info */
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229 rga_img_info_t dst; /* dst image info */
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230 rga_img_info_t pat; /* patten image info */
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232 uint32_t rop_mask_addr; /* rop4 mask addr */
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233 uint32_t LUT_addr; /* LUT addr */
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235 RECT clip; /* dst clip window default value is dst_vir */
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236 /* value from [0, w-1] / [0, h-1]*/
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238 int32_t sina; /* dst angle default value 0 16.16 scan from table */
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239 int32_t cosa; /* dst angle default value 0 16.16 scan from table */
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241 uint16_t alpha_rop_flag; /* alpha rop process flag */
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242 /* ([0] = 1 alpha_rop_enable) */
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243 /* ([1] = 1 rop enable) */
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244 /* ([2] = 1 fading_enable) */
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245 /* ([3] = 1 PD_enable) */
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246 /* ([4] = 1 alpha cal_mode_sel) */
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247 /* ([5] = 1 dither_enable) */
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248 /* ([6] = 1 gradient fill mode sel) */
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249 /* ([7] = 1 AA_enable) */
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251 uint8_t scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */
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253 uint32_t color_key_max; /* color key max */
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254 uint32_t color_key_min; /* color key min */
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256 uint32_t fg_color; /* foreground color */
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257 uint32_t bg_color; /* background color */
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259 COLOR_FILL gr_color; /* color fill use gradient */
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261 line_draw_t line_draw_info;
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265 uint8_t PD_mode; /* porter duff alpha mode sel */
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267 uint8_t alpha_global_value; /* global alpha value */
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269 uint16_t rop_code; /* rop2/3/4 code scan from rop code table*/
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271 uint8_t bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type*/
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273 uint8_t palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp*/
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275 uint8_t yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */
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277 uint8_t endian_mode; /* 0/big endian 1/little endian*/
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279 uint8_t rotate_mode; /* (enum) rotate mode */
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280 /* 0x0, no rotate */
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282 /* 0x2, x_mirror */
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283 /* 0x3, y_mirror */
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285 uint8_t color_fill_mode; /* 0 solid color / 1 patten color */
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287 MMU mmu_info; /* mmu information */
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289 uint8_t alpha_rop_mode; /* ([0~1] alpha mode) */
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290 /* ([2~3] rop mode) */
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291 /* ([4] zero mode en) */
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292 /* ([5] dst alpha mode) */
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294 uint8_t src_trans_mode;
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298 typedef struct TILE_INFO
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302 uint16_t tile_x_num; /* x axis tile num / tile size is 8x8 pixel */
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303 uint16_t tile_y_num; /* y axis tile num */
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305 int16_t dst_x_tmp; /* dst pos x = (xstart - xoff) default value 0 */
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306 int16_t dst_y_tmp; /* dst pos y = (ystart - yoff) default value 0 */
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310 int16_t tile_start_x_coor;
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311 int16_t tile_start_y_coor;
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315 int32_t tile_temp_xstart;
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316 int32_t tile_temp_ystart;
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318 /* src tile incr */
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324 mdp_img_act dst_ctrl;
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331 * struct for process session which connect to rga
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333 * @author ZhangShengqin (2012-2-15)
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335 typedef struct rga_session {
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336 /* a linked list of data so we can access them for debugging */
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337 struct list_head list_session;
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338 /* a linked list of register data waiting for process */
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339 struct list_head waiting;
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340 /* a linked list of register data in processing */
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341 struct list_head running;
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342 /* all coommand this thread done */
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344 wait_queue_head_t wait;
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346 atomic_t task_running;
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351 rga_session *session;
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352 struct list_head session_link; /* link to rga service session */
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353 struct list_head status_link; /* link to register set list */
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354 uint32_t sys_reg[RGA_REG_CTRL_LEN];
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355 uint32_t cmd_reg[RGA_REG_CMD_LEN];
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356 uint32_t *MMU_base;
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357 atomic_t int_enable;
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362 typedef struct rga_service_info {
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364 struct timer_list timer; /* timer for power off */
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365 struct list_head waiting; /* link to link_reg in struct vpu_reg */
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366 struct list_head running; /* link to link_reg in struct vpu_reg */
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367 struct list_head done; /* link to link_reg in struct vpu_reg */
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368 struct list_head session; /* link to list_session in struct vpu_session */
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369 atomic_t total_running;
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371 struct rga_reg *reg;
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372 uint32_t cmd_buff[28*16];/* cmd_buff for rga */
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373 uint32_t *pre_scale_buf;
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374 atomic_t int_disable; /* 0 int enable 1 int disable */
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376 atomic_t src_format_swt;
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377 int last_prc_src_format;
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378 atomic_t rga_working;
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380 struct mutex mutex; // mutex
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381 } rga_service_info;
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385 #define RGA_BASE 0x10114000
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387 //General Registers
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388 #define RGA_SYS_CTRL 0x000
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389 #define RGA_CMD_CTRL 0x004
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390 #define RGA_CMD_ADDR 0x008
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391 #define RGA_STATUS 0x00c
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392 #define RGA_INT 0x010
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393 #define RGA_AXI_ID 0x014
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394 #define RGA_MMU_STA_CTRL 0x018
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395 #define RGA_MMU_STA 0x01c
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397 //Command code start
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398 #define RGA_MODE_CTRL 0x100
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400 //Source Image Registers
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401 #define RGA_SRC_Y_MST 0x104
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402 #define RGA_SRC_CB_MST 0x108
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403 #define RGA_MASK_READ_MST 0x108 //repeat
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404 #define RGA_SRC_CR_MST 0x10c
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405 #define RGA_SRC_VIR_INFO 0x110
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406 #define RGA_SRC_ACT_INFO 0x114
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407 #define RGA_SRC_X_PARA 0x118
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408 #define RGA_SRC_Y_PARA 0x11c
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409 #define RGA_SRC_TILE_XINFO 0x120
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410 #define RGA_SRC_TILE_YINFO 0x124
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411 #define RGA_SRC_TILE_H_INCR 0x128
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412 #define RGA_SRC_TILE_V_INCR 0x12c
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413 #define RGA_SRC_TILE_OFFSETX 0x130
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414 #define RGA_SRC_TILE_OFFSETY 0x134
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415 #define RGA_SRC_BG_COLOR 0x138
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416 #define RGA_SRC_FG_COLOR 0x13c
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417 #define RGA_LINE_DRAWING_COLOR 0x13c //repeat
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418 #define RGA_SRC_TR_COLOR0 0x140
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419 #define RGA_CP_GR_A 0x140 //repeat
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420 #define RGA_SRC_TR_COLOR1 0x144
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421 #define RGA_CP_GR_B 0x144 //repeat
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423 #define RGA_LINE_DRAW 0x148
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424 #define RGA_PAT_START_POINT 0x148 //repeat
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426 //Destination Image Registers
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427 #define RGA_DST_MST 0x14c
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428 #define RGA_LUT_MST 0x14c //repeat
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429 #define RGA_PAT_MST 0x14c //repeat
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430 #define RGA_LINE_DRAWING_MST 0x14c //repeat
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432 #define RGA_DST_VIR_INFO 0x150
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434 #define RGA_DST_CTR_INFO 0x154
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435 #define RGA_LINE_DRAW_XY_INFO 0x154 //repeat
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437 //Alpha/ROP Registers
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438 #define RGA_ALPHA_CON 0x158
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440 #define RGA_PAT_CON 0x15c
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441 #define RGA_DST_VIR_WIDTH_PIX 0x15c //repeat
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443 #define RGA_ROP_CON0 0x160
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444 #define RGA_CP_GR_G 0x160 //repeat
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445 #define RGA_PRESCL_CB_MST 0x160 //repeat
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447 #define RGA_ROP_CON1 0x164
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448 #define RGA_CP_GR_R 0x164 //repeat
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449 #define RGA_PRESCL_CR_MST 0x164 //repeat
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452 #define RGA_FADING_CON 0x168
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453 #define RGA_MMU_CTRL 0x168 //repeat
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455 #define RGA_MMU_TBL 0x16c //repeat
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458 #define RGA_BLIT_COMPLETE_EVENT 1
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463 #endif /*_RK29_IPP_DRIVER_H_*/
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