2 //#include <linux/kernel.h>
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3 #include <linux/memory.h>
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4 #include <linux/kernel.h>
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5 #include <linux/init.h>
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6 #include <linux/module.h>
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7 #include <linux/platform_device.h>
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8 #include <linux/sched.h>
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9 #include <linux/mutex.h>
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10 #include <linux/err.h>
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11 #include <linux/clk.h>
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12 #include <asm/delay.h>
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13 #include <linux/dma-mapping.h>
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14 #include <linux/delay.h>
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16 #include <linux/irq.h>
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17 #include <linux/interrupt.h>
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18 #include <mach/io.h>
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19 #include <mach/irqs.h>
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20 #include <linux/fs.h>
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21 #include <asm/uaccess.h>
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22 #include <linux/miscdevice.h>
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23 #include <linux/poll.h>
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24 #include <linux/delay.h>
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25 #include <linux/wait.h>
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26 #include <linux/syscalls.h>
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27 #include <linux/timer.h>
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28 #include <linux/time.h>
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29 #include <asm/cacheflush.h>
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30 #include <linux/slab.h>
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31 #include <linux/fb.h>
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32 #include <linux/wakelock.h>
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34 #include "rga_reg_info.h"
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35 #include "rga_rop.h"
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39 /*************************************************************
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41 RGA_pixel_width_init
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43 select pixel_width form data format
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48 **************************************************************/
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50 RGA_pixel_width_init(unsigned int format)
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52 unsigned char pixel_width;
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59 case RK_FORMAT_RGBA_8888 : pixel_width = 4; break;
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60 case RK_FORMAT_RGBX_8888 : pixel_width = 4; break;
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61 case RK_FORMAT_RGB_888 : pixel_width = 3; break;
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62 case RK_FORMAT_BGRA_8888 : pixel_width = 4; break;
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63 case RK_FORMAT_RGB_565 : pixel_width = 2; break;
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64 case RK_FORMAT_RGBA_5551 : pixel_width = 2; break;
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65 case RK_FORMAT_RGBA_4444 : pixel_width = 2; break;
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66 case RK_FORMAT_BGR_888 : pixel_width = 3; break;
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69 case RK_FORMAT_YCbCr_422_SP : pixel_width = 1; break;
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70 case RK_FORMAT_YCbCr_422_P : pixel_width = 1; break;
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71 case RK_FORMAT_YCbCr_420_SP : pixel_width = 1; break;
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72 case RK_FORMAT_YCbCr_420_P : pixel_width = 1; break;
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73 case RK_FORMAT_YCrCb_422_SP : pixel_width = 1; break;
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74 case RK_FORMAT_YCrCb_422_P : pixel_width = 1; break;
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75 case RK_FORMAT_YCrCb_420_SP : pixel_width = 1; break;
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76 case RK_FORMAT_YCrCb_420_P : pixel_width = 1; break;
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77 //case default : pixel_width = 0; break;
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83 /*************************************************************
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87 calculate dst act window position / width / height
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88 and set the tile struct
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93 **************************************************************/
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95 dst_ctrl_cal(const struct rga_req *msg, TILE_INFO *tile)
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97 u32 width = msg->dst.act_w;
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98 u32 height = msg->dst.act_h;
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99 s32 xoff = msg->dst.x_offset;
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100 s32 yoff = msg->dst.y_offset;
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102 s32 x0, y0, x1, y1, x2, y2;
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103 s32 x00,y00,x10,y10,x20,y20;
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104 s32 xx, xy, yx, yy;
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107 s32 xmax, xmin, ymax, ymin;
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109 s32 sina = msg->sina; /* 16.16 */
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110 s32 cosa = msg->cosa; /* 16.16 */
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112 xmax = xmin = ymax = ymin = 0;
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114 if((msg->rotate_mode == 0)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
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120 pos[3] = yoff + height - 1;
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122 pos[4] = xoff + width - 1;
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123 pos[5] = yoff + height - 1;
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125 pos[6] = xoff + width - 1;
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128 xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
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129 xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
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131 ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
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132 ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
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134 //printk("xmax = %d, xmin = %d, ymin = %d, ymax = %d\n", xmax, xmin, ymin, ymax);
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136 else if(msg->rotate_mode == 1)
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138 if((sina == 0) || (cosa == 0))
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140 if((sina == 0) && (cosa == -65536))
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143 pos[0] = xoff - width + 1;
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144 pos[1] = yoff - height + 1;
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146 pos[2] = xoff - width + 1;
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153 pos[7] = yoff - height + 1;
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155 else if((cosa == 0)&&(sina == 65536))
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158 pos[0] = xoff - height + 1;
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161 pos[2] = xoff - height + 1;
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162 pos[3] = yoff + width - 1;
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165 pos[5] = yoff + width - 1;
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170 else if((cosa == 0)&&(sina == -65536))
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174 pos[1] = yoff - width + 1;
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179 pos[4] = xoff + height - 1;
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182 pos[6] = xoff + height - 1;
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183 pos[7] = yoff - width + 1;
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192 pos[3] = yoff + height - 1;
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194 pos[4] = xoff + width - 1;
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195 pos[5] = yoff + height - 1;
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197 pos[6] = xoff + width - 1;
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201 xmax = MIN(MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmax);
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202 xmin = MAX(MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]), msg->clip.xmin);
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204 ymax = MIN(MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymax);
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205 ymin = MAX(MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]), msg->clip.ymin);
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218 y1 = height + yoff;
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221 y2 = height + yoff;
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226 pos[2] = x00 = (((x0 - xoff)*xx - (y0 - yoff)*xy)>>16) + xoff;
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227 pos[3] = y00 = (((x0 - xoff)*yx + (y0 - yoff)*yy)>>16) + yoff;
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229 pos[4] = x10 = (((x1 - xoff)*xx - (y1 - yoff)*xy)>>16) + xoff;
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230 pos[5] = y10 = (((x1 - xoff)*yx + (y1 - yoff)*yy)>>16) + yoff;
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232 pos[6] = x20 = (((x2 - xoff)*xx - (y2 - yoff)*xy)>>16) + xoff;
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233 pos[7] = y20 = (((x2 - xoff)*yx + (y2 - yoff)*yy)>>16) + yoff;
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235 xmax = MAX(MAX(MAX(x00, xoff), x10), x20) + 2;
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236 xmin = MIN(MIN(MIN(x00, xoff), x10), x20) - 1;
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238 ymax = MAX(MAX(MAX(y00, yoff), y10), y20) + 2;
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239 ymin = MIN(MIN(MIN(y00, yoff), y10), y20) - 1;
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241 xmax = MIN(xmax, msg->clip.xmax);
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242 xmin = MAX(xmin, msg->clip.xmin);
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244 ymax = MIN(ymax, msg->clip.ymax);
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245 ymin = MAX(ymin, msg->clip.ymin);
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247 //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
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251 if ((xmax < xmin) || (ymax < ymin)) {
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256 if ((xmin >= msg->dst.vir_w)||(xmax < 0)||(ymin >= msg->dst.vir_h)||(ymax < 0)) {
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257 xmin = xmax = ymin = ymax = 0;
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260 //printk("xmin = %d, xmax = %d, ymin = %d, ymax = %d\n", xmin, xmax, ymin, ymax);
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262 tile->dst_ctrl.w = (xmax - xmin);
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263 tile->dst_ctrl.h = (ymax - ymin);
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264 tile->dst_ctrl.x_off = xmin;
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265 tile->dst_ctrl.y_off = ymin;
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267 //printk("tile->dst_ctrl.w = %x, tile->dst_ctrl.h = %x\n", tile->dst_ctrl.w, tile->dst_ctrl.h);
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269 tile->tile_x_num = (xmax - xmin + 1 + 7)>>3;
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270 tile->tile_y_num = (ymax - ymin + 1 + 7)>>3;
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272 tile->dst_x_tmp = xmin - msg->dst.x_offset;
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273 tile->dst_y_tmp = ymin - msg->dst.y_offset;
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276 /*************************************************************
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280 calculate src remap window position / width / height
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281 and set the tile struct
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285 20012-2-2 10:59:25
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286 **************************************************************/
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289 src_tile_info_cal(const struct rga_req *msg, TILE_INFO *tile)
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291 s32 x0, x1, x2, x3, y0, y1, y2, y3;
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293 int64_t xx, xy, yx, yy;
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298 int64_t x_dx, x_dy, y_dx, y_dy;
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299 int64_t x_temp_start, y_temp_start;
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300 int64_t xmax, xmin, ymax, ymin;
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302 int64_t t_xoff, t_yoff;
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304 xx = tile->matrix[0]; /* 32.32 */
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305 xy = tile->matrix[1]; /* 32.32 */
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306 yx = tile->matrix[2]; /* 32.32 */
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307 yy = tile->matrix[3]; /* 32.32 */
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309 if(msg->rotate_mode == 1)
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311 x0 = tile->dst_x_tmp;
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312 y0 = tile->dst_y_tmp;
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323 pos[0] = (x0*xx + y0*yx);
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324 pos[1] = (x0*xy + y0*yy);
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326 pos[2] = (x1*xx + y1*yx);
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327 pos[3] = (x1*xy + y1*yy);
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329 pos[4] = (x2*xx + y2*yx);
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330 pos[5] = (x2*xy + y2*yy);
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332 pos[6] = (x3*xx + y3*yx);
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333 pos[7] = (x3*xy + y3*yy);
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343 epos[2] = (x1*xx + y1*yx);
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344 epos[3] = (x1*xy + y1*yy);
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346 epos[4] = (x2*xx + y2*yx);
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347 epos[5] = (x2*xy + y2*yy);
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349 epos[6] = (x3*xx + y3*yx);
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350 epos[7] = (x3*xy + y3*yy);
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352 x_dx = pos[6] - pos[0];
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353 x_dy = pos[7] - pos[1];
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355 y_dx = pos[2] - pos[0];
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356 y_dy = pos[3] - pos[1];
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358 tile->x_dx = (s32)(x_dx >> 22 );
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359 tile->x_dy = (s32)(x_dy >> 22 );
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360 tile->y_dx = (s32)(y_dx >> 22 );
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361 tile->y_dy = (s32)(y_dy >> 22 );
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363 x_temp_start = x0*xx + y0*yx;
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364 y_temp_start = x0*xy + y0*yy;
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366 xmax = (MAX(MAX(MAX(epos[0], epos[2]), epos[4]), epos[6]));
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367 xmin = (MIN(MIN(MIN(epos[0], epos[2]), epos[4]), epos[6]));
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369 ymax = (MAX(MAX(MAX(epos[1], epos[3]), epos[5]), epos[7]));
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370 ymin = (MIN(MIN(MIN(epos[1], epos[3]), epos[5]), epos[7]));
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372 t_xoff = (x_temp_start - xmin)>>18;
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373 t_yoff = (y_temp_start - ymin)>>18;
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375 tile->tile_xoff = (s32)t_xoff;
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376 tile->tile_yoff = (s32)t_yoff;
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378 tile->tile_w = (u16)((xmax - xmin)>>21); //.11
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379 tile->tile_h = (u16)((ymax - ymin)>>21); //.11
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381 tile->tile_start_x_coor = (s16)(xmin>>29); //.3
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382 tile->tile_start_y_coor = (s16)(ymin>>29); //.3
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384 else if (msg->rotate_mode == 2)
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386 tile->x_dx = (s32)((8*xx)>>22);
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389 tile->y_dy = (s32)((8*yy)>>22);
\r
391 tile->tile_w = ABS((s32)((7*xx)>>21));
\r
392 tile->tile_h = ABS((s32)((7*yy)>>21));
\r
394 tile->tile_xoff = ABS((s32)((7*xx)>>18));
\r
395 tile->tile_yoff = 0;
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397 tile->tile_start_x_coor = (((msg->src.act_w - 1)<<11) - (tile->tile_w))>>8;
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398 tile->tile_start_y_coor = 0;
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400 else if (msg->rotate_mode == 3)
\r
402 tile->x_dx = (s32)((8*xx)>>22);
\r
405 tile->y_dy = (s32)((8*yy)>>22);
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407 tile->tile_w = ABS((s32)((7*xx)>>21));
\r
408 tile->tile_h = ABS((s32)((7*yy)>>21));
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410 tile->tile_xoff = 0;
\r
411 tile->tile_yoff = ABS((s32)((7*yy)>>18));
\r
413 tile->tile_start_x_coor = 0;
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414 tile->tile_start_y_coor = (((msg->src.act_h - 1)<<11) - (tile->tile_h))>>8;
\r
417 if ((msg->scale_mode == 2)||(msg->alpha_rop_flag >> 7))
\r
419 tile->tile_start_x_coor -= (1<<3);
\r
420 tile->tile_start_y_coor -= (1<<3);
\r
421 tile->tile_w += (2 << 11);
\r
422 tile->tile_h += (2 << 11);
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423 tile->tile_xoff += (1<<14);
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424 tile->tile_yoff += (1<<14);
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429 /*************************************************************
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433 fill mode ctrl reg info
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437 20012-2-2 10:59:25
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438 **************************************************************/
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441 RGA_set_mode_ctrl(u8 *base, const struct rga_req *msg)
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443 u32 *bRGA_MODE_CTL;
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446 u8 src_rgb_pack = 0;
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450 u8 src_cbcr_swp = 0;
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452 u8 dst_rgb_pack = 0;
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457 bRGA_MODE_CTL = (u32 *)(base + RGA_MODE_CTRL_OFFSET);
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459 reg = ((reg & (~m_RGA_MODE_CTRL_2D_RENDER_MODE)) | (s_RGA_MODE_CTRL_2D_RENDER_MODE(msg->render_mode)));
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463 if (msg->render_mode == color_palette_mode || msg->render_mode == update_palette_table_mode)
\r
465 src_format = 0x10 | (msg->palette_mode & 3);
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469 switch (msg->src.format)
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471 case RK_FORMAT_RGBA_8888 : src_format = 0x0; break;
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472 case RK_FORMAT_RGBA_4444 : src_format = 0x3; break;
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473 case RK_FORMAT_RGBA_5551 : src_format = 0x2; break;
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474 case RK_FORMAT_BGRA_8888 : src_format = 0x0; src_rb_swp = 0x1; break;
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475 case RK_FORMAT_RGBX_8888 : src_format = 0x0; break;
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476 case RK_FORMAT_RGB_565 : src_format = 0x1; break;
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477 case RK_FORMAT_RGB_888 : src_format = 0x0; src_rgb_pack = 1; break;
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478 case RK_FORMAT_BGR_888 : src_format = 0x0; src_rgb_pack = 1; src_rb_swp = 1; break;
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480 case RK_FORMAT_YCbCr_422_SP : src_format = 0x4; break;
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481 case RK_FORMAT_YCbCr_422_P : src_format = 0x5; break;
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482 case RK_FORMAT_YCbCr_420_SP : src_format = 0x6; break;
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483 case RK_FORMAT_YCbCr_420_P : src_format = 0x7; break;
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485 case RK_FORMAT_YCrCb_422_SP : src_format = 0x4; src_cbcr_swp = 1; break;
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486 case RK_FORMAT_YCrCb_422_P : src_format = 0x5; src_cbcr_swp = 1; break;
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487 case RK_FORMAT_YCrCb_420_SP : src_format = 0x6; src_cbcr_swp = 1; break;
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488 case RK_FORMAT_YCrCb_420_P : src_format = 0x7; src_cbcr_swp = 1; break;
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492 src_a_swp = msg->src.alpha_swap & 1;
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494 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RGB_PACK)) | (s_RGA_MODE_CTRL_SRC_RGB_PACK(src_rgb_pack)));
\r
495 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_FORMAT)) | (s_RGA_MODE_CTRL_SRC_FORMAT(src_format)));
\r
496 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_RB_SWAP)) | (s_RGA_MODE_CTRL_SRC_RB_SWAP(src_rb_swp)));
\r
497 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_SRC_ALPHA_SWAP(src_a_swp)));
\r
498 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_UV_SWAP_MODE )) | (s_RGA_MODE_CTRL_SRC_UV_SWAP_MODE (src_cbcr_swp)));
\r
501 /* YUV2RGB MODE */
\r
502 reg = ((reg & (~m_RGA_MODE_CTRL_YUV2RGB_CON_MODE)) | (s_RGA_MODE_CTRL_YUV2RGB_CON_MODE(msg->yuv2rgb_mode)));
\r
505 reg = ((reg & (~m_RGA_MODE_CTRL_ROTATE_MODE)) | (s_RGA_MODE_CTRL_ROTATE_MODE(msg->rotate_mode)));
\r
508 reg = ((reg & (~m_RGA_MODE_CTRL_SCALE_MODE)) | (s_RGA_MODE_CTRL_SCALE_MODE(msg->scale_mode)));
\r
510 /* COLOR FILL MODE */
\r
511 reg = ((reg & (~m_RGA_MODE_CTRL_PAT_SEL)) | (s_RGA_MODE_CTRL_PAT_SEL(msg->color_fill_mode)));
\r
514 if ((msg->render_mode == update_palette_table_mode)||(msg->render_mode == update_patten_buff_mode))
\r
516 dst_format = msg->pat.format;
\r
520 dst_format = (u8)msg->dst.format;
\r
523 /* dst info set */
\r
524 switch (dst_format)
\r
526 case RK_FORMAT_BGRA_8888 : dst_format = 0x0; dst_rb_swp = 0x1; break;
\r
527 case RK_FORMAT_RGBA_4444 : dst_format = 0x3; break;
\r
528 case RK_FORMAT_RGBA_5551 : dst_format = 0x2; break;
\r
529 case RK_FORMAT_RGBA_8888 : dst_format = 0x0; break;
\r
530 case RK_FORMAT_RGB_565 : dst_format = 0x1; break;
\r
531 case RK_FORMAT_RGB_888 : dst_format = 0x0; dst_rgb_pack = 0x1; break;
\r
532 case RK_FORMAT_BGR_888 : dst_format = 0x0; dst_rgb_pack = 0x1; dst_rb_swp = 1; break;
\r
533 case RK_FORMAT_RGBX_8888 : dst_format = 0x0; break;
\r
536 dst_a_swp = msg->dst.alpha_swap & 1;
\r
538 reg = ((reg & (~m_RGA_MODE_CTRL_DST_FORMAT)) | (s_RGA_MODE_CTRL_DST_FORMAT(dst_format)));
\r
539 reg = ((reg & (~m_RGA_MODE_CTRL_DST_RGB_PACK)) | (s_RGA_MODE_CTRL_DST_RGB_PACK(dst_rgb_pack)));
\r
540 reg = ((reg & (~m_RGA_MODE_CTRL_DST_RB_SWAP)) | (s_RGA_MODE_CTRL_DST_RB_SWAP(dst_rb_swp)));
\r
541 reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_SWAP)) | (s_RGA_MODE_CTRL_DST_ALPHA_SWAP(dst_a_swp)));
\r
542 reg = ((reg & (~m_RGA_MODE_CTRL_LUT_ENDIAN_MODE)) | (s_RGA_MODE_CTRL_LUT_ENDIAN_MODE(msg->endian_mode & 1)));
\r
543 reg = ((reg & (~m_RGA_MODE_CTRL_SRC_TRANS_MODE)) | (s_RGA_MODE_CTRL_SRC_TRANS_MODE(msg->src_trans_mode)));
\r
544 reg = ((reg & (~m_RGA_MODE_CTRL_ZERO_MODE_ENABLE)) | (s_RGA_MODE_CTRL_ZERO_MODE_ENABLE(msg->alpha_rop_mode >> 4)));
\r
545 reg = ((reg & (~m_RGA_MODE_CTRL_DST_ALPHA_ENABLE)) | (s_RGA_MODE_CTRL_DST_ALPHA_ENABLE(msg->alpha_rop_mode >> 5)));
\r
547 *bRGA_MODE_CTL = reg;
\r
553 /*************************************************************
\r
557 fill src relate reg info
\r
561 20012-2-2 10:59:25
\r
562 **************************************************************/
\r
565 RGA_set_src(u8 *base, const struct rga_req *msg)
\r
567 u32 *bRGA_SRC_VIR_INFO;
\r
568 u32 *bRGA_SRC_ACT_INFO;
\r
569 u32 *bRGA_SRC_Y_MST;
\r
570 u32 *bRGA_SRC_CB_MST;
\r
571 u32 *bRGA_SRC_CR_MST;
\r
573 s16 x_off, y_off, stride;
\r
574 s16 uv_x_off, uv_y_off, uv_stride;
\r
577 uv_x_off = uv_y_off = uv_stride = 0;
\r
579 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
\r
580 bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
\r
581 bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
\r
582 bRGA_SRC_VIR_INFO = (u32 *)(base + RGA_SRC_VIR_INFO_OFFSET);
\r
583 bRGA_SRC_ACT_INFO = (u32 *)(base + RGA_SRC_ACT_INFO_OFFSET);
\r
585 x_off = msg->src.x_offset;
\r
586 y_off = msg->src.y_offset;
\r
588 pixel_width = RGA_pixel_width_init(msg->src.format);
\r
590 stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
\r
592 switch(msg->src.format)
\r
594 case RK_FORMAT_YCbCr_422_SP :
\r
595 uv_stride = stride;
\r
599 case RK_FORMAT_YCbCr_422_P :
\r
600 uv_stride = stride >> 1;
\r
601 uv_x_off = x_off >> 1;
\r
604 case RK_FORMAT_YCbCr_420_SP :
\r
605 uv_stride = stride;
\r
607 uv_y_off = y_off >> 1;
\r
609 case RK_FORMAT_YCbCr_420_P :
\r
610 uv_stride = stride >> 1;
\r
611 uv_x_off = x_off >> 1;
\r
612 uv_y_off = y_off >> 1;
\r
614 case RK_FORMAT_YCrCb_422_SP :
\r
615 uv_stride = stride;
\r
619 case RK_FORMAT_YCrCb_422_P :
\r
620 uv_stride = stride >> 1;
\r
621 uv_x_off = x_off >> 1;
\r
624 case RK_FORMAT_YCrCb_420_SP :
\r
625 uv_stride = stride;
\r
627 uv_y_off = y_off >> 1;
\r
629 case RK_FORMAT_YCrCb_420_P :
\r
630 uv_stride = stride >> 1;
\r
631 uv_x_off = x_off >> 1;
\r
632 uv_y_off = y_off >> 1;
\r
637 /* src addr set */
\r
638 *bRGA_SRC_Y_MST = msg->src.yrgb_addr + (y_off * stride) + (x_off * pixel_width);
\r
639 *bRGA_SRC_CB_MST = msg->src.uv_addr + uv_y_off * uv_stride + uv_x_off;
\r
640 *bRGA_SRC_CR_MST = msg->src.v_addr + uv_y_off * uv_stride + uv_x_off;
\r
642 if((msg->alpha_rop_flag >> 1) & 1)
\r
643 *bRGA_SRC_CB_MST = (u32)msg->rop_mask_addr;
\r
645 if (msg->render_mode == color_palette_mode)
\r
649 shift = 3 - (msg->palette_mode & 3);
\r
650 sw = msg->src.vir_w;
\r
652 byte_num = sw >> shift;
\r
653 stride = (byte_num + 3) & (~3);
\r
656 /* src act window / vir window set */
\r
657 *bRGA_SRC_VIR_INFO = ((stride >> 2) | (msg->src.vir_h)<<16);
\r
658 *bRGA_SRC_ACT_INFO = ((msg->src.act_w-1) | (msg->src.act_h-1)<<16);
\r
662 /*************************************************************
\r
666 fill dst relate reg info
\r
670 20012-2-2 10:59:25
\r
671 **************************************************************/
\r
673 s32 RGA_set_dst(u8 *base, const struct rga_req *msg)
\r
676 u32 *bRGA_DST_VIR_INFO;
\r
677 u32 *bRGA_DST_CTR_INFO;
\r
678 u32 *bRGA_PRESCL_CB_MST;
\r
679 u32 *bRGA_PRESCL_CR_MST;
\r
683 s16 x_off = msg->dst.x_offset;
\r
684 s16 y_off = msg->dst.y_offset;
\r
685 u16 stride, rop_mask_stride;
\r
687 bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
\r
688 bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
\r
689 bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
\r
690 bRGA_PRESCL_CB_MST = (u32 *)(base + RGA_PRESCL_CB_MST_OFFSET);
\r
691 bRGA_PRESCL_CR_MST = (u32 *)(base + RGA_PRESCL_CR_MST_OFFSET);
\r
693 pw = RGA_pixel_width_init(msg->dst.format);
\r
695 stride = (msg->dst.vir_w * pw + 3) & (~3);
\r
697 *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (y_off * stride) + (x_off * pw);
\r
699 if (msg->render_mode == pre_scaling_mode)
\r
701 switch(msg->dst.format)
\r
703 case RK_FORMAT_YCbCr_422_SP :
\r
704 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
\r
706 case RK_FORMAT_YCbCr_422_P :
\r
707 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
\r
708 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);
\r
710 case RK_FORMAT_YCbCr_420_SP :
\r
711 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
\r
713 case RK_FORMAT_YCbCr_420_P :
\r
714 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
\r
715 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
\r
717 case RK_FORMAT_YCrCb_422_SP :
\r
718 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off) * pw);
\r
720 case RK_FORMAT_YCrCb_422_P :
\r
721 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off) * stride) + ((x_off>>1) * pw);
\r
722 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off) * stride) + ((x_off>>1) * pw);
\r
724 case RK_FORMAT_YCrCb_420_SP :
\r
725 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off) * pw);
\r
727 case RK_FORMAT_YCrCb_420_P :
\r
728 *bRGA_PRESCL_CB_MST = (u32)msg->dst.uv_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
\r
729 *bRGA_PRESCL_CR_MST = (u32)msg->dst.v_addr + ((y_off>>1) * stride) + ((x_off>>1) * pw);
\r
734 rop_mask_stride = (((msg->src.vir_w + 7)>>3) + 3) & (~3);//not dst_vir.w,hxx,2011.7.21
\r
736 reg = (stride >> 2) & 0xffff;
\r
737 reg = reg | ((rop_mask_stride>>2) << 16);
\r
739 #if defined(CONFIG_ARCH_RK2928)
\r
740 reg = reg | ((msg->alpha_rop_mode & 3) << 28);
\r
743 if (msg->render_mode == line_point_drawing_mode)
\r
746 reg = reg | (msg->dst.vir_h << 16);
\r
749 *bRGA_DST_VIR_INFO = reg;
\r
750 *bRGA_DST_CTR_INFO = (msg->dst.act_w - 1) | ((msg->dst.act_h - 1) << 16);
\r
756 /*************************************************************
\r
760 fill alpha rop some relate reg bit
\r
764 20012-2-2 10:59:25
\r
765 **************************************************************/
\r
767 RGA_set_alpha_rop(u8 *base, const struct rga_req *msg)
\r
769 u32 *bRGA_ALPHA_CON;
\r
770 u32 *bRGA_ROP_CON0;
\r
771 u32 *bRGA_ROP_CON1;
\r
773 u32 rop_con0, rop_con1;
\r
775 u8 rop_mode = (msg->alpha_rop_mode) & 3;
\r
776 u8 alpha_mode = msg->alpha_rop_mode & 3;
\r
778 rop_con0 = rop_con1 = 0;
\r
780 bRGA_ALPHA_CON = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
\r
782 reg = ((reg & (~m_RGA_ALPHA_CON_ENABLE) )| (s_RGA_ALPHA_CON_ENABLE(msg->alpha_rop_flag & 1)));
\r
783 reg = ((reg & (~m_RGA_ALPHA_CON_A_OR_R_SEL)) | (s_RGA_ALPHA_CON_A_OR_R_SEL((msg->alpha_rop_flag >> 1) & 1)));
\r
784 reg = ((reg & (~m_RGA_ALPHA_CON_ALPHA_MODE)) | (s_RGA_ALPHA_CON_ALPHA_MODE(alpha_mode)));
\r
785 reg = ((reg & (~m_RGA_ALPHA_CON_PD_MODE)) | (s_RGA_ALPHA_CON_PD_MODE(msg->PD_mode)));
\r
786 reg = ((reg & (~m_RGA_ALPHA_CON_SET_CONSTANT_VALUE)) | (s_RGA_ALPHA_CON_SET_CONSTANT_VALUE(msg->alpha_global_value)));
\r
787 reg = ((reg & (~m_RGA_ALPHA_CON_PD_M_SEL)) | (s_RGA_ALPHA_CON_PD_M_SEL(msg->alpha_rop_flag >> 3)));
\r
788 reg = ((reg & (~m_RGA_ALPHA_CON_FADING_ENABLE)) | (s_RGA_ALPHA_CON_FADING_ENABLE(msg->alpha_rop_flag >> 2)));
\r
789 reg = ((reg & (~m_RGA_ALPHA_CON_ROP_MODE_SEL)) | (s_RGA_ALPHA_CON_ROP_MODE_SEL(rop_mode)));
\r
790 reg = ((reg & (~m_RGA_ALPHA_CON_CAL_MODE_SEL)) | (s_RGA_ALPHA_CON_CAL_MODE_SEL(msg->alpha_rop_flag >> 4)));
\r
791 reg = ((reg & (~m_RGA_ALPHA_CON_DITHER_ENABLE)) | (s_RGA_ALPHA_CON_DITHER_ENABLE(msg->alpha_rop_flag >> 5)));
\r
792 reg = ((reg & (~m_RGA_ALPHA_CON_GRADIENT_CAL_MODE)) | (s_RGA_ALPHA_CON_GRADIENT_CAL_MODE(msg->alpha_rop_flag >> 6)));
\r
793 reg = ((reg & (~m_RGA_ALPHA_CON_AA_SEL)) | (s_RGA_ALPHA_CON_AA_SEL(msg->alpha_rop_flag >> 7)));
\r
795 *bRGA_ALPHA_CON = reg;
\r
797 if(rop_mode == 0) {
\r
798 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
\r
800 else if(rop_mode == 1) {
\r
801 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
\r
803 else if(rop_mode == 2) {
\r
804 rop_con0 = ROP3_code[(msg->rop_code & 0xff)];
\r
805 rop_con1 = ROP3_code[(msg->rop_code & 0xff00)>>8];
\r
808 bRGA_ROP_CON0 = (u32 *)(base + RGA_ROP_CON0_OFFSET);
\r
809 bRGA_ROP_CON1 = (u32 *)(base + RGA_ROP_CON1_OFFSET);
\r
811 *bRGA_ROP_CON0 = (u32)rop_con0;
\r
812 *bRGA_ROP_CON1 = (u32)rop_con1;
\r
816 /*************************************************************
\r
820 fill color some relate reg bit
\r
825 20012-2-2 10:59:25
\r
826 **************************************************************/
\r
829 RGA_set_color(u8 *base, const struct rga_req *msg)
\r
831 u32 *bRGA_SRC_TR_COLOR0;
\r
832 u32 *bRGA_SRC_TR_COLOR1;
\r
833 u32 *bRGA_SRC_BG_COLOR;
\r
834 u32 *bRGA_SRC_FG_COLOR;
\r
837 bRGA_SRC_BG_COLOR = (u32 *)(base + RGA_SRC_BG_COLOR_OFFSET);
\r
838 bRGA_SRC_FG_COLOR = (u32 *)(base + RGA_SRC_FG_COLOR_OFFSET);
\r
840 *bRGA_SRC_BG_COLOR = msg->bg_color; /* 1bpp 0 */
\r
841 *bRGA_SRC_FG_COLOR = msg->fg_color; /* 1bpp 1 */
\r
843 bRGA_SRC_TR_COLOR0 = (u32 *)(base + RGA_SRC_TR_COLOR0_OFFSET);
\r
844 bRGA_SRC_TR_COLOR1 = (u32 *)(base + RGA_SRC_TR_COLOR1_OFFSET);
\r
846 *bRGA_SRC_TR_COLOR0 = msg->color_key_min;
\r
847 *bRGA_SRC_TR_COLOR1 = msg->color_key_max;
\r
851 /*************************************************************
\r
855 fill fading some relate reg bit
\r
859 20012-2-2 10:59:25
\r
860 **************************************************************/
\r
863 RGA_set_fading(u8 *base, const struct rga_req *msg)
\r
865 u32 *bRGA_FADING_CON;
\r
869 bRGA_FADING_CON = (u32 *)(base + RGA_FADING_CON_OFFSET);
\r
875 reg = (r<<8) | (g<<16) | (b<<24) | reg;
\r
877 *bRGA_FADING_CON = reg;
\r
883 /*************************************************************
\r
887 fill patten some relate reg bit
\r
891 20012-2-2 10:59:25
\r
892 **************************************************************/
\r
895 RGA_set_pat(u8 *base, const struct rga_req *msg)
\r
898 u32 *bRGA_PAT_START_POINT;
\r
901 bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
\r
903 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
\r
905 *bRGA_PAT_START_POINT = (msg->pat.act_w * msg->pat.y_offset) + msg->pat.x_offset;
\r
907 reg = (msg->pat.act_w - 1) | ((msg->pat.act_h - 1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
\r
908 *bRGA_PAT_CON = reg;
\r
916 /*************************************************************
\r
918 RGA_set_bitblt_reg_info
\r
920 fill bitblt mode relate ren info
\r
924 20012-2-2 10:59:25
\r
925 **************************************************************/
\r
928 RGA_set_bitblt_reg_info(u8 *base, const struct rga_req * msg, TILE_INFO *tile)
\r
930 u32 *bRGA_SRC_Y_MST;
\r
931 u32 *bRGA_SRC_CB_MST;
\r
932 u32 *bRGA_SRC_CR_MST;
\r
933 u32 *bRGA_SRC_X_PARA;
\r
934 u32 *bRGA_SRC_Y_PARA;
\r
935 u32 *bRGA_SRC_TILE_XINFO;
\r
936 u32 *bRGA_SRC_TILE_YINFO;
\r
937 u32 *bRGA_SRC_TILE_H_INCR;
\r
938 u32 *bRGA_SRC_TILE_V_INCR;
\r
939 u32 *bRGA_SRC_TILE_OFFSETX;
\r
940 u32 *bRGA_SRC_TILE_OFFSETY;
\r
943 u32 *bRGA_DST_CTR_INFO;
\r
945 s32 m0, m1, m2, m3;
\r
947 //s32 x_dx, x_dy, y_dx, y_dy;
\r
948 s32 xmin, xmax, ymin, ymax;
\r
950 u32 y_addr, u_addr, v_addr;
\r
951 u32 pixel_width, stride;
\r
953 u_addr = v_addr = 0;
\r
957 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
\r
958 bRGA_SRC_CB_MST = (u32 *)(base + RGA_SRC_CB_MST_OFFSET);
\r
959 bRGA_SRC_CR_MST = (u32 *)(base + RGA_SRC_CR_MST_OFFSET);
\r
961 bRGA_SRC_X_PARA = (u32 *)(base + RGA_SRC_X_PARA_OFFSET);
\r
962 bRGA_SRC_Y_PARA = (u32 *)(base + RGA_SRC_Y_PARA_OFFSET);
\r
964 bRGA_SRC_TILE_XINFO = (u32 *)(base + RGA_SRC_TILE_XINFO_OFFSET);
\r
965 bRGA_SRC_TILE_YINFO = (u32 *)(base + RGA_SRC_TILE_YINFO_OFFSET);
\r
966 bRGA_SRC_TILE_H_INCR = (u32 *)(base + RGA_SRC_TILE_H_INCR_OFFSET);
\r
967 bRGA_SRC_TILE_V_INCR = (u32 *)(base + RGA_SRC_TILE_V_INCR_OFFSET);
\r
968 bRGA_SRC_TILE_OFFSETX = (u32 *)(base + RGA_SRC_TILE_OFFSETX_OFFSET);
\r
969 bRGA_SRC_TILE_OFFSETY = (u32 *)(base + RGA_SRC_TILE_OFFSETY_OFFSET);
\r
971 bRGA_DST_MST = (u32 *)(base + RGA_DST_MST_OFFSET);
\r
972 bRGA_DST_CTR_INFO = (u32 *)(base + RGA_DST_CTR_INFO_OFFSET);
\r
974 /* Matrix reg fill */
\r
975 m0 = (s32)(tile->matrix[0] >> 18);
\r
976 m1 = (s32)(tile->matrix[1] >> 18);
\r
977 m2 = (s32)(tile->matrix[2] >> 18);
\r
978 m3 = (s32)(tile->matrix[3] >> 18);
\r
980 *bRGA_SRC_X_PARA = (m0 & 0xffff) | (m2 << 16);
\r
981 *bRGA_SRC_Y_PARA = (m1 & 0xffff) | (m3 << 16);
\r
983 /* src tile information setting */
\r
984 if(msg->rotate_mode != 0)//add by hxx,2011.7.12,for rtl0707,when line scanning ,do not calc src tile info
\r
986 *bRGA_SRC_TILE_XINFO = (tile->tile_start_x_coor & 0xffff) | (tile->tile_w << 16);
\r
987 *bRGA_SRC_TILE_YINFO = (tile->tile_start_y_coor & 0xffff) | (tile->tile_h << 16);
\r
989 *bRGA_SRC_TILE_H_INCR = ((tile->x_dx) & 0xffff) | ((tile->x_dy) << 16);
\r
990 *bRGA_SRC_TILE_V_INCR = ((tile->y_dx) & 0xffff) | ((tile->y_dy) << 16);
\r
992 *bRGA_SRC_TILE_OFFSETX = tile->tile_xoff;
\r
993 *bRGA_SRC_TILE_OFFSETY = tile->tile_yoff;
\r
996 pixel_width = RGA_pixel_width_init(msg->src.format);
\r
998 stride = ((msg->src.vir_w * pixel_width) + 3) & (~3);
\r
1000 if ((msg->rotate_mode == 1)||(msg->rotate_mode == 2)||(msg->rotate_mode == 3))
\r
1002 pos[0] = tile->tile_start_x_coor<<8;
\r
1003 pos[1] = tile->tile_start_y_coor<<8;
\r
1006 pos[3] = pos[1] + tile->tile_h;
\r
1008 pos[4] = pos[0] + tile->tile_w;
\r
1009 pos[5] = pos[1] + tile->tile_h;
\r
1011 pos[6] = pos[0] + tile->tile_w;
\r
1026 xmax = (MAX(MAX(MAX(pos[0], pos[2]), pos[4]), pos[6]) + 1);
\r
1027 xmin = (MIN(MIN(MIN(pos[0], pos[2]), pos[4]), pos[6]));
\r
1029 ymax = (MAX(MAX(MAX(pos[1], pos[3]), pos[5]), pos[7]) + 1);
\r
1030 ymin = (MIN(MIN(MIN(pos[1], pos[3]), pos[5]), pos[7]));
\r
1032 xp = xmin + msg->src.x_offset;
\r
1033 yp = ymin + msg->src.y_offset;
\r
1035 if (!((xmax < 0)||(xmin > msg->src.act_w - 1)||(ymax < 0)||(ymin > msg->src.act_h - 1)))
\r
1037 xp = CLIP(xp, msg->src.x_offset, msg->src.x_offset + msg->src.act_w - 1);
\r
1038 yp = CLIP(yp, msg->src.y_offset, msg->src.y_offset + msg->src.act_h - 1);
\r
1041 switch(msg->src.format)
\r
1043 case RK_FORMAT_YCbCr_420_P :
\r
1044 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1045 u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
\r
1046 v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);
\r
1048 case RK_FORMAT_YCbCr_420_SP :
\r
1049 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1050 u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
\r
1052 case RK_FORMAT_YCbCr_422_P :
\r
1053 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1054 u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
\r
1055 v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);
\r
1057 case RK_FORMAT_YCbCr_422_SP:
\r
1058 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1059 u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);
\r
1061 case RK_FORMAT_YCrCb_420_P :
\r
1062 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1063 u_addr = msg->src.uv_addr + (yp>>1)*(stride>>1) + (xp>>1);
\r
1064 v_addr = msg->src.v_addr + (yp>>1)*(stride>>1) + (xp>>1);
\r
1066 case RK_FORMAT_YCrCb_420_SP :
\r
1067 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1068 u_addr = msg->src.uv_addr + (yp>>1)*stride + ((xp>>1)<<1);
\r
1070 case RK_FORMAT_YCrCb_422_P :
\r
1071 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1072 u_addr = msg->src.uv_addr + (yp)*(stride>>1) + (xp>>1);
\r
1073 v_addr = msg->src.v_addr + (yp)*(stride>>1) + (xp>>1);
\r
1075 case RK_FORMAT_YCrCb_422_SP:
\r
1076 y_addr = msg->src.yrgb_addr + yp*stride + xp;
\r
1077 u_addr = msg->src.uv_addr + yp*stride + ((xp>>1)<<1);
\r
1080 y_addr = msg->src.yrgb_addr + yp*stride + xp*pixel_width;
\r
1084 *bRGA_SRC_Y_MST = y_addr;
\r
1085 *bRGA_SRC_CB_MST = u_addr;
\r
1086 *bRGA_SRC_CR_MST = v_addr;
\r
1090 pixel_width = RGA_pixel_width_init(msg->dst.format);
\r
1091 stride = (msg->dst.vir_w * pixel_width + 3) & (~3);
\r
1092 *bRGA_DST_MST = (u32)msg->dst.yrgb_addr + (tile->dst_ctrl.y_off * stride) + (tile->dst_ctrl.x_off * pixel_width);
\r
1093 *bRGA_DST_CTR_INFO = (tile->dst_ctrl.w) | ((tile->dst_ctrl.h) << 16);
\r
1095 *bRGA_DST_CTR_INFO |= (1<<29);
\r
1101 /*************************************************************
\r
1103 RGA_set_color_palette_reg_info
\r
1105 fill color palette process some relate reg bit
\r
1109 20012-2-2 10:59:25
\r
1110 **************************************************************/
\r
1113 RGA_set_color_palette_reg_info(u8 *base, const struct rga_req *msg)
\r
1115 u32 *bRGA_SRC_Y_MST;
\r
1122 x_off = msg->src.x_offset;
\r
1123 y_off = msg->src.y_offset;
\r
1125 sw = msg->src.vir_w;
\r
1126 shift = 3 - (msg->palette_mode & 3);
\r
1127 byte_num = sw >> shift;
\r
1128 src_stride = (byte_num + 3) & (~3);
\r
1130 p = msg->src.yrgb_addr;
\r
1131 p = p + (x_off>>shift) + y_off*src_stride;
\r
1133 bRGA_SRC_Y_MST = (u32 *)(base + RGA_SRC_Y_MST_OFFSET);
\r
1134 *bRGA_SRC_Y_MST = (u32)p;
\r
1138 /*************************************************************
\r
1140 RGA_set_color_fill_reg_info
\r
1142 fill color fill process some relate reg bit
\r
1146 20012-2-2 10:59:25
\r
1147 **************************************************************/
\r
1149 RGA_set_color_fill_reg_info(u8 *base, const struct rga_req *msg)
\r
1152 u32 *bRGA_CP_GR_A;
\r
1153 u32 *bRGA_CP_GR_B;
\r
1154 u32 *bRGA_CP_GR_G;
\r
1155 u32 *bRGA_CP_GR_R;
\r
1157 u32 *bRGA_PAT_CON;
\r
1159 bRGA_CP_GR_A = (u32 *)(base + RGA_CP_GR_A_OFFSET);
\r
1160 bRGA_CP_GR_B = (u32 *)(base + RGA_CP_GR_B_OFFSET);
\r
1161 bRGA_CP_GR_G = (u32 *)(base + RGA_CP_GR_G_OFFSET);
\r
1162 bRGA_CP_GR_R = (u32 *)(base + RGA_CP_GR_R_OFFSET);
\r
1164 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
\r
1166 *bRGA_CP_GR_A = (msg->gr_color.gr_x_a & 0xffff) | (msg->gr_color.gr_y_a << 16);
\r
1167 *bRGA_CP_GR_B = (msg->gr_color.gr_x_b & 0xffff) | (msg->gr_color.gr_y_b << 16);
\r
1168 *bRGA_CP_GR_G = (msg->gr_color.gr_x_g & 0xffff) | (msg->gr_color.gr_y_g << 16);
\r
1169 *bRGA_CP_GR_R = (msg->gr_color.gr_x_r & 0xffff) | (msg->gr_color.gr_y_r << 16);
\r
1171 *bRGA_PAT_CON = (msg->pat.vir_w-1) | ((msg->pat.vir_h-1) << 8) | (msg->pat.x_offset << 16) | (msg->pat.y_offset << 24);
\r
1176 /*************************************************************
\r
1178 RGA_set_line_drawing_reg_info
\r
1180 fill line drawing process some relate reg bit
\r
1184 20012-2-2 10:59:25
\r
1185 **************************************************************/
\r
1187 s32 RGA_set_line_drawing_reg_info(u8 *base, const struct rga_req *msg)
\r
1189 u32 *bRGA_LINE_DRAW;
\r
1190 u32 *bRGA_DST_VIR_INFO;
\r
1191 u32 *bRGA_LINE_DRAW_XY_INFO;
\r
1192 u32 *bRGA_LINE_DRAW_WIDTH;
\r
1193 u32 *bRGA_LINE_DRAWING_COLOR;
\r
1194 u32 *bRGA_LINE_DRAWING_MST;
\r
1198 s16 x_width, y_width;
\r
1199 u16 abs_x, abs_y, delta;
\r
1203 u8 line_dir, dir_major, dir_semi_major;
\r
1206 bRGA_LINE_DRAW = (u32 *)(base + RGA_LINE_DRAW_OFFSET);
\r
1207 bRGA_DST_VIR_INFO = (u32 *)(base + RGA_DST_VIR_INFO_OFFSET);
\r
1208 bRGA_LINE_DRAW_XY_INFO = (u32 *)(base + RGA_LINE_DRAW_XY_INFO_OFFSET);
\r
1209 bRGA_LINE_DRAW_WIDTH = (u32 *)(base + RGA_LINE_DRAWING_WIDTH_OFFSET);
\r
1210 bRGA_LINE_DRAWING_COLOR = (u32 *)(base + RGA_LINE_DRAWING_COLOR_OFFSET);
\r
1211 bRGA_LINE_DRAWING_MST = (u32 *)(base + RGA_LINE_DRAWING_MST_OFFSET);
\r
1213 pw = RGA_pixel_width_init(msg->dst.format);
\r
1215 stride = (msg->dst.vir_w * pw + 3) & (~3);
\r
1217 start_addr = msg->dst.yrgb_addr
\r
1218 + (msg->line_draw_info.start_point.y * stride)
\r
1219 + (msg->line_draw_info.start_point.x * pw);
\r
1221 x_width = msg->line_draw_info.start_point.x - msg->line_draw_info.end_point.x;
\r
1222 y_width = msg->line_draw_info.start_point.y - msg->line_draw_info.end_point.y;
\r
1224 abs_x = abs(x_width);
\r
1225 abs_y = abs(y_width);
\r
1227 if (abs_x >= abs_y)
\r
1230 dir_semi_major = 1;
\r
1232 dir_semi_major = 0;
\r
1239 if((abs_x == 0)||(abs_y == 0))
\r
1242 delta = (abs_y<<12)/abs_x;
\r
1247 major_width = abs_x;
\r
1253 dir_semi_major = 1;
\r
1255 dir_semi_major = 0;
\r
1262 delta = (abs_x<<12)/abs_y;
\r
1263 major_width = abs_y;
\r
1267 reg = (reg & (~m_RGA_LINE_DRAW_MAJOR_WIDTH)) | (s_RGA_LINE_DRAW_MAJOR_WIDTH(major_width));
\r
1268 reg = (reg & (~m_RGA_LINE_DRAW_LINE_DIRECTION)) | (s_RGA_LINE_DRAW_LINE_DIRECTION(line_dir));
\r
1269 reg = (reg & (~m_RGA_LINE_DRAW_LINE_WIDTH)) | (s_RGA_LINE_DRAW_LINE_WIDTH(msg->line_draw_info.line_width - 1));
\r
1270 reg = (reg & (~m_RGA_LINE_DRAW_INCR_VALUE)) | (s_RGA_LINE_DRAW_INCR_VALUE(delta));
\r
1271 reg = (reg & (~m_RGA_LINE_DRAW_DIR_SEMI_MAJOR)) | (s_RGA_LINE_DRAW_DIR_SEMI_MAJOR(dir_semi_major));
\r
1272 reg = (reg & (~m_RGA_LINE_DRAW_DIR_MAJOR)) | (s_RGA_LINE_DRAW_DIR_MAJOR(dir_major));
\r
1273 reg = (reg & (~m_RGA_LINE_DRAW_LAST_POINT)) | (s_RGA_LINE_DRAW_LAST_POINT(msg->line_draw_info.flag >> 1));
\r
1274 reg = (reg & (~m_RGA_LINE_DRAW_ANTI_ALISING)) | (s_RGA_LINE_DRAW_ANTI_ALISING(msg->line_draw_info.flag));
\r
1276 *bRGA_LINE_DRAW = reg;
\r
1278 reg = (msg->line_draw_info.start_point.x & 0xfff) | ((msg->line_draw_info.start_point.y & 0xfff) << 16);
\r
1279 *bRGA_LINE_DRAW_XY_INFO = reg;
\r
1281 *bRGA_LINE_DRAW_WIDTH = msg->dst.vir_w;
\r
1283 *bRGA_LINE_DRAWING_COLOR = msg->line_draw_info.color;
\r
1285 *bRGA_LINE_DRAWING_MST = (u32)start_addr;
\r
1293 RGA_set_filter_reg_info(u8 *base, const struct rga_req *msg)
\r
1295 u32 *bRGA_BLUR_SHARP_INFO;
\r
1298 bRGA_BLUR_SHARP_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
\r
1300 reg = *bRGA_BLUR_SHARP_INFO;
\r
1302 reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_TYPE)) | (s_RGA_BLUR_SHARP_FILTER_TYPE(msg->bsfilter_flag & 3)));
\r
1303 reg = ((reg & (~m_RGA_BLUR_SHARP_FILTER_MODE)) | (s_RGA_BLUR_SHARP_FILTER_MODE(msg->bsfilter_flag >>2)));
\r
1305 *bRGA_BLUR_SHARP_INFO = reg;
\r
1313 RGA_set_pre_scale_reg_info(u8 *base, const struct rga_req *msg)
\r
1315 u32 *bRGA_PRE_SCALE_INFO;
\r
1319 u32 ps_yuv_flag = 0;
\r
1320 u32 src_width, src_height;
\r
1321 u32 dst_width, dst_height;
\r
1323 src_width = msg->src.act_w;
\r
1324 src_height = msg->src.act_h;
\r
1326 dst_width = msg->dst.act_w;
\r
1327 dst_height = msg->dst.act_h;
\r
1329 if((dst_width == 0) || (dst_height == 0))
\r
1331 printk("pre scale reg info error ratio is divide zero\n");
\r
1335 h_ratio = (src_width <<16) / dst_width;
\r
1336 v_ratio = (src_height<<16) / dst_height;
\r
1338 if (h_ratio <= (1<<16))
\r
1340 else if (h_ratio <= (2<<16))
\r
1342 else if (h_ratio <= (4<<16))
\r
1344 else if (h_ratio <= (8<<16))
\r
1347 if (v_ratio <= (1<<16))
\r
1349 else if (v_ratio <= (2<<16))
\r
1351 else if (v_ratio <= (4<<16))
\r
1353 else if (v_ratio <= (8<<16))
\r
1356 if(msg->src.format == msg->dst.format)
\r
1361 bRGA_PRE_SCALE_INFO = (u32 *)(base + RGA_ALPHA_CON_OFFSET);
\r
1363 reg = *bRGA_PRE_SCALE_INFO;
\r
1364 reg = ((reg & (~m_RGA_PRE_SCALE_HOR_RATIO)) | (s_RGA_PRE_SCALE_HOR_RATIO((u8)h_ratio)));
\r
1365 reg = ((reg & (~m_RGA_PRE_SCALE_VER_RATIO)) | (s_RGA_PRE_SCALE_VER_RATIO((u8)v_ratio)));
\r
1366 reg = ((reg & (~m_RGA_PRE_SCALE_OUTPUT_FORMAT)) | (s_RGA_PRE_SCALE_OUTPUT_FORMAT(ps_yuv_flag)));
\r
1368 *bRGA_PRE_SCALE_INFO = reg;
\r
1377 RGA_set_update_palette_table_reg_info(u8 *base, const struct rga_req *msg)
\r
1379 u32 *bRGA_LUT_MST;
\r
1381 if (!msg->LUT_addr) {
\r
1385 bRGA_LUT_MST = (u32 *)(base + RGA_LUT_MST_OFFSET);
\r
1387 *bRGA_LUT_MST = (u32)msg->LUT_addr;
\r
1396 RGA_set_update_patten_buff_reg_info(u8 *base, const struct rga_req *msg)
\r
1398 u32 *bRGA_PAT_MST;
\r
1399 u32 *bRGA_PAT_CON;
\r
1400 u32 *bRGA_PAT_START_POINT;
\r
1402 rga_img_info_t *pat;
\r
1404 pat = (rga_img_info_t *)&msg->pat;
\r
1406 bRGA_PAT_START_POINT = (u32 *)(base + RGA_PAT_START_POINT_OFFSET);
\r
1407 bRGA_PAT_MST = (u32 *)(base + RGA_PAT_MST_OFFSET);
\r
1408 bRGA_PAT_CON = (u32 *)(base + RGA_PAT_CON_OFFSET);
\r
1410 if ( !pat->yrgb_addr ) {
\r
1413 *bRGA_PAT_MST = (u32)pat->yrgb_addr;
\r
1415 if ((pat->vir_w > 256)||(pat->x_offset > 256)||(pat->y_offset > 256)) {
\r
1418 *bRGA_PAT_START_POINT = (pat->vir_w * pat->y_offset) + pat->x_offset;
\r
1420 reg = (pat->vir_w-1) | ((pat->vir_h-1) << 8) | (pat->x_offset << 16) | (pat->y_offset << 24);
\r
1421 *bRGA_PAT_CON = reg;
\r
1427 /*************************************************************
\r
1429 RGA_set_mmu_ctrl_reg_info
\r
1431 fill mmu relate some reg info
\r
1435 20012-2-2 10:59:25
\r
1436 **************************************************************/
\r
1439 RGA_set_mmu_ctrl_reg_info(u8 *base, const struct rga_req *msg)
\r
1441 u32 *RGA_MMU_TLB, *RGA_MMU_CTRL_ADDR;
\r
1443 u8 TLB_size, mmu_enable, src_flag, dst_flag, CMD_flag;
\r
1446 mmu_addr = (u32)msg->mmu_info.base_addr;
\r
1447 TLB_size = (msg->mmu_info.mmu_flag >> 4) & 0x3;
\r
1448 mmu_enable = msg->mmu_info.mmu_flag & 0x1;
\r
1450 src_flag = (msg->mmu_info.mmu_flag >> 1) & 0x1;
\r
1451 dst_flag = (msg->mmu_info.mmu_flag >> 2) & 0x1;
\r
1452 CMD_flag = (msg->mmu_info.mmu_flag >> 3) & 0x1;
\r
1454 RGA_MMU_TLB = (u32 *)(base + RGA_MMU_TLB_OFFSET);
\r
1455 RGA_MMU_CTRL_ADDR = (u32 *)(base + RGA_FADING_CON_OFFSET);
\r
1457 reg = ((reg & (~m_RGA_MMU_CTRL_TLB_ADDR)) | s_RGA_MMU_CTRL_TLB_ADDR(mmu_addr));
\r
1458 *RGA_MMU_TLB = reg;
\r
1460 reg = *RGA_MMU_CTRL_ADDR;
\r
1461 reg = ((reg & (~m_RGA_MMU_CTRL_PAGE_TABLE_SIZE)) | s_RGA_MMU_CTRL_PAGE_TABLE_SIZE(TLB_size));
\r
1462 reg = ((reg & (~m_RGA_MMU_CTRL_MMU_ENABLE)) | s_RGA_MMU_CTRL_MMU_ENABLE(mmu_enable));
\r
1463 reg = ((reg & (~m_RGA_MMU_CTRL_SRC_FLUSH)) | s_RGA_MMU_CTRL_SRC_FLUSH(1));
\r
1464 reg = ((reg & (~m_RGA_MMU_CTRL_DST_FLUSH)) | s_RGA_MMU_CTRL_DST_FLUSH(1));
\r
1465 reg = ((reg & (~m_RGA_MMU_CTRL_CMD_CHAN_FLUSH)) | s_RGA_MMU_CTRL_CMD_CHAN_FLUSH(1));
\r
1466 *RGA_MMU_CTRL_ADDR = reg;
\r
1473 /*************************************************************
\r
1477 Generate RGA command reg list from rga_req struct.
\r
1481 20012-2-2 10:59:25
\r
1482 **************************************************************/
\r
1484 RGA_gen_reg_info(const struct rga_req *msg, unsigned char *base)
\r
1488 memset(base, 0x0, 28*4);
\r
1489 RGA_set_mode_ctrl(base, msg);
\r
1491 switch(msg->render_mode)
\r
1493 case bitblt_mode :
\r
1494 RGA_set_alpha_rop(base, msg);
\r
1495 RGA_set_src(base, msg);
\r
1496 RGA_set_dst(base, msg);
\r
1497 RGA_set_color(base, msg);
\r
1498 RGA_set_fading(base, msg);
\r
1499 RGA_set_pat(base, msg);
\r
1500 matrix_cal(msg, &tile);
\r
1501 dst_ctrl_cal(msg, &tile);
\r
1502 src_tile_info_cal(msg, &tile);
\r
1503 RGA_set_bitblt_reg_info(base, msg, &tile);
\r
1505 case color_palette_mode :
\r
1506 RGA_set_src(base, msg);
\r
1507 RGA_set_dst(base, msg);
\r
1508 RGA_set_color(base, msg);
\r
1509 RGA_set_color_palette_reg_info(base, msg);
\r
1511 case color_fill_mode :
\r
1512 RGA_set_alpha_rop(base, msg);
\r
1513 RGA_set_dst(base, msg);
\r
1514 RGA_set_color(base, msg);
\r
1515 RGA_set_pat(base, msg);
\r
1516 RGA_set_color_fill_reg_info(base, msg);
\r
1518 case line_point_drawing_mode :
\r
1519 RGA_set_alpha_rop(base, msg);
\r
1520 RGA_set_dst(base, msg);
\r
1521 RGA_set_color(base, msg);
\r
1522 RGA_set_line_drawing_reg_info(base, msg);
\r
1524 case blur_sharp_filter_mode :
\r
1525 RGA_set_src(base, msg);
\r
1526 RGA_set_dst(base, msg);
\r
1527 RGA_set_filter_reg_info(base, msg);
\r
1529 case pre_scaling_mode :
\r
1530 RGA_set_src(base, msg);
\r
1531 RGA_set_dst(base, msg);
\r
1532 if(RGA_set_pre_scale_reg_info(base, msg) == -EINVAL)
\r
1535 case update_palette_table_mode :
\r
1536 if (RGA_set_update_palette_table_reg_info(base, msg)) {
\r
1540 case update_patten_buff_mode:
\r
1541 if (RGA_set_update_patten_buff_reg_info(base, msg)){
\r
1548 RGA_set_mmu_ctrl_reg_info(base, msg);
\r