drivers/video/rockchip/screen/s1d13521ioctl.h

   1 //-----------------------------------------------------------------------------
   2 //
   3 // linux/drivers/video/epson/s1d1352ioctl.h -- IOCTL definitions for Epson
   4 // S1D13521 controller frame buffer driver.
   5 //
   6 // Copyright(c) Seiko Epson Corporation 2009.
   7 // All rights reserved.
   8 //
   9 // This file is subject to the terms and conditions of the GNU General Public
  10 // License. See the file COPYING in the main directory of this archive for
  11 // more details.
  12 //
  13 //----------------------------------------------------------------------------
  14
  15 /* ioctls
  16     0x45 is 'E'                                                          */
  17
  18 struct s1d13521_ioctl_hwc
  19 {
  20         unsigned addr;
  21         unsigned value;
  22         void* buffer;
  23 };
  24
  25 #define S1D13521_REGREAD                0x4540
  26 #define S1D13521_REGWRITE               0x4541
  27 #define S1D13521_MEMBURSTREAD           0x4546
  28 #define S1D13521_MEMBURSTWRITE          0x4547
  29 #define S1D13521_VBUF_REFRESH           0x4548
  30
  31 // System commands
  32 #define INIT_CMD_SET                    0x00
  33 #define INIT_PLL_STANDBY                0x01
  34 #define RUN_SYS                         0x02
  35 #define STBY                            0x04
  36 #define SLP                             0x05
  37 #define INIT_SYS_RUN                    0x06
  38 #define INIT_SYS_STBY                   0x07
  39 #define INIT_SDRAM                      0x08
  40 #define INIT_DSPE_CFG                   0x09
  41 #define INIT_DSPE_TMG                   0x0A
  42 #define INIT_ROTMODE                    0x0B
  43
  44 // Register and memory access commands
  45 #define RD_REG                          0x10
  46 #define WR_REG                          0x11
  47 #define RD_SFM                          0x12
  48 #define WR_SFM                          0x13
  49 #define END_SFM                         0x14
  50
  51 // Burst access commands
  52 #define BST_RD_SDR                      0x1C
  53 #define BST_WR_SDR                      0x1D
  54 #define BST_END_SDR                     0x1E
  55
  56 // Image loading commands
  57 #define LD_IMG                          0x20
  58 #define LD_IMG_AREA                     0x22
  59 #define LD_IMG_END                      0x23
  60 #define LD_IMG_WAIT                     0x24
  61 #define LD_IMG_SETADR                   0x25
  62 #define LD_IMG_DSPEADR                  0x26
  63
  64 // Polling commands
  65 #define WAIT_DSPE_TRG                   0x28
  66 #define WAIT_DSPE_FREND                 0x29
  67 #define WAIT_DSPE_LUTFREE               0x2A
  68 #define WAIT_DSPE_MLUTFREE              0x2B
  69
  70 // Waveform update commands
  71 #define RD_WFM_INFO                     0x30
  72 #define UPD_INIT                        0x32
  73 #define UPD_FULL                        0x33
  74 #define UPD_FULL_AREA                   0x34
  75 #define UPD_PART                        0x35
  76 #define UPD_PART_AREA                   0x36
  77 #define UPD_GDRV_CLR                    0x37
  78 #define UPD_SET_IMGADR                  0x38
  79
  80 #pragma pack(1)
  81
  82 typedef struct
  83 {
  84         u16 param[5];
  85 }s1d13521_ioctl_cmd_params;
  86
  87 #pragma pack()
  88
  89 #define S1D13521_INIT_CMD_SET           (0x4500 | INIT_CMD_SET)
  90 #define S1D13521_INIT_PLL_STANDBY       (0x4500 | INIT_PLL_STANDBY)
  91 #define S1D13521_RUN_SYS                (0x4500 | RUN_SYS)
  92 #define S1D13521_STBY                   (0x4500 | STBY)
  93 #define S1D13521_SLP                    (0x4500 | SLP)
  94 #define S1D13521_INIT_SYS_RUN           (0x4500 | INIT_SYS_RUN)
  95 #define S1D13521_INIT_SYS_STBY          (0x4500 | INIT_SYS_STBY)
  96 #define S1D13521_INIT_SDRAM             (0x4500 | INIT_SDRAM)
  97 #define S1D13521_INIT_DSPE_CFG          (0x4500 | INIT_DSPE_CFG)
  98 #define S1D13521_INIT_DSPE_TMG          (0x4500 | INIT_DSPE_TMG)
  99 #define S1D13521_INIT_ROTMODE           (0x4500 | INIT_ROTMODE)
 100 #define S1D13521_RD_REG                 (0x4500 | RD_REG)
 101 #define S1D13521_WR_REG                 (0x4500 | WR_REG)
 102 #define S1D13521_RD_SFM                 (0x4500 | RD_SFM)
 103 #define S1D13521_WR_SFM                 (0x4500 | WR_SFM)
 104 #define S1D13521_END_SFM                (0x4500 | END_SFM)
 105
 106 // Burst access commands
 107 #define S1D13521_BST_RD_SDR             (0x4500 | BST_RD_SDR)
 108 #define S1D13521_BST_WR_SDR             (0x4500 | BST_WR_SDR)
 109 #define S1D13521_BST_END_SDR            (0x4500 | BST_END_SDR)
 110
 111 // Image loading IOCTL commands
 112 #define S1D13521_LD_IMG                 (0x4500 | LD_IMG)
 113 #define S1D13521_LD_IMG_AREA            (0x4500 | LD_IMG_AREA)
 114 #define S1D13521_LD_IMG_END             (0x4500 | LD_IMG_END)
 115 #define S1D13521_LD_IMG_WAIT            (0x4500 | LD_IMG_WAIT)
 116 #define S1D13521_LD_IMG_SETADR          (0x4500 | LD_IMG_SETADR)
 117 #define S1D13521_LD_IMG_DSPEADR         (0x4500 | LD_IMG_DSPEADR)
 118
 119 // Polling commands
 120 #define S1D13521_WAIT_DSPE_TRG          (0x4500 | WAIT_DSPE_TRG)
 121 #define S1D13521_WAIT_DSPE_FREND        (0x4500 | WAIT_DSPE_FREND)
 122 #define S1D13521_WAIT_DSPE_LUTFREE      (0x4500 | WAIT_DSPE_LUTFREE)
 123 #define S1D13521_WAIT_DSPE_MLUTFREE     (0x4500 | WAIT_DSPE_MLUTFREE)
 124
 125 // Waveform update IOCTL commands
 126 #define S1D13521_RD_WFM_INFO            (0x4500 | RD_WFM_INFO)
 127 #define S1D13521_UPD_INIT               (0x4500 | UPD_INIT)
 128 #define S1D13521_UPD_FULL               (0x4500 | UPD_FULL)
 129 #define S1D13521_UPD_FULL_AREA          (0x4500 | UPD_FULL_AREA)
 130 #define S1D13521_UPD_PART               (0x4500 | UPD_PART)
 131 #define S1D13521_UPD_PART_AREA          (0x4500 | UPD_PART_AREA)
 132 #define S1D13521_UPD_GDRV_CLR           (0x4500 | UPD_GDRV_CLR)
 133 #define S1D13521_UPD_SET_IMGADR         (0x4500 | UPD_SET_IMGADR)
 134