4 #include<linux/rk_fb.h>
7 #define ANX6345_SCL_RATE (100*1000)
13 #define DP_TX_PORT0_ADDR 0x70
14 #define HDMI_TX_PORT0_ADDR 0x72
16 #define DP_TIMEOUT_LOOP_CNT 100
20 /***************************************************************/
21 // DEV_ADDR = 0x7A or 0x7B , MIPI Rx Registers
22 #define MIPI_ANALOG_PWD_CTRL0 0x00
23 #define MIPI_ANALOG_PWD_CTRL1 0x01
24 #define MIPI_ANALOG_PWD_CTRL2 0x02
26 #define MIPI_MISC_CTRL 0x03
28 #define MIPI_TIMING_REG0 0x04
29 #define MIPI_TIMING_REG1 0x05
30 #define MIPI_TIMING_REG2 0x06
31 #define MIPI_TIMING_REG3 0x07
32 #define MIPI_TIMING_REG4 0x08
33 #define MIPI_TIMING_REG5 0x09
34 #define MIPI_TIMING_REG6 0x0a
36 #define MIPI_HS_JITTER_REG 0x0B
38 #define MIPI_VID_STABLE_CNT 0x0C
40 #define MIPI_ANALOG_CTRL0 0x0D
41 #define MIPI_ANALOG_CTRL1 0x0E
42 #define MIPI_ANALOG_CTRL2 0x0F
44 #define MIPI_PRBS_REG 0x10
45 #define MIPI_PROTOCOL_STATE 0x11
48 //End for DEV_addr 0x7A/0x7E
50 /***************************************************************/
51 // DEV_ADDR = 0x70 or 0x78 , Displayport mode and HDCP registers
52 #define HDCP_STATUS 0x00
53 #define HDCP_AUTH_PASS 0x02//bit position
55 #define HDCP_CONTROL_0_REG 0x01
56 #define HDCP_CONTROL_0_STORE_AN 0x80//bit position
57 #define HDCP_CONTROL_0_RX_REPEATER 0x40//bit position
58 #define HDCP_CONTROL_0_RE_AUTH 0x20//bit position
59 #define HDCP_CONTROL_0_SW_AUTH_OK 0x10//bit position
60 #define HDCP_CONTROL_0_HARD_AUTH_EN 0x08//bit position
61 #define HDCP_CONTROL_0_HDCP_ENC_EN 0x04//bit position
62 #define HDCP_CONTROL_0_BKSV_SRM_PASS 0x02//bit position
63 #define HDCP_CONTROL_0_KSVLIST_VLD 0x01//bit position
66 #define HDCP_CONTROL_1_REG 0x02
67 #define HDCP_CONTROL_1_DDC_NO_STOP 0x20//bit position
68 #define HDCP_CONTROL_1_DDC_NO_ACK 0x10//bit position
69 #define HDCP_CONTROL_1_EDDC_NO_ACK 0x08//bit position
70 //#define HDCP_CONTROL_1_HDCP_EMB_SCREEN_EN 0x04//bit position
71 #define HDCP_CONTROL_1_RCV_11_EN 0x02//bit position
72 #define HDCP_CONTROL_1_HDCP_11_EN 0x01//bit position
74 #define HDCP_LINK_CHK_FRAME_NUM 0x03
75 #define HDCP_CONTROL_2_REG 0x04
77 #define HDCP_AKSV0 0x05
78 #define HDCP_AKSV1 0x06
79 #define HDCP_AKSV2 0x07
80 #define HDCP_AKSV3 0x08
81 #define HDCP_AKSV4 0x09
94 #define HDCP_BKSV0 0x12
95 #define HDCP_BKSV1 0x13
96 #define HDCP_BKSV2 0x14
97 #define HDCP_BKSV3 0x15
98 #define HDCP_BKSV4 0x16
100 #define HDCP_R0_L 0x17
101 #define HDCP_R0_H 0x18
110 #define HDCP_R0_WAIT_Timer 0x40
114 #define SYS_CTRL1_REG 0x80
115 //#define SYS_CTRL1_PD_IO 0x80 // bit position
116 //#define SYS_CTRL1_PD_VID 0x40 // bit position
117 //#define SYS_CTRL1_PD_LINK 0x20 // bit position
118 //#define SYS_CTRL1_PD_TOTAL 0x10 // bit position
119 //#define SYS_CTRL1_MODE_SEL 0x08 // bit position
120 #define SYS_CTRL1_DET_STA 0x04 // bit position
121 #define SYS_CTRL1_FORCE_DET 0x02 // bit position
122 #define SYS_CTRL1_DET_CTRL 0x01 // bit position
124 #define SYS_CTRL2_REG 0x81
125 // #define SYS_CTRL2_ENHANCED 0x08 //bit position
126 #define SYS_CTRL2_CHA_STA 0x04 // bit position
127 #define SYS_CTRL2_FORCE_CHA 0x02 // bit position
128 #define SYS_CTRL2_CHA_CTRL 0x01 // bit position
130 #define SYS_CTRL3_REG 0x82
131 #define SYS_CTRL3_HPD_STATUS 0x40 // bit position
132 #define SYS_CTRL3_F_HPD 0x20 // bit position
133 #define SYS_CTRL3_HPD_CTRL 0x10 // bit position
134 #define SYS_CTRL3_STRM_VALID 0x04 // bit position
135 #define SYS_CTRL3_F_VALID 0x02 // bit position
136 #define SYS_CTRL3_VALID_CTRL 0x01 // bit position
138 #define SYS_CTRL4_REG 0x83
139 #define SYS_CTRL4_ENHANCED 0x08//bit position
141 #define VID_CTRL 0x84
143 #define AUD_CTRL 0x87
144 #define AUD_CTRL_AUD_EN 0x01
147 #define PKT_EN_REG 0x90
148 #define PKT_AUD_UP 0x80 // bit position
149 #define PKT_AVI_UD 0x40 // bit position
150 #define PKT_MPEG_UD 0x20 // bit position
151 #define PKT_SPD_UD 0x10 // bit position
152 #define PKT_AUD_EN 0x08 // bit position=
153 #define PKT_AVI_EN 0x04 // bit position
154 #define PKT_MPEG_EN 0x02 // bit position
155 #define PKT_SPD_EN 0x01 // bit position
158 #define HDCP_CTRL 0x92
160 #define LINK_BW_SET_REG 0xA0
161 #define LANE_COUNT_SET_REG 0xA1
163 #define TRAINING_PTN_SET_REG 0xA2
164 #define SCRAMBLE_DISABLE 0x20//bit 5
166 #define TRAINING_LANE0_SET_REG 0xA3
167 #define TRAINING_LANE0_SET_MAX_PRE_REACH 0x20 // bit position
168 #define TRAINING_LANE0_SET_MAX_DRIVE_REACH 0x04 // bit position
170 #define TRAINING_LANE1_SET_REG 0xA4
173 #define SSC_CTRL_REG1 0xA7
174 #define SPREAD_AMP 0x10//bit 4
175 #define MODULATION_FREQ 0x01//bit 0
178 #define LINK_TRAINING_CTRL_REG 0xA8
179 #define LINK_TRAINING_CTRL_EN 0x01 // bit position
182 #define DEBUG_REG1 0xB0
183 #define DEBUG_HPD_POLLING_DET 0x40//bit position
184 #define DEBUG_HPD_POLLING_EN 0x20//bit position
185 #define DEBUG_PLL_LOCK 0x10//bit position
188 #define LINK_DEBUG_REG 0xB8
189 #define LINK_DEBUG_INSERT_ER 0x02 // bit position
190 #define LINK_DEBUG_PRBS31_EN 0x01 // bit position
192 #define SINK_COUNT_REG 0xB9
194 #define LINK_STATUS_REG1 0xBB
196 #define SINK_STATUS_REG 0xBE
197 #define SINK_STATUS_SINK_STATUS_1 0x02 // bit position
198 #define SINK_STATUS_SINK_STATUS_0 0x01 // bit position
201 //#define LINK_TEST_COUNT 0xC0
204 #define PLL_CTRL_REG 0xC7
205 #define PLL_CTRL_PLL_PD 0x80 // bit position
206 #define PLL_CTRL_PLL_RESET 0x40 // bit position
207 //#define PLL_CTRL_CPREG_BLEED 0x08 // bit position
209 #define ANALOG_POWER_DOWN_REG 0xC8
210 #define ANALOG_POWER_DOWN_MACRO_PD 0x20 // bit position
211 #define ANALOG_POWER_DOWN_AUX_PD 0x10 // bit position
212 //#define ANALOG_POWER_DOWN_CH3_PD 0x08 // bit position
213 //#define ANALOG_POWER_DOWN_CH2_PD 0x04 // bit position
214 #define ANALOG_POWER_DOWN_CH1_PD 0x02 // bit position
215 #define ANALOG_POWER_DOWN_CH0_PD 0x01 // bit position
218 #define ANALOG_TEST_REG 0xC9
219 #define ANALOG_TEST_MACRO_RST 0x20 // bit position
220 #define ANALOG_TEST_PLL_TEST 0x10 // bit position
221 #define ANALOG_TEST_CH3_TEST 0x08 // bit position
222 #define ANALOG_TEST_CH2_TEST 0x04 // bit position
223 #define ANALOG_TEST_CH1_TEST 0x02 // bit position
224 #define ANALOG_TEST_CH0_TEST 0x01 // bit position
226 #define GNS_CTRL_REG 0xCD
227 #define SP_EQ_LOOP_CNT 0x40//bit position
228 #define VIDEO_MAP_CTRL 0x02 // bit position
229 #define RS_CTRL 0x01 // bit position
231 #define DOWN_SPREADING_CTRL1 0xD0 //guochuncheng
232 #define DOWN_SPREADING_CTRL2 0xD1
233 #define DOWN_SPREADING_CTRL3 0xD2
234 #define SSC_D_CTRL 0x40 //bit position
235 #define FS_CTRL_TH_CTRL 0x20 //bit position
237 #define M_CALCU_CTRL 0xD9
238 #define M_GEN_CLK_SEL 0x01//bit 0
241 #define EXTRA_ADDR_REG 0xCE
242 #define I2C_STRETCH_CTRL_REG 0xDB
243 #define AUX_STATUS 0xE0
244 #define DEFER_CTRL_REG 0xE2
245 #define SP_TXL_DEFER_CTRL_EN 0x80 // bit position
247 #define BUF_DATA_COUNT_REG 0xE4
248 #define AUX_CTRL_REG 0xE5
249 #define MOT_BIT 0x04//bit 2
251 #define AUX_ADDR_7_0_REG 0xE6
252 #define AUX_ADDR_15_8_REG 0xE7
253 #define AUX_ADDR_19_16_REG 0xE8
255 #define AUX_CTRL_REG2 0xE9
256 #define ADDR_ONLY_BIT 0x02//bit 1
258 #define BUF_DATA_0_REG 0xf0
259 #define BUF_DATA_1_REG 0xf1
260 #define BUF_DATA_2_REG 0xf2
261 #define BUF_DATA_3_REG 0xf3
262 #define BUF_DATA_4_REG 0xf4
263 #define BUF_DATA_5_REG 0xf5
264 #define BUF_DATA_6_REG 0xf6
265 #define BUF_DATA_7_REG 0xf7
266 #define BUF_DATA_8_REG 0xf8
267 #define BUF_DATA_9_REG 0xf9
268 #define BUF_DATA_10_REG 0xfa
269 #define BUF_DATA_11_REG 0xfb
270 #define BUF_DATA_12_REG 0xfc
271 #define BUF_DATA_13_REG 0xfd
272 #define BUF_DATA_14_REG 0xfe
273 #define BUF_DATA_15_REG 0xff
275 //End for Address 0x70 or 0x78
277 /***************************************************************/
278 // DEV_ADDR = 0x72 or 0x76, System control registers
279 #define VND_IDL_REG 0x00
280 #define VND_IDH_REG 0x01
281 #define DEV_IDL_REG 0x02
282 #define DEV_IDH_REG 0x03
283 #define DEV_REV_REG 0x04
285 #define SP_POWERD_CTRL_REG 0x05
286 #define SP_POWERD_REGISTER_REG 0x80// bit position
287 //#define SP_POWERD_MISC_REG 0x40// bit position
288 #define SP_POWERD_IO_REG 0x20// bit position
289 #define SP_POWERD_AUDIO_REG 0x10// bit position
290 #define SP_POWERD_VIDEO_REG 0x08// bit position
291 #define SP_POWERD_LINK_REG 0x04// bit position
292 #define SP_POWERD_TOTAL_REG 0x02// bit position
293 #define SP_MODE_SEL_REG 0x01// bit position
295 #define RST_CTRL_REG 0x06
296 #define RST_MISC_REG 0x80 // bit position
297 #define RST_VIDCAP_REG 0x40 // bit position
298 #define RST_VIDFIF_REG 0x20 // bit position
299 #define RST_AUDFIF_REG 0x10 // bit position
300 #define RST_AUDCAP_REG 0x08 // bit position
301 #define RST_HDCP_REG 0x04 // bit position
302 #define RST_SW_RST 0x02 // bit position
303 #define RST_HW_RST 0x01 // bit position
305 #define RST_CTRL2_REG 0x07
306 #define RST_SSC 0x80//bit position
307 #define AC_MODE 0x40//bit position
308 //#define DDC_RST 0x10//bit position
309 //#define TMDS_BIST_RST 0x08//bit position
310 #define AUX_RST 0x04//bit position
311 #define SERDES_FIFO_RST 0x02//bit position
312 #define I2C_REG_RST 0x01//bit position
315 #define VID_CTRL1_REG 0x08
316 #define VID_CTRL1_VID_EN 0x80 // bit position
317 #define VID_CTRL1_VID_MUTE 0x40 // bit position
318 #define VID_CTRL1_DE_GEN 0x20 // bit position
319 #define VID_CTRL1_DEMUX 0x10 // bit position
320 #define VID_CTRL1_IN_BIT 0x04 // bit position
321 #define VID_CTRL1_DDRCTRL 0x02 // bit position
322 #define VID_CTRL1_EDGE 0x01 // bit position
324 #define VID_CTRL2_REG 0x09
325 #define VID_CTRL1_YCBIT_SEL 0x04 // bit position
327 #define VID_CTRL3_REG 0x0A
329 #define VID_CTRL4_REG 0x0B
330 #define VID_CTRL4_E_SYNC_EN 0x80 //bit position
331 #define VID_CTRL4_EX_E_SYNC 0x40 // bit position
332 #define VID_CTRL4_BIST 0x08 // bit position
333 #define VID_CTRL4_BIST_WIDTH 0x04 // bit position
335 #define VID_CTRL5_REG 0x0C
337 #define VID_CTRL6_REG 0x0D
338 #define VID_UPSAMPLE 0x02//bit position
340 #define VID_CTRL7_REG 0x0E
341 #define VID_CTRL8_REG 0x0F
342 #define VID_CTRL9_REG 0x10
344 #define VID_CTRL10_REG 0x11
345 #define VID_CTRL10_INV_F 0x08 // bit position
346 #define VID_CTRL10_I_SCAN 0x04 // bit position
347 #define VID_CTRL10_VSYNC_POL 0x02 // bit position
348 #define VID_CTRL10_HSYNC_POL 0x01 // bit position
350 #define TOTAL_LINEL_REG 0x12
351 #define TOTAL_LINEH_REG 0x13
352 #define ACT_LINEL_REG 0x14
353 #define ACT_LINEH_REG 0x15
354 #define VF_PORCH_REG 0x16
355 #define VSYNC_CFG_REG 0x17
356 #define VB_PORCH_REG 0x18
357 #define TOTAL_PIXELL_REG 0x19
358 #define TOTAL_PIXELH_REG 0x1A
359 #define ACT_PIXELL_REG 0x1B
360 #define ACT_PIXELH_REG 0x1C
361 #define HF_PORCHL_REG 0x1D
362 #define HF_PORCHH_REG 0x1E
363 #define HSYNC_CFGL_REG 0x1F
364 #define HSYNC_CFGH_REG 0x20
365 #define HB_PORCHL_REG 0x21
366 #define HB_PORCHH_REG 0x22
368 #define VID_STATUS 0x23
370 #define TOTAL_LINE_STA_L 0x24
371 #define TOTAL_LINE_STA_H 0x25
372 #define ACT_LINE_STA_L 0x26
373 #define ACT_LINE_STA_H 0x27
374 #define V_F_PORCH_STA 0x28
375 #define V_SYNC_STA 0x29
376 #define V_B_PORCH_STA 0x2A
377 #define TOTAL_PIXEL_STA_L 0x2B
378 #define TOTAL_PIXEL_STA_H 0x2C
379 #define ACT_PIXEL_STA_L 0x2D
380 #define ACT_PIXEL_STA_H 0x2E
381 #define H_F_PORCH_STA_L 0x2F
382 #define H_F_PORCH_STA_H 0x30
383 #define H_SYNC_STA_L 0x31
384 #define H_SYNC_STA_H 0x32
385 #define H_B_PORCH_STA_L 0x33
386 #define H_B_PORCH_STA_H 0x34
388 #define Video_Interface_BIST 0x35
390 #define SPDIF_AUDIO_CTRL0 0x36
391 #define SPDIF_AUDIO_CTRL0_SPDIF_IN 0x80 // bit position
393 #define SPDIF_AUDIO_STATUS0 0x38
394 #define SPDIF_AUDIO_STATUS0_CLK_DET 0x80
395 #define SPDIF_AUDIO_STATUS0_AUD_DET 0x01
397 #define SPDIF_AUDIO_STATUS1 0x39
399 #define AUDIO_BIST_CTRL 0x3c
400 #define AUDIO_BIST_EN 0x01
402 //#define AUDIO_BIST_CHANNEL_STATUS1 0xd0
403 //#define AUDIO_BIST_CHANNEL_STATUS2 0xd1
404 //#define AUDIO_BIST_CHANNEL_STATUS3 0xd2
405 //#define AUDIO_BIST_CHANNEL_STATUS4 0xd3
406 //#define AUDIO_BIST_CHANNEL_STATUS5 0xd4
408 #define VIDEO_BIT_CTRL_0_REG 0x40
409 #define VIDEO_BIT_CTRL_1_REG 0x41
410 #define VIDEO_BIT_CTRL_2_REG 0x42
411 #define VIDEO_BIT_CTRL_3_REG 0x43
412 #define VIDEO_BIT_CTRL_4_REG 0x44
413 #define VIDEO_BIT_CTRL_5_REG 0x45
414 #define VIDEO_BIT_CTRL_6_REG 0x46
415 #define VIDEO_BIT_CTRL_7_REG 0x47
416 #define VIDEO_BIT_CTRL_8_REG 0x48
417 #define VIDEO_BIT_CTRL_9_REG 0x49
418 #define VIDEO_BIT_CTRL_10_REG 0x4a
419 #define VIDEO_BIT_CTRL_11_REG 0x4b
420 #define VIDEO_BIT_CTRL_12_REG 0x4c
421 #define VIDEO_BIT_CTRL_13_REG 0x4d
422 #define VIDEO_BIT_CTRL_14_REG 0x4e
423 #define VIDEO_BIT_CTRL_15_REG 0x4f
424 #define VIDEO_BIT_CTRL_16_REG 0x50
425 #define VIDEO_BIT_CTRL_17_REG 0x51
426 #define VIDEO_BIT_CTRL_18_REG 0x52
427 #define VIDEO_BIT_CTRL_19_REG 0x53
428 #define VIDEO_BIT_CTRL_20_REG 0x54
429 #define VIDEO_BIT_CTRL_21_REG 0x55
430 #define VIDEO_BIT_CTRL_22_REG 0x56
431 #define VIDEO_BIT_CTRL_23_REG 0x57
432 #define VIDEO_BIT_CTRL_24_REG 0x58
433 #define VIDEO_BIT_CTRL_25_REG 0x59
434 #define VIDEO_BIT_CTRL_26_REG 0x5a
435 #define VIDEO_BIT_CTRL_27_REG 0x5b
436 #define VIDEO_BIT_CTRL_28_REG 0x5c
437 #define VIDEO_BIT_CTRL_29_REG 0x5d
438 #define VIDEO_BIT_CTRL_30_REG 0x5e
439 #define VIDEO_BIT_CTRL_31_REG 0x5f
440 #define VIDEO_BIT_CTRL_32_REG 0x60
441 #define VIDEO_BIT_CTRL_33_REG 0x61
442 #define VIDEO_BIT_CTRL_34_REG 0x62
443 #define VIDEO_BIT_CTRL_35_REG 0x63
444 #define VIDEO_BIT_CTRL_36_REG 0x64
445 #define VIDEO_BIT_CTRL_37_REG 0x65
446 #define VIDEO_BIT_CTRL_38_REG 0x66
447 #define VIDEO_BIT_CTRL_39_REG 0x67
448 #define VIDEO_BIT_CTRL_40_REG 0x68
449 #define VIDEO_BIT_CTRL_41_REG 0x69
450 #define VIDEO_BIT_CTRL_42_REG 0x6a
451 #define VIDEO_BIT_CTRL_43_REG 0x6b
452 #define VIDEO_BIT_CTRL_44_REG 0x6c
453 #define VIDEO_BIT_CTRL_45_REG 0x6d
454 #define VIDEO_BIT_CTRL_46_REG 0x6e
455 #define VIDEO_BIT_CTRL_47_REG 0x6f
458 #define AVI_TYPE 0x70
471 #define AVI_DB10 0x7D
472 #define AVI_DB11 0x7E
473 #define AVI_DB12 0x7F
474 #define AVI_DB13 0x80
475 #define AVI_DB14 0x81
476 #define AVI_DB15 0x82
479 #define AUD_TYPE 0x83
492 #define AUD_DB10 0x90
495 #define SPD_TYPE 0x91
498 #define SPD_DATA0 0x94
499 #define SPD_DATA1 0x95
500 #define SPD_DATA2 0x96
501 #define SPD_DATA3 0x97
502 #define SPD_DATA4 0x98
503 #define SPD_DATA5 0x99
504 #define SPD_DATA6 0x9A
505 #define SPD_DATA7 0x9B
506 #define SPD_DATA8 0x9C
507 #define SPD_DATA9 0x9D
508 #define SPD_DATA10 0x9E
509 #define SPD_DATA11 0x9F
510 #define SPD_DATA12 0xA0
511 #define SPD_DATA13 0xA1
512 #define SPD_DATA14 0xA2
513 #define SPD_DATA15 0xA3
514 #define SPD_DATA16 0xA4
515 #define SPD_DATA17 0xA5
516 #define SPD_DATA18 0xA6
517 #define SPD_DATA19 0xA7
518 #define SPD_DATA20 0xA8
519 #define SPD_DATA21 0xA9
520 #define SPD_DATA22 0xAA
521 #define SPD_DATA23 0xAB
522 #define SPD_DATA24 0xAC
523 #define SPD_DATA25 0xAD
524 #define SPD_DATA26 0xAE
525 #define SPD_DATA27 0xAF
527 //Mpeg source info frame
528 #define MPEG_TYPE 0xB0
529 #define MPEG_VER 0xB1
530 #define MPEG_LEN 0xB2
531 #define MPEG_DATA0 0xB3
532 #define MPEG_DATA1 0xB4
533 #define MPEG_DATA2 0xB5
534 #define MPEG_DATA3 0xB6
535 #define MPEG_DATA4 0xB7
536 #define MPEG_DATA5 0xB8
537 #define MPEG_DATA6 0xB9
538 #define MPEG_DATA7 0xBA
539 #define MPEG_DATA8 0xBB
540 #define MPEG_DATA9 0xBC
541 #define MPEG_DATA10 0xBD
542 #define MPEG_DATA11 0xBE
543 #define MPEG_DATA12 0xBF
544 #define MPEG_DATA13 0xC0
545 #define MPEG_DATA14 0xC1
546 #define MPEG_DATA15 0xC2
547 #define MPEG_DATA16 0xC3
548 #define MPEG_DATA17 0xC4
549 #define MPEG_DATA18 0xC5
550 #define MPEG_DATA19 0xC6
551 #define MPEG_DATA20 0xC7
552 #define MPEG_DATA21 0xC8
553 #define MPEG_DATA22 0xC9
554 #define MPEG_DATA23 0xCA
555 #define MPEG_DATA24 0xCB
556 #define MPEG_DATA25 0xCC
557 #define MPEG_DATA26 0xCD
558 #define MPEG_DATA27 0xCE
560 //#define GNSS_CTRL_REG 0xCD
561 //#define ENABLE_SSC_FILTER 0x80//bit
563 //#define SSC_D_VALUE 0xD0
564 //#define SSC_CTRL_REG2 0xD1
566 #define ANALOG_DEBUG_REG1 0xDC
567 #define ANALOG_SEL_BG 0x40//bit 4
568 #define ANALOG_SWING_A_30PER 0x08//bit 3
570 #define ANALOG_DEBUG_REG2 0xDD
571 #define ANALOG_24M_SEL 0x08//bit 3
572 //#define ANALOG_FILTER_ENABLED 0x10//bit 4
575 #define ANALOG_DEBUG_REG3 0xDE
577 #define PLL_FILTER_CTRL1 0xDF
578 #define PD_RING_OSC 0x40//bit 6
580 #define PLL_FILTER_CTRL2 0xE0
581 #define PLL_FILTER_CTRL3 0xE1
582 #define PLL_FILTER_CTRL4 0xE2
583 #define PLL_FILTER_CTRL5 0xE3
584 #define PLL_FILTER_CTRL6 0xE4
586 #define I2S_CTRL 0xE6
588 #define I2S_CH_Status1 0xD0
589 #define I2S_CH_Status2 0xD1
590 #define I2S_CH_Status3 0xD2
591 #define I2S_CH_Status4 0xD3
592 #define I2S_CH_Status5 0xD4
595 #define SP_COMMON_INT_STATUS1 0xF1
596 #define SP_COMMON_INT1_PLL_LOCK_CHG 0x40//bit position
597 #define SP_COMMON_INT1_VIDEO_FORMAT_CHG 0x08//bit position
598 #define SP_COMMON_INT1_AUDIO_CLK_CHG 0x04//bit position
599 #define SP_COMMON_INT1_VIDEO_CLOCK_CHG 0x02//bit position
602 #define SP_COMMON_INT_STATUS2 0xF2
603 #define SP_COMMON_INT2_AUTHCHG 0x02 //bit position
604 #define SP_COMMON_INT2_AUTHDONE 0x01 //bit position
606 #define SP_COMMON_INT_STATUS3 0xF3
607 #define SP_COMMON_INT3_AFIFO_UNDER 0x80//bit position
608 #define SP_COMMON_INT3_AFIFO_OVER 0x40//bit position
610 #define SP_COMMON_INT_STATUS4 0xF4
611 #define SP_COMMON_INT4_PLUG 0x01 // bit position
612 #define SP_COMMON_INT4_ESYNC_ERR 0x10 // bit position
613 #define SP_COMMON_INT4_HPDLOST 0x02 //bit position
614 #define SP_COMMON_INT4_HPD_CHANGE 0x04 //bit position
617 #define INT_STATUS1 0xF7
618 #define INT_STATUS1_HPD 0x40 //bit position
619 #define INT_STATUS1_TRAINING_Finish 0x20 // bit position
620 #define INT_STATUS1_POLLING_ERR 0x10 // bit position
622 #define INT_SINK_CHG 0x08//bit position
625 #define AUX_CH_STA 0xe0
626 #define AUX_BUSY (0x1 << 4)
627 #define AUX_STATUS_MASK (0xf << 0)
628 #define DP_AUX_RX_COMM 0xe3
629 #define BUF_DATA_CTL 0xe4
630 #define BUF_CLR (0x1 << 7)
631 #define DP_AUX_CH_CTL_1 0xe5
632 #define AUX_LENGTH(x) (((x - 1) & 0xf) << 4)
633 #define AUX_TX_COMM_MASK (0xf << 0)
634 #define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3)
635 #define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3)
636 #define AUX_TX_COMM_MOT (0x1 << 2)
637 #define AUX_TX_COMM_WRITE (0x0 << 0)
638 #define AUX_TX_COMM_READ (0x1 << 0)
640 #define DP_AUX_ADDR_7_0 0xe6
641 #define DP_AUX_ADDR_15_8 0xe7
642 #define DP_AUX_ADDR_19_16 0xe8
644 #define DP_AUX_CH_CTL_2 0xe9
645 #define ADDR_ONLY (0x1 << 1)
646 #define AUX_EN (0x1 << 0)
648 #define BUF_DATA_0 0xf0
650 #define DP_INT_STA 0xf7
651 #define RPLY_RECEIV (0x1 << 1)
652 #define AUX_ERR (0x1 << 0)
653 #define SP_COMMON_INT_MASK1 0xF8
654 #define SP_COMMON_INT_MASK2 0xF9
655 #define SP_COMMON_INT_MASK3 0xFA
656 #define SP_COMMON_INT_MASK4 0xFB
657 #define SP_INT_MASK 0xFE
658 #define INT_CTRL_REG 0xFF
659 //End for dev_addr 0x72 or 0x76
661 /***************************************************************/
662 /***************************************************************/
666 struct anx6345_platform_data {
667 unsigned int dvdd33_en_pin;
669 unsigned int dvdd18_en_pin;
671 unsigned int edp_rst_pin;
672 int (*power_ctl)(struct anx6345_platform_data *pdata);
677 struct i2c_client *client;
678 struct anx6345_platform_data *pdata;
679 struct rk_screen screen;
680 struct fb_monspecs specs;
681 struct dentry *debugfs_dir;
682 #ifdef CONFIG_HAS_EARLYSUSPEND
683 struct early_suspend early_suspend;
685 int (*edp_anx_init)(struct i2c_client *client);