drivers/video/rockchip/transmitter/dp_anx6345.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/time.h>
   4 #include <linux/delay.h>
   5 #include <linux/slab.h>
   6 #include <linux/device.h>
   7 #include <linux/i2c.h>
   8
   9 #if defined(CONFIG_HAS_EARLYSUSPEND)
  10 #include<linux/earlysuspend.h>
  11 #endif
  12 #if defined(CONFIG_OF)
  13 #include <linux/of_gpio.h>
  14 #endif
  15 #include "anx6345.h"
  16 #include "dpcd_edid.h"
  17 #if defined(CONFIG_DEBUG_FS)
  18 #include <linux/fs.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/seq_file.h>
  21 #endif
  22
  23
  24 static struct edp_anx6345 *edp;
  25 //#define BIST_MODE 0
  26 static int i2c_master_reg8_send(const struct i2c_client *client,
  27                 const char reg, const char *buf, int count, int scl_rate)
  28 {
  29         struct i2c_adapter *adap=client->adapter;
  30         struct i2c_msg msg;
  31         int ret;
  32         char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
  33         if(!tx_buf)
  34                 return -ENOMEM;
  35         tx_buf[0] = reg;
  36         memcpy(tx_buf+1, buf, count);
  37
  38         msg.addr = client->addr;
  39         msg.flags = client->flags;
  40         msg.len = count + 1;
  41         msg.buf = (char *)tx_buf;
  42         msg.scl_rate = scl_rate;
  43
  44         ret = i2c_transfer(adap, &msg, 1);
  45         kfree(tx_buf);
  46         return (ret == 1) ? count : ret;
  47
  48 }
  49
  50 static int i2c_master_reg8_recv(const struct i2c_client *client,
  51                 const char reg, char *buf, int count, int scl_rate)
  52 {
  53         struct i2c_adapter *adap=client->adapter;
  54         struct i2c_msg msgs[2];
  55         int ret;
  56         char reg_buf = reg;
  57
  58         msgs[0].addr = client->addr;
  59         msgs[0].flags = client->flags;
  60         msgs[0].len = 1;
  61         msgs[0].buf = &reg_buf;
  62         msgs[0].scl_rate = scl_rate;
  63
  64         msgs[1].addr = client->addr;
  65         msgs[1].flags = client->flags | I2C_M_RD;
  66         msgs[1].len = count;
  67         msgs[1].buf = (char *)buf;
  68         msgs[1].scl_rate = scl_rate;
  69
  70         ret = i2c_transfer(adap, msgs, 2);
  71
  72         return (ret == 2)? count : ret;
  73 }
  74
  75 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
  76 {
  77         int ret;
  78         client->addr = DP_TX_PORT0_ADDR >> 1;
  79         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  80         if(ret < 0)
  81         {
  82                 printk(KERN_ERR "%s>>err\n",__func__);
  83         }
  84
  85         return ret;
  86 }
  87 static int  anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
  88 {
  89         int ret;
  90         client->addr = DP_TX_PORT0_ADDR >> 1;
  91         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  92         if(ret < 0)
  93         {
  94                 printk(KERN_ERR "%s>>err\n",__func__);
  95         }
  96
  97         return ret;
  98 }
  99 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
 100 {
 101         int ret;
 102         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 103         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 104         if(ret < 0)
 105         {
 106                 printk(KERN_ERR "%s>>err\n",__func__);
 107         }
 108
 109         return ret;
 110 }
 111
 112 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
 113 {
 114         int ret;
 115         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 116         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 117         if(ret < 0)
 118         {
 119                 printk(KERN_ERR "%s>>err\n",__func__);
 120         }
 121
 122         return ret;
 123 }
 124
 125 #if defined(CONFIG_DEBUG_FS)
 126 static int edp_reg_show(struct seq_file *s, void *v)
 127 {
 128         int i = 0;
 129         char val;
 130         struct edp_anx6345 *anx6345 = s->private;
 131         if(!anx6345)
 132         {
 133                 printk(KERN_ERR "no edp device!\n");
 134                 return 0;
 135         }
 136
 137         seq_printf(s,"0x70:\n");
 138         for(i=0;i< MAX_REG;i++)
 139         {
 140                 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
 141                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 142         }
 143
 144         seq_printf(s,"\n0x72:\n");
 145         for(i=0;i< MAX_REG;i++)
 146         {
 147                 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
 148                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 149         }
 150         return 0;
 151 }
 152
 153 static int edp_reg_open(struct inode *inode, struct file *file)
 154 {
 155         struct edp_anx6345 *anx6345 = inode->i_private;
 156         return single_open(file, edp_reg_show, anx6345);
 157 }
 158
 159 static const struct file_operations edp_reg_fops = {
 160         .owner          = THIS_MODULE,
 161         .open           = edp_reg_open,
 162         .read           = seq_read,
 163         .llseek         = seq_lseek,
 164         .release        = single_release,
 165 };
 166 #endif
 167
 168 //get chip ID. Make sure I2C is OK
 169 static int get_dp_chip_id(struct i2c_client *client)
 170 {
 171         char c1,c2;
 172         int id;
 173         anx6345_i2c_read_p1_reg(client,DEV_IDL_REG,&c1);
 174         anx6345_i2c_read_p1_reg(client,DEV_IDH_REG,&c2);
 175         id = c2;
 176         return (id<<8)|c1;
 177 }
 178
 179 #if defined(BIST_MODE)
 180 static int anx980x_bist_mode(struct i2c_client *client)
 181 {
 182         char val,i;
 183         u8 cnt=0;
 184
 185         //Power on total and select DP mode
 186         val = 00;
 187         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 188
 189         //HW reset
 190         val = DP_TX_RST_HW_RST;
 191         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 192         msleep(10);
 193         val = 0x00;
 194         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 195
 196
 197         anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 198         val = 0x00;
 199         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 200
 201
 202         //get chip ID. Make sure I2C is OK
 203         anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
 204         if (val==0x98)
 205                 printk("Chip found\n");
 206
 207         //for clocl detect
 208         for(i=0;i<100;i++)
 209         {
 210                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 211                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 212                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 213                 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
 214                 {
 215                         printk("clock is detected.\n");
 216                         break;
 217                 }
 218
 219                 msleep(10);
 220         }
 221        //check whther clock is stable
 222         for(i=0;i<50;i++)
 223         {
 224                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 225                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 226                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 227                 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
 228                 {
 229                         printk("clock is stable.\n");
 230                         break;
 231                 }
 232                 msleep(10);
 233         }
 234
 235         //VESA range, 8bits BPC, RGB
 236         val = 0x10;
 237         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
 238         //RK_EDP chip analog setting
 239         val = 0x07;
 240         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 241         val = 0x19;
 242         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 243         val = 0xd9;
 244         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 245
 246         //Select AC mode
 247         val = 0x40;
 248         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 249
 250         //RK_EDP chip analog setting
 251         val = 0xf0;
 252         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 253         val = 0x99;
 254         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 255         val = 0x7b;
 256         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 257         val = 0x30;
 258         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 259         val = 0x06;
 260         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
 261
 262         //force HPD
 263         val = 0x30;
 264         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
 265         //power on 4 lanes
 266         val = 0x00;
 267         anx6345_i2c_write_p0_reg(client, 0xc8, &val);
 268         //lanes setting
 269         anx6345_i2c_write_p0_reg(client, 0xa3, &val);
 270         anx6345_i2c_write_p0_reg(client, 0xa4, &val);
 271         anx6345_i2c_write_p0_reg(client, 0xa5,&val);
 272         anx6345_i2c_write_p0_reg(client, 0xa6, &val);
 273
 274         //reset AUX CH
 275         val = 0x44;
 276         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 277         val = 0x40;
 278         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 279
 280         //Select 1.62G
 281         val = 0x06;
 282         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 283         //Select 4 lanes
 284         val = 0x04;
 285         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 286
 287         //strart link traing
 288         //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
 289         #if 1
 290         val = DP_TX_LINK_TRAINING_CTRL_EN;
 291         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 292         msleep(5);
 293         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 294         while((val&0x01)&&(cnt++ < 10))
 295         {
 296                 printk("Waiting...\n");
 297                 msleep(5);
 298                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 299         }
 300
 301         if(cnt >= 10)
 302         {
 303                 printk(KERN_INFO "HW LT fail\n");
 304         }
 305         else
 306         {
 307                 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
 308         }
 309         #else
 310         DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
 311         #endif
 312         //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
 313
 314         //Set bist format 2048x1536
 315         val = 0x2c;
 316         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
 317         val = 0x06;
 318         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
 319
 320         val = 0x00;
 321         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
 322         val = 0x06;
 323         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
 324         val = 0x02;
 325         anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
 326         val = 0x04;
 327         anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
 328         val = 0x26;
 329         anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
 330         val = 0x50;
 331         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
 332         val = 0x04;
 333         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
 334         val = 0x00;
 335         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
 336         val = 0x04;
 337         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
 338
 339         val = 0x18;
 340         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
 341         val = 0x00;
 342         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
 343
 344         val = 0x10;
 345         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
 346         val = 0x00;
 347         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
 348         val = 0x28;
 349         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
 350         val = 0x00;
 351         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
 352         val = 0x03;
 353         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
 354
 355         //enable BIST
 356         val = DP_TX_VID_CTRL4_BIST;
 357         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
 358         //enable video input
 359         val = 0x8d;
 360         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 361         //force HPD and stream valid
 362         val = 0x33;
 363         anx6345_i2c_write_p0_reg(client, 0x82, &val);
 364
 365         return 0;
 366 }
 367 #endif
 368 static int anx980x_aux_rst(struct i2c_client *client)
 369 {
 370         char val;
 371         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 372         val |= DP_TX_AUX_RST;
 373         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 374         val &= ~DP_TX_AUX_RST;
 375         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 376         return 0;
 377 }
 378
 379
 380 static int anx980x_wait_aux_finished(struct i2c_client *client)
 381 {
 382         char val,cnt;
 383         cnt = 0;
 384
 385         anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
 386         while(val&0x01)
 387         {
 388                 //delay_ms(20);
 389                 cnt ++;
 390                 if(cnt == 10)
 391                 {
 392                    printk("aux break");
 393                     anx980x_aux_rst(client);
 394                     //cnt = 0;
 395                     break;
 396                 }
 397                 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
 404 {
 405         char val,i;
 406
 407         val = 0x80;
 408         anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
 409
 410         //set read cmd and count
 411         val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
 412         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
 413
 414         //set aux address15:0
 415         val = (char)addr&0xff;
 416         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
 417         val = (char)((addr>>8)&0xff);
 418         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
 419
 420         //set address19:16 and enable aux
 421         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 422         val &=(0xf0)|(char)((addr>>16)&0xff);
 423         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 424
 425         //Enable Aux
 426         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 427         val |= 0x01;
 428         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 429
 430         //delay_ms(2);
 431         anx980x_wait_aux_finished(client);
 432
 433         for(i =0;i<cCount;i++)
 434         {
 435                 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
 436
 437                 //debug_printf("c = %.2x\n",(WORD)c);
 438                 *(pBuf+i) = val;
 439
 440                 if(i >= MAX_BUF_CNT)
 441                         return 1;
 442                         //break;
 443         }
 444
 445         return 0;
 446
 447
 448 }
 449
 450 static int anx_video_map_config(struct i2c_client *client)
 451 {
 452         char val = 0;
 453         char i = 0;
 454         anx6345_i2c_write_p1_reg(client,  0x40, &val);
 455         anx6345_i2c_write_p1_reg(client,  0x41, &val);
 456         anx6345_i2c_write_p1_reg(client,  0x48, &val);
 457         anx6345_i2c_write_p1_reg(client,  0x49, &val);
 458         anx6345_i2c_write_p1_reg(client,  0x50, &val);
 459         anx6345_i2c_write_p1_reg(client,  0x51, &val);
 460         for(i=0; i<6; i++)
 461         {
 462                 val = i;
 463                 anx6345_i2c_write_p1_reg(client,  0x42+i, &val);
 464         }
 465
 466         for(i=0; i<6; i++)
 467         {
 468                 val = 6+i;
 469                 anx6345_i2c_write_p1_reg(client,  0x4a+i, &val);
 470         }
 471
 472         for(i=0; i<6; i++)
 473         {
 474                 val = 0x0c+i;
 475                 anx6345_i2c_write_p1_reg(client,  0x52+i, &val);
 476         }
 477
 478         return 0;
 479
 480 }
 481 static int anx980x_eanble_video_input(struct i2c_client *client)
 482 {
 483         char val;
 484
 485         anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 486         val |= DP_TX_VID_CTRL1_VID_EN;
 487         anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 488
 489         anx_video_map_config(client);
 490
 491         return 0;
 492 }
 493
 494 static int anx980x_init(struct i2c_client *client)
 495 {
 496         char val = 0x00;
 497         char safe_mode = 0;
 498         char ByteBuf[2];
 499         char dp_tx_bw,dp_tx_lane_count;
 500         char cnt = 10;
 501
 502 #if defined(BIST_MODE)
 503         return anx980x_bist_mode(client);
 504 #endif
 505          //power on all block and select DisplayPort mode
 506         val |= DP_POWERD_AUDIO_REG;
 507         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
 508
 509         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 510         val &= ~DP_TX_VID_CTRL1_VID_EN;
 511         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 512
 513         //software reset
 514         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 515         val |= DP_TX_RST_SW_RST;
 516         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
 517         val &= ~DP_TX_RST_SW_RST;
 518         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 519
 520
 521         val = 0x07;
 522         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 523         val = 0x50;
 524         anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
 525
 526         //24bit SDR,negedge latch, and wait video stable
 527         val = 0x01;
 528         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
 529         val = 0x19;
 530         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 531         val = 0xd9;
 532         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 533
 534         //serdes ac mode.
 535         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 536         val |= DP_TX_AC_MODE;
 537         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 538
 539         //set termination
 540         val = 0xf0;
 541         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 542         //set duty cycle
 543         val = 0x99;
 544         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 545
 546         anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 547         val |= 0x2a;
 548         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 549
 550         //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
 551         val = 0x30;
 552         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 553
 554         //for DP link CTS
 555         anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 556         val |= 0x40;
 557         anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 558
 559         //power down  PLL filter
 560         val = 0x06;
 561         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
 562
 563         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
 564         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
 565         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
 566         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
 567
 568         val = 0x06;
 569         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 570         val = 0x04;
 571         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 572
 573         val = DP_TX_LINK_TRAINING_CTRL_EN;
 574         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
 575         msleep(2);
 576         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 577         while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
 578         {
 579                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 580                 cnt--;
 581         }
 582         if(cnt < 0)
 583         {
 584                 printk(KERN_INFO "HW LT fail\n");
 585         }
 586         else
 587                 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
 588         //DP_TX_Config_Video(client);
 589         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 590         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL1_REG, &val);
 591         if(!(val & DP_TX_SYS_CTRL1_DET_STA))
 592         {
 593                 printk("No pclk\n");
 594                 //return;  //mask by yxj
 595         }
 596
 597         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 598         anx6345_i2c_write_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 599         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 600         if(val & DP_TX_SYS_CTRL2_CHA_STA)
 601         {
 602                 printk("pclk not stable!\n");
 603                 //return; mask by yxj
 604         }
 605
 606         anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
 607         dp_tx_bw = ByteBuf[0];
 608         dp_tx_lane_count = ByteBuf[1] & 0x0f;
 609         printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
 610
 611         if(!safe_mode)
 612         {
 613                 //set Input BPC mode & color space
 614                 anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 615                 val &= 0x8c;
 616                 val = val |((char)(0) << 4);  //8bits  ,rgb
 617                 anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 618         }
 619
 620
 621
 622         //enable video input
 623          anx980x_eanble_video_input(client);
 624
 625         return 0;
 626 }
 627
 628 #if defined(BIST_MODE)
 629 static int anx6345_bist_mode(struct i2c_client *client)
 630 {
 631         struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
 632         struct rk_screen *screen = &anx6345->screen;
 633         u16 x_total ,y_total, x_act;
 634         char val = 0x00;
 635         //these register are for bist mode
 636         x_total = screen->mode.left_margin + screen->mode.right_margin +
 637                         screen->mode.xres + screen->mode.hsync_len;
 638         y_total = screen->mode.upper_margin + screen->mode.lower_margin +
 639                         screen->mode.yres + screen->mode.vsync_len;
 640         x_total >>= 1;
 641         x_act = screen->mode.xres >> 1;
 642         val = y_total & 0xff;
 643         anx6345_i2c_write_p1_reg(client,TOTAL_LINEL_REG,&val);
 644         val = (y_total >> 8);
 645         anx6345_i2c_write_p1_reg(client,TOTAL_LINEH_REG,&val);
 646         val = (screen->mode.yres & 0xff);
 647         anx6345_i2c_write_p1_reg(client,ACT_LINEL_REG,&val);
 648         val = (screen->mode.yres >> 8);
 649         anx6345_i2c_write_p1_reg(client,ACT_LINEH_REG,&val);
 650         val = screen->mode.lower_margin;
 651         anx6345_i2c_write_p1_reg(client,VF_PORCH_REG,&val);
 652         val = screen->mode.vsync_len;
 653         anx6345_i2c_write_p1_reg(client,VSYNC_CFG_REG,&val);
 654         val = screen->mode.upper_margin;
 655         anx6345_i2c_write_p1_reg(client,VB_PORCH_REG,&val);
 656         val = x_total & 0xff;
 657         anx6345_i2c_write_p1_reg(client,TOTAL_PIXELL_REG,&val);
 658         val = x_total >> 8;
 659         anx6345_i2c_write_p1_reg(client,TOTAL_PIXELH_REG,&val);
 660         val = (x_act & 0xff);
 661         anx6345_i2c_write_p1_reg(client,ACT_PIXELL_REG,&val);
 662         val = (x_act >> 8);
 663         anx6345_i2c_write_p1_reg(client,ACT_PIXELH_REG,&val);
 664         val = screen->mode.right_margin & 0xff;
 665         anx6345_i2c_write_p1_reg(client,HF_PORCHL_REG,&val);
 666         val = screen->mode.right_margin >> 8;
 667         anx6345_i2c_write_p1_reg(client,HF_PORCHH_REG,&val);
 668         val = screen->mode.hsync_len & 0xff;
 669         anx6345_i2c_write_p1_reg(client,HSYNC_CFGL_REG,&val);
 670         val = screen->mode.hsync_len >> 8;
 671         anx6345_i2c_write_p1_reg(client,HSYNC_CFGH_REG,&val);
 672         val = screen->mode.left_margin & 0xff;
 673         anx6345_i2c_write_p1_reg(client,HB_PORCHL_REG,&val);
 674         val = screen->mode.left_margin  >> 8;
 675         anx6345_i2c_write_p1_reg(client,HB_PORCHH_REG,&val);
 676         val = 0x13;
 677         anx6345_i2c_write_p1_reg(client,VID_CTRL10_REG,&val);
 678
 679
 680        //enable BIST. In normal mode, don't need to config this reg
 681         val = 0x08;
 682         anx6345_i2c_write_p1_reg(client, VID_CTRL4_REG, &val);
 683         printk("anx6345 enter bist mode\n");
 684
 685         return 0;
 686 }
 687 #endif
 688
 689 int anx6345_start_aux_transaction(struct i2c_client  *client)
 690 {
 691         char val;
 692         int retval = 0;
 693         int timeout_loop = 0;
 694         int aux_timeout = 0;
 695
 696
 697         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 698         val |= AUX_EN;
 699         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 700
 701         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 702         while (val & AUX_EN) {
 703                 aux_timeout++;
 704                 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
 705                         dev_err(&client->dev, "AUX CH enable timeout!\n");
 706                         return -ETIMEDOUT;
 707                 }
 708                 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 709                 udelay(100);
 710         }
 711
 712         /* Is AUX CH command redply received? */
 713         anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
 714         while (!(val & RPLY_RECEIV)) {
 715                 timeout_loop++;
 716                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 717                         dev_err(&client->dev, "AUX CH command redply failed!\n");
 718                         return -ETIMEDOUT;
 719                 }
 720                 anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
 721                 udelay(10);
 722         }
 723
 724         /* Clear interrupt source for AUX CH command redply */
 725         anx6345_i2c_write_p1_reg(client, DP_INT_STA, &val);
 726
 727         /* Check AUX CH error access status */
 728         anx6345_i2c_read_p0_reg(client, AUX_CH_STA, &val);
 729         if ((val & AUX_STATUS_MASK) != 0) {
 730                 dev_err(&client->dev, "AUX CH error happens: %d\n\n",
 731                         val & AUX_STATUS_MASK);
 732                 return -EREMOTEIO;
 733         }
 734
 735         return retval;
 736 }
 737
 738 int anx6345_dpcd_write_bytes(struct i2c_client *client,
 739                                 unsigned int val_addr,
 740                                 unsigned int count,
 741                                 unsigned char data[])
 742 {
 743         char val;
 744         unsigned int start_offset;
 745         unsigned int cur_data_count;
 746         unsigned int cur_data_idx;
 747         int retval = 0;
 748
 749         start_offset = 0;
 750         while (start_offset < count) {
 751                 /* Buffer size of AUX CH is 16 * 4bytes */
 752                 if ((count - start_offset) > 16)
 753                         cur_data_count = 16;
 754                 else
 755                         cur_data_count = count - start_offset;
 756
 757                 val = BUF_CLR;
 758                 anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
 759
 760                 val = AUX_ADDR_7_0(val_addr + start_offset);
 761                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 762                 val = AUX_ADDR_15_8(val_addr + start_offset);
 763                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 764                 val = AUX_ADDR_19_16(val_addr + start_offset);
 765                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 766
 767                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 768                      cur_data_idx++) {
 769                         val = data[start_offset + cur_data_idx];
 770                         anx6345_i2c_write_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 771                 }
 772
 773                 /*
 774                  * Set DisplayPort transaction and write
 775                  * If bit 3 is 1, DisplayPort transaction.
 776                  * If Bit 3 is 0, I2C transaction.
 777                  */
 778                 val = AUX_LENGTH(cur_data_count) |
 779                         AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 780                 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 781
 782                 /* Start AUX transaction */
 783                 retval = anx6345_start_aux_transaction(client);
 784                 if (retval == 0)
 785                         break;
 786                 else
 787                         dev_dbg(&client->dev, "Aux Transaction fail!\n");
 788
 789
 790                 start_offset += cur_data_count;
 791         }
 792
 793         return retval;
 794 }
 795
 796
 797 int anx6345_dpcd_read_bytes(struct i2c_client *client,
 798                                 unsigned int val_addr,
 799                                 unsigned int count,
 800                                 unsigned char data[])
 801 {
 802         char val;
 803         unsigned int start_offset;
 804         unsigned int cur_data_count;
 805         unsigned int cur_data_idx;
 806         int i;
 807         int retval = 0;
 808
 809         start_offset = 0;
 810         while (start_offset < count) {
 811                 /* Buffer size of AUX CH is 16 * 4bytes */
 812                 if ((count - start_offset) > 16)
 813                         cur_data_count = 16;
 814                 else
 815                         cur_data_count = count - start_offset;
 816
 817                 /* AUX CH Request Transaction process */
 818                 for (i = 0; i < 10; i++) {
 819                         /* Select DPCD device address */
 820                         val = AUX_ADDR_7_0(val_addr + start_offset);
 821                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 822                         val = AUX_ADDR_15_8(val_addr + start_offset);
 823                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 824                         val = AUX_ADDR_19_16(val_addr + start_offset);
 825                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 826
 827                         /*
 828                          * Set DisplayPort transaction and read
 829                          * If bit 3 is 1, DisplayPort transaction.
 830                          * If Bit 3 is 0, I2C transaction.
 831                          */
 832                         val = AUX_LENGTH(cur_data_count) |
 833                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 834                         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 835
 836                         val = BUF_CLR;
 837                         anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
 838
 839                         /* Start AUX transaction */
 840                         retval = anx6345_start_aux_transaction(client);
 841                         if (retval == 0)
 842                                 break;
 843                         else
 844                                 dev_dbg(&client->dev, "Aux Transaction fail!\n");
 845                 }
 846
 847                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 848                     cur_data_idx++) {
 849                         anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 850                         data[start_offset + cur_data_idx] = val;
 851                         dev_dbg(&client->dev, "0x%05x :0x%02x\n",cur_data_idx, val);
 852                 }
 853
 854                 start_offset += cur_data_count;
 855         }
 856
 857         return retval;
 858 }
 859
 860
 861 int anx6345_select_i2c_device(struct i2c_client *client,
 862                                 unsigned int device_addr,
 863                                 char val_addr)
 864 {
 865         char val;
 866         int retval;
 867
 868         /* Set normal AUX CH command */
 869         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 870         val &= ~ADDR_ONLY;
 871         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 872         /* Set EDID device address */
 873         val = device_addr;
 874         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 875         val = 0;
 876         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 877         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 878
 879         /* Set offset from base address of EDID device */
 880         anx6345_i2c_write_p0_reg(client, BUF_DATA_0, &val_addr);
 881
 882         /*
 883          * Set I2C transaction and write address
 884          * If bit 3 is 1, DisplayPort transaction.
 885          * If Bit 3 is 0, I2C transaction.
 886          */
 887         val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 888                 AUX_TX_COMM_WRITE;
 889         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 890
 891         /* Start AUX transaction */
 892         retval = anx6345_start_aux_transaction(client);
 893         if (retval != 0)
 894                 dev_dbg(&client->dev, "Aux Transaction fail!\n");
 895
 896         return retval;
 897 }
 898
 899 int anx6345_edid_read_bytes(struct i2c_client *client,
 900                                 unsigned int device_addr,
 901                                 unsigned int val_addr,
 902                                 unsigned char count,
 903                                 unsigned char edid[])
 904 {
 905         char val;
 906         unsigned int i;
 907         unsigned int start_offset;
 908         unsigned int cur_data_idx;
 909         unsigned int cur_data_cnt;
 910         unsigned int defer = 0;
 911         int retval = 0;
 912
 913         for (i = 0; i < count; i += 16) {
 914                 start_offset = i;
 915                 if ((count - start_offset) > 16)
 916                                 cur_data_cnt = 16;
 917                         else
 918                                 cur_data_cnt = count - start_offset;
 919                 /*
 920                  * If Rx sends defer, Tx sends only reads
 921                  * request without sending addres
 922                  */
 923                 if (!defer)
 924                         retval = anx6345_select_i2c_device(client,
 925                                         device_addr, val_addr + i);
 926                 else
 927                         defer = 0;
 928
 929                 /*
 930                  * Set I2C transaction and write data
 931                  * If bit 3 is 1, DisplayPort transaction.
 932                  * If Bit 3 is 0, I2C transaction.
 933                  */
 934                 val = AUX_LENGTH(cur_data_cnt) | AUX_TX_COMM_I2C_TRANSACTION |
 935                         AUX_TX_COMM_READ;
 936                 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 937
 938                 /* Start AUX transaction */
 939                 retval = anx6345_start_aux_transaction(client);
 940                 if (retval < 0)
 941                         dev_dbg(&client->dev, "Aux Transaction fail!\n");
 942
 943                 /* Check if Rx sends defer */
 944                 anx6345_i2c_read_p0_reg(client, DP_AUX_RX_COMM, &val);
 945                 if (val == AUX_RX_COMM_AUX_DEFER ||
 946                         val == AUX_RX_COMM_I2C_DEFER) {
 947                         dev_err(&client->dev, "Defer: %d\n\n", val);
 948                         defer = 1;
 949                 }
 950
 951
 952                 for (cur_data_idx = 0; cur_data_idx < cur_data_cnt; cur_data_idx++) {
 953                         anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 954                         edid[i + cur_data_idx] = val;
 955                         dev_dbg(&client->dev, "0x%02x : 0x%02x\n", i + cur_data_idx, val);
 956                 }
 957         }
 958
 959         return retval;
 960 }
 961
 962 static int anx6345_read_edid(struct i2c_client *client)
 963 {
 964         unsigned char edid[EDID_LENGTH * 2];
 965         unsigned char extend_block = 0;
 966         unsigned char sum;
 967         unsigned char test_vector;
 968         int retval;
 969         char addr;
 970         struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
 971
 972
 973         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 974         retval = anx6345_edid_read_bytes(client, EDID_ADDR,
 975                                 EDID_EXTENSION_FLAG,1,&extend_block);
 976         if (retval < 0) {
 977                 dev_err(&client->dev, "EDID extension flag failed!\n");
 978                 return -EIO;
 979         }
 980
 981         if (extend_block > 0) {
 982                 dev_dbg(&client->dev, "EDID data includes a single extension!\n");
 983
 984                 /* Read EDID data */
 985                 retval = anx6345_edid_read_bytes(client, EDID_ADDR,
 986                                                 EDID_HEADER,
 987                                                 EDID_LENGTH,
 988                                                 &edid[EDID_HEADER]);
 989                 if (retval != 0) {
 990                         dev_err(&client->dev, "EDID Read failed!\n");
 991                         return -EIO;
 992                 }
 993                 sum = edp_calc_edid_check_sum(edid);
 994                 if (sum != 0) {
 995                         dev_warn(&client->dev, "EDID bad checksum!\n");
 996                         return 0;
 997                 }
 998
 999                 /* Read additional EDID data */
1000                 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_LENGTH,
1001                                                         EDID_LENGTH, &edid[EDID_LENGTH]);
1002                 if (retval != 0) {
1003                         dev_err(&client->dev, "EDID Read failed!\n");
1004                         return -EIO;
1005                 }
1006                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
1007                 if (sum != 0) {
1008                         dev_warn(&client->dev, "EDID bad checksum!\n");
1009                         return 0;
1010                 }
1011
1012                 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1013                                                 1, &test_vector);
1014                 if (retval < 0) {
1015                         dev_err(&client->dev, "DPCD EDID Read failed!\n");
1016                         return retval;
1017                 }
1018
1019                 if (test_vector & DPCD_TEST_EDID_READ) {
1020                         retval = anx6345_dpcd_write_bytes(client,
1021                                         DPCD_TEST_EDID_CHECKSUM,1,
1022                                         &edid[EDID_LENGTH + EDID_CHECKSUM]);
1023                         if (retval < 0) {
1024                                 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1025                                 return retval;
1026                         }
1027
1028                         addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1029                         retval = anx6345_dpcd_write_bytes(client,
1030                                         DPCD_TEST_RESPONSE, 1, &addr);
1031                         if (retval < 0) {
1032                                 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1033                                 return retval;
1034                         }
1035                 }
1036         } else {
1037                 dev_info(&client->dev, "EDID data does not include any extensions.\n");
1038
1039                 /* Read EDID data */
1040                 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_HEADER,
1041                                           EDID_LENGTH, &edid[EDID_HEADER]);
1042                 if (retval != 0) {
1043                         dev_err(&client->dev, "EDID Read failed!\n");
1044                         return -EIO;
1045                 }
1046
1047                 sum = edp_calc_edid_check_sum(edid);
1048                 if (sum != 0) {
1049                         dev_warn(&client->dev, "EDID bad checksum!\n");
1050                         return 0;
1051                 }
1052
1053                 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1054                                                 1,&test_vector);
1055                 if (retval < 0) {
1056                         dev_err(&client->dev, "DPCD EDID Read failed!\n");
1057                         return retval;
1058                 }
1059
1060                 if (test_vector & DPCD_TEST_EDID_READ) {
1061                         retval = anx6345_dpcd_write_bytes(client,
1062                                         DPCD_TEST_EDID_CHECKSUM, 1,
1063                                         &edid[EDID_CHECKSUM]);
1064                         if (retval < 0) {
1065                                 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1066                                 return retval;
1067                         }
1068                         addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1069                         retval = anx6345_dpcd_write_bytes(client, DPCD_TEST_RESPONSE,
1070                                         1, &addr);
1071                         if (retval < 0) {
1072                                 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1073                                 return retval;
1074                         }
1075                 }
1076         }
1077         fb_edid_to_monspecs(edid, &anx6345->specs);
1078         dev_info(&client->dev, "EDID Read success!\n");
1079         return 0;
1080 }
1081
1082 static int anx6345_init(struct i2c_client *client)
1083 {
1084         char val = 0x00;
1085         char i = 0;
1086         char lc,bw;
1087         char cnt = 50;
1088         u8 buf[12];
1089
1090         val = 0x30;
1091         anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
1092
1093         //clock detect
1094         for(i=0;i<50;i++)
1095         {
1096
1097                 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1098                 anx6345_i2c_write_p0_reg(client, SYS_CTRL1_REG, &val);
1099                 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1100                 if((val&SYS_CTRL1_DET_STA)!=0)
1101                 {
1102                         break;
1103                 }
1104
1105                 mdelay(10);
1106         }
1107         if(i>49)
1108                 printk("no clock detected by anx6345\n");
1109
1110         //check whether clock is stable
1111         for(i=0;i<50;i++)
1112         {
1113                 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1114                 anx6345_i2c_write_p0_reg(client,SYS_CTRL2_REG, &val);
1115                 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1116                 if((val&SYS_CTRL2_CHA_STA)==0)
1117                 {
1118                         break;
1119                 }
1120                 mdelay(10);
1121         }
1122         if(i>49)
1123                 printk("clk is not stable\n");
1124
1125         anx6345_dpcd_read_bytes(client, DPCD_REV, 12, buf);
1126         anx6345_read_edid(client);
1127
1128         //VESA range, 6bits BPC, RGB
1129         val = 0x00;
1130         anx6345_i2c_write_p1_reg(client, VID_CTRL2_REG, &val);
1131
1132         //ANX6345 chip pll setting
1133         val = 0x00;
1134         anx6345_i2c_write_p0_reg(client, PLL_CTRL_REG, &val);                  //UPDATE: FROM 0X07 TO 0X00
1135
1136
1137         //ANX chip analog setting
1138         val = 0x70;
1139         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);               //UPDATE: FROM 0XF0 TO 0X70
1140         val = 0x30;
1141         anx6345_i2c_write_p0_reg(client, LINK_DEBUG_REG, &val);
1142
1143         //force HPD
1144         //anx6345_i2c_write_p0_reg(client, SYS_CTRL3_REG, &val);
1145
1146
1147         //reset AUX
1148         anx6345_i2c_read_p1_reg(client, RST_CTRL2_REG, &val);
1149         val |= AUX_RST;
1150         anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1151         val &= ~AUX_RST;
1152         anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1153
1154         //Select 2.7G
1155         val = 0x0a;
1156         anx6345_i2c_write_p0_reg(client, LINK_BW_SET_REG, &val);
1157         //Select 2 lanes
1158         val = 0x02;
1159         anx6345_i2c_write_p0_reg(client,LANE_COUNT_SET_REG,&val);
1160
1161         val = LINK_TRAINING_CTRL_EN;
1162         anx6345_i2c_write_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1163         mdelay(5);
1164         anx6345_i2c_read_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1165         while((val&0x80)&&(cnt))                                                                                //UPDATE: FROM 0X01 TO 0X80
1166         {
1167                 printk("Waiting...\n");
1168                 mdelay(5);
1169                 anx6345_i2c_read_p0_reg(client,LINK_TRAINING_CTRL_REG,&val);
1170                 cnt--;
1171         }
1172         if(cnt <= 0)
1173         {
1174                 printk(KERN_INFO "HW LT fail\n");
1175         }
1176         else
1177                 printk("HW LT Success>>:times:%d\n",(51-cnt));
1178
1179
1180
1181         //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
1182         //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
1183
1184 #if defined(BIST_MODE)
1185         anx6345_bist_mode(client);
1186         val = 0x8f;
1187 #else
1188         val = 0x81;
1189 #endif
1190         anx6345_i2c_write_p1_reg(client,VID_CTRL1_REG,&val);
1191
1192         anx_video_map_config(client);
1193         //force HPD and stream valid
1194         val = 0x33;
1195         anx6345_i2c_write_p0_reg(client,SYS_CTRL3_REG,&val);
1196
1197         anx6345_i2c_read_p0_reg(client,LANE_COUNT_SET_REG, &lc);
1198         anx6345_i2c_read_p0_reg(client,LINK_BW_SET_REG, &bw);
1199         printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
1200
1201         return 0;
1202 }
1203
1204
1205 static int  anx6345_disable(void)
1206 {
1207         struct edp_anx6345 *anx6345 = edp;
1208
1209         if (!anx6345->pdata->pwron)
1210                 return 0;
1211         gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
1212         gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
1213         anx6345->pdata->pwron = false;
1214
1215         return 0;
1216
1217 }
1218
1219
1220 static int anx6345_enable(void)
1221 {
1222         struct edp_anx6345 *anx6345 = edp;
1223
1224         if (!anx6345->pdata->pwron) {
1225                 gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
1226                 msleep(5);
1227                 gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
1228                 gpio_set_value(anx6345->pdata->edp_rst_pin,0);
1229                 msleep(50);
1230                 gpio_set_value(anx6345->pdata->edp_rst_pin,1);
1231                 anx6345->pdata->pwron = true;
1232         }
1233         anx6345->edp_anx_init(anx6345->client);
1234         return 0;
1235 }
1236 #ifdef CONFIG_HAS_EARLYSUSPEND
1237 static void anx6345_early_suspend(struct early_suspend *h)
1238 {
1239         anx6345_disable();
1240 }
1241
1242 static void anx6345_late_resume(struct early_suspend *h)
1243 {
1244         anx6345_enable();
1245 }
1246 #endif
1247
1248 #if defined(CONFIG_OF)
1249
1250 static int anx6345_power_ctl(struct anx6345_platform_data  *pdata)
1251 {
1252        int ret;
1253        ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
1254        if (ret != 0) {
1255                gpio_free(pdata->dvdd33_en_pin);
1256                printk(KERN_ERR "request dvdd33 en pin fail!\n");
1257                return -1;
1258        } else {
1259                gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
1260        }
1261        mdelay(5);
1262
1263        ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
1264        if (ret != 0) {
1265                gpio_free(pdata->dvdd18_en_pin);
1266                printk(KERN_ERR "request dvdd18 en pin fail!\n");
1267                return -1;
1268        } else {
1269                gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
1270        }
1271
1272        ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
1273        if (ret != 0) {
1274                gpio_free(pdata->edp_rst_pin);
1275                printk(KERN_ERR "request rst pin fail!\n");
1276                return -1;
1277        } else {
1278                gpio_direction_output(pdata->edp_rst_pin, 0);
1279                msleep(50);
1280                gpio_direction_output(pdata->edp_rst_pin, 1);
1281        }
1282        pdata->pwron = true;
1283        return 0;
1284
1285 }
1286
1287
1288 struct rk_fb_trsm_ops  trsm_edp_ops = {
1289         .enable = anx6345_enable,
1290         .disable = anx6345_disable,
1291
1292 };
1293 static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
1294 {
1295         struct device_node *np = anx6345->client->dev.of_node;
1296         struct anx6345_platform_data *pdata;
1297         enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
1298         pdata = devm_kzalloc(&anx6345->client->dev,
1299                         sizeof(struct anx6345_platform_data ), GFP_KERNEL);
1300         if (!pdata) {
1301                 dev_err(&anx6345->client->dev,
1302                         "failed to allocate platform data\n");
1303                 return ;
1304         }
1305         pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
1306         pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
1307         pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
1308         pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1309         pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1310         pdata->power_ctl = anx6345_power_ctl;
1311         anx6345->pdata = pdata;
1312
1313 }
1314 #else
1315 static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
1316 {
1317
1318 }
1319 #endif
1320 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
1321 {
1322         struct edp_anx6345 *anx6345;
1323         int chip_id;
1324
1325
1326         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1327         {
1328                 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
1329                 return -ENODEV;
1330         }
1331         anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
1332                                 GFP_KERNEL);
1333         if (unlikely(!anx6345)) {
1334                 dev_err(&client->dev, "alloc for struct anx6345 fail\n");
1335                 return -ENOMEM;
1336         }
1337
1338         anx6345->client = client;
1339         anx6345->pdata = dev_get_platdata(&client->dev);
1340         if (!anx6345->pdata) {
1341                 anx6345_parse_dt(anx6345);
1342         }
1343         i2c_set_clientdata(client,anx6345);
1344         rk_fb_get_prmry_screen(&anx6345->screen);
1345         if (anx6345->screen.type != SCREEN_EDP){
1346                 dev_err(&client->dev, "screen is not edp!\n");
1347                 return -EINVAL;
1348         }
1349         if(anx6345->pdata->power_ctl)
1350                 anx6345->pdata->power_ctl(anx6345->pdata);
1351
1352 #if defined(CONFIG_DEBUG_FS)
1353         anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
1354         if (IS_ERR(anx6345->debugfs_dir)) {
1355                 dev_err(&client->dev, "failed to create debugfs dir for edp!\n");
1356         }
1357         else
1358                 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
1359 #endif
1360
1361 #ifdef CONFIG_HAS_EARLYSUSPEND
1362         anx6345->early_suspend.suspend = anx6345_early_suspend;
1363         anx6345->early_suspend.resume = anx6345_late_resume;
1364         anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
1365         register_early_suspend(&anx6345->early_suspend);
1366 #endif
1367         chip_id = get_dp_chip_id(client);
1368         if(chip_id == 0x9805)
1369                 anx6345->edp_anx_init = anx980x_init;
1370         else
1371                 anx6345->edp_anx_init = anx6345_init;
1372         edp = anx6345;
1373
1374         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1375
1376         dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
1377
1378         return 0;
1379 }
1380
1381 static int  anx6345_i2c_remove(struct i2c_client *client)
1382 {
1383         return 0;
1384 }
1385
1386 static const struct i2c_device_id id_table[] = {
1387         {"anx6345", 0 },
1388         { }
1389 };
1390
1391 #if defined(CONFIG_OF)
1392 static struct of_device_id anx6345_dt_ids[] = {
1393         { .compatible = "analogix, anx6345" },
1394         { }
1395 };
1396 #endif
1397
1398 static struct i2c_driver anx6345_i2c_driver  = {
1399         .driver = {
1400                 .name  = "anx6345",
1401                 .owner = THIS_MODULE,
1402 #if defined(CONFIG_OF)
1403                 .of_match_table = of_match_ptr(anx6345_dt_ids),
1404 #endif
1405         },
1406         .probe          = &anx6345_i2c_probe,
1407         .remove         = &anx6345_i2c_remove,
1408         .id_table       = id_table,
1409 };
1410
1411
1412 static int __init anx6345_module_init(void)
1413 {
1414         return i2c_add_driver(&anx6345_i2c_driver);
1415 }
1416
1417 static void __exit anx6345_module_exit(void)
1418 {
1419         i2c_del_driver(&anx6345_i2c_driver);
1420 }
1421
1422 fs_initcall(anx6345_module_init);
1423 module_exit(anx6345_module_exit);
1424