drivers/video/rockchip/transmitter/dp_anx6345.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/time.h>
   4 #include <linux/delay.h>
   5 #include <linux/slab.h>
   6 #include <linux/device.h>
   7 #include <linux/i2c.h>
   8 #include <linux/gpio.h>
   9 #include <linux/anx6345.h>
  10
  11 #if defined(CONFIG_DEBUG_FS)
  12 #include <linux/fs.h>
  13 #include <linux/debugfs.h>
  14 #include <linux/seq_file.h>
  15 #endif
  16
  17
  18 //#define BIST_MODE 0
  19
  20 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
  21 {
  22         int ret;
  23         client->addr = DP_TX_PORT0_ADDR >> 1;
  24         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  25         if(ret < 0)
  26         {
  27                 printk(KERN_ERR "%s>>err\n",__func__);
  28         }
  29
  30         return ret;
  31 }
  32 static int  anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
  33 {
  34         int ret;
  35         client->addr = DP_TX_PORT0_ADDR >> 1;
  36         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  37         if(ret < 0)
  38         {
  39                 printk(KERN_ERR "%s>>err\n",__func__);
  40         }
  41
  42         return ret;
  43 }
  44 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
  45 {
  46         int ret;
  47         client->addr = HDMI_TX_PORT0_ADDR >> 1;
  48         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  49         if(ret < 0)
  50         {
  51                 printk(KERN_ERR "%s>>err\n",__func__);
  52         }
  53
  54         return ret;
  55 }
  56
  57 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
  58 {
  59         int ret;
  60         client->addr = HDMI_TX_PORT0_ADDR >> 1;
  61         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  62         if(ret < 0)
  63         {
  64                 printk(KERN_ERR "%s>>err\n",__func__);
  65         }
  66
  67         return ret;
  68 }
  69
  70 #if defined(CONFIG_DEBUG_FS)
  71 static int edp_reg_show(struct seq_file *s, void *v)
  72 {
  73         int i = 0;
  74         char val;
  75         struct edp_anx6345 *anx6345 = s->private;
  76         if(!anx6345)
  77         {
  78                 printk(KERN_ERR "no edp device!\n");
  79                 return 0;
  80         }
  81
  82         seq_printf(s,"0x70:\n");
  83         for(i=0;i< MAX_REG;i++)
  84         {
  85                 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
  86                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
  87         }
  88
  89
  90         seq_printf(s,"\n0x72:\n");
  91         for(i=0;i< MAX_REG;i++)
  92         {
  93                 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
  94                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
  95         }
  96         return 0;
  97 }
  98
  99 static int edp_reg_open(struct inode *inode, struct file *file)
 100 {
 101         struct edp_anx6345 *anx6345 = inode->i_private;
 102         return single_open(file, edp_reg_show, anx6345);
 103 }
 104
 105 static const struct file_operations edp_reg_fops = {
 106         .owner          = THIS_MODULE,
 107         .open           = edp_reg_open,
 108         .read           = seq_read,
 109         .llseek         = seq_lseek,
 110         .release        = single_release,
 111 };
 112 #endif
 113
 114 //get chip ID. Make sure I2C is OK
 115 static int get_dp_chip_id(struct i2c_client *client)
 116 {
 117         char c1,c2;
 118         int id;
 119         anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1);
 120         anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2);
 121         id = c2;
 122         return (id<<8)|c1;
 123 }
 124
 125
 126 static int anx980x_bist_mode(struct i2c_client *client)
 127 {
 128         char val,i;
 129         u8 cnt=0;
 130
 131         //Power on total and select DP mode
 132         val = 00;
 133         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 134
 135         //HW reset
 136         val = DP_TX_RST_HW_RST;
 137         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 138         msleep(10);
 139         val = 0x00;
 140         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 141
 142
 143         anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 144         val = 0x00;
 145         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 146
 147
 148         //get chip ID. Make sure I2C is OK
 149         anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
 150         if (val==0x98)
 151                 printk("Chip found\n");
 152
 153         //for clocl detect
 154         for(i=0;i<100;i++)
 155         {
 156                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 157                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 158                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 159                 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
 160                 {
 161                         printk("clock is detected.\n");
 162                         break;
 163                 }
 164
 165                 msleep(10);
 166         }
 167        //check whther clock is stable
 168         for(i=0;i<50;i++)
 169         {
 170                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 171                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 172                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 173                 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
 174                 {
 175                         printk("clock is stable.\n");
 176                         break;
 177                 }
 178                 msleep(10);
 179         }
 180
 181         //VESA range, 8bits BPC, RGB
 182         val = 0x10;
 183         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
 184         //RK_EDP chip analog setting
 185         val = 0x07;
 186         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 187         val = 0x19;
 188         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 189         val = 0xd9;
 190         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 191
 192         //Select AC mode
 193         val = 0x40;
 194         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 195
 196         //RK_EDP chip analog setting
 197         val = 0xf0;
 198         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 199         val = 0x99;
 200         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 201         val = 0x7b;
 202         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 203         val = 0x30;
 204         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 205         val = 0x06;
 206         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
 207
 208         //force HPD
 209         val = 0x30;
 210         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
 211         //power on 4 lanes
 212         val = 0x00;
 213         anx6345_i2c_write_p0_reg(client, 0xc8, &val);
 214         //lanes setting
 215         anx6345_i2c_write_p0_reg(client, 0xa3, &val);
 216         anx6345_i2c_write_p0_reg(client, 0xa4, &val);
 217         anx6345_i2c_write_p0_reg(client, 0xa5,&val);
 218         anx6345_i2c_write_p0_reg(client, 0xa6, &val);
 219
 220         //reset AUX CH
 221         val = 0x44;
 222         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 223         val = 0x40;
 224         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 225
 226         //Select 1.62G
 227         val = 0x06;
 228         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 229         //Select 4 lanes
 230         val = 0x04;
 231         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 232
 233         //strart link traing
 234         //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
 235         #if 1
 236         val = DP_TX_LINK_TRAINING_CTRL_EN;
 237         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 238         msleep(5);
 239         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 240         while((val&0x01)&&(cnt++ < 10))
 241         {
 242                 printk("Waiting...\n");
 243                 msleep(5);
 244                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 245         }
 246
 247         if(cnt >= 10)
 248         {
 249                 printk(KERN_INFO "HW LT fail\n");
 250         }
 251         else
 252         {
 253                 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
 254         }
 255         #else
 256         DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
 257         #endif
 258         //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
 259
 260         //Set bist format 2048x1536
 261         val = 0x2c;
 262         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
 263         val = 0x06;
 264         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
 265
 266         val = 0x00;
 267         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
 268         val = 0x06;
 269         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
 270         val = 0x02;
 271         anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
 272         val = 0x04;
 273         anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
 274         val = 0x26;
 275         anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
 276         val = 0x50;
 277         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
 278         val = 0x04;
 279         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
 280         val = 0x00;
 281         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
 282         val = 0x04;
 283         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
 284
 285         val = 0x18;
 286         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
 287         val = 0x00;
 288         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
 289
 290         val = 0x10;
 291         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
 292         val = 0x00;
 293         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
 294         val = 0x28;
 295         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
 296         val = 0x00;
 297         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
 298         val = 0x03;
 299         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
 300
 301         //enable BIST
 302         val = DP_TX_VID_CTRL4_BIST;
 303         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
 304         //enable video input
 305         val = 0x8d;
 306         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 307         //force HPD and stream valid
 308         val = 0x33;
 309         anx6345_i2c_write_p0_reg(client, 0x82, &val);
 310
 311         return 0;
 312 }
 313
 314 static int anx980x_aux_rst(struct i2c_client *client)
 315 {
 316         char val;
 317         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 318         val |= DP_TX_AUX_RST;
 319         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 320         val &= ~DP_TX_AUX_RST;
 321         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 322         return 0;
 323 }
 324
 325
 326 static int anx980x_wait_aux_finished(struct i2c_client *client)
 327 {
 328         char val,cnt;
 329         cnt = 0;
 330
 331         anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
 332         while(val&0x01)
 333         {
 334                 //delay_ms(20);
 335                 cnt ++;
 336                 if(cnt == 10)
 337                 {
 338                    printk("aux break");
 339                     anx980x_aux_rst(client);
 340                     //cnt = 0;
 341                     break;
 342                 }
 343                 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
 350 {
 351         char val,i;
 352
 353         val = 0x80;
 354         anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
 355
 356         //set read cmd and count
 357         val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
 358         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
 359
 360         //set aux address15:0
 361         val = (char)addr&0xff;
 362         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
 363         val = (char)((addr>>8)&0xff);
 364         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
 365
 366         //set address19:16 and enable aux
 367         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 368         val &=(0xf0)|(char)((addr>>16)&0xff);
 369         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 370
 371         //Enable Aux
 372         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 373         val |= 0x01;
 374         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 375
 376         //delay_ms(2);
 377         anx980x_wait_aux_finished(client);
 378
 379         for(i =0;i<cCount;i++)
 380         {
 381                 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
 382
 383                 //debug_printf("c = %.2x\n",(WORD)c);
 384                 *(pBuf+i) = val;
 385
 386                 if(i >= MAX_BUF_CNT)
 387                         return 1;
 388                         //break;
 389         }
 390
 391         return 0;
 392
 393
 394 }
 395
 396 static int anx_video_map_config(struct i2c_client *client)
 397 {
 398         char val = 0;
 399         char i = 0;
 400         anx6345_i2c_write_p1_reg(client,  0x40, &val);
 401         anx6345_i2c_write_p1_reg(client,  0x41, &val);
 402         anx6345_i2c_write_p1_reg(client,  0x48, &val);
 403         anx6345_i2c_write_p1_reg(client,  0x49, &val);
 404         anx6345_i2c_write_p1_reg(client,  0x50, &val);
 405         anx6345_i2c_write_p1_reg(client,  0x51, &val);
 406         for(i=0; i<6; i++)
 407         {
 408                 val = i;
 409                 anx6345_i2c_write_p1_reg(client,  0x42+i, &val);
 410         }
 411
 412         for(i=0; i<6; i++)
 413         {
 414                 val = 6+i;
 415                 anx6345_i2c_write_p1_reg(client,  0x4a+i, &val);
 416         }
 417
 418         for(i=0; i<6; i++)
 419         {
 420                 val = 0x0c+i;
 421                 anx6345_i2c_write_p1_reg(client,  0x52+i, &val);
 422         }
 423
 424         return 0;
 425
 426 }
 427 static int anx980x_eanble_video_input(struct i2c_client *client)
 428 {
 429         char val;
 430
 431         anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 432         val |= DP_TX_VID_CTRL1_VID_EN;
 433         anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 434
 435         anx_video_map_config(client);
 436
 437         return 0;
 438 }
 439
 440 static int anx980x_init(struct i2c_client *client)
 441 {
 442         char val = 0x00;
 443         char safe_mode = 0;
 444         char ByteBuf[2];
 445         char dp_tx_bw,dp_tx_lane_count;
 446         char cnt = 10;
 447
 448 #if defined(BIST_MODE)
 449         return anx980x_bist_mode(client);
 450 #endif
 451          //power on all block and select DisplayPort mode
 452         val |= DP_POWERD_AUDIO_REG;
 453         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
 454
 455         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 456         val &= ~DP_TX_VID_CTRL1_VID_EN;
 457         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 458
 459         //software reset
 460         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 461         val |= DP_TX_RST_SW_RST;
 462         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
 463         val &= ~DP_TX_RST_SW_RST;
 464         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 465
 466
 467         val = 0x07;
 468         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 469         val = 0x50;
 470         anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
 471
 472         //24bit SDR,negedge latch, and wait video stable
 473         val = 0x01;
 474         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
 475         val = 0x19;
 476         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 477         val = 0xd9;
 478         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 479
 480         //serdes ac mode.
 481         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 482         val |= DP_TX_AC_MODE;
 483         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 484
 485         //set termination
 486         val = 0xf0;
 487         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 488         //set duty cycle
 489         val = 0x99;
 490         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 491
 492         anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 493         val |= 0x2a;
 494         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 495
 496         //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
 497         val = 0x30;
 498         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 499
 500         //for DP link CTS
 501         anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 502         val |= 0x40;
 503         anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 504
 505         //power down  PLL filter
 506         val = 0x06;
 507         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
 508
 509         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
 510         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
 511         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
 512         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
 513
 514         val = 0x06;
 515         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 516         val = 0x04;
 517         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 518
 519         val = DP_TX_LINK_TRAINING_CTRL_EN;
 520         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
 521         msleep(2);
 522         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 523         while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
 524         {
 525                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 526                 cnt--;
 527         }
 528         if(cnt < 0)
 529         {
 530                 printk(KERN_INFO "HW LT fail\n");
 531         }
 532         else
 533                 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
 534         //DP_TX_Config_Video(client);
 535         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 536         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL1_REG, &val);
 537         if(!(val & DP_TX_SYS_CTRL1_DET_STA))
 538         {
 539                 printk("No pclk\n");
 540                 //return;  //mask by yxj
 541         }
 542
 543         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 544         anx6345_i2c_write_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 545         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 546         if(val & DP_TX_SYS_CTRL2_CHA_STA)
 547         {
 548                 printk("pclk not stable!\n");
 549                 //return; mask by yxj
 550         }
 551
 552         anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
 553         dp_tx_bw = ByteBuf[0];
 554         dp_tx_lane_count = ByteBuf[1] & 0x0f;
 555         printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
 556
 557         if(!safe_mode)
 558         {
 559                 //set Input BPC mode & color space
 560                 anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 561                 val &= 0x8c;
 562                 val = val |((char)(0) << 4);  //8bits  ,rgb
 563                 anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 564         }
 565
 566
 567
 568         //enable video input
 569          anx980x_eanble_video_input(client);
 570
 571         return 0;
 572 }
 573
 574 static int anx6345_bist_mode(struct i2c_client *client)
 575 {
 576         char val = 0x00;
 577         //these register are for bist mode
 578         val = 0x2c;
 579         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
 580         val = 0x06;
 581         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
 582         val = 0x00;
 583         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
 584         val = 0x06;
 585         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
 586         val = 0x02;
 587         anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
 588         val = 0x04;
 589         anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
 590         val = 0x26;
 591         anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
 592         val = 0x50;
 593         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
 594         val = 0x04;
 595         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
 596         val = 0x00;
 597         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
 598         val = 0x04;
 599         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
 600         val = 0x18;
 601         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
 602         val = 0x00;
 603         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
 604         val = 0x10;
 605         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
 606         val = 0x00;
 607         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
 608         val = 0x28;
 609         anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
 610         val = 0x13;
 611         anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
 612
 613
 614        //enable BIST. In normal mode, don't need to config this reg
 615         val = 0x08;
 616         anx6345_i2c_write_p1_reg(client, 0x0b, &val);
 617         printk("anx6345 enter bist mode\n");
 618
 619         return 0;
 620 }
 621 static int anx6345_init(struct i2c_client *client)
 622 {
 623         char val = 0x00;
 624         char i = 0;
 625         char lc,bw;
 626         char cnt = 50;
 627
 628         val = 0x30;
 629         anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
 630
 631         //clock detect
 632         for(i=0;i<50;i++)
 633         {
 634
 635                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 636                 anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 637                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 638                 if((val&SP_TX_SYS_CTRL1_DET_STA)!=0)
 639                 {
 640                         break;
 641                 }
 642
 643                 mdelay(10);
 644         }
 645         if(i>49)
 646                 printk("no clock detected by anx6345\n");
 647
 648         //check whether clock is stable
 649         for(i=0;i<50;i++)
 650         {
 651                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
 652                 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val);
 653                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
 654                 if((val&SP_TX_SYS_CTRL2_CHA_STA)==0)
 655                 {
 656                         break;
 657                 }
 658                 mdelay(10);
 659         }
 660         if(i>49)
 661                 printk("clk is not stable\n");
 662
 663         //VESA range, 6bits BPC, RGB
 664         val = 0x00;
 665         anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val);
 666
 667         //ANX6345 chip pll setting
 668         val = 0x00;
 669         anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val);                  //UPDATE: FROM 0X07 TO 0X00
 670
 671
 672         //ANX chip analog setting
 673         val = 0x70;
 674         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);               //UPDATE: FROM 0XF0 TO 0X70
 675         val = 0x30;
 676         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val);
 677
 678         //force HPD
 679         //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val);
 680
 681
 682         //reset AUX
 683         anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 684         val |= SP_TX_AUX_RST;
 685         anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 686         val &= ~SP_TX_AUX_RST;
 687         anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 688
 689         //Select 2.7G
 690         val = 0x0a;
 691         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val);
 692         //Select 2 lanes
 693         val = 0x02;
 694         anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val);
 695
 696         val = SP_TX_LINK_TRAINING_CTRL_EN;
 697         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
 698         mdelay(5);
 699         anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
 700         while((val&0x80)&&(cnt))                                                                                //UPDATE: FROM 0X01 TO 0X80
 701         {
 702                 printk("Waiting...\n");
 703                 mdelay(5);
 704                 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val);
 705                 cnt--;
 706         }
 707         if(cnt <= 0)
 708         {
 709                 printk(KERN_INFO "HW LT fail\n");
 710         }
 711         else
 712                 printk("HW LT Success>>:times:%d\n",(51-cnt));
 713
 714
 715
 716         //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
 717         //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
 718
 719 #if defined(BIST_MODE)
 720         anx6345_bist_mode(client);
 721         val = 0x8f;
 722 #else
 723         val = 0x81;
 724 #endif
 725         anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val);
 726
 727         anx_video_map_config(client);
 728         //force HPD and stream valid
 729         val = 0x33;
 730         anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val);
 731
 732         anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc);
 733         anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw);
 734         printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
 735
 736         return 0;
 737 }
 738
 739
 740 #ifdef CONFIG_HAS_EARLYSUSPEND
 741 static void anx6345_early_suspend(struct early_suspend *h)
 742 {
 743         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
 744         gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
 745         gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
 746 }
 747
 748 static void anx6345_late_resume(struct early_suspend *h)
 749 {
 750         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
 751         gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
 752         msleep(5);
 753         gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
 754         gpio_set_value(anx6345->pdata->edp_rst_pin,0);
 755         msleep(50);
 756         gpio_set_value(anx6345->pdata->edp_rst_pin,1);
 757         anx6345->edp_anx_init(anx6345->client);
 758 }
 759 #endif
 760
 761 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
 762 {
 763         int ret;
 764
 765         struct edp_anx6345 *anx6345 = NULL;
 766         int chip_id;
 767
 768
 769         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
 770         {
 771                 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
 772                 ret = -ENODEV;
 773         }
 774         anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL);
 775         if (anx6345 == NULL)
 776         {
 777                 printk(KERN_ALERT "alloc for struct anx6345 fail\n");
 778                 ret = -ENOMEM;
 779         }
 780
 781         anx6345->client = client;
 782         anx6345->pdata = client->dev.platform_data;
 783         i2c_set_clientdata(client,anx6345);
 784         if(anx6345->pdata->power_ctl)
 785                 anx6345->pdata->power_ctl();
 786
 787 #if defined(CONFIG_DEBUG_FS)
 788         anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
 789         if (IS_ERR(anx6345->debugfs_dir))
 790         {
 791                 printk(KERN_ERR "failed to create debugfs dir for edp!\n");
 792         }
 793         else
 794                 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
 795 #endif
 796
 797 #ifdef CONFIG_HAS_EARLYSUSPEND
 798         anx6345->early_suspend.suspend = anx6345_early_suspend;
 799         anx6345->early_suspend.resume = anx6345_late_resume;
 800         anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
 801         register_early_suspend(&anx6345->early_suspend);
 802 #endif
 803         chip_id = get_dp_chip_id(client);
 804         if(chip_id == 0x9805)
 805                 anx6345->edp_anx_init = anx980x_init;
 806         else
 807                 anx6345->edp_anx_init = anx6345_init;
 808
 809         anx6345->edp_anx_init(client);
 810
 811         printk("edp anx%x probe ok\n",get_dp_chip_id(client));
 812
 813         return ret;
 814 }
 815
 816 static int __devexit anx6345_i2c_remove(struct i2c_client *client)
 817 {
 818         return 0;
 819 }
 820
 821 static const struct i2c_device_id id_table[] = {
 822         {"anx6345", 0 },
 823         { }
 824 };
 825
 826 static struct i2c_driver anx6345_i2c_driver  = {
 827         .driver = {
 828                 .name  = "anx6345",
 829                 .owner = THIS_MODULE,
 830         },
 831         .probe          = &anx6345_i2c_probe,
 832         .remove         = &anx6345_i2c_remove,
 833         .id_table       = id_table,
 834 };
 835
 836
 837 static int __init anx6345_module_init(void)
 838 {
 839         return i2c_add_driver(&anx6345_i2c_driver);
 840 }
 841
 842 static void __exit anx6345_module_exit(void)
 843 {
 844         i2c_del_driver(&anx6345_i2c_driver);
 845 }
 846
 847 fs_initcall_sync(anx6345_module_init);
 848 module_exit(anx6345_module_exit);
 849