1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/time.h>
4 #include <linux/delay.h>
5 #include <linux/slab.h>
6 #include <linux/device.h>
9 #if defined(CONFIG_HAS_EARLYSUSPEND)
10 #include<linux/earlysuspend.h>
12 #if defined(CONFIG_OF)
13 #include <linux/of_gpio.h>
17 #if defined(CONFIG_DEBUG_FS)
19 #include <linux/debugfs.h>
20 #include <linux/seq_file.h>
25 static int i2c_master_reg8_send(const struct i2c_client *client,
26 const char reg, const char *buf, int count, int scl_rate)
28 struct i2c_adapter *adap=client->adapter;
31 char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
35 memcpy(tx_buf+1, buf, count);
37 msg.addr = client->addr;
38 msg.flags = client->flags;
40 msg.buf = (char *)tx_buf;
41 msg.scl_rate = scl_rate;
43 ret = i2c_transfer(adap, &msg, 1);
45 return (ret == 1) ? count : ret;
49 static int i2c_master_reg8_recv(const struct i2c_client *client,
50 const char reg, char *buf, int count, int scl_rate)
52 struct i2c_adapter *adap=client->adapter;
53 struct i2c_msg msgs[2];
57 msgs[0].addr = client->addr;
58 msgs[0].flags = client->flags;
60 msgs[0].buf = ®_buf;
61 msgs[0].scl_rate = scl_rate;
63 msgs[1].addr = client->addr;
64 msgs[1].flags = client->flags | I2C_M_RD;
66 msgs[1].buf = (char *)buf;
67 msgs[1].scl_rate = scl_rate;
69 ret = i2c_transfer(adap, msgs, 2);
71 return (ret == 2)? count : ret;
74 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
77 client->addr = DP_TX_PORT0_ADDR >> 1;
78 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
81 printk(KERN_ERR "%s>>err\n",__func__);
86 static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
89 client->addr = DP_TX_PORT0_ADDR >> 1;
90 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
93 printk(KERN_ERR "%s>>err\n",__func__);
98 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
101 client->addr = HDMI_TX_PORT0_ADDR >> 1;
102 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
105 printk(KERN_ERR "%s>>err\n",__func__);
111 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
114 client->addr = HDMI_TX_PORT0_ADDR >> 1;
115 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
118 printk(KERN_ERR "%s>>err\n",__func__);
124 #if defined(CONFIG_DEBUG_FS)
125 static int edp_reg_show(struct seq_file *s, void *v)
129 struct edp_anx6345 *anx6345 = s->private;
132 printk(KERN_ERR "no edp device!\n");
136 seq_printf(s,"0x70:\n");
137 for(i=0;i< MAX_REG;i++)
139 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
140 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
143 seq_printf(s,"\n0x72:\n");
144 for(i=0;i< MAX_REG;i++)
146 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
147 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
152 static int edp_reg_open(struct inode *inode, struct file *file)
154 struct edp_anx6345 *anx6345 = inode->i_private;
155 return single_open(file, edp_reg_show, anx6345);
158 static const struct file_operations edp_reg_fops = {
159 .owner = THIS_MODULE,
160 .open = edp_reg_open,
163 .release = single_release,
167 //get chip ID. Make sure I2C is OK
168 static int get_dp_chip_id(struct i2c_client *client)
172 anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1);
173 anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2);
179 static int anx980x_bist_mode(struct i2c_client *client)
184 //Power on total and select DP mode
186 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
189 val = DP_TX_RST_HW_RST;
190 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
193 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
196 anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
198 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
201 //get chip ID. Make sure I2C is OK
202 anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
204 printk("Chip found\n");
209 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
210 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
211 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
212 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
214 printk("clock is detected.\n");
220 //check whther clock is stable
223 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
224 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
225 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
226 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
228 printk("clock is stable.\n");
234 //VESA range, 8bits BPC, RGB
236 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
237 //RK_EDP chip analog setting
239 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
241 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
243 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
247 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
249 //RK_EDP chip analog setting
251 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
253 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
255 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
257 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
259 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
263 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
266 anx6345_i2c_write_p0_reg(client, 0xc8, &val);
268 anx6345_i2c_write_p0_reg(client, 0xa3, &val);
269 anx6345_i2c_write_p0_reg(client, 0xa4, &val);
270 anx6345_i2c_write_p0_reg(client, 0xa5,&val);
271 anx6345_i2c_write_p0_reg(client, 0xa6, &val);
275 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
277 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
281 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
284 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
287 //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
289 val = DP_TX_LINK_TRAINING_CTRL_EN;
290 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
292 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
293 while((val&0x01)&&(cnt++ < 10))
295 printk("Waiting...\n");
297 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
302 printk(KERN_INFO "HW LT fail\n");
306 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
309 DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
311 //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
313 //Set bist format 2048x1536
315 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
317 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
320 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
322 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
324 anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
326 anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
328 anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
330 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
332 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
334 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
336 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
339 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
341 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
344 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
346 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
348 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
350 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
352 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
355 val = DP_TX_VID_CTRL4_BIST;
356 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
359 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
360 //force HPD and stream valid
362 anx6345_i2c_write_p0_reg(client, 0x82, &val);
367 static int anx980x_aux_rst(struct i2c_client *client)
370 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
371 val |= DP_TX_AUX_RST;
372 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
373 val &= ~DP_TX_AUX_RST;
374 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
379 static int anx980x_wait_aux_finished(struct i2c_client *client)
384 anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
392 anx980x_aux_rst(client);
396 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
402 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
407 anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
409 //set read cmd and count
410 val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
411 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
413 //set aux address15:0
414 val = (char)addr&0xff;
415 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
416 val = (char)((addr>>8)&0xff);
417 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
419 //set address19:16 and enable aux
420 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
421 val &=(0xf0)|(char)((addr>>16)&0xff);
422 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
425 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
427 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
430 anx980x_wait_aux_finished(client);
432 for(i =0;i<cCount;i++)
434 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
436 //debug_printf("c = %.2x\n",(WORD)c);
449 static int anx_video_map_config(struct i2c_client *client)
453 anx6345_i2c_write_p1_reg(client, 0x40, &val);
454 anx6345_i2c_write_p1_reg(client, 0x41, &val);
455 anx6345_i2c_write_p1_reg(client, 0x48, &val);
456 anx6345_i2c_write_p1_reg(client, 0x49, &val);
457 anx6345_i2c_write_p1_reg(client, 0x50, &val);
458 anx6345_i2c_write_p1_reg(client, 0x51, &val);
462 anx6345_i2c_write_p1_reg(client, 0x42+i, &val);
468 anx6345_i2c_write_p1_reg(client, 0x4a+i, &val);
474 anx6345_i2c_write_p1_reg(client, 0x52+i, &val);
480 static int anx980x_eanble_video_input(struct i2c_client *client)
484 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
485 val |= DP_TX_VID_CTRL1_VID_EN;
486 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
488 anx_video_map_config(client);
493 static int anx980x_init(struct i2c_client *client)
498 char dp_tx_bw,dp_tx_lane_count;
501 #if defined(BIST_MODE)
502 return anx980x_bist_mode(client);
504 //power on all block and select DisplayPort mode
505 val |= DP_POWERD_AUDIO_REG;
506 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
508 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
509 val &= ~DP_TX_VID_CTRL1_VID_EN;
510 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
513 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
514 val |= DP_TX_RST_SW_RST;
515 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
516 val &= ~DP_TX_RST_SW_RST;
517 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
521 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
523 anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
525 //24bit SDR,negedge latch, and wait video stable
527 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
529 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
531 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
534 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
535 val |= DP_TX_AC_MODE;
536 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
540 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
543 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
545 anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
547 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
549 //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
551 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
554 anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
556 anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
558 //power down PLL filter
560 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
562 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
563 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
564 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
565 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
568 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
570 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
572 val = DP_TX_LINK_TRAINING_CTRL_EN;
573 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
575 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
576 while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
578 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
583 printk(KERN_INFO "HW LT fail\n");
586 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
587 //DP_TX_Config_Video(client);
588 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
589 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
590 if(!(val & DP_TX_SYS_CTRL1_DET_STA))
593 //return; //mask by yxj
596 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
597 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
598 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
599 if(val & DP_TX_SYS_CTRL2_CHA_STA)
601 printk("pclk not stable!\n");
602 //return; mask by yxj
605 anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
606 dp_tx_bw = ByteBuf[0];
607 dp_tx_lane_count = ByteBuf[1] & 0x0f;
608 printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
612 //set Input BPC mode & color space
613 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
615 val = val |((char)(0) << 4); //8bits ,rgb
616 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
622 anx980x_eanble_video_input(client);
628 static int anx6345_bist_mode(struct i2c_client *client)
630 struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
631 struct rk_screen *screen = &anx6345->screen;
632 u16 x_total ,y_total;
633 u32 total, act_total;
635 //these register are for bist mode
636 x_total = screen->mode.left_margin + screen->mode.right_margin +
637 screen->mode.xres + screen->mode.hsync_len;
638 y_total = screen->mode.upper_margin + screen->mode.lower_margin +
639 screen->mode.yres + screen->mode.vsync_len;
640 total = x_total * y_total;
641 printk("%s>>>>total:0x%08x\n",__func__, total);
642 act_total = screen->mode.xres * screen->mode.yres;
643 val = y_total & 0xff;
644 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
645 val = (y_total >> 8);
646 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
647 val = (screen->mode.yres & 0xff);
648 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
649 val = (screen->mode.yres >> 8);
650 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
651 val = screen->mode.lower_margin;
652 anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
653 val = screen->mode.vsync_len;
654 anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
655 val = screen->mode.upper_margin;
656 anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
659 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
662 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
663 val = (act_total & 0xff);
665 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
666 val = (act_total >> 8);
668 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
669 val = screen->mode.right_margin & 0xff;
670 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
671 val = screen->mode.right_margin >> 8;
672 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
673 val = screen->mode.hsync_len & 0xff;
674 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
675 val = screen->mode.hsync_len >> 8;
676 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
677 val = screen->mode.left_margin & 0xff;
678 anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
679 val = screen->mode.left_margin >> 8;
680 anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHH_REG,&val);
682 anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
685 //enable BIST. In normal mode, don't need to config this reg
687 anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
688 printk("anx6345 enter bist mode\n");
693 static int anx6345_bist_mode(struct i2c_client *client)
696 //these register are for bist mode
698 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
700 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
702 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
704 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
706 anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
708 anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
710 anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
712 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
714 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
716 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
718 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
720 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
722 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
724 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
726 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
728 anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
730 anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
731 //enable BIST. In normal mode, don't need to config this reg
733 anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
734 printk("anx6345 enter bist mode\n");
741 static int anx6345_init(struct i2c_client *client)
749 anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
755 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
756 anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
757 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
758 if((val&SP_TX_SYS_CTRL1_DET_STA)!=0)
766 printk("no clock detected by anx6345\n");
768 //check whether clock is stable
771 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
772 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val);
773 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
774 if((val&SP_TX_SYS_CTRL2_CHA_STA)==0)
781 printk("clk is not stable\n");
783 //VESA range, 6bits BPC, RGB
785 anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val);
787 //ANX6345 chip pll setting
789 anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00
792 //ANX chip analog setting
794 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70
796 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val);
799 //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val);
803 anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
804 val |= SP_TX_AUX_RST;
805 anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
806 val &= ~SP_TX_AUX_RST;
807 anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
811 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val);
814 anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val);
816 val = SP_TX_LINK_TRAINING_CTRL_EN;
817 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
819 anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
820 while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80
822 printk("Waiting...\n");
824 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val);
829 printk(KERN_INFO "HW LT fail\n");
832 printk("HW LT Success>>:times:%d\n",(51-cnt));
836 //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
837 //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
839 #if defined(BIST_MODE)
840 anx6345_bist_mode(client);
845 anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val);
847 anx_video_map_config(client);
848 //force HPD and stream valid
850 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val);
852 anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc);
853 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw);
854 printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
860 #ifdef CONFIG_HAS_EARLYSUSPEND
861 static void anx6345_early_suspend(struct early_suspend *h)
863 struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
864 gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
865 gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
868 static void anx6345_late_resume(struct early_suspend *h)
870 struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
871 gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
873 gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
874 gpio_set_value(anx6345->pdata->edp_rst_pin,0);
876 gpio_set_value(anx6345->pdata->edp_rst_pin,1);
877 anx6345->edp_anx_init(anx6345->client);
881 #if defined(CONFIG_OF)
883 static int anx6345_power_ctl(struct anx6345_platform_data *pdata)
886 ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
888 gpio_free(pdata->dvdd33_en_pin);
889 printk(KERN_ERR "request dvdd33 en pin fail!\n");
892 gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
896 ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
898 gpio_free(pdata->dvdd18_en_pin);
899 printk(KERN_ERR "request dvdd18 en pin fail!\n");
902 gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
905 ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
907 gpio_free(pdata->edp_rst_pin);
908 printk(KERN_ERR "request rst pin fail!\n");
911 gpio_direction_output(pdata->edp_rst_pin, 0);
913 gpio_direction_output(pdata->edp_rst_pin, 1);
919 static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
921 struct device_node *np = anx6345->client->dev.of_node;
922 struct anx6345_platform_data *pdata;
923 enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
924 pdata = devm_kzalloc(&anx6345->client->dev,
925 sizeof(struct anx6345_platform_data ), GFP_KERNEL);
927 dev_err(&anx6345->client->dev,
928 "failed to allocate platform data\n");
931 pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
932 pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
933 pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
934 pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
935 pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
936 pdata->power_ctl = anx6345_power_ctl;
937 anx6345->pdata = pdata;
941 static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
946 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
948 struct edp_anx6345 *anx6345;
952 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
954 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
957 anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
959 if (unlikely(!anx6345)) {
960 dev_err(&client->dev, "alloc for struct anx6345 fail\n");
964 anx6345->client = client;
965 anx6345->pdata = dev_get_platdata(&client->dev);
966 if (!anx6345->pdata) {
967 anx6345_parse_dt(anx6345);
969 i2c_set_clientdata(client,anx6345);
970 rk_fb_get_prmry_screen(&anx6345->screen);
971 if(anx6345->pdata->power_ctl)
972 anx6345->pdata->power_ctl(anx6345->pdata);
974 #if defined(CONFIG_DEBUG_FS)
975 anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
976 if (IS_ERR(anx6345->debugfs_dir))
978 printk(KERN_ERR "failed to create debugfs dir for edp!\n");
981 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
984 #ifdef CONFIG_HAS_EARLYSUSPEND
985 anx6345->early_suspend.suspend = anx6345_early_suspend;
986 anx6345->early_suspend.resume = anx6345_late_resume;
987 anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
988 register_early_suspend(&anx6345->early_suspend);
990 chip_id = get_dp_chip_id(client);
991 if(chip_id == 0x9805)
992 anx6345->edp_anx_init = anx980x_init;
994 anx6345->edp_anx_init = anx6345_init;
996 anx6345->edp_anx_init(client);
998 dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
1003 static int anx6345_i2c_remove(struct i2c_client *client)
1008 static const struct i2c_device_id id_table[] = {
1013 #if defined(CONFIG_OF)
1014 static struct of_device_id anx6345_dt_ids[] = {
1015 { .compatible = "analogix, anx6345" },
1020 static struct i2c_driver anx6345_i2c_driver = {
1023 .owner = THIS_MODULE,
1024 #if defined(CONFIG_OF)
1025 .of_match_table = of_match_ptr(anx6345_dt_ids),
1028 .probe = &anx6345_i2c_probe,
1029 .remove = &anx6345_i2c_remove,
1030 .id_table = id_table,
1034 static int __init anx6345_module_init(void)
1036 return i2c_add_driver(&anx6345_i2c_driver);
1039 static void __exit anx6345_module_exit(void)
1041 i2c_del_driver(&anx6345_i2c_driver);
1044 fs_initcall_sync(anx6345_module_init);
1045 module_exit(anx6345_module_exit);