drivers/video/rockchip/transmitter/dp_anx6345.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/time.h>
   4 #include <linux/delay.h>
   5 #include <linux/slab.h>
   6 #include <linux/device.h>
   7 #include <linux/i2c.h>
   8
   9 #if defined(CONFIG_HAS_EARLYSUSPEND)
  10 #include<linux/earlysuspend.h>
  11 #endif
  12 #if defined(CONFIG_OF)
  13 #include <linux/of_gpio.h>
  14 #endif
  15 #include "anx6345.h"
  16
  17 #if defined(CONFIG_DEBUG_FS)
  18 #include <linux/fs.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/seq_file.h>
  21 #endif
  22
  23
  24 //#define BIST_MODE 0
  25 static int i2c_master_reg8_send(const struct i2c_client *client,
  26                 const char reg, const char *buf, int count, int scl_rate)
  27 {
  28         struct i2c_adapter *adap=client->adapter;
  29         struct i2c_msg msg;
  30         int ret;
  31         char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
  32         if(!tx_buf)
  33                 return -ENOMEM;
  34         tx_buf[0] = reg;
  35         memcpy(tx_buf+1, buf, count);
  36
  37         msg.addr = client->addr;
  38         msg.flags = client->flags;
  39         msg.len = count + 1;
  40         msg.buf = (char *)tx_buf;
  41         msg.scl_rate = scl_rate;
  42
  43         ret = i2c_transfer(adap, &msg, 1);
  44         kfree(tx_buf);
  45         return (ret == 1) ? count : ret;
  46
  47 }
  48
  49 static int i2c_master_reg8_recv(const struct i2c_client *client,
  50                 const char reg, char *buf, int count, int scl_rate)
  51 {
  52         struct i2c_adapter *adap=client->adapter;
  53         struct i2c_msg msgs[2];
  54         int ret;
  55         char reg_buf = reg;
  56
  57         msgs[0].addr = client->addr;
  58         msgs[0].flags = client->flags;
  59         msgs[0].len = 1;
  60         msgs[0].buf = &reg_buf;
  61         msgs[0].scl_rate = scl_rate;
  62
  63         msgs[1].addr = client->addr;
  64         msgs[1].flags = client->flags | I2C_M_RD;
  65         msgs[1].len = count;
  66         msgs[1].buf = (char *)buf;
  67         msgs[1].scl_rate = scl_rate;
  68
  69         ret = i2c_transfer(adap, msgs, 2);
  70
  71         return (ret == 2)? count : ret;
  72 }
  73
  74 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
  75 {
  76         int ret;
  77         client->addr = DP_TX_PORT0_ADDR >> 1;
  78         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  79         if(ret < 0)
  80         {
  81                 printk(KERN_ERR "%s>>err\n",__func__);
  82         }
  83
  84         return ret;
  85 }
  86 static int  anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
  87 {
  88         int ret;
  89         client->addr = DP_TX_PORT0_ADDR >> 1;
  90         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  91         if(ret < 0)
  92         {
  93                 printk(KERN_ERR "%s>>err\n",__func__);
  94         }
  95
  96         return ret;
  97 }
  98 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
  99 {
 100         int ret;
 101         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 102         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 103         if(ret < 0)
 104         {
 105                 printk(KERN_ERR "%s>>err\n",__func__);
 106         }
 107
 108         return ret;
 109 }
 110
 111 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
 112 {
 113         int ret;
 114         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 115         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 116         if(ret < 0)
 117         {
 118                 printk(KERN_ERR "%s>>err\n",__func__);
 119         }
 120
 121         return ret;
 122 }
 123
 124 #if defined(CONFIG_DEBUG_FS)
 125 static int edp_reg_show(struct seq_file *s, void *v)
 126 {
 127         int i = 0;
 128         char val;
 129         struct edp_anx6345 *anx6345 = s->private;
 130         if(!anx6345)
 131         {
 132                 printk(KERN_ERR "no edp device!\n");
 133                 return 0;
 134         }
 135
 136         seq_printf(s,"0x70:\n");
 137         for(i=0;i< MAX_REG;i++)
 138         {
 139                 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
 140                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 141         }
 142
 143         seq_printf(s,"\n0x72:\n");
 144         for(i=0;i< MAX_REG;i++)
 145         {
 146                 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
 147                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 148         }
 149         return 0;
 150 }
 151
 152 static int edp_reg_open(struct inode *inode, struct file *file)
 153 {
 154         struct edp_anx6345 *anx6345 = inode->i_private;
 155         return single_open(file, edp_reg_show, anx6345);
 156 }
 157
 158 static const struct file_operations edp_reg_fops = {
 159         .owner          = THIS_MODULE,
 160         .open           = edp_reg_open,
 161         .read           = seq_read,
 162         .llseek         = seq_lseek,
 163         .release        = single_release,
 164 };
 165 #endif
 166
 167 //get chip ID. Make sure I2C is OK
 168 static int get_dp_chip_id(struct i2c_client *client)
 169 {
 170         char c1,c2;
 171         int id;
 172         anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1);
 173         anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2);
 174         id = c2;
 175         return (id<<8)|c1;
 176 }
 177
 178
 179 static int anx980x_bist_mode(struct i2c_client *client)
 180 {
 181         char val,i;
 182         u8 cnt=0;
 183
 184         //Power on total and select DP mode
 185         val = 00;
 186         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 187
 188         //HW reset
 189         val = DP_TX_RST_HW_RST;
 190         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 191         msleep(10);
 192         val = 0x00;
 193         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 194
 195
 196         anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 197         val = 0x00;
 198         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 199
 200
 201         //get chip ID. Make sure I2C is OK
 202         anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
 203         if (val==0x98)
 204                 printk("Chip found\n");
 205
 206         //for clocl detect
 207         for(i=0;i<100;i++)
 208         {
 209                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 210                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 211                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 212                 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
 213                 {
 214                         printk("clock is detected.\n");
 215                         break;
 216                 }
 217
 218                 msleep(10);
 219         }
 220        //check whther clock is stable
 221         for(i=0;i<50;i++)
 222         {
 223                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 224                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 225                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 226                 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
 227                 {
 228                         printk("clock is stable.\n");
 229                         break;
 230                 }
 231                 msleep(10);
 232         }
 233
 234         //VESA range, 8bits BPC, RGB
 235         val = 0x10;
 236         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
 237         //RK_EDP chip analog setting
 238         val = 0x07;
 239         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 240         val = 0x19;
 241         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 242         val = 0xd9;
 243         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 244
 245         //Select AC mode
 246         val = 0x40;
 247         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 248
 249         //RK_EDP chip analog setting
 250         val = 0xf0;
 251         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 252         val = 0x99;
 253         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 254         val = 0x7b;
 255         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 256         val = 0x30;
 257         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 258         val = 0x06;
 259         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
 260
 261         //force HPD
 262         val = 0x30;
 263         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
 264         //power on 4 lanes
 265         val = 0x00;
 266         anx6345_i2c_write_p0_reg(client, 0xc8, &val);
 267         //lanes setting
 268         anx6345_i2c_write_p0_reg(client, 0xa3, &val);
 269         anx6345_i2c_write_p0_reg(client, 0xa4, &val);
 270         anx6345_i2c_write_p0_reg(client, 0xa5,&val);
 271         anx6345_i2c_write_p0_reg(client, 0xa6, &val);
 272
 273         //reset AUX CH
 274         val = 0x44;
 275         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 276         val = 0x40;
 277         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 278
 279         //Select 1.62G
 280         val = 0x06;
 281         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 282         //Select 4 lanes
 283         val = 0x04;
 284         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 285
 286         //strart link traing
 287         //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
 288         #if 1
 289         val = DP_TX_LINK_TRAINING_CTRL_EN;
 290         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 291         msleep(5);
 292         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 293         while((val&0x01)&&(cnt++ < 10))
 294         {
 295                 printk("Waiting...\n");
 296                 msleep(5);
 297                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 298         }
 299
 300         if(cnt >= 10)
 301         {
 302                 printk(KERN_INFO "HW LT fail\n");
 303         }
 304         else
 305         {
 306                 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
 307         }
 308         #else
 309         DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
 310         #endif
 311         //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
 312
 313         //Set bist format 2048x1536
 314         val = 0x2c;
 315         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
 316         val = 0x06;
 317         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
 318
 319         val = 0x00;
 320         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
 321         val = 0x06;
 322         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
 323         val = 0x02;
 324         anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
 325         val = 0x04;
 326         anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
 327         val = 0x26;
 328         anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
 329         val = 0x50;
 330         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
 331         val = 0x04;
 332         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
 333         val = 0x00;
 334         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
 335         val = 0x04;
 336         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
 337
 338         val = 0x18;
 339         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
 340         val = 0x00;
 341         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
 342
 343         val = 0x10;
 344         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
 345         val = 0x00;
 346         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
 347         val = 0x28;
 348         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
 349         val = 0x00;
 350         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
 351         val = 0x03;
 352         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
 353
 354         //enable BIST
 355         val = DP_TX_VID_CTRL4_BIST;
 356         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
 357         //enable video input
 358         val = 0x8d;
 359         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 360         //force HPD and stream valid
 361         val = 0x33;
 362         anx6345_i2c_write_p0_reg(client, 0x82, &val);
 363
 364         return 0;
 365 }
 366
 367 static int anx980x_aux_rst(struct i2c_client *client)
 368 {
 369         char val;
 370         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 371         val |= DP_TX_AUX_RST;
 372         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 373         val &= ~DP_TX_AUX_RST;
 374         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 375         return 0;
 376 }
 377
 378
 379 static int anx980x_wait_aux_finished(struct i2c_client *client)
 380 {
 381         char val,cnt;
 382         cnt = 0;
 383
 384         anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
 385         while(val&0x01)
 386         {
 387                 //delay_ms(20);
 388                 cnt ++;
 389                 if(cnt == 10)
 390                 {
 391                    printk("aux break");
 392                     anx980x_aux_rst(client);
 393                     //cnt = 0;
 394                     break;
 395                 }
 396                 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
 403 {
 404         char val,i;
 405
 406         val = 0x80;
 407         anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
 408
 409         //set read cmd and count
 410         val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
 411         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
 412
 413         //set aux address15:0
 414         val = (char)addr&0xff;
 415         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
 416         val = (char)((addr>>8)&0xff);
 417         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
 418
 419         //set address19:16 and enable aux
 420         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 421         val &=(0xf0)|(char)((addr>>16)&0xff);
 422         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 423
 424         //Enable Aux
 425         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 426         val |= 0x01;
 427         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 428
 429         //delay_ms(2);
 430         anx980x_wait_aux_finished(client);
 431
 432         for(i =0;i<cCount;i++)
 433         {
 434                 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
 435
 436                 //debug_printf("c = %.2x\n",(WORD)c);
 437                 *(pBuf+i) = val;
 438
 439                 if(i >= MAX_BUF_CNT)
 440                         return 1;
 441                         //break;
 442         }
 443
 444         return 0;
 445
 446
 447 }
 448
 449 static int anx_video_map_config(struct i2c_client *client)
 450 {
 451         char val = 0;
 452         char i = 0;
 453         anx6345_i2c_write_p1_reg(client,  0x40, &val);
 454         anx6345_i2c_write_p1_reg(client,  0x41, &val);
 455         anx6345_i2c_write_p1_reg(client,  0x48, &val);
 456         anx6345_i2c_write_p1_reg(client,  0x49, &val);
 457         anx6345_i2c_write_p1_reg(client,  0x50, &val);
 458         anx6345_i2c_write_p1_reg(client,  0x51, &val);
 459         for(i=0; i<6; i++)
 460         {
 461                 val = i;
 462                 anx6345_i2c_write_p1_reg(client,  0x42+i, &val);
 463         }
 464
 465         for(i=0; i<6; i++)
 466         {
 467                 val = 6+i;
 468                 anx6345_i2c_write_p1_reg(client,  0x4a+i, &val);
 469         }
 470
 471         for(i=0; i<6; i++)
 472         {
 473                 val = 0x0c+i;
 474                 anx6345_i2c_write_p1_reg(client,  0x52+i, &val);
 475         }
 476
 477         return 0;
 478
 479 }
 480 static int anx980x_eanble_video_input(struct i2c_client *client)
 481 {
 482         char val;
 483
 484         anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 485         val |= DP_TX_VID_CTRL1_VID_EN;
 486         anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 487
 488         anx_video_map_config(client);
 489
 490         return 0;
 491 }
 492
 493 static int anx980x_init(struct i2c_client *client)
 494 {
 495         char val = 0x00;
 496         char safe_mode = 0;
 497         char ByteBuf[2];
 498         char dp_tx_bw,dp_tx_lane_count;
 499         char cnt = 10;
 500
 501 #if defined(BIST_MODE)
 502         return anx980x_bist_mode(client);
 503 #endif
 504          //power on all block and select DisplayPort mode
 505         val |= DP_POWERD_AUDIO_REG;
 506         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
 507
 508         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 509         val &= ~DP_TX_VID_CTRL1_VID_EN;
 510         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 511
 512         //software reset
 513         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 514         val |= DP_TX_RST_SW_RST;
 515         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
 516         val &= ~DP_TX_RST_SW_RST;
 517         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 518
 519
 520         val = 0x07;
 521         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 522         val = 0x50;
 523         anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
 524
 525         //24bit SDR,negedge latch, and wait video stable
 526         val = 0x01;
 527         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
 528         val = 0x19;
 529         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 530         val = 0xd9;
 531         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 532
 533         //serdes ac mode.
 534         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 535         val |= DP_TX_AC_MODE;
 536         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 537
 538         //set termination
 539         val = 0xf0;
 540         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 541         //set duty cycle
 542         val = 0x99;
 543         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 544
 545         anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 546         val |= 0x2a;
 547         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 548
 549         //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
 550         val = 0x30;
 551         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 552
 553         //for DP link CTS
 554         anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 555         val |= 0x40;
 556         anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 557
 558         //power down  PLL filter
 559         val = 0x06;
 560         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
 561
 562         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
 563         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
 564         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
 565         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
 566
 567         val = 0x06;
 568         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 569         val = 0x04;
 570         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 571
 572         val = DP_TX_LINK_TRAINING_CTRL_EN;
 573         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
 574         msleep(2);
 575         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 576         while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
 577         {
 578                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 579                 cnt--;
 580         }
 581         if(cnt < 0)
 582         {
 583                 printk(KERN_INFO "HW LT fail\n");
 584         }
 585         else
 586                 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
 587         //DP_TX_Config_Video(client);
 588         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 589         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL1_REG, &val);
 590         if(!(val & DP_TX_SYS_CTRL1_DET_STA))
 591         {
 592                 printk("No pclk\n");
 593                 //return;  //mask by yxj
 594         }
 595
 596         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 597         anx6345_i2c_write_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 598         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 599         if(val & DP_TX_SYS_CTRL2_CHA_STA)
 600         {
 601                 printk("pclk not stable!\n");
 602                 //return; mask by yxj
 603         }
 604
 605         anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
 606         dp_tx_bw = ByteBuf[0];
 607         dp_tx_lane_count = ByteBuf[1] & 0x0f;
 608         printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
 609
 610         if(!safe_mode)
 611         {
 612                 //set Input BPC mode & color space
 613                 anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 614                 val &= 0x8c;
 615                 val = val |((char)(0) << 4);  //8bits  ,rgb
 616                 anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 617         }
 618
 619
 620
 621         //enable video input
 622          anx980x_eanble_video_input(client);
 623
 624         return 0;
 625 }
 626
 627 #if 1
 628 static int anx6345_bist_mode(struct i2c_client *client)
 629 {
 630         struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
 631         struct rk_screen *screen = &anx6345->screen;
 632         u16 x_total ,y_total;
 633         u32 total, act_total;
 634         char val = 0x00;
 635         //these register are for bist mode
 636         x_total = screen->mode.left_margin + screen->mode.right_margin +
 637                         screen->mode.xres + screen->mode.hsync_len;
 638         y_total = screen->mode.upper_margin + screen->mode.lower_margin +
 639                         screen->mode.yres + screen->mode.vsync_len;
 640         total = x_total * y_total;
 641         printk("%s>>>>total:0x%08x\n",__func__, total);
 642         act_total = screen->mode.xres * screen->mode.yres;
 643         val = y_total & 0xff;
 644         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
 645         val = (y_total >> 8);
 646         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
 647         val = (screen->mode.yres & 0xff);
 648         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
 649         val = (screen->mode.yres >> 8);
 650         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
 651         val = screen->mode.lower_margin;
 652         anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
 653         val = screen->mode.vsync_len;
 654         anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
 655         val = screen->mode.upper_margin;
 656         anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
 657         val = total & 0xff;
 658         val = 0x50;
 659         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
 660         val = total >> 8;
 661         val = 0x04;
 662         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
 663         val = (act_total & 0xff);
 664         val = 0x00;
 665         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
 666         val = (act_total >> 8);
 667         val = 0x04;
 668         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
 669         val = screen->mode.right_margin & 0xff;
 670         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
 671         val = screen->mode.right_margin >> 8;
 672         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
 673         val = screen->mode.hsync_len & 0xff;
 674         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
 675         val = screen->mode.hsync_len >> 8;
 676         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
 677         val = screen->mode.left_margin & 0xff;
 678         anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
 679         val = screen->mode.left_margin  >> 8;
 680         anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHH_REG,&val);
 681         val = 0x13;
 682         anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
 683
 684
 685        //enable BIST. In normal mode, don't need to config this reg
 686         val = 0x08;
 687         anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
 688         printk("anx6345 enter bist mode\n");
 689
 690         return 0;
 691 }
 692 #else
 693 static int anx6345_bist_mode(struct i2c_client *client)
 694 {
 695         char val = 0x00;
 696         //these register are for bist mode
 697         val = 0x2c;
 698         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
 699         val = 0x06;
 700         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
 701         val = 0x00;
 702         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
 703         val = 0x06;
 704         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
 705         val = 0x02;
 706         anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
 707         val = 0x04;
 708         anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
 709         val = 0x26;
 710         anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
 711         val = 0x50;
 712         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
 713         val = 0x04;
 714         anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
 715         val = 0x00;
 716         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
 717         val = 0x04;
 718         anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
 719         val = 0x18;
 720         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
 721         val = 0x00;
 722         anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
 723         val = 0x10;
 724         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
 725         val = 0x00;
 726         anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
 727         val = 0x28;
 728         anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
 729         val = 0x13;
 730         anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
 731          //enable BIST. In normal mode, don't need to config this reg
 732         val = 0x08;
 733         anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL4_REG, &val);
 734         printk("anx6345 enter bist mode\n");
 735
 736         return 0;
 737 }
 738
 739 #endif
 740
 741 static int anx6345_init(struct i2c_client *client)
 742 {
 743         char val = 0x00;
 744         char i = 0;
 745         char lc,bw;
 746         char cnt = 50;
 747
 748         val = 0x30;
 749         anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
 750
 751         //clock detect
 752         for(i=0;i<50;i++)
 753         {
 754
 755                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 756                 anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 757                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
 758                 if((val&SP_TX_SYS_CTRL1_DET_STA)!=0)
 759                 {
 760                         break;
 761                 }
 762
 763                 mdelay(10);
 764         }
 765         if(i>49)
 766                 printk("no clock detected by anx6345\n");
 767
 768         //check whether clock is stable
 769         for(i=0;i<50;i++)
 770         {
 771                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
 772                 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val);
 773                 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
 774                 if((val&SP_TX_SYS_CTRL2_CHA_STA)==0)
 775                 {
 776                         break;
 777                 }
 778                 mdelay(10);
 779         }
 780         if(i>49)
 781                 printk("clk is not stable\n");
 782
 783         //VESA range, 6bits BPC, RGB
 784         val = 0x00;
 785         anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val);
 786
 787         //ANX6345 chip pll setting
 788         val = 0x00;
 789         anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val);                  //UPDATE: FROM 0X07 TO 0X00
 790
 791
 792         //ANX chip analog setting
 793         val = 0x70;
 794         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);               //UPDATE: FROM 0XF0 TO 0X70
 795         val = 0x30;
 796         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val);
 797
 798         //force HPD
 799         //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val);
 800
 801
 802         //reset AUX
 803         anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 804         val |= SP_TX_AUX_RST;
 805         anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 806         val &= ~SP_TX_AUX_RST;
 807         anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
 808
 809         //Select 2.7G
 810         val = 0x0a;
 811         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val);
 812         //Select 2 lanes
 813         val = 0x02;
 814         anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val);
 815
 816         val = SP_TX_LINK_TRAINING_CTRL_EN;
 817         anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
 818         mdelay(5);
 819         anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
 820         while((val&0x80)&&(cnt))                                                                                //UPDATE: FROM 0X01 TO 0X80
 821         {
 822                 printk("Waiting...\n");
 823                 mdelay(5);
 824                 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val);
 825                 cnt--;
 826         }
 827         if(cnt <= 0)
 828         {
 829                 printk(KERN_INFO "HW LT fail\n");
 830         }
 831         else
 832                 printk("HW LT Success>>:times:%d\n",(51-cnt));
 833
 834
 835
 836         //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
 837         //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
 838
 839 #if defined(BIST_MODE)
 840         anx6345_bist_mode(client);
 841         val = 0x8f;
 842 #else
 843         val = 0x81;
 844 #endif
 845         anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val);
 846
 847         anx_video_map_config(client);
 848         //force HPD and stream valid
 849         val = 0x33;
 850         anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val);
 851
 852         anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc);
 853         anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw);
 854         printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
 855
 856         return 0;
 857 }
 858
 859
 860 #ifdef CONFIG_HAS_EARLYSUSPEND
 861 static void anx6345_early_suspend(struct early_suspend *h)
 862 {
 863         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
 864         gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
 865         gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
 866 }
 867
 868 static void anx6345_late_resume(struct early_suspend *h)
 869 {
 870         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
 871         gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
 872         msleep(5);
 873         gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
 874         gpio_set_value(anx6345->pdata->edp_rst_pin,0);
 875         msleep(50);
 876         gpio_set_value(anx6345->pdata->edp_rst_pin,1);
 877         anx6345->edp_anx_init(anx6345->client);
 878 }
 879 #endif
 880
 881 #if defined(CONFIG_OF)
 882
 883 static int anx6345_power_ctl(struct anx6345_platform_data  *pdata)
 884 {
 885        int ret;
 886        ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
 887        if (ret != 0) {
 888                gpio_free(pdata->dvdd33_en_pin);
 889                printk(KERN_ERR "request dvdd33 en pin fail!\n");
 890                return -1;
 891        } else {
 892                gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
 893        }
 894        mdelay(5);
 895
 896        ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
 897        if (ret != 0) {
 898                gpio_free(pdata->dvdd18_en_pin);
 899                printk(KERN_ERR "request dvdd18 en pin fail!\n");
 900                return -1;
 901        } else {
 902                gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
 903        }
 904
 905        ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
 906        if (ret != 0) {
 907                gpio_free(pdata->edp_rst_pin);
 908                printk(KERN_ERR "request rst pin fail!\n");
 909                return -1;
 910        } else {
 911                gpio_direction_output(pdata->edp_rst_pin, 0);
 912                msleep(50);
 913                gpio_direction_output(pdata->edp_rst_pin, 1);
 914        }
 915        return 0;
 916
 917 }
 918
 919 static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
 920 {
 921         struct device_node *np = anx6345->client->dev.of_node;
 922         struct anx6345_platform_data *pdata;
 923         enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
 924         pdata = devm_kzalloc(&anx6345->client->dev,
 925                         sizeof(struct anx6345_platform_data ), GFP_KERNEL);
 926         if (!pdata) {
 927                 dev_err(&anx6345->client->dev,
 928                         "failed to allocate platform data\n");
 929                 return ;
 930         }
 931         pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
 932         pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
 933         pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
 934         pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
 935         pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
 936         pdata->power_ctl = anx6345_power_ctl;
 937         anx6345->pdata = pdata;
 938
 939 }
 940 #else
 941 static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
 942 {
 943
 944 }
 945 #endif
 946 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
 947 {
 948         struct edp_anx6345 *anx6345;
 949         int chip_id;
 950
 951
 952         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
 953         {
 954                 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
 955                 return -ENODEV;
 956         }
 957         anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
 958                                 GFP_KERNEL);
 959         if (unlikely(!anx6345)) {
 960                 dev_err(&client->dev, "alloc for struct anx6345 fail\n");
 961                 return -ENOMEM;
 962         }
 963
 964         anx6345->client = client;
 965         anx6345->pdata = dev_get_platdata(&client->dev);
 966         if (!anx6345->pdata) {
 967                 anx6345_parse_dt(anx6345);
 968         }
 969         i2c_set_clientdata(client,anx6345);
 970         rk_fb_get_prmry_screen(&anx6345->screen);
 971         if(anx6345->pdata->power_ctl)
 972                 anx6345->pdata->power_ctl(anx6345->pdata);
 973
 974 #if defined(CONFIG_DEBUG_FS)
 975         anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
 976         if (IS_ERR(anx6345->debugfs_dir))
 977         {
 978                 printk(KERN_ERR "failed to create debugfs dir for edp!\n");
 979         }
 980         else
 981                 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
 982 #endif
 983
 984 #ifdef CONFIG_HAS_EARLYSUSPEND
 985         anx6345->early_suspend.suspend = anx6345_early_suspend;
 986         anx6345->early_suspend.resume = anx6345_late_resume;
 987         anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
 988         register_early_suspend(&anx6345->early_suspend);
 989 #endif
 990         chip_id = get_dp_chip_id(client);
 991         if(chip_id == 0x9805)
 992                 anx6345->edp_anx_init = anx980x_init;
 993         else
 994                 anx6345->edp_anx_init = anx6345_init;
 995
 996         anx6345->edp_anx_init(client);
 997
 998         dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
 999
1000         return 0;
1001 }
1002
1003 static int  anx6345_i2c_remove(struct i2c_client *client)
1004 {
1005         return 0;
1006 }
1007
1008 static const struct i2c_device_id id_table[] = {
1009         {"anx6345", 0 },
1010         { }
1011 };
1012
1013 #if defined(CONFIG_OF)
1014 static struct of_device_id anx6345_dt_ids[] = {
1015         { .compatible = "analogix, anx6345" },
1016         { }
1017 };
1018 #endif
1019
1020 static struct i2c_driver anx6345_i2c_driver  = {
1021         .driver = {
1022                 .name  = "anx6345",
1023                 .owner = THIS_MODULE,
1024 #if defined(CONFIG_OF)
1025                 .of_match_table = of_match_ptr(anx6345_dt_ids),
1026 #endif
1027         },
1028         .probe          = &anx6345_i2c_probe,
1029         .remove         = &anx6345_i2c_remove,
1030         .id_table       = id_table,
1031 };
1032
1033
1034 static int __init anx6345_module_init(void)
1035 {
1036         return i2c_add_driver(&anx6345_i2c_driver);
1037 }
1038
1039 static void __exit anx6345_module_exit(void)
1040 {
1041         i2c_del_driver(&anx6345_i2c_driver);
1042 }
1043
1044 fs_initcall_sync(anx6345_module_init);
1045 module_exit(anx6345_module_exit);
1046