1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/time.h>
4 #include <linux/delay.h>
5 #include <linux/slab.h>
6 #include <linux/device.h>
9 #if defined(CONFIG_HAS_EARLYSUSPEND)
10 #include<linux/earlysuspend.h>
12 #if defined(CONFIG_OF)
13 #include <linux/of_gpio.h>
16 #include "dpcd_edid.h"
17 #if defined(CONFIG_DEBUG_FS)
19 #include <linux/debugfs.h>
20 #include <linux/seq_file.h>
24 static struct edp_anx6345 *edp;
26 static int i2c_master_reg8_send(const struct i2c_client *client,
27 const char reg, const char *buf, int count, int scl_rate)
29 struct i2c_adapter *adap=client->adapter;
32 char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
36 memcpy(tx_buf+1, buf, count);
38 msg.addr = client->addr;
39 msg.flags = client->flags;
41 msg.buf = (char *)tx_buf;
42 msg.scl_rate = scl_rate;
44 ret = i2c_transfer(adap, &msg, 1);
46 return (ret == 1) ? count : ret;
50 static int i2c_master_reg8_recv(const struct i2c_client *client,
51 const char reg, char *buf, int count, int scl_rate)
53 struct i2c_adapter *adap=client->adapter;
54 struct i2c_msg msgs[2];
58 msgs[0].addr = client->addr;
59 msgs[0].flags = client->flags;
61 msgs[0].buf = ®_buf;
62 msgs[0].scl_rate = scl_rate;
64 msgs[1].addr = client->addr;
65 msgs[1].flags = client->flags | I2C_M_RD;
67 msgs[1].buf = (char *)buf;
68 msgs[1].scl_rate = scl_rate;
70 ret = i2c_transfer(adap, msgs, 2);
72 return (ret == 2)? count : ret;
75 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
78 client->addr = DP_TX_PORT0_ADDR >> 1;
79 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
82 printk(KERN_ERR "%s>>err\n",__func__);
87 static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
90 client->addr = DP_TX_PORT0_ADDR >> 1;
91 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
94 printk(KERN_ERR "%s>>err\n",__func__);
99 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
102 client->addr = HDMI_TX_PORT0_ADDR >> 1;
103 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
106 printk(KERN_ERR "%s>>err\n",__func__);
112 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
115 client->addr = HDMI_TX_PORT0_ADDR >> 1;
116 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
119 printk(KERN_ERR "%s>>err\n",__func__);
125 #if defined(CONFIG_DEBUG_FS)
126 static int edp_reg_show(struct seq_file *s, void *v)
130 struct edp_anx6345 *anx6345 = s->private;
133 printk(KERN_ERR "no edp device!\n");
137 seq_printf(s,"0x70:\n");
138 for(i=0;i< MAX_REG;i++)
140 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
141 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
144 seq_printf(s,"\n0x72:\n");
145 for(i=0;i< MAX_REG;i++)
147 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
148 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
153 static int edp_reg_open(struct inode *inode, struct file *file)
155 struct edp_anx6345 *anx6345 = inode->i_private;
156 return single_open(file, edp_reg_show, anx6345);
159 static const struct file_operations edp_reg_fops = {
160 .owner = THIS_MODULE,
161 .open = edp_reg_open,
164 .release = single_release,
168 //get chip ID. Make sure I2C is OK
169 static int get_dp_chip_id(struct i2c_client *client)
173 anx6345_i2c_read_p1_reg(client,DEV_IDL_REG,&c1);
174 anx6345_i2c_read_p1_reg(client,DEV_IDH_REG,&c2);
180 static int anx980x_bist_mode(struct i2c_client *client)
185 //Power on total and select DP mode
187 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
190 val = DP_TX_RST_HW_RST;
191 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
194 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
197 anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
199 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
202 //get chip ID. Make sure I2C is OK
203 anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
205 printk("Chip found\n");
210 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
211 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
212 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
213 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
215 printk("clock is detected.\n");
221 //check whther clock is stable
224 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
225 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
226 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
227 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
229 printk("clock is stable.\n");
235 //VESA range, 8bits BPC, RGB
237 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
238 //RK_EDP chip analog setting
240 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
242 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
244 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
248 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
250 //RK_EDP chip analog setting
252 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
254 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
256 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
258 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
260 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
264 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
267 anx6345_i2c_write_p0_reg(client, 0xc8, &val);
269 anx6345_i2c_write_p0_reg(client, 0xa3, &val);
270 anx6345_i2c_write_p0_reg(client, 0xa4, &val);
271 anx6345_i2c_write_p0_reg(client, 0xa5,&val);
272 anx6345_i2c_write_p0_reg(client, 0xa6, &val);
276 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
278 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
282 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
285 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
288 //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
290 val = DP_TX_LINK_TRAINING_CTRL_EN;
291 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
293 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
294 while((val&0x01)&&(cnt++ < 10))
296 printk("Waiting...\n");
298 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
303 printk(KERN_INFO "HW LT fail\n");
307 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
310 DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
312 //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
314 //Set bist format 2048x1536
316 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
318 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
321 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
323 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
325 anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
327 anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
329 anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
331 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
333 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
335 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
337 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
340 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
342 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
345 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
347 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
349 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
351 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
353 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
356 val = DP_TX_VID_CTRL4_BIST;
357 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
360 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
361 //force HPD and stream valid
363 anx6345_i2c_write_p0_reg(client, 0x82, &val);
368 static int anx980x_aux_rst(struct i2c_client *client)
371 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
372 val |= DP_TX_AUX_RST;
373 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
374 val &= ~DP_TX_AUX_RST;
375 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
380 static int anx980x_wait_aux_finished(struct i2c_client *client)
385 anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
393 anx980x_aux_rst(client);
397 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
403 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
408 anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
410 //set read cmd and count
411 val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
412 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
414 //set aux address15:0
415 val = (char)addr&0xff;
416 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
417 val = (char)((addr>>8)&0xff);
418 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
420 //set address19:16 and enable aux
421 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
422 val &=(0xf0)|(char)((addr>>16)&0xff);
423 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
426 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
428 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
431 anx980x_wait_aux_finished(client);
433 for(i =0;i<cCount;i++)
435 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
437 //debug_printf("c = %.2x\n",(WORD)c);
450 static int anx_video_map_config(struct i2c_client *client)
454 anx6345_i2c_write_p1_reg(client, 0x40, &val);
455 anx6345_i2c_write_p1_reg(client, 0x41, &val);
456 anx6345_i2c_write_p1_reg(client, 0x48, &val);
457 anx6345_i2c_write_p1_reg(client, 0x49, &val);
458 anx6345_i2c_write_p1_reg(client, 0x50, &val);
459 anx6345_i2c_write_p1_reg(client, 0x51, &val);
463 anx6345_i2c_write_p1_reg(client, 0x42+i, &val);
469 anx6345_i2c_write_p1_reg(client, 0x4a+i, &val);
475 anx6345_i2c_write_p1_reg(client, 0x52+i, &val);
481 static int anx980x_eanble_video_input(struct i2c_client *client)
485 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
486 val |= DP_TX_VID_CTRL1_VID_EN;
487 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
489 anx_video_map_config(client);
494 static int anx980x_init(struct i2c_client *client)
499 char dp_tx_bw,dp_tx_lane_count;
502 #if defined(BIST_MODE)
503 return anx980x_bist_mode(client);
505 //power on all block and select DisplayPort mode
506 val |= DP_POWERD_AUDIO_REG;
507 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
509 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
510 val &= ~DP_TX_VID_CTRL1_VID_EN;
511 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
514 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
515 val |= DP_TX_RST_SW_RST;
516 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
517 val &= ~DP_TX_RST_SW_RST;
518 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
522 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
524 anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
526 //24bit SDR,negedge latch, and wait video stable
528 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
530 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
532 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
535 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
536 val |= DP_TX_AC_MODE;
537 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
541 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
544 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
546 anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
548 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
550 //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
552 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
555 anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
557 anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
559 //power down PLL filter
561 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
563 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
564 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
565 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
566 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
569 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
571 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
573 val = DP_TX_LINK_TRAINING_CTRL_EN;
574 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
576 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
577 while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
579 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
584 printk(KERN_INFO "HW LT fail\n");
587 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
588 //DP_TX_Config_Video(client);
589 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
590 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
591 if(!(val & DP_TX_SYS_CTRL1_DET_STA))
594 //return; //mask by yxj
597 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
598 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
599 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
600 if(val & DP_TX_SYS_CTRL2_CHA_STA)
602 printk("pclk not stable!\n");
603 //return; mask by yxj
606 anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
607 dp_tx_bw = ByteBuf[0];
608 dp_tx_lane_count = ByteBuf[1] & 0x0f;
609 printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
613 //set Input BPC mode & color space
614 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
616 val = val |((char)(0) << 4); //8bits ,rgb
617 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
623 anx980x_eanble_video_input(client);
629 static int anx6345_bist_mode(struct i2c_client *client)
631 struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
632 struct rk_screen *screen = &anx6345->screen;
633 u16 x_total ,y_total, x_act;
635 //these register are for bist mode
636 x_total = screen->mode.left_margin + screen->mode.right_margin +
637 screen->mode.xres + screen->mode.hsync_len;
638 y_total = screen->mode.upper_margin + screen->mode.lower_margin +
639 screen->mode.yres + screen->mode.vsync_len;
641 x_act = screen->mode.xres >> 1;
642 val = y_total & 0xff;
643 anx6345_i2c_write_p1_reg(client,TOTAL_LINEL_REG,&val);
644 val = (y_total >> 8);
645 anx6345_i2c_write_p1_reg(client,TOTAL_LINEH_REG,&val);
646 val = (screen->mode.yres & 0xff);
647 anx6345_i2c_write_p1_reg(client,ACT_LINEL_REG,&val);
648 val = (screen->mode.yres >> 8);
649 anx6345_i2c_write_p1_reg(client,ACT_LINEH_REG,&val);
650 val = screen->mode.lower_margin;
651 anx6345_i2c_write_p1_reg(client,VF_PORCH_REG,&val);
652 val = screen->mode.vsync_len;
653 anx6345_i2c_write_p1_reg(client,VSYNC_CFG_REG,&val);
654 val = screen->mode.upper_margin;
655 anx6345_i2c_write_p1_reg(client,VB_PORCH_REG,&val);
656 val = x_total & 0xff;
657 anx6345_i2c_write_p1_reg(client,TOTAL_PIXELL_REG,&val);
659 anx6345_i2c_write_p1_reg(client,TOTAL_PIXELH_REG,&val);
660 val = (x_act & 0xff);
661 anx6345_i2c_write_p1_reg(client,ACT_PIXELL_REG,&val);
663 anx6345_i2c_write_p1_reg(client,ACT_PIXELH_REG,&val);
664 val = screen->mode.right_margin & 0xff;
665 anx6345_i2c_write_p1_reg(client,HF_PORCHL_REG,&val);
666 val = screen->mode.right_margin >> 8;
667 anx6345_i2c_write_p1_reg(client,HF_PORCHH_REG,&val);
668 val = screen->mode.hsync_len & 0xff;
669 anx6345_i2c_write_p1_reg(client,HSYNC_CFGL_REG,&val);
670 val = screen->mode.hsync_len >> 8;
671 anx6345_i2c_write_p1_reg(client,HSYNC_CFGH_REG,&val);
672 val = screen->mode.left_margin & 0xff;
673 anx6345_i2c_write_p1_reg(client,HB_PORCHL_REG,&val);
674 val = screen->mode.left_margin >> 8;
675 anx6345_i2c_write_p1_reg(client,HB_PORCHH_REG,&val);
677 anx6345_i2c_write_p1_reg(client,VID_CTRL10_REG,&val);
680 //enable BIST. In normal mode, don't need to config this reg
682 anx6345_i2c_write_p1_reg(client, VID_CTRL4_REG, &val);
683 printk("anx6345 enter bist mode\n");
689 int anx6345_start_aux_transaction(struct i2c_client *client)
693 int timeout_loop = 0;
697 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
699 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
701 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
702 while (val & AUX_EN) {
704 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
705 dev_err(&client->dev, "AUX CH enable timeout!\n");
708 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
712 /* Is AUX CH command redply received? */
713 anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
714 while (!(val & RPLY_RECEIV)) {
716 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
717 dev_err(&client->dev, "AUX CH command redply failed!\n");
720 anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
724 /* Clear interrupt source for AUX CH command redply */
725 anx6345_i2c_write_p1_reg(client, DP_INT_STA, &val);
727 /* Check AUX CH error access status */
728 anx6345_i2c_read_p0_reg(client, AUX_CH_STA, &val);
729 if ((val & AUX_STATUS_MASK) != 0) {
730 dev_err(&client->dev, "AUX CH error happens: %d\n\n",
731 val & AUX_STATUS_MASK);
738 int anx6345_dpcd_write_bytes(struct i2c_client *client,
739 unsigned int val_addr,
741 unsigned char data[])
744 unsigned int start_offset;
745 unsigned int cur_data_count;
746 unsigned int cur_data_idx;
750 while (start_offset < count) {
751 /* Buffer size of AUX CH is 16 * 4bytes */
752 if ((count - start_offset) > 16)
755 cur_data_count = count - start_offset;
758 anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
760 val = AUX_ADDR_7_0(val_addr + start_offset);
761 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
762 val = AUX_ADDR_15_8(val_addr + start_offset);
763 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
764 val = AUX_ADDR_19_16(val_addr + start_offset);
765 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
767 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
769 val = data[start_offset + cur_data_idx];
770 anx6345_i2c_write_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
774 * Set DisplayPort transaction and write
775 * If bit 3 is 1, DisplayPort transaction.
776 * If Bit 3 is 0, I2C transaction.
778 val = AUX_LENGTH(cur_data_count) |
779 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
780 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
782 /* Start AUX transaction */
783 retval = anx6345_start_aux_transaction(client);
787 dev_dbg(&client->dev, "Aux Transaction fail!\n");
790 start_offset += cur_data_count;
797 int anx6345_dpcd_read_bytes(struct i2c_client *client,
798 unsigned int val_addr,
800 unsigned char data[])
803 unsigned int start_offset;
804 unsigned int cur_data_count;
805 unsigned int cur_data_idx;
810 while (start_offset < count) {
811 /* Buffer size of AUX CH is 16 * 4bytes */
812 if ((count - start_offset) > 16)
815 cur_data_count = count - start_offset;
817 /* AUX CH Request Transaction process */
818 for (i = 0; i < 10; i++) {
819 /* Select DPCD device address */
820 val = AUX_ADDR_7_0(val_addr + start_offset);
821 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
822 val = AUX_ADDR_15_8(val_addr + start_offset);
823 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
824 val = AUX_ADDR_19_16(val_addr + start_offset);
825 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
828 * Set DisplayPort transaction and read
829 * If bit 3 is 1, DisplayPort transaction.
830 * If Bit 3 is 0, I2C transaction.
832 val = AUX_LENGTH(cur_data_count) |
833 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
834 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
837 anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
839 /* Start AUX transaction */
840 retval = anx6345_start_aux_transaction(client);
844 dev_dbg(&client->dev, "Aux Transaction fail!\n");
847 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
849 anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
850 data[start_offset + cur_data_idx] = val;
851 dev_dbg(&client->dev, "0x%05x :0x%02x\n",cur_data_idx, val);
854 start_offset += cur_data_count;
861 int anx6345_select_i2c_device(struct i2c_client *client,
862 unsigned int device_addr,
868 /* Set normal AUX CH command */
869 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
871 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
872 /* Set EDID device address */
874 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
876 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
877 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
879 /* Set offset from base address of EDID device */
880 anx6345_i2c_write_p0_reg(client, BUF_DATA_0, &val_addr);
883 * Set I2C transaction and write address
884 * If bit 3 is 1, DisplayPort transaction.
885 * If Bit 3 is 0, I2C transaction.
887 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
889 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
891 /* Start AUX transaction */
892 retval = anx6345_start_aux_transaction(client);
894 dev_dbg(&client->dev, "Aux Transaction fail!\n");
899 int anx6345_edid_read_bytes(struct i2c_client *client,
900 unsigned int device_addr,
901 unsigned int val_addr,
903 unsigned char edid[])
907 unsigned int start_offset;
908 unsigned int cur_data_idx;
909 unsigned int cur_data_cnt;
910 unsigned int defer = 0;
913 for (i = 0; i < count; i += 16) {
915 if ((count - start_offset) > 16)
918 cur_data_cnt = count - start_offset;
920 * If Rx sends defer, Tx sends only reads
921 * request without sending addres
924 retval = anx6345_select_i2c_device(client,
925 device_addr, val_addr + i);
930 * Set I2C transaction and write data
931 * If bit 3 is 1, DisplayPort transaction.
932 * If Bit 3 is 0, I2C transaction.
934 val = AUX_LENGTH(cur_data_cnt) | AUX_TX_COMM_I2C_TRANSACTION |
936 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
938 /* Start AUX transaction */
939 retval = anx6345_start_aux_transaction(client);
941 dev_dbg(&client->dev, "Aux Transaction fail!\n");
943 /* Check if Rx sends defer */
944 anx6345_i2c_read_p0_reg(client, DP_AUX_RX_COMM, &val);
945 if (val == AUX_RX_COMM_AUX_DEFER ||
946 val == AUX_RX_COMM_I2C_DEFER) {
947 dev_err(&client->dev, "Defer: %d\n\n", val);
952 for (cur_data_idx = 0; cur_data_idx < cur_data_cnt; cur_data_idx++) {
953 anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
954 edid[i + cur_data_idx] = val;
955 dev_dbg(&client->dev, "0x%02x : 0x%02x\n", i + cur_data_idx, val);
962 static int anx6345_read_edid(struct i2c_client *client)
964 unsigned char edid[EDID_LENGTH * 2];
965 unsigned char extend_block = 0;
967 unsigned char test_vector;
970 struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
973 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
974 retval = anx6345_edid_read_bytes(client, EDID_ADDR,
975 EDID_EXTENSION_FLAG,1,&extend_block);
977 dev_err(&client->dev, "EDID extension flag failed!\n");
981 if (extend_block > 0) {
982 dev_dbg(&client->dev, "EDID data includes a single extension!\n");
985 retval = anx6345_edid_read_bytes(client, EDID_ADDR,
990 dev_err(&client->dev, "EDID Read failed!\n");
993 sum = edp_calc_edid_check_sum(edid);
995 dev_warn(&client->dev, "EDID bad checksum!\n");
999 /* Read additional EDID data */
1000 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_LENGTH,
1001 EDID_LENGTH, &edid[EDID_LENGTH]);
1003 dev_err(&client->dev, "EDID Read failed!\n");
1006 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
1008 dev_warn(&client->dev, "EDID bad checksum!\n");
1012 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1015 dev_err(&client->dev, "DPCD EDID Read failed!\n");
1019 if (test_vector & DPCD_TEST_EDID_READ) {
1020 retval = anx6345_dpcd_write_bytes(client,
1021 DPCD_TEST_EDID_CHECKSUM,1,
1022 &edid[EDID_LENGTH + EDID_CHECKSUM]);
1024 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1028 addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1029 retval = anx6345_dpcd_write_bytes(client,
1030 DPCD_TEST_RESPONSE, 1, &addr);
1032 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1037 dev_info(&client->dev, "EDID data does not include any extensions.\n");
1039 /* Read EDID data */
1040 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_HEADER,
1041 EDID_LENGTH, &edid[EDID_HEADER]);
1043 dev_err(&client->dev, "EDID Read failed!\n");
1047 sum = edp_calc_edid_check_sum(edid);
1049 dev_warn(&client->dev, "EDID bad checksum!\n");
1053 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1056 dev_err(&client->dev, "DPCD EDID Read failed!\n");
1060 if (test_vector & DPCD_TEST_EDID_READ) {
1061 retval = anx6345_dpcd_write_bytes(client,
1062 DPCD_TEST_EDID_CHECKSUM, 1,
1063 &edid[EDID_CHECKSUM]);
1065 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1068 addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1069 retval = anx6345_dpcd_write_bytes(client, DPCD_TEST_RESPONSE,
1072 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1077 fb_edid_to_monspecs(edid, &anx6345->specs);
1078 dev_info(&client->dev, "EDID Read success!\n");
1082 static int anx6345_init(struct i2c_client *client)
1091 anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
1097 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1098 anx6345_i2c_write_p0_reg(client, SYS_CTRL1_REG, &val);
1099 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1100 if((val&SYS_CTRL1_DET_STA)!=0)
1108 printk("no clock detected by anx6345\n");
1110 //check whether clock is stable
1113 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1114 anx6345_i2c_write_p0_reg(client,SYS_CTRL2_REG, &val);
1115 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1116 if((val&SYS_CTRL2_CHA_STA)==0)
1123 printk("clk is not stable\n");
1125 anx6345_dpcd_read_bytes(client, DPCD_REV, 12, buf);
1126 anx6345_read_edid(client);
1128 //VESA range, 6bits BPC, RGB
1130 anx6345_i2c_write_p1_reg(client, VID_CTRL2_REG, &val);
1132 //ANX6345 chip pll setting
1134 anx6345_i2c_write_p0_reg(client, PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00
1137 //ANX chip analog setting
1139 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70
1141 anx6345_i2c_write_p0_reg(client, LINK_DEBUG_REG, &val);
1144 //anx6345_i2c_write_p0_reg(client, SYS_CTRL3_REG, &val);
1148 anx6345_i2c_read_p1_reg(client, RST_CTRL2_REG, &val);
1150 anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1152 anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1156 anx6345_i2c_write_p0_reg(client, LINK_BW_SET_REG, &val);
1159 anx6345_i2c_write_p0_reg(client,LANE_COUNT_SET_REG,&val);
1161 val = LINK_TRAINING_CTRL_EN;
1162 anx6345_i2c_write_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1164 anx6345_i2c_read_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1165 while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80
1167 printk("Waiting...\n");
1169 anx6345_i2c_read_p0_reg(client,LINK_TRAINING_CTRL_REG,&val);
1174 printk(KERN_INFO "HW LT fail\n");
1177 printk("HW LT Success>>:times:%d\n",(51-cnt));
1181 //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
1182 //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
1184 #if defined(BIST_MODE)
1185 anx6345_bist_mode(client);
1190 anx6345_i2c_write_p1_reg(client,VID_CTRL1_REG,&val);
1192 anx_video_map_config(client);
1193 //force HPD and stream valid
1195 anx6345_i2c_write_p0_reg(client,SYS_CTRL3_REG,&val);
1197 anx6345_i2c_read_p0_reg(client,LANE_COUNT_SET_REG, &lc);
1198 anx6345_i2c_read_p0_reg(client,LINK_BW_SET_REG, &bw);
1199 printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
1205 static int anx6345_disable(void)
1207 struct edp_anx6345 *anx6345 = edp;
1209 if (!anx6345->pdata->pwron)
1211 gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
1212 gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
1213 anx6345->pdata->pwron = false;
1220 static int anx6345_enable(void)
1222 struct edp_anx6345 *anx6345 = edp;
1224 if (!anx6345->pdata->pwron) {
1225 gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
1227 gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
1228 gpio_set_value(anx6345->pdata->edp_rst_pin,0);
1230 gpio_set_value(anx6345->pdata->edp_rst_pin,1);
1231 anx6345->pdata->pwron = true;
1233 anx6345->edp_anx_init(anx6345->client);
1236 #ifdef CONFIG_HAS_EARLYSUSPEND
1237 static void anx6345_early_suspend(struct early_suspend *h)
1242 static void anx6345_late_resume(struct early_suspend *h)
1248 #if defined(CONFIG_OF)
1250 static int anx6345_power_ctl(struct anx6345_platform_data *pdata)
1253 ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
1255 gpio_free(pdata->dvdd33_en_pin);
1256 printk(KERN_ERR "request dvdd33 en pin fail!\n");
1259 gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
1263 ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
1265 gpio_free(pdata->dvdd18_en_pin);
1266 printk(KERN_ERR "request dvdd18 en pin fail!\n");
1269 gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
1272 ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
1274 gpio_free(pdata->edp_rst_pin);
1275 printk(KERN_ERR "request rst pin fail!\n");
1278 gpio_direction_output(pdata->edp_rst_pin, 0);
1280 gpio_direction_output(pdata->edp_rst_pin, 1);
1282 pdata->pwron = true;
1288 struct rk_fb_trsm_ops trsm_edp_ops = {
1289 .enable = anx6345_enable,
1290 .disable = anx6345_disable,
1293 static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
1295 struct device_node *np = anx6345->client->dev.of_node;
1296 struct anx6345_platform_data *pdata;
1297 enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
1298 pdata = devm_kzalloc(&anx6345->client->dev,
1299 sizeof(struct anx6345_platform_data ), GFP_KERNEL);
1301 dev_err(&anx6345->client->dev,
1302 "failed to allocate platform data\n");
1305 pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
1306 pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
1307 pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
1308 pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1309 pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1310 pdata->power_ctl = anx6345_power_ctl;
1311 anx6345->pdata = pdata;
1315 static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
1320 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
1322 struct edp_anx6345 *anx6345;
1326 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1328 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
1331 anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
1333 if (unlikely(!anx6345)) {
1334 dev_err(&client->dev, "alloc for struct anx6345 fail\n");
1338 anx6345->client = client;
1339 anx6345->pdata = dev_get_platdata(&client->dev);
1340 if (!anx6345->pdata) {
1341 anx6345_parse_dt(anx6345);
1343 i2c_set_clientdata(client,anx6345);
1344 rk_fb_get_prmry_screen(&anx6345->screen);
1345 if (anx6345->screen.type != SCREEN_EDP){
1346 dev_err(&client->dev, "screen is not edp!\n");
1349 if(anx6345->pdata->power_ctl)
1350 anx6345->pdata->power_ctl(anx6345->pdata);
1352 #if defined(CONFIG_DEBUG_FS)
1353 anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
1354 if (IS_ERR(anx6345->debugfs_dir)) {
1355 dev_err(&client->dev, "failed to create debugfs dir for edp!\n");
1358 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
1361 #ifdef CONFIG_HAS_EARLYSUSPEND
1362 anx6345->early_suspend.suspend = anx6345_early_suspend;
1363 anx6345->early_suspend.resume = anx6345_late_resume;
1364 anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
1365 register_early_suspend(&anx6345->early_suspend);
1367 chip_id = get_dp_chip_id(client);
1368 if(chip_id == 0x9805)
1369 anx6345->edp_anx_init = anx980x_init;
1371 anx6345->edp_anx_init = anx6345_init;
1374 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1376 dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
1381 static int anx6345_i2c_remove(struct i2c_client *client)
1386 static const struct i2c_device_id id_table[] = {
1391 #if defined(CONFIG_OF)
1392 static struct of_device_id anx6345_dt_ids[] = {
1393 { .compatible = "analogix, anx6345" },
1398 static struct i2c_driver anx6345_i2c_driver = {
1401 .owner = THIS_MODULE,
1402 #if defined(CONFIG_OF)
1403 .of_match_table = of_match_ptr(anx6345_dt_ids),
1406 .probe = &anx6345_i2c_probe,
1407 .remove = &anx6345_i2c_remove,
1408 .id_table = id_table,
1412 static int __init anx6345_module_init(void)
1414 return i2c_add_driver(&anx6345_i2c_driver);
1417 static void __exit anx6345_module_exit(void)
1419 i2c_del_driver(&anx6345_i2c_driver);
1422 fs_initcall(anx6345_module_init);
1423 module_exit(anx6345_module_exit);