drivers/video/rockchip/transmitter/dp_anx6345.c

   1 #include <linux/kernel.h>
   2 #include <linux/module.h>
   3 #include <linux/time.h>
   4 #include <linux/delay.h>
   5 #include <linux/slab.h>
   6 #include <linux/device.h>
   7 #include <linux/i2c.h>
   8
   9 #if defined(CONFIG_HAS_EARLYSUSPEND)
  10 #include<linux/earlysuspend.h>
  11 #endif
  12 #if defined(CONFIG_OF)
  13 #include <linux/of_gpio.h>
  14 #endif
  15 #include "anx6345.h"
  16 #include "dpcd_edid.h"
  17 #if defined(CONFIG_DEBUG_FS)
  18 #include <linux/fs.h>
  19 #include <linux/debugfs.h>
  20 #include <linux/seq_file.h>
  21 #endif
  22
  23
  24 //#define BIST_MODE 0
  25 static int i2c_master_reg8_send(const struct i2c_client *client,
  26                 const char reg, const char *buf, int count, int scl_rate)
  27 {
  28         struct i2c_adapter *adap=client->adapter;
  29         struct i2c_msg msg;
  30         int ret;
  31         char *tx_buf = (char *)kmalloc(count + 1, GFP_KERNEL);
  32         if(!tx_buf)
  33                 return -ENOMEM;
  34         tx_buf[0] = reg;
  35         memcpy(tx_buf+1, buf, count);
  36
  37         msg.addr = client->addr;
  38         msg.flags = client->flags;
  39         msg.len = count + 1;
  40         msg.buf = (char *)tx_buf;
  41         msg.scl_rate = scl_rate;
  42
  43         ret = i2c_transfer(adap, &msg, 1);
  44         kfree(tx_buf);
  45         return (ret == 1) ? count : ret;
  46
  47 }
  48
  49 static int i2c_master_reg8_recv(const struct i2c_client *client,
  50                 const char reg, char *buf, int count, int scl_rate)
  51 {
  52         struct i2c_adapter *adap=client->adapter;
  53         struct i2c_msg msgs[2];
  54         int ret;
  55         char reg_buf = reg;
  56
  57         msgs[0].addr = client->addr;
  58         msgs[0].flags = client->flags;
  59         msgs[0].len = 1;
  60         msgs[0].buf = &reg_buf;
  61         msgs[0].scl_rate = scl_rate;
  62
  63         msgs[1].addr = client->addr;
  64         msgs[1].flags = client->flags | I2C_M_RD;
  65         msgs[1].len = count;
  66         msgs[1].buf = (char *)buf;
  67         msgs[1].scl_rate = scl_rate;
  68
  69         ret = i2c_transfer(adap, msgs, 2);
  70
  71         return (ret == 2)? count : ret;
  72 }
  73
  74 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
  75 {
  76         int ret;
  77         client->addr = DP_TX_PORT0_ADDR >> 1;
  78         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  79         if(ret < 0)
  80         {
  81                 printk(KERN_ERR "%s>>err\n",__func__);
  82         }
  83
  84         return ret;
  85 }
  86 static int  anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
  87 {
  88         int ret;
  89         client->addr = DP_TX_PORT0_ADDR >> 1;
  90         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
  91         if(ret < 0)
  92         {
  93                 printk(KERN_ERR "%s>>err\n",__func__);
  94         }
  95
  96         return ret;
  97 }
  98 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
  99 {
 100         int ret;
 101         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 102         ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 103         if(ret < 0)
 104         {
 105                 printk(KERN_ERR "%s>>err\n",__func__);
 106         }
 107
 108         return ret;
 109 }
 110
 111 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
 112 {
 113         int ret;
 114         client->addr = HDMI_TX_PORT0_ADDR >> 1;
 115         ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
 116         if(ret < 0)
 117         {
 118                 printk(KERN_ERR "%s>>err\n",__func__);
 119         }
 120
 121         return ret;
 122 }
 123
 124 #if defined(CONFIG_DEBUG_FS)
 125 static int edp_reg_show(struct seq_file *s, void *v)
 126 {
 127         int i = 0;
 128         char val;
 129         struct edp_anx6345 *anx6345 = s->private;
 130         if(!anx6345)
 131         {
 132                 printk(KERN_ERR "no edp device!\n");
 133                 return 0;
 134         }
 135
 136         seq_printf(s,"0x70:\n");
 137         for(i=0;i< MAX_REG;i++)
 138         {
 139                 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
 140                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 141         }
 142
 143         seq_printf(s,"\n0x72:\n");
 144         for(i=0;i< MAX_REG;i++)
 145         {
 146                 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
 147                 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
 148         }
 149         return 0;
 150 }
 151
 152 static int edp_reg_open(struct inode *inode, struct file *file)
 153 {
 154         struct edp_anx6345 *anx6345 = inode->i_private;
 155         return single_open(file, edp_reg_show, anx6345);
 156 }
 157
 158 static const struct file_operations edp_reg_fops = {
 159         .owner          = THIS_MODULE,
 160         .open           = edp_reg_open,
 161         .read           = seq_read,
 162         .llseek         = seq_lseek,
 163         .release        = single_release,
 164 };
 165 #endif
 166
 167 //get chip ID. Make sure I2C is OK
 168 static int get_dp_chip_id(struct i2c_client *client)
 169 {
 170         char c1,c2;
 171         int id;
 172         anx6345_i2c_read_p1_reg(client,DEV_IDL_REG,&c1);
 173         anx6345_i2c_read_p1_reg(client,DEV_IDH_REG,&c2);
 174         id = c2;
 175         return (id<<8)|c1;
 176 }
 177
 178
 179 static int anx980x_bist_mode(struct i2c_client *client)
 180 {
 181         char val,i;
 182         u8 cnt=0;
 183
 184         //Power on total and select DP mode
 185         val = 00;
 186         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 187
 188         //HW reset
 189         val = DP_TX_RST_HW_RST;
 190         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 191         msleep(10);
 192         val = 0x00;
 193         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 194
 195
 196         anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 197         val = 0x00;
 198         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
 199
 200
 201         //get chip ID. Make sure I2C is OK
 202         anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
 203         if (val==0x98)
 204                 printk("Chip found\n");
 205
 206         //for clocl detect
 207         for(i=0;i<100;i++)
 208         {
 209                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 210                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 211                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 212                 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
 213                 {
 214                         printk("clock is detected.\n");
 215                         break;
 216                 }
 217
 218                 msleep(10);
 219         }
 220        //check whther clock is stable
 221         for(i=0;i<50;i++)
 222         {
 223                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 224                 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 225                 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
 226                 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
 227                 {
 228                         printk("clock is stable.\n");
 229                         break;
 230                 }
 231                 msleep(10);
 232         }
 233
 234         //VESA range, 8bits BPC, RGB
 235         val = 0x10;
 236         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
 237         //RK_EDP chip analog setting
 238         val = 0x07;
 239         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 240         val = 0x19;
 241         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 242         val = 0xd9;
 243         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 244
 245         //Select AC mode
 246         val = 0x40;
 247         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 248
 249         //RK_EDP chip analog setting
 250         val = 0xf0;
 251         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 252         val = 0x99;
 253         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 254         val = 0x7b;
 255         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 256         val = 0x30;
 257         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 258         val = 0x06;
 259         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
 260
 261         //force HPD
 262         val = 0x30;
 263         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
 264         //power on 4 lanes
 265         val = 0x00;
 266         anx6345_i2c_write_p0_reg(client, 0xc8, &val);
 267         //lanes setting
 268         anx6345_i2c_write_p0_reg(client, 0xa3, &val);
 269         anx6345_i2c_write_p0_reg(client, 0xa4, &val);
 270         anx6345_i2c_write_p0_reg(client, 0xa5,&val);
 271         anx6345_i2c_write_p0_reg(client, 0xa6, &val);
 272
 273         //reset AUX CH
 274         val = 0x44;
 275         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 276         val = 0x40;
 277         anx6345_i2c_write_p1_reg(client,  DP_TX_RST_CTRL2_REG, &val);
 278
 279         //Select 1.62G
 280         val = 0x06;
 281         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 282         //Select 4 lanes
 283         val = 0x04;
 284         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 285
 286         //strart link traing
 287         //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
 288         #if 1
 289         val = DP_TX_LINK_TRAINING_CTRL_EN;
 290         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 291         msleep(5);
 292         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 293         while((val&0x01)&&(cnt++ < 10))
 294         {
 295                 printk("Waiting...\n");
 296                 msleep(5);
 297                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 298         }
 299
 300         if(cnt >= 10)
 301         {
 302                 printk(KERN_INFO "HW LT fail\n");
 303         }
 304         else
 305         {
 306                 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
 307         }
 308         #else
 309         DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
 310         #endif
 311         //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
 312
 313         //Set bist format 2048x1536
 314         val = 0x2c;
 315         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
 316         val = 0x06;
 317         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
 318
 319         val = 0x00;
 320         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
 321         val = 0x06;
 322         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
 323         val = 0x02;
 324         anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
 325         val = 0x04;
 326         anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
 327         val = 0x26;
 328         anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
 329         val = 0x50;
 330         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
 331         val = 0x04;
 332         anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
 333         val = 0x00;
 334         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
 335         val = 0x04;
 336         anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
 337
 338         val = 0x18;
 339         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
 340         val = 0x00;
 341         anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
 342
 343         val = 0x10;
 344         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
 345         val = 0x00;
 346         anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
 347         val = 0x28;
 348         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
 349         val = 0x00;
 350         anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
 351         val = 0x03;
 352         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
 353
 354         //enable BIST
 355         val = DP_TX_VID_CTRL4_BIST;
 356         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
 357         //enable video input
 358         val = 0x8d;
 359         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 360         //force HPD and stream valid
 361         val = 0x33;
 362         anx6345_i2c_write_p0_reg(client, 0x82, &val);
 363
 364         return 0;
 365 }
 366
 367 static int anx980x_aux_rst(struct i2c_client *client)
 368 {
 369         char val;
 370         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 371         val |= DP_TX_AUX_RST;
 372         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 373         val &= ~DP_TX_AUX_RST;
 374         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 375         return 0;
 376 }
 377
 378
 379 static int anx980x_wait_aux_finished(struct i2c_client *client)
 380 {
 381         char val,cnt;
 382         cnt = 0;
 383
 384         anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
 385         while(val&0x01)
 386         {
 387                 //delay_ms(20);
 388                 cnt ++;
 389                 if(cnt == 10)
 390                 {
 391                    printk("aux break");
 392                     anx980x_aux_rst(client);
 393                     //cnt = 0;
 394                     break;
 395                 }
 396                 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 397         }
 398
 399         return 0;
 400 }
 401
 402 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
 403 {
 404         char val,i;
 405
 406         val = 0x80;
 407         anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
 408
 409         //set read cmd and count
 410         val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
 411         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
 412
 413         //set aux address15:0
 414         val = (char)addr&0xff;
 415         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
 416         val = (char)((addr>>8)&0xff);
 417         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
 418
 419         //set address19:16 and enable aux
 420         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 421         val &=(0xf0)|(char)((addr>>16)&0xff);
 422         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
 423
 424         //Enable Aux
 425         anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 426         val |= 0x01;
 427         anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
 428
 429         //delay_ms(2);
 430         anx980x_wait_aux_finished(client);
 431
 432         for(i =0;i<cCount;i++)
 433         {
 434                 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
 435
 436                 //debug_printf("c = %.2x\n",(WORD)c);
 437                 *(pBuf+i) = val;
 438
 439                 if(i >= MAX_BUF_CNT)
 440                         return 1;
 441                         //break;
 442         }
 443
 444         return 0;
 445
 446
 447 }
 448
 449 static int anx_video_map_config(struct i2c_client *client)
 450 {
 451         char val = 0;
 452         char i = 0;
 453         anx6345_i2c_write_p1_reg(client,  0x40, &val);
 454         anx6345_i2c_write_p1_reg(client,  0x41, &val);
 455         anx6345_i2c_write_p1_reg(client,  0x48, &val);
 456         anx6345_i2c_write_p1_reg(client,  0x49, &val);
 457         anx6345_i2c_write_p1_reg(client,  0x50, &val);
 458         anx6345_i2c_write_p1_reg(client,  0x51, &val);
 459         for(i=0; i<6; i++)
 460         {
 461                 val = i;
 462                 anx6345_i2c_write_p1_reg(client,  0x42+i, &val);
 463         }
 464
 465         for(i=0; i<6; i++)
 466         {
 467                 val = 6+i;
 468                 anx6345_i2c_write_p1_reg(client,  0x4a+i, &val);
 469         }
 470
 471         for(i=0; i<6; i++)
 472         {
 473                 val = 0x0c+i;
 474                 anx6345_i2c_write_p1_reg(client,  0x52+i, &val);
 475         }
 476
 477         return 0;
 478
 479 }
 480 static int anx980x_eanble_video_input(struct i2c_client *client)
 481 {
 482         char val;
 483
 484         anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 485         val |= DP_TX_VID_CTRL1_VID_EN;
 486         anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL1_REG, &val);
 487
 488         anx_video_map_config(client);
 489
 490         return 0;
 491 }
 492
 493 static int anx980x_init(struct i2c_client *client)
 494 {
 495         char val = 0x00;
 496         char safe_mode = 0;
 497         char ByteBuf[2];
 498         char dp_tx_bw,dp_tx_lane_count;
 499         char cnt = 10;
 500
 501 #if defined(BIST_MODE)
 502         return anx980x_bist_mode(client);
 503 #endif
 504          //power on all block and select DisplayPort mode
 505         val |= DP_POWERD_AUDIO_REG;
 506         anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
 507
 508         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 509         val &= ~DP_TX_VID_CTRL1_VID_EN;
 510         anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
 511
 512         //software reset
 513         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 514         val |= DP_TX_RST_SW_RST;
 515         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
 516         val &= ~DP_TX_RST_SW_RST;
 517         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
 518
 519
 520         val = 0x07;
 521         anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
 522         val = 0x50;
 523         anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
 524
 525         //24bit SDR,negedge latch, and wait video stable
 526         val = 0x01;
 527         anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
 528         val = 0x19;
 529         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
 530         val = 0xd9;
 531         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
 532
 533         //serdes ac mode.
 534         anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 535         val |= DP_TX_AC_MODE;
 536         anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
 537
 538         //set termination
 539         val = 0xf0;
 540         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
 541         //set duty cycle
 542         val = 0x99;
 543         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
 544
 545         anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 546         val |= 0x2a;
 547         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
 548
 549         //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
 550         val = 0x30;
 551         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
 552
 553         //for DP link CTS
 554         anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 555         val |= 0x40;
 556         anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
 557
 558         //power down  PLL filter
 559         val = 0x06;
 560         anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
 561
 562         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
 563         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
 564         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
 565         anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
 566
 567         val = 0x06;
 568         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
 569         val = 0x04;
 570         anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
 571
 572         val = DP_TX_LINK_TRAINING_CTRL_EN;
 573         anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
 574         msleep(2);
 575         anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 576         while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
 577         {
 578                 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
 579                 cnt--;
 580         }
 581         if(cnt < 0)
 582         {
 583                 printk(KERN_INFO "HW LT fail\n");
 584         }
 585         else
 586                 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
 587         //DP_TX_Config_Video(client);
 588         anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
 589         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL1_REG, &val);
 590         if(!(val & DP_TX_SYS_CTRL1_DET_STA))
 591         {
 592                 printk("No pclk\n");
 593                 //return;  //mask by yxj
 594         }
 595
 596         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 597         anx6345_i2c_write_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 598         anx6345_i2c_read_p0_reg(client,  DP_TX_SYS_CTRL2_REG, &val);
 599         if(val & DP_TX_SYS_CTRL2_CHA_STA)
 600         {
 601                 printk("pclk not stable!\n");
 602                 //return; mask by yxj
 603         }
 604
 605         anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
 606         dp_tx_bw = ByteBuf[0];
 607         dp_tx_lane_count = ByteBuf[1] & 0x0f;
 608         printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
 609
 610         if(!safe_mode)
 611         {
 612                 //set Input BPC mode & color space
 613                 anx6345_i2c_read_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 614                 val &= 0x8c;
 615                 val = val |((char)(0) << 4);  //8bits  ,rgb
 616                 anx6345_i2c_write_p1_reg(client,  DP_TX_VID_CTRL2_REG, &val);
 617         }
 618
 619
 620
 621         //enable video input
 622          anx980x_eanble_video_input(client);
 623
 624         return 0;
 625 }
 626
 627
 628 static int anx6345_bist_mode(struct i2c_client *client)
 629 {
 630         struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
 631         struct rk_screen *screen = &anx6345->screen;
 632         u16 x_total ,y_total, x_act;
 633         char val = 0x00;
 634         //these register are for bist mode
 635         x_total = screen->mode.left_margin + screen->mode.right_margin +
 636                         screen->mode.xres + screen->mode.hsync_len;
 637         y_total = screen->mode.upper_margin + screen->mode.lower_margin +
 638                         screen->mode.yres + screen->mode.vsync_len;
 639         x_total >>= 1;
 640         x_act = screen->mode.xres >> 1;
 641         val = y_total & 0xff;
 642         anx6345_i2c_write_p1_reg(client,TOTAL_LINEL_REG,&val);
 643         val = (y_total >> 8);
 644         anx6345_i2c_write_p1_reg(client,TOTAL_LINEH_REG,&val);
 645         val = (screen->mode.yres & 0xff);
 646         anx6345_i2c_write_p1_reg(client,ACT_LINEL_REG,&val);
 647         val = (screen->mode.yres >> 8);
 648         anx6345_i2c_write_p1_reg(client,ACT_LINEH_REG,&val);
 649         val = screen->mode.lower_margin;
 650         anx6345_i2c_write_p1_reg(client,VF_PORCH_REG,&val);
 651         val = screen->mode.vsync_len;
 652         anx6345_i2c_write_p1_reg(client,VSYNC_CFG_REG,&val);
 653         val = screen->mode.upper_margin;
 654         anx6345_i2c_write_p1_reg(client,VB_PORCH_REG,&val);
 655         val = x_total & 0xff;
 656         anx6345_i2c_write_p1_reg(client,TOTAL_PIXELL_REG,&val);
 657         val = x_total >> 8;
 658         anx6345_i2c_write_p1_reg(client,TOTAL_PIXELH_REG,&val);
 659         val = (x_act & 0xff);
 660         anx6345_i2c_write_p1_reg(client,ACT_PIXELL_REG,&val);
 661         val = (x_act >> 8);
 662         anx6345_i2c_write_p1_reg(client,ACT_PIXELH_REG,&val);
 663         val = screen->mode.right_margin & 0xff;
 664         anx6345_i2c_write_p1_reg(client,HF_PORCHL_REG,&val);
 665         val = screen->mode.right_margin >> 8;
 666         anx6345_i2c_write_p1_reg(client,HF_PORCHH_REG,&val);
 667         val = screen->mode.hsync_len & 0xff;
 668         anx6345_i2c_write_p1_reg(client,HSYNC_CFGL_REG,&val);
 669         val = screen->mode.hsync_len >> 8;
 670         anx6345_i2c_write_p1_reg(client,HSYNC_CFGH_REG,&val);
 671         val = screen->mode.left_margin & 0xff;
 672         anx6345_i2c_write_p1_reg(client,HB_PORCHL_REG,&val);
 673         val = screen->mode.left_margin  >> 8;
 674         anx6345_i2c_write_p1_reg(client,HB_PORCHH_REG,&val);
 675         val = 0x13;
 676         anx6345_i2c_write_p1_reg(client,VID_CTRL10_REG,&val);
 677
 678
 679        //enable BIST. In normal mode, don't need to config this reg
 680         val = 0x08;
 681         anx6345_i2c_write_p1_reg(client, VID_CTRL4_REG, &val);
 682         printk("anx6345 enter bist mode\n");
 683
 684         return 0;
 685 }
 686
 687
 688 int anx6345_start_aux_transaction(struct i2c_client  *client)
 689 {
 690         char val;
 691         int retval = 0;
 692         int timeout_loop = 0;
 693         int aux_timeout = 0;
 694
 695
 696         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 697         val |= AUX_EN;
 698         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 699
 700         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 701         while (val & AUX_EN) {
 702                 aux_timeout++;
 703                 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
 704                         dev_err(&client->dev, "AUX CH enable timeout!\n");
 705                         return -ETIMEDOUT;
 706                 }
 707                 anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 708                 udelay(100);
 709         }
 710
 711         /* Is AUX CH command redply received? */
 712         anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
 713         while (!(val & RPLY_RECEIV)) {
 714                 timeout_loop++;
 715                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 716                         dev_err(&client->dev, "AUX CH command redply failed!\n");
 717                         return -ETIMEDOUT;
 718                 }
 719                 anx6345_i2c_read_p1_reg(client, DP_INT_STA, &val);
 720                 udelay(10);
 721         }
 722
 723         /* Clear interrupt source for AUX CH command redply */
 724         anx6345_i2c_write_p1_reg(client, DP_INT_STA, &val);
 725
 726         /* Check AUX CH error access status */
 727         anx6345_i2c_read_p0_reg(client, AUX_CH_STA, &val);
 728         if ((val & AUX_STATUS_MASK) != 0) {
 729                 dev_err(&client->dev, "AUX CH error happens: %d\n\n",
 730                         val & AUX_STATUS_MASK);
 731                 return -EREMOTEIO;
 732         }
 733
 734         return retval;
 735 }
 736
 737 int anx6345_dpcd_write_bytes(struct i2c_client *client,
 738                                 unsigned int val_addr,
 739                                 unsigned int count,
 740                                 unsigned char data[])
 741 {
 742         char val;
 743         unsigned int start_offset;
 744         unsigned int cur_data_count;
 745         unsigned int cur_data_idx;
 746         int retval = 0;
 747
 748         start_offset = 0;
 749         while (start_offset < count) {
 750                 /* Buffer size of AUX CH is 16 * 4bytes */
 751                 if ((count - start_offset) > 16)
 752                         cur_data_count = 16;
 753                 else
 754                         cur_data_count = count - start_offset;
 755
 756                 val = BUF_CLR;
 757                 anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
 758
 759                 val = AUX_ADDR_7_0(val_addr + start_offset);
 760                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 761                 val = AUX_ADDR_15_8(val_addr + start_offset);
 762                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 763                 val = AUX_ADDR_19_16(val_addr + start_offset);
 764                 anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 765
 766                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 767                      cur_data_idx++) {
 768                         val = data[start_offset + cur_data_idx];
 769                         anx6345_i2c_write_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 770                 }
 771
 772                 /*
 773                  * Set DisplayPort transaction and write
 774                  * If bit 3 is 1, DisplayPort transaction.
 775                  * If Bit 3 is 0, I2C transaction.
 776                  */
 777                 val = AUX_LENGTH(cur_data_count) |
 778                         AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 779                 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 780
 781                 /* Start AUX transaction */
 782                 retval = anx6345_start_aux_transaction(client);
 783                 if (retval == 0)
 784                         break;
 785                 else
 786                         dev_dbg(&client->dev, "Aux Transaction fail!\n");
 787
 788
 789                 start_offset += cur_data_count;
 790         }
 791
 792         return retval;
 793 }
 794
 795
 796 int anx6345_dpcd_read_bytes(struct i2c_client *client,
 797                                 unsigned int val_addr,
 798                                 unsigned int count,
 799                                 unsigned char data[])
 800 {
 801         char val;
 802         unsigned int start_offset;
 803         unsigned int cur_data_count;
 804         unsigned int cur_data_idx;
 805         int i;
 806         int retval = 0;
 807
 808         start_offset = 0;
 809         while (start_offset < count) {
 810                 /* Buffer size of AUX CH is 16 * 4bytes */
 811                 if ((count - start_offset) > 16)
 812                         cur_data_count = 16;
 813                 else
 814                         cur_data_count = count - start_offset;
 815
 816                 /* AUX CH Request Transaction process */
 817                 for (i = 0; i < 10; i++) {
 818                         /* Select DPCD device address */
 819                         val = AUX_ADDR_7_0(val_addr + start_offset);
 820                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 821                         val = AUX_ADDR_15_8(val_addr + start_offset);
 822                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 823                         val = AUX_ADDR_19_16(val_addr + start_offset);
 824                         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 825
 826                         /*
 827                          * Set DisplayPort transaction and read
 828                          * If bit 3 is 1, DisplayPort transaction.
 829                          * If Bit 3 is 0, I2C transaction.
 830                          */
 831                         val = AUX_LENGTH(cur_data_count) |
 832                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 833                         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 834
 835                         val = BUF_CLR;
 836                         anx6345_i2c_write_p0_reg(client, BUF_DATA_CTL, &val);
 837
 838                         /* Start AUX transaction */
 839                         retval = anx6345_start_aux_transaction(client);
 840                         if (retval == 0)
 841                                 break;
 842                         else
 843                                 dev_dbg(&client->dev, "Aux Transaction fail!\n");
 844                 }
 845
 846                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 847                     cur_data_idx++) {
 848                         anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 849                         data[start_offset + cur_data_idx] = val;
 850                         dev_dbg(&client->dev, "0x%05x :0x%02x\n",cur_data_idx, val);
 851                 }
 852
 853                 start_offset += cur_data_count;
 854         }
 855
 856         return retval;
 857 }
 858
 859
 860 int anx6345_select_i2c_device(struct i2c_client *client,
 861                                 unsigned int device_addr,
 862                                 char val_addr)
 863 {
 864         char val;
 865         int retval;
 866
 867         /* Set normal AUX CH command */
 868         anx6345_i2c_read_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 869         val &= ~ADDR_ONLY;
 870         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_2, &val);
 871         /* Set EDID device address */
 872         val = device_addr;
 873         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_7_0, &val);
 874         val = 0;
 875         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_15_8, &val);
 876         anx6345_i2c_write_p0_reg(client, DP_AUX_ADDR_19_16, &val);
 877
 878         /* Set offset from base address of EDID device */
 879         anx6345_i2c_write_p0_reg(client, BUF_DATA_0, &val_addr);
 880
 881         /*
 882          * Set I2C transaction and write address
 883          * If bit 3 is 1, DisplayPort transaction.
 884          * If Bit 3 is 0, I2C transaction.
 885          */
 886         val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 887                 AUX_TX_COMM_WRITE;
 888         anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 889
 890         /* Start AUX transaction */
 891         retval = anx6345_start_aux_transaction(client);
 892         if (retval != 0)
 893                 dev_dbg(&client->dev, "Aux Transaction fail!\n");
 894
 895         return retval;
 896 }
 897
 898 int anx6345_edid_read_bytes(struct i2c_client *client,
 899                                 unsigned int device_addr,
 900                                 unsigned int val_addr,
 901                                 unsigned char count,
 902                                 unsigned char edid[])
 903 {
 904         char val;
 905         unsigned int i;
 906         unsigned int start_offset;
 907         unsigned int cur_data_idx;
 908         unsigned int cur_data_cnt;
 909         unsigned int defer = 0;
 910         int retval = 0;
 911
 912         for (i = 0; i < count; i += 16) {
 913                 start_offset = i;
 914                 if ((count - start_offset) > 16)
 915                                 cur_data_cnt = 16;
 916                         else
 917                                 cur_data_cnt = count - start_offset;
 918                 /*
 919                  * If Rx sends defer, Tx sends only reads
 920                  * request without sending addres
 921                  */
 922                 if (!defer)
 923                         retval = anx6345_select_i2c_device(client,
 924                                         device_addr, val_addr + i);
 925                 else
 926                         defer = 0;
 927
 928                 /*
 929                  * Set I2C transaction and write data
 930                  * If bit 3 is 1, DisplayPort transaction.
 931                  * If Bit 3 is 0, I2C transaction.
 932                  */
 933                 val = AUX_LENGTH(cur_data_cnt) | AUX_TX_COMM_I2C_TRANSACTION |
 934                         AUX_TX_COMM_READ;
 935                 anx6345_i2c_write_p0_reg(client, DP_AUX_CH_CTL_1, &val);
 936
 937                 /* Start AUX transaction */
 938                 retval = anx6345_start_aux_transaction(client);
 939                 if (retval < 0)
 940                         dev_dbg(&client->dev, "Aux Transaction fail!\n");
 941
 942                 /* Check if Rx sends defer */
 943                 anx6345_i2c_read_p0_reg(client, DP_AUX_RX_COMM, &val);
 944                 if (val == AUX_RX_COMM_AUX_DEFER ||
 945                         val == AUX_RX_COMM_I2C_DEFER) {
 946                         dev_err(&client->dev, "Defer: %d\n\n", val);
 947                         defer = 1;
 948                 }
 949
 950
 951                 for (cur_data_idx = 0; cur_data_idx < cur_data_cnt; cur_data_idx++) {
 952                         anx6345_i2c_read_p0_reg(client, BUF_DATA_0 + cur_data_idx, &val);
 953                         edid[i + cur_data_idx] = val;
 954                         dev_dbg(&client->dev, "0x%02x : 0x%02x\n", i + cur_data_idx, val);
 955                 }
 956         }
 957
 958         return retval;
 959 }
 960
 961 static int anx6345_read_edid(struct i2c_client *client)
 962 {
 963         unsigned char edid[EDID_LENGTH * 2];
 964         unsigned char extend_block = 0;
 965         unsigned char sum;
 966         unsigned char test_vector;
 967         int retval;
 968         char addr;
 969         struct edp_anx6345 *anx6345 = i2c_get_clientdata(client);
 970
 971
 972         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 973         retval = anx6345_edid_read_bytes(client, EDID_ADDR,
 974                                 EDID_EXTENSION_FLAG,1,&extend_block);
 975         if (retval < 0) {
 976                 dev_err(&client->dev, "EDID extension flag failed!\n");
 977                 return -EIO;
 978         }
 979
 980         if (extend_block > 0) {
 981                 dev_dbg(&client->dev, "EDID data includes a single extension!\n");
 982
 983                 /* Read EDID data */
 984                 retval = anx6345_edid_read_bytes(client, EDID_ADDR,
 985                                                 EDID_HEADER,
 986                                                 EDID_LENGTH,
 987                                                 &edid[EDID_HEADER]);
 988                 if (retval != 0) {
 989                         dev_err(&client->dev, "EDID Read failed!\n");
 990                         return -EIO;
 991                 }
 992                 sum = edp_calc_edid_check_sum(edid);
 993                 if (sum != 0) {
 994                         dev_warn(&client->dev, "EDID bad checksum!\n");
 995                         return 0;
 996                 }
 997
 998                 /* Read additional EDID data */
 999                 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_LENGTH,
1000                                                         EDID_LENGTH, &edid[EDID_LENGTH]);
1001                 if (retval != 0) {
1002                         dev_err(&client->dev, "EDID Read failed!\n");
1003                         return -EIO;
1004                 }
1005                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
1006                 if (sum != 0) {
1007                         dev_warn(&client->dev, "EDID bad checksum!\n");
1008                         return 0;
1009                 }
1010
1011                 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1012                                                 1, &test_vector);
1013                 if (retval < 0) {
1014                         dev_err(&client->dev, "DPCD EDID Read failed!\n");
1015                         return retval;
1016                 }
1017
1018                 if (test_vector & DPCD_TEST_EDID_READ) {
1019                         retval = anx6345_dpcd_write_bytes(client,
1020                                         DPCD_TEST_EDID_CHECKSUM,1,
1021                                         &edid[EDID_LENGTH + EDID_CHECKSUM]);
1022                         if (retval < 0) {
1023                                 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1024                                 return retval;
1025                         }
1026
1027                         addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1028                         retval = anx6345_dpcd_write_bytes(client,
1029                                         DPCD_TEST_RESPONSE, 1, &addr);
1030                         if (retval < 0) {
1031                                 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1032                                 return retval;
1033                         }
1034                 }
1035         } else {
1036                 dev_info(&client->dev, "EDID data does not include any extensions.\n");
1037
1038                 /* Read EDID data */
1039                 retval = anx6345_edid_read_bytes(client, EDID_ADDR, EDID_HEADER,
1040                                           EDID_LENGTH, &edid[EDID_HEADER]);
1041                 if (retval != 0) {
1042                         dev_err(&client->dev, "EDID Read failed!\n");
1043                         return -EIO;
1044                 }
1045
1046                 sum = edp_calc_edid_check_sum(edid);
1047                 if (sum != 0) {
1048                         dev_warn(&client->dev, "EDID bad checksum!\n");
1049                         return 0;
1050                 }
1051
1052                 retval = anx6345_dpcd_read_bytes(client, DPCD_TEST_REQUEST,
1053                                                 1,&test_vector);
1054                 if (retval < 0) {
1055                         dev_err(&client->dev, "DPCD EDID Read failed!\n");
1056                         return retval;
1057                 }
1058
1059                 if (test_vector & DPCD_TEST_EDID_READ) {
1060                         retval = anx6345_dpcd_write_bytes(client,
1061                                         DPCD_TEST_EDID_CHECKSUM, 1,
1062                                         &edid[EDID_CHECKSUM]);
1063                         if (retval < 0) {
1064                                 dev_err(&client->dev, "DPCD EDID Write failed!\n");
1065                                 return retval;
1066                         }
1067                         addr = DPCD_TEST_EDID_CHECKSUM_WRITE;
1068                         retval = anx6345_dpcd_write_bytes(client, DPCD_TEST_RESPONSE,
1069                                         1, &addr);
1070                         if (retval < 0) {
1071                                 dev_err(&client->dev, "DPCD EDID checksum failed!\n");
1072                                 return retval;
1073                         }
1074                 }
1075         }
1076         fb_edid_to_monspecs(edid, &anx6345->specs);
1077         dev_info(&client->dev, "EDID Read success!\n");
1078         return 0;
1079 }
1080
1081 static int anx6345_init(struct i2c_client *client)
1082 {
1083         char val = 0x00;
1084         char i = 0;
1085         char lc,bw;
1086         char cnt = 50;
1087         u8 buf[12];
1088
1089         val = 0x30;
1090         anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
1091
1092         //clock detect
1093         for(i=0;i<50;i++)
1094         {
1095
1096                 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1097                 anx6345_i2c_write_p0_reg(client, SYS_CTRL1_REG, &val);
1098                 anx6345_i2c_read_p0_reg(client, SYS_CTRL1_REG, &val);
1099                 if((val&SYS_CTRL1_DET_STA)!=0)
1100                 {
1101                         break;
1102                 }
1103
1104                 mdelay(10);
1105         }
1106         if(i>49)
1107                 printk("no clock detected by anx6345\n");
1108
1109         //check whether clock is stable
1110         for(i=0;i<50;i++)
1111         {
1112                 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1113                 anx6345_i2c_write_p0_reg(client,SYS_CTRL2_REG, &val);
1114                 anx6345_i2c_read_p0_reg(client, SYS_CTRL2_REG, &val);
1115                 if((val&SYS_CTRL2_CHA_STA)==0)
1116                 {
1117                         break;
1118                 }
1119                 mdelay(10);
1120         }
1121         if(i>49)
1122                 printk("clk is not stable\n");
1123
1124         anx6345_dpcd_read_bytes(client, DPCD_REV, 12, buf);
1125         anx6345_read_edid(client);
1126
1127         //VESA range, 6bits BPC, RGB
1128         val = 0x00;
1129         anx6345_i2c_write_p1_reg(client, VID_CTRL2_REG, &val);
1130
1131         //ANX6345 chip pll setting
1132         val = 0x00;
1133         anx6345_i2c_write_p0_reg(client, PLL_CTRL_REG, &val);                  //UPDATE: FROM 0X07 TO 0X00
1134
1135
1136         //ANX chip analog setting
1137         val = 0x70;
1138         anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);               //UPDATE: FROM 0XF0 TO 0X70
1139         val = 0x30;
1140         anx6345_i2c_write_p0_reg(client, LINK_DEBUG_REG, &val);
1141
1142         //force HPD
1143         //anx6345_i2c_write_p0_reg(client, SYS_CTRL3_REG, &val);
1144
1145
1146         //reset AUX
1147         anx6345_i2c_read_p1_reg(client, RST_CTRL2_REG, &val);
1148         val |= AUX_RST;
1149         anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1150         val &= ~AUX_RST;
1151         anx6345_i2c_write_p1_reg(client, RST_CTRL2_REG, &val);
1152
1153         //Select 2.7G
1154         val = 0x0a;
1155         anx6345_i2c_write_p0_reg(client, LINK_BW_SET_REG, &val);
1156         //Select 2 lanes
1157         val = 0x02;
1158         anx6345_i2c_write_p0_reg(client,LANE_COUNT_SET_REG,&val);
1159
1160         val = LINK_TRAINING_CTRL_EN;
1161         anx6345_i2c_write_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1162         mdelay(5);
1163         anx6345_i2c_read_p0_reg(client, LINK_TRAINING_CTRL_REG, &val);
1164         while((val&0x80)&&(cnt))                                                                                //UPDATE: FROM 0X01 TO 0X80
1165         {
1166                 printk("Waiting...\n");
1167                 mdelay(5);
1168                 anx6345_i2c_read_p0_reg(client,LINK_TRAINING_CTRL_REG,&val);
1169                 cnt--;
1170         }
1171         if(cnt <= 0)
1172         {
1173                 printk(KERN_INFO "HW LT fail\n");
1174         }
1175         else
1176                 printk("HW LT Success>>:times:%d\n",(51-cnt));
1177
1178
1179
1180         //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
1181         //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
1182
1183 #if defined(BIST_MODE)
1184         anx6345_bist_mode(client);
1185         val = 0x8f;
1186 #else
1187         val = 0x81;
1188 #endif
1189         anx6345_i2c_write_p1_reg(client,VID_CTRL1_REG,&val);
1190
1191         anx_video_map_config(client);
1192         //force HPD and stream valid
1193         val = 0x33;
1194         anx6345_i2c_write_p0_reg(client,SYS_CTRL3_REG,&val);
1195
1196         anx6345_i2c_read_p0_reg(client,LANE_COUNT_SET_REG, &lc);
1197         anx6345_i2c_read_p0_reg(client,LINK_BW_SET_REG, &bw);
1198         printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
1199
1200         return 0;
1201 }
1202
1203
1204 #ifdef CONFIG_HAS_EARLYSUSPEND
1205 static void anx6345_early_suspend(struct early_suspend *h)
1206 {
1207         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
1208         gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
1209         gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
1210 }
1211
1212 static void anx6345_late_resume(struct early_suspend *h)
1213 {
1214         struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
1215         gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
1216         msleep(5);
1217         gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
1218         gpio_set_value(anx6345->pdata->edp_rst_pin,0);
1219         msleep(50);
1220         gpio_set_value(anx6345->pdata->edp_rst_pin,1);
1221         anx6345->edp_anx_init(anx6345->client);
1222 }
1223 #endif
1224
1225 #if defined(CONFIG_OF)
1226
1227 static int anx6345_power_ctl(struct anx6345_platform_data  *pdata)
1228 {
1229        int ret;
1230        ret = gpio_request(pdata->dvdd33_en_pin, "dvdd33_en_pin");
1231        if (ret != 0) {
1232                gpio_free(pdata->dvdd33_en_pin);
1233                printk(KERN_ERR "request dvdd33 en pin fail!\n");
1234                return -1;
1235        } else {
1236                gpio_direction_output(pdata->dvdd33_en_pin, pdata->dvdd33_en_val);
1237        }
1238        mdelay(5);
1239
1240        ret = gpio_request(pdata->dvdd18_en_pin, "dvdd18_en_pin");
1241        if (ret != 0) {
1242                gpio_free(pdata->dvdd18_en_pin);
1243                printk(KERN_ERR "request dvdd18 en pin fail!\n");
1244                return -1;
1245        } else {
1246                gpio_direction_output(pdata->dvdd18_en_pin, pdata->dvdd18_en_pin);
1247        }
1248
1249        ret = gpio_request(pdata->edp_rst_pin, "edp_rst_pin");
1250        if (ret != 0) {
1251                gpio_free(pdata->edp_rst_pin);
1252                printk(KERN_ERR "request rst pin fail!\n");
1253                return -1;
1254        } else {
1255                gpio_direction_output(pdata->edp_rst_pin, 0);
1256                msleep(50);
1257                gpio_direction_output(pdata->edp_rst_pin, 1);
1258        }
1259        return 0;
1260
1261 }
1262
1263 static void anx6345_parse_dt(struct edp_anx6345 *anx6345)
1264 {
1265         struct device_node *np = anx6345->client->dev.of_node;
1266         struct anx6345_platform_data *pdata;
1267         enum of_gpio_flags dvdd33_flags,dvdd18_flags,rst_flags;
1268         pdata = devm_kzalloc(&anx6345->client->dev,
1269                         sizeof(struct anx6345_platform_data ), GFP_KERNEL);
1270         if (!pdata) {
1271                 dev_err(&anx6345->client->dev,
1272                         "failed to allocate platform data\n");
1273                 return ;
1274         }
1275         pdata->dvdd33_en_pin = of_get_named_gpio_flags(np, "dvdd33-gpio", 0, &dvdd33_flags);
1276         pdata->dvdd18_en_pin = of_get_named_gpio_flags(np, "dvdd18-gpio", 0, &dvdd18_flags);
1277         pdata->edp_rst_pin = of_get_named_gpio_flags(np, "reset-gpio", 0, &rst_flags);
1278         pdata->dvdd33_en_val = (dvdd33_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1279         pdata->dvdd18_en_val = (dvdd18_flags & OF_GPIO_ACTIVE_LOW) ? 0 : 1;
1280         pdata->power_ctl = anx6345_power_ctl;
1281         anx6345->pdata = pdata;
1282
1283 }
1284 #else
1285 static void anx6345_parse_dt(struct edp_anx6345 * anx6345)
1286 {
1287
1288 }
1289 #endif
1290 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
1291 {
1292         struct edp_anx6345 *anx6345;
1293         int chip_id;
1294
1295
1296         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
1297         {
1298                 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
1299                 return -ENODEV;
1300         }
1301         anx6345 = devm_kzalloc(&client->dev, sizeof(struct edp_anx6345),
1302                                 GFP_KERNEL);
1303         if (unlikely(!anx6345)) {
1304                 dev_err(&client->dev, "alloc for struct anx6345 fail\n");
1305                 return -ENOMEM;
1306         }
1307
1308         anx6345->client = client;
1309         anx6345->pdata = dev_get_platdata(&client->dev);
1310         if (!anx6345->pdata) {
1311                 anx6345_parse_dt(anx6345);
1312         }
1313         i2c_set_clientdata(client,anx6345);
1314         rk_fb_get_prmry_screen(&anx6345->screen);
1315         if(anx6345->pdata->power_ctl)
1316                 anx6345->pdata->power_ctl(anx6345->pdata);
1317
1318 #if defined(CONFIG_DEBUG_FS)
1319         anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
1320         if (IS_ERR(anx6345->debugfs_dir))
1321         {
1322                 printk(KERN_ERR "failed to create debugfs dir for edp!\n");
1323         }
1324         else
1325                 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
1326 #endif
1327
1328 #ifdef CONFIG_HAS_EARLYSUSPEND
1329         anx6345->early_suspend.suspend = anx6345_early_suspend;
1330         anx6345->early_suspend.resume = anx6345_late_resume;
1331         anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
1332         register_early_suspend(&anx6345->early_suspend);
1333 #endif
1334         chip_id = get_dp_chip_id(client);
1335         if(chip_id == 0x9805)
1336                 anx6345->edp_anx_init = anx980x_init;
1337         else
1338                 anx6345->edp_anx_init = anx6345_init;
1339
1340         anx6345->edp_anx_init(client);
1341
1342         dev_info(&client->dev, "edp anx%x probe ok \n", get_dp_chip_id(client));
1343
1344         return 0;
1345 }
1346
1347 static int  anx6345_i2c_remove(struct i2c_client *client)
1348 {
1349         return 0;
1350 }
1351
1352 static const struct i2c_device_id id_table[] = {
1353         {"anx6345", 0 },
1354         { }
1355 };
1356
1357 #if defined(CONFIG_OF)
1358 static struct of_device_id anx6345_dt_ids[] = {
1359         { .compatible = "analogix, anx6345" },
1360         { }
1361 };
1362 #endif
1363
1364 static struct i2c_driver anx6345_i2c_driver  = {
1365         .driver = {
1366                 .name  = "anx6345",
1367                 .owner = THIS_MODULE,
1368 #if defined(CONFIG_OF)
1369                 .of_match_table = of_match_ptr(anx6345_dt_ids),
1370 #endif
1371         },
1372         .probe          = &anx6345_i2c_probe,
1373         .remove         = &anx6345_i2c_remove,
1374         .id_table       = id_table,
1375 };
1376
1377
1378 static int __init anx6345_module_init(void)
1379 {
1380         return i2c_add_driver(&anx6345_i2c_driver);
1381 }
1382
1383 static void __exit anx6345_module_exit(void)
1384 {
1385         i2c_del_driver(&anx6345_i2c_driver);
1386 }
1387
1388 fs_initcall_sync(anx6345_module_init);
1389 module_exit(anx6345_module_exit);
1390