1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/time.h>
4 #include <linux/delay.h>
5 #include <linux/slab.h>
6 #include <linux/device.h>
8 #include <linux/gpio.h>
9 #include <linux/anx6345.h>
11 #if defined(CONFIG_DEBUG_FS)
13 #include <linux/debugfs.h>
14 #include <linux/seq_file.h>
20 static int anx6345_i2c_read_p0_reg(struct i2c_client *client, char reg, char *val)
23 client->addr = DP_TX_PORT0_ADDR >> 1;
24 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
27 printk(KERN_ERR "%s>>err\n",__func__);
32 static int anx6345_i2c_write_p0_reg(struct i2c_client *client, char reg, char *val)
35 client->addr = DP_TX_PORT0_ADDR >> 1;
36 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
39 printk(KERN_ERR "%s>>err\n",__func__);
44 static int anx6345_i2c_read_p1_reg(struct i2c_client *client, char reg, char *val)
47 client->addr = HDMI_TX_PORT0_ADDR >> 1;
48 ret = i2c_master_reg8_recv(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
51 printk(KERN_ERR "%s>>err\n",__func__);
57 static int anx6345_i2c_write_p1_reg(struct i2c_client *client, char reg, char *val)
60 client->addr = HDMI_TX_PORT0_ADDR >> 1;
61 ret = i2c_master_reg8_send(client, reg, val, 1, ANX6345_SCL_RATE) > 0? 0: -EINVAL;
64 printk(KERN_ERR "%s>>err\n",__func__);
70 #if defined(CONFIG_DEBUG_FS)
71 static int edp_reg_show(struct seq_file *s, void *v)
75 struct edp_anx6345 *anx6345 = s->private;
78 printk(KERN_ERR "no edp device!\n");
82 seq_printf(s,"0x70:\n");
83 for(i=0;i< MAX_REG;i++)
85 anx6345_i2c_read_p0_reg(anx6345->client, i , &val);
86 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
90 seq_printf(s,"\n0x72:\n");
91 for(i=0;i< MAX_REG;i++)
93 anx6345_i2c_read_p1_reg(anx6345->client, i , &val);
94 seq_printf(s,"0x%02x>>0x%02x\n",i,val);
99 static int edp_reg_open(struct inode *inode, struct file *file)
101 struct edp_anx6345 *anx6345 = inode->i_private;
102 return single_open(file, edp_reg_show, anx6345);
105 static const struct file_operations edp_reg_fops = {
106 .owner = THIS_MODULE,
107 .open = edp_reg_open,
110 .release = single_release,
114 //get chip ID. Make sure I2C is OK
115 static int get_dp_chip_id(struct i2c_client *client)
119 anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDL_REG,&c1);
120 anx6345_i2c_read_p1_reg(client,SP_TX_DEV_IDH_REG,&c2);
126 static int anx980x_bist_mode(struct i2c_client *client)
131 //Power on total and select DP mode
133 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
136 val = DP_TX_RST_HW_RST;
137 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
140 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
143 anx6345_i2c_read_p1_reg(client, DP_POWERD_CTRL_REG, &val);
145 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val);
148 //get chip ID. Make sure I2C is OK
149 anx6345_i2c_read_p1_reg(client, DP_TX_DEV_IDH_REG , &val);
151 printk("Chip found\n");
156 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
157 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
158 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
159 if((val&DP_TX_SYS_CTRL1_DET_STA)!=0)
161 printk("clock is detected.\n");
167 //check whther clock is stable
170 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
171 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
172 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
173 if((val&DP_TX_SYS_CTRL2_CHA_STA)==0)
175 printk("clock is stable.\n");
181 //VESA range, 8bits BPC, RGB
183 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
184 //RK_EDP chip analog setting
186 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
188 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
190 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
194 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
196 //RK_EDP chip analog setting
198 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
200 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
202 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
204 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
206 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL, &val);
210 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL3_REG, &val);
213 anx6345_i2c_write_p0_reg(client, 0xc8, &val);
215 anx6345_i2c_write_p0_reg(client, 0xa3, &val);
216 anx6345_i2c_write_p0_reg(client, 0xa4, &val);
217 anx6345_i2c_write_p0_reg(client, 0xa5,&val);
218 anx6345_i2c_write_p0_reg(client, 0xa6, &val);
222 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
224 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
228 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
231 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
234 //DP_TX_LINK_TRAINING_CTRL_EN is self clear. If link training is OK, it will self cleared.
236 val = DP_TX_LINK_TRAINING_CTRL_EN;
237 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
239 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
240 while((val&0x01)&&(cnt++ < 10))
242 printk("Waiting...\n");
244 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
249 printk(KERN_INFO "HW LT fail\n");
253 printk(KERN_INFO "HW LT success ...cnt:%d\n",cnt);
256 DP_TX_HW_LT(client,0x0a,0x04); //2.7Gpbs 4lane
258 //DP_TX_Write_Reg(0x7a, 0x7c, 0x02);
260 //Set bist format 2048x1536
262 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEL_REG, &val);
264 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_LINEH_REG, &val);
267 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEL_REG, &val);
269 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_LINEH_REG,&val);
271 anx6345_i2c_write_p1_reg(client, DP_TX_VF_PORCH_REG, &val);
273 anx6345_i2c_write_p1_reg(client, DP_TX_VSYNC_CFG_REG,&val);
275 anx6345_i2c_write_p1_reg(client, DP_TX_VB_PORCH_REG, &val);
277 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELL_REG, &val);
279 anx6345_i2c_write_p1_reg(client, DP_TX_TOTAL_PIXELH_REG, &val);
281 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELL_REG, &val);
283 anx6345_i2c_write_p1_reg(client, DP_TX_ACT_PIXELH_REG, &val);
286 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHL_REG, &val);
288 anx6345_i2c_write_p1_reg(client, DP_TX_HF_PORCHH_REG, &val);
291 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGL_REG,&val);
293 anx6345_i2c_write_p1_reg(client, DP_TX_HSYNC_CFGH_REG,&val);
295 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHL_REG, &val);
297 anx6345_i2c_write_p1_reg(client, DP_TX_HB_PORCHH_REG, &val);
299 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL10_REG, &val);
302 val = DP_TX_VID_CTRL4_BIST;
303 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL4_REG, &val);
306 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
307 //force HPD and stream valid
309 anx6345_i2c_write_p0_reg(client, 0x82, &val);
314 static int anx980x_aux_rst(struct i2c_client *client)
317 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
318 val |= DP_TX_AUX_RST;
319 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
320 val &= ~DP_TX_AUX_RST;
321 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
326 static int anx980x_wait_aux_finished(struct i2c_client *client)
331 anx6345_i2c_read_p0_reg(client,DP_TX_AUX_CTRL_REG2, &val);
339 anx980x_aux_rst(client);
343 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
349 static int anx980x_aux_dpcdread_bytes(struct i2c_client *client,unsigned long addr, char cCount,char* pBuf)
354 anx6345_i2c_write_p0_reg(client, DP_TX_BUF_DATA_COUNT_REG, &val);
356 //set read cmd and count
357 val = (((char)(cCount-1) <<4)&(0xf0))|0x09;
358 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG, &val);
360 //set aux address15:0
361 val = (char)addr&0xff;
362 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_7_0_REG, &val);
363 val = (char)((addr>>8)&0xff);
364 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_15_8_REG, &val);
366 //set address19:16 and enable aux
367 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
368 val &=(0xf0)|(char)((addr>>16)&0xff);
369 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_ADDR_19_16_REG, &val);
372 anx6345_i2c_read_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
374 anx6345_i2c_write_p0_reg(client, DP_TX_AUX_CTRL_REG2, &val);
377 anx980x_wait_aux_finished(client);
379 for(i =0;i<cCount;i++)
381 anx6345_i2c_read_p0_reg(client, DP_TX_BUF_DATA_0_REG+i, &val);
383 //debug_printf("c = %.2x\n",(WORD)c);
396 static int anx_video_map_config(struct i2c_client *client)
400 anx6345_i2c_write_p1_reg(client, 0x40, &val);
401 anx6345_i2c_write_p1_reg(client, 0x41, &val);
402 anx6345_i2c_write_p1_reg(client, 0x48, &val);
403 anx6345_i2c_write_p1_reg(client, 0x49, &val);
404 anx6345_i2c_write_p1_reg(client, 0x50, &val);
405 anx6345_i2c_write_p1_reg(client, 0x51, &val);
409 anx6345_i2c_write_p1_reg(client, 0x42+i, &val);
415 anx6345_i2c_write_p1_reg(client, 0x4a+i, &val);
421 anx6345_i2c_write_p1_reg(client, 0x52+i, &val);
427 static int anx980x_eanble_video_input(struct i2c_client *client)
431 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
432 val |= DP_TX_VID_CTRL1_VID_EN;
433 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
435 anx_video_map_config(client);
440 static int anx980x_init(struct i2c_client *client)
445 char dp_tx_bw,dp_tx_lane_count;
448 #if defined(BIST_MODE)
449 return anx980x_bist_mode(client);
451 //power on all block and select DisplayPort mode
452 val |= DP_POWERD_AUDIO_REG;
453 anx6345_i2c_write_p1_reg(client, DP_POWERD_CTRL_REG, &val );
455 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
456 val &= ~DP_TX_VID_CTRL1_VID_EN;
457 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);
460 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
461 val |= DP_TX_RST_SW_RST;
462 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG,&val);
463 val &= ~DP_TX_RST_SW_RST;
464 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL_REG, &val);
468 anx6345_i2c_write_p0_reg(client, DP_TX_PLL_CTRL_REG, &val);
470 anx6345_i2c_write_p0_reg(client, DP_TX_EXTRA_ADDR_REG, &val);
472 //24bit SDR,negedge latch, and wait video stable
474 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL1_REG, &val);//72:08 for 9804 SDR, neg edge 05/04/09 extra pxl
476 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL3, &val);
478 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_CTRL3, &val);
481 anx6345_i2c_read_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
482 val |= DP_TX_AC_MODE;
483 anx6345_i2c_write_p1_reg(client, DP_TX_RST_CTRL2_REG, &val);
487 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val);
490 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG3, &val);
492 anx6345_i2c_read_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
494 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL1, &val);
496 //anx6345_i2c_write_p0_reg(client, DP_TX_HDCP_CTRL, 0x01);
498 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_DEBUG_REG,&val);
501 anx6345_i2c_read_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
503 anx6345_i2c_write_p0_reg(client, DP_TX_GNS_CTRL_REG, &val);
505 //power down PLL filter
507 anx6345_i2c_write_p1_reg(client, DP_TX_PLL_FILTER_CTRL,&val);
509 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE0_SET_REG, &val);
510 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE1_SET_REG, &val);
511 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE2_SET_REG, &val);
512 anx6345_i2c_write_p0_reg(client, DP_TX_TRAINING_LANE3_SET_REG, &val);
515 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_BW_SET_REG, &val);
517 anx6345_i2c_write_p0_reg(client, DP_TX_LANE_COUNT_SET_REG, &val);
519 val = DP_TX_LINK_TRAINING_CTRL_EN;
520 anx6345_i2c_write_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG,&val);
522 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
523 while((val & DP_TX_LINK_TRAINING_CTRL_EN)&&(cnt--))
525 anx6345_i2c_read_p0_reg(client, DP_TX_LINK_TRAINING_CTRL_REG, &val);
530 printk(KERN_INFO "HW LT fail\n");
533 printk(KERN_INFO "HW LT Success!>>:times:%d\n",(11-cnt));
534 //DP_TX_Config_Video(client);
535 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
536 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL1_REG, &val);
537 if(!(val & DP_TX_SYS_CTRL1_DET_STA))
540 //return; //mask by yxj
543 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
544 anx6345_i2c_write_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
545 anx6345_i2c_read_p0_reg(client, DP_TX_SYS_CTRL2_REG, &val);
546 if(val & DP_TX_SYS_CTRL2_CHA_STA)
548 printk("pclk not stable!\n");
549 //return; mask by yxj
552 anx980x_aux_dpcdread_bytes(client,(unsigned long)0x00001,2,ByteBuf);
553 dp_tx_bw = ByteBuf[0];
554 dp_tx_lane_count = ByteBuf[1] & 0x0f;
555 printk("%s..lc:%d--bw:%d\n",__func__,dp_tx_lane_count,dp_tx_bw);
559 //set Input BPC mode & color space
560 anx6345_i2c_read_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
562 val = val |((char)(0) << 4); //8bits ,rgb
563 anx6345_i2c_write_p1_reg(client, DP_TX_VID_CTRL2_REG, &val);
569 anx980x_eanble_video_input(client);
574 static int anx6345_bist_mode(struct i2c_client *client)
577 //these register are for bist mode
579 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEL_REG,&val);
581 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_LINEH_REG,&val);
583 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEL_REG,&val);
585 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_LINEH_REG,&val);
587 anx6345_i2c_write_p1_reg(client,SP_TX_VF_PORCH_REG,&val);
589 anx6345_i2c_write_p1_reg(client,SP_TX_VSYNC_CFG_REG,&val);
591 anx6345_i2c_write_p1_reg(client,SP_TX_VB_PORCH_REG,&val);
593 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELL_REG,&val);
595 anx6345_i2c_write_p1_reg(client,SP_TX_TOTAL_PIXELH_REG,&val);
597 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELL_REG,&val);
599 anx6345_i2c_write_p1_reg(client,SP_TX_ACT_PIXELH_REG,&val);
601 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHL_REG,&val);
603 anx6345_i2c_write_p1_reg(client,SP_TX_HF_PORCHH_REG,&val);
605 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGL_REG,&val);
607 anx6345_i2c_write_p1_reg(client,SP_TX_HSYNC_CFGH_REG,&val);
609 anx6345_i2c_write_p1_reg(client,SP_TX_HB_PORCHL_REG,&val);
611 anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL10_REG,&val);
614 //enable BIST. In normal mode, don't need to config this reg
616 anx6345_i2c_write_p1_reg(client, 0x0b, &val);
617 printk("anx6345 enter bist mode\n");
621 static int anx6345_init(struct i2c_client *client)
629 anx6345_i2c_write_p1_reg(client,SP_POWERD_CTRL_REG,&val);
635 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
636 anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
637 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL1_REG, &val);
638 if((val&SP_TX_SYS_CTRL1_DET_STA)!=0)
646 printk("no clock detected by anx6345\n");
648 //check whether clock is stable
651 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
652 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL2_REG, &val);
653 anx6345_i2c_read_p0_reg(client, SP_TX_SYS_CTRL2_REG, &val);
654 if((val&SP_TX_SYS_CTRL2_CHA_STA)==0)
661 printk("clk is not stable\n");
663 //VESA range, 6bits BPC, RGB
665 anx6345_i2c_write_p1_reg(client, SP_TX_VID_CTRL2_REG, &val);
667 //ANX6345 chip pll setting
669 anx6345_i2c_write_p0_reg(client, SP_TX_PLL_CTRL_REG, &val); //UPDATE: FROM 0X07 TO 0X00
672 //ANX chip analog setting
674 anx6345_i2c_write_p1_reg(client, ANALOG_DEBUG_REG1, &val); //UPDATE: FROM 0XF0 TO 0X70
676 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_DEBUG_REG, &val);
679 //anx6345_i2c_write_p0_reg(client, SP_TX_SYS_CTRL3_REG, &val);
683 anx6345_i2c_read_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
684 val |= SP_TX_AUX_RST;
685 anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
686 val &= ~SP_TX_AUX_RST;
687 anx6345_i2c_write_p1_reg(client, SP_TX_RST_CTRL2_REG, &val);
691 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_BW_SET_REG, &val);
694 anx6345_i2c_write_p0_reg(client,SP_TX_LANE_COUNT_SET_REG,&val);
696 val = SP_TX_LINK_TRAINING_CTRL_EN;
697 anx6345_i2c_write_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
699 anx6345_i2c_read_p0_reg(client, SP_TX_LINK_TRAINING_CTRL_REG, &val);
700 while((val&0x80)&&(cnt)) //UPDATE: FROM 0X01 TO 0X80
702 printk("Waiting...\n");
704 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_TRAINING_CTRL_REG,&val);
709 printk(KERN_INFO "HW LT fail\n");
712 printk("HW LT Success>>:times:%d\n",(51-cnt));
716 //enable video input, set DDR mode, the input DCLK should be 102.5MHz;
717 //In normal mode, set this reg to 0x81, SDR mode, the input DCLK should be 205MHz
719 #if defined(BIST_MODE)
720 anx6345_bist_mode(client);
725 anx6345_i2c_write_p1_reg(client,SP_TX_VID_CTRL1_REG,&val);
727 anx_video_map_config(client);
728 //force HPD and stream valid
730 anx6345_i2c_write_p0_reg(client,SP_TX_SYS_CTRL3_REG,&val);
732 anx6345_i2c_read_p0_reg(client,SP_TX_LANE_COUNT_SET_REG, &lc);
733 anx6345_i2c_read_p0_reg(client,SP_TX_LINK_BW_SET_REG, &bw);
734 printk("%s..lc:%d--bw:%d\n",__func__,lc,bw);
740 #ifdef CONFIG_HAS_EARLYSUSPEND
741 static void anx6345_early_suspend(struct early_suspend *h)
743 struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
744 gpio_set_value(anx6345->pdata->dvdd33_en_pin,!anx6345->pdata->dvdd33_en_val);
745 gpio_set_value(anx6345->pdata->dvdd18_en_pin,!anx6345->pdata->dvdd18_en_val);
748 static void anx6345_late_resume(struct early_suspend *h)
750 struct edp_anx6345 *anx6345 = container_of(h, struct edp_anx6345, early_suspend);
751 gpio_set_value(anx6345->pdata->dvdd33_en_pin,anx6345->pdata->dvdd33_en_val);
753 gpio_set_value(anx6345->pdata->dvdd18_en_pin,anx6345->pdata->dvdd18_en_val);
754 gpio_set_value(anx6345->pdata->edp_rst_pin,0);
756 gpio_set_value(anx6345->pdata->edp_rst_pin,1);
757 anx6345->edp_anx_init(anx6345->client);
761 static int anx6345_i2c_probe(struct i2c_client *client,const struct i2c_device_id *id)
765 struct edp_anx6345 *anx6345 = NULL;
769 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
771 dev_err(&client->dev, "Must have I2C_FUNC_I2C.\n");
774 anx6345 = kzalloc(sizeof(struct edp_anx6345), GFP_KERNEL);
777 printk(KERN_ALERT "alloc for struct anx6345 fail\n");
781 anx6345->client = client;
782 anx6345->pdata = client->dev.platform_data;
783 i2c_set_clientdata(client,anx6345);
784 if(anx6345->pdata->power_ctl)
785 anx6345->pdata->power_ctl();
787 #if defined(CONFIG_DEBUG_FS)
788 anx6345->debugfs_dir = debugfs_create_dir("edp", NULL);
789 if (IS_ERR(anx6345->debugfs_dir))
791 printk(KERN_ERR "failed to create debugfs dir for edp!\n");
794 debugfs_create_file("edp-reg", S_IRUSR,anx6345->debugfs_dir,anx6345,&edp_reg_fops);
797 #ifdef CONFIG_HAS_EARLYSUSPEND
798 anx6345->early_suspend.suspend = anx6345_early_suspend;
799 anx6345->early_suspend.resume = anx6345_late_resume;
800 anx6345->early_suspend.level = EARLY_SUSPEND_LEVEL_STOP_DRAWING;
801 register_early_suspend(&anx6345->early_suspend);
803 chip_id = get_dp_chip_id(client);
804 if(chip_id == 0x9805)
805 anx6345->edp_anx_init = anx980x_init;
807 anx6345->edp_anx_init = anx6345_init;
809 anx6345->edp_anx_init(client);
811 printk("edp anx%x probe ok\n",get_dp_chip_id(client));
816 static int __devexit anx6345_i2c_remove(struct i2c_client *client)
821 static const struct i2c_device_id id_table[] = {
826 static struct i2c_driver anx6345_i2c_driver = {
829 .owner = THIS_MODULE,
831 .probe = &anx6345_i2c_probe,
832 .remove = &anx6345_i2c_remove,
833 .id_table = id_table,
837 static int __init anx6345_module_init(void)
839 return i2c_add_driver(&anx6345_i2c_driver);
842 static void __exit anx6345_module_exit(void)
844 i2c_del_driver(&anx6345_i2c_driver);
847 fs_initcall_sync(anx6345_module_init);
848 module_exit(anx6345_module_exit);