3 #include "../../edid.h"
6 #define DPCD_MAX_LINK_RATE 0x01
7 #define DPCD_MAX_LANE_CNT 0x02
9 #define DPCD_MAX_DOWNSPREAD 0x03
10 #define DPCD_NORP 0x04
11 #define DPCD_DOWNSTREAMPORT_PRESENT 0x05
13 #define DPCD_RECEIVE_PORT0_CAP_0 0x08
14 #define DPCD_RECEIVE_PORT0_CAP_1 0x09
15 #define DPCD_RECEIVE_PORT0_CAP_2 0x0a
16 #define DPCD_RECEIVE_PORT0_CAP_3 0x0b
18 #define DPCD_LINK_BW_SET 0x100
19 #define DPCD_LANE_CNT_SET 0x101
20 #define DPCD_TRAINING_PATTERN_SET 0x102
21 #define DPCD_TRAINING_LANE0_SET 0x103
22 #define DPCD_TRAINING_LANE1_SET 0x104
23 #define DPCD_TRAINING_LANE2_SET 0x105
24 #define DPCD_TRAINING_LANE3_SET 0x106
25 #define DPCD_DOWNSPREAD_CTRL 0x107
27 #define DPCD_SINK_COUNT 0x200
28 #define DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x201
29 #define DPCD_LANE0_1_STATUS 0x202
30 #define DPCD_LANE2_3_STATUS 0x203
31 #define DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
32 #define DPCD_SINK_STATUS 0x205
33 #define DPCD_ADJUST_REQUEST_LANE0_1 0x206
34 #define DPCD_ADJUST_REQUEST_LANE2_3 0x207
35 #define DPCD_TRAINING_SCORE_LANE0 0x208
36 #define DPCD_TRAINING_SCORE_LANE1 0x209
37 #define DPCD_TRAINING_SCORE_LANE2 0x20a
38 #define DPCD_TRAINING_SCORE_LANE3 0x20b
39 #define DPCD_SINK_POWER_STATE 0x0600
41 /* DPCD_ADDR_MAX_LANE_COUNT */
42 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
43 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
45 /* DPCD_ADDR_LANE_COUNT_SET */
46 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
47 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
49 /* DPCD_ADDR_TRAINING_PATTERN_SET */
50 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
51 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
52 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
53 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
54 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
56 /* DPCD_ADDR_TRAINING_LANE0_SET */
57 #define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
58 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
59 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
60 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
61 #define DPCD_MAX_SWING_REACHED (0x1 << 2)
62 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
63 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
64 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
66 /* DPCD_ADDR_LANE0_1_STATUS */
67 #define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
68 #define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
69 #define DPCD_LANE_CR_DONE (0x1 << 0)
70 #define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
71 DPCD_LANE_CHANNEL_EQ_DONE|\
72 DPCD_LANE_SYMBOL_LOCKED)
74 #define DPCD_TEST_REQUEST 0x218
75 #define DPCD_TEST_LINK_RATE 0x219
77 #define DPCD_TEST_LANE_COUNT 0x220
78 #define DPCD_TEST_RESPONSE 0x260
79 #define DPCD_TEST_EDID_CHECKSUM 0x261
81 #define DPCD_TEST_EDID_Checksum_Write 0x04//bit position
83 #define DPCD_TEST_EDID_Checksum 0x261
86 #define DPCD_SPECIFIC_INTERRUPT 0x10
87 #define DPCD_USER_COMM1 0x22//define for downstream HDMI Rx sense detection
89 #define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff)
90 #define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff)
91 #define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f)
93 #define AUX_RX_COMM_I2C_DEFER (0x2 << 2)
94 #define AUX_RX_COMM_AUX_DEFER (0x2 << 0)
96 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
97 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
98 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
99 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
101 /* DPCD_ADDR_TEST_REQUEST */
102 #define DPCD_TEST_EDID_READ (0x1 << 2)
104 /* DPCD_ADDR_TEST_RESPONSE */
105 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
107 /* DPCD_ADDR_SINK_POWER_STATE */
108 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
109 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
113 * EDID device address is 0x50.
114 * However, if necessary, you must have set upper address
115 * into E-EDID in I2C device, 0x30.
118 #define EDID_ADDR 0x50
119 #define E_EDID_ADDR 0x30
120 #define EDID_EXTENSION_FLAG 0x7e
121 #define EDID_CHECKSUM 0x7f
123 static unsigned char edp_calc_edid_check_sum(unsigned char *edid_data)
126 unsigned char sum = 0;
128 for (i = 0; i < EDID_LENGTH; i++)
129 sum = sum + edid_data[i];