2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/clk.h>
24 #include <linux/platform_device.h>
25 #include <linux/uaccess.h>
26 #include <linux/rockchip/iomap.h>
27 #include <linux/rockchip/grf.h>
30 #if defined(CONFIG_OF)
34 #if defined(CONFIG_DEBUG_FS)
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
40 //#define EDP_BIST_MODE
42 static struct rk32_edp *rk32_edp;
44 static int rk32_edp_clk_enable(struct rk32_edp *edp)
47 clk_enable(edp->pclk);
48 clk_enable(edp->clk_edp);
49 clk_enable(edp->clk_24m);
56 static int rk32_edp_clk_disable(struct rk32_edp *edp)
59 clk_disable(edp->pclk);
60 clk_disable(edp->clk_edp);
61 clk_disable(edp->clk_24m);
68 static int rk32_edp_pre_init(void)
71 val = GRF_EDP_REF_CLK_SEL_INTER |
72 (GRF_EDP_REF_CLK_SEL_INTER << 16);
73 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
76 writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
79 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
83 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
89 static int rk32_edp_init_edp(struct rk32_edp *edp)
91 struct rk_screen *screen = &edp->screen;
95 if (screen->lcdc_id == 1) /*select lcdc*/
96 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
98 val = EDP_SEL_VOP_LIT << 16;
99 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
103 rk32_edp_init_refclk(edp);
104 rk32_edp_init_interrupt(edp);
106 rk32_edp_enable_sw_function(edp);
108 rk32_edp_init_analog_func(edp);
110 rk32_edp_init_hpd(edp);
111 rk32_edp_init_aux(edp);
116 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
118 int timeout_loop = 0;
120 rk32_edp_init_hpd(edp);
124 while (rk32_edp_get_plug_in_status(edp) != 0) {
126 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
127 dev_err(edp->dev, "failed to get hpd plug status\n");
136 static int rk32_edp_read_edid(struct rk32_edp *edp)
138 unsigned char edid[EDID_LENGTH * 2];
139 unsigned int extend_block = 0;
141 unsigned char test_vector;
145 * EDID device address is 0x50.
146 * However, if necessary, you must have set upper address
147 * into E-EDID in I2C device, 0x30.
150 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
151 retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
154 dev_err(edp->dev, "EDID extension flag failed!\n");
158 if (extend_block > 0) {
159 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
162 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
163 EDID_LENGTH, &edid[EDID_HEADER]);
165 dev_err(edp->dev, "EDID Read failed!\n");
168 sum = edp_calc_edid_check_sum(edid);
170 dev_warn(edp->dev, "EDID bad checksum!\n");
174 /* Read additional EDID data */
175 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
176 EDID_LENGTH, &edid[EDID_LENGTH]);
178 dev_err(edp->dev, "EDID Read failed!\n");
181 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
183 dev_warn(edp->dev, "EDID bad checksum!\n");
187 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
190 dev_err(edp->dev, "DPCD EDID Read failed!\n");
194 if (test_vector & DPCD_TEST_EDID_READ) {
195 retval = rk32_edp_write_byte_to_dpcd(edp,
196 DPCD_TEST_EDID_CHECKSUM,
197 edid[EDID_LENGTH + EDID_CHECKSUM]);
199 dev_err(edp->dev, "DPCD EDID Write failed!\n");
202 retval = rk32_edp_write_byte_to_dpcd(edp,
204 DPCD_TEST_EDID_CHECKSUM_WRITE);
206 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
211 dev_info(edp->dev, "EDID data does not include any extensions.\n");
214 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
215 EDID_LENGTH, &edid[EDID_HEADER]);
217 dev_err(edp->dev, "EDID Read failed!\n");
220 sum = edp_calc_edid_check_sum(edid);
222 dev_warn(edp->dev, "EDID bad checksum!\n");
226 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
229 dev_err(edp->dev, "DPCD EDID Read failed!\n");
233 if (test_vector & DPCD_TEST_EDID_READ) {
234 retval = rk32_edp_write_byte_to_dpcd(edp,
235 DPCD_TEST_EDID_CHECKSUM,
236 edid[EDID_CHECKSUM]);
238 dev_err(edp->dev, "DPCD EDID Write failed!\n");
241 retval = rk32_edp_write_byte_to_dpcd(edp,
243 DPCD_TEST_EDID_CHECKSUM_WRITE);
245 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
250 fb_edid_to_monspecs(edid, &edp->specs);
251 dev_err(edp->dev, "EDID Read success!\n");
255 static int rk32_edp_handle_edid(struct rk32_edp *edp)
261 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
262 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
266 for (i=0 ;i < 12; i++)
267 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
269 for (i = 0; i < 3; i++) {
270 retval = rk32_edp_read_edid(edp);
278 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
284 retval = rk32_edp_read_byte_from_dpcd(edp,
285 DPCD_LANE_CNT_SET, &data);
290 retval = rk32_edp_write_byte_to_dpcd(edp,
292 DPCD_ENHANCED_FRAME_EN |
293 DPCD_LANE_COUNT_SET(data));
295 /*retval = rk32_edp_write_byte_to_dpcd(edp,
296 DPCD_ADDR_CONFIGURATION_SET, 0);*/
298 retval = rk32_edp_write_byte_to_dpcd(edp,
300 DPCD_LANE_COUNT_SET(data));
306 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
308 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
309 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
312 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
313 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
315 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
319 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
324 retval = rk32_edp_read_byte_from_dpcd(edp,
325 DPCD_MAX_LANE_CNT, &data);
329 return DPCD_ENHANCED_FRAME_CAP(data);
332 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
334 /*rk32_edp_write_byte_to_dpcd(edp,
335 DPCD_ADDR_USER_DEFINED1, 0);
336 rk32_edp_write_byte_to_dpcd(edp,
337 DPCD_ADDR_USER_DEFINED2, 0x83);
338 rk32_edp_write_byte_to_dpcd(edp,
339 DPCD_ADDR_USER_DEFINED3, 0x27);*/
342 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
347 retval = rk32_edp_is_enhanced_mode_available(edp);
352 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
356 rk32_edp_enable_enhanced_mode(edp, data);
361 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
365 rk32_edp_set_training_pattern(edp, DP_NONE);
367 retval = rk32_edp_write_byte_to_dpcd(edp,
368 DPCD_TRAINING_PATTERN_SET,
369 DPCD_TRAINING_PATTERN_DISABLED);
376 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
377 int pre_emphasis, int lane)
381 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
384 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
388 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
392 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
397 static int rk32_edp_link_start(struct rk32_edp *edp)
404 lane_count = edp->link_train.lane_count;
406 edp->link_train.lt_state = LT_CLK_RECOVERY;
407 edp->link_train.eq_loop = 0;
409 for (lane = 0; lane < lane_count; lane++)
410 edp->link_train.cr_loop[lane] = 0;
412 /* Set sink to D0 (Sink Not Ready) mode. */
413 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
414 DPCD_SET_POWER_STATE_D0);
416 dev_err(edp->dev, "failed to set sink device to D0!\n");
420 /* Set link rate and count as you want to establish*/
421 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
422 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
424 /* Setup RX configuration */
425 buf[0] = edp->link_train.link_rate;
426 buf[1] = edp->link_train.lane_count;
427 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
430 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
434 /* Set TX pre-emphasis to level1 */
435 for (lane = 0; lane < lane_count; lane++)
436 rk32_edp_set_lane_lane_pre_emphasis(edp,
437 PRE_EMPHASIS_LEVEL_1, lane);
439 /* Set training pattern 1 */
440 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
442 /* Set RX training pattern */
443 retval = rk32_edp_write_byte_to_dpcd(edp,
444 DPCD_TRAINING_PATTERN_SET,
445 DPCD_SCRAMBLING_DISABLED |
446 DPCD_TRAINING_PATTERN_1);
448 dev_err(edp->dev, "failed to set training pattern 1!\n");
452 for (lane = 0; lane < lane_count; lane++)
453 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
454 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
455 retval = rk32_edp_write_bytes_to_dpcd(edp,
456 DPCD_TRAINING_LANE0_SET,
459 dev_err(edp->dev, "failed to set training lane!\n");
466 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
468 int shift = (lane & 1) * 4;
469 u8 link_value = link_status[lane>>1];
471 return (link_value >> shift) & 0xf;
474 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
479 for (lane = 0; lane < lane_count; lane++) {
480 lane_status = rk32_edp_get_lane_status(link_status, lane);
481 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
487 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
493 lane_align = link_align[2];
494 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
497 for (lane = 0; lane < lane_count; lane++) {
498 lane_status = rk32_edp_get_lane_status(link_align, lane);
499 lane_status &= DPCD_CHANNEL_EQ_BITS;
500 if (lane_status != DPCD_CHANNEL_EQ_BITS)
507 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
510 int shift = (lane & 1) * 4;
511 u8 link_value = adjust_request[lane>>1];
513 return (link_value >> shift) & 0x3;
516 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
517 u8 adjust_request[2],
520 int shift = (lane & 1) * 4;
521 u8 link_value = adjust_request[lane>>1];
523 return ((link_value >> shift) & 0xc) >> 2;
526 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
527 u8 training_lane_set, int lane)
531 rk32_edp_set_lane0_link_training(edp, training_lane_set);
534 rk32_edp_set_lane1_link_training(edp, training_lane_set);
538 rk32_edp_set_lane2_link_training(edp, training_lane_set);
542 rk32_edp_set_lane3_link_training(edp, training_lane_set);
547 static unsigned int rk32_edp_get_lane_link_training(
548 struct rk32_edp *edp,
555 reg = rk32_edp_get_lane0_link_training(edp);
558 reg = rk32_edp_get_lane1_link_training(edp);
561 reg = rk32_edp_get_lane2_link_training(edp);
564 reg = rk32_edp_get_lane3_link_training(edp);
571 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
573 rk32_edp_training_pattern_dis(edp);
575 edp->link_train.lt_state = FAILED;
578 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
584 u8 adjust_request[2];
592 lane_count = edp->link_train.lane_count;
594 retval = rk32_edp_read_bytes_from_dpcd(edp,
598 dev_err(edp->dev, "failed to read lane status!\n");
602 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
603 /* set training pattern 2 for EQ */
604 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
606 for (lane = 0; lane < lane_count; lane++) {
607 retval = rk32_edp_read_bytes_from_dpcd(edp,
608 DPCD_ADJUST_REQUEST_LANE0_1,
611 dev_err(edp->dev, "failed to read adjust request!\n");
615 voltage_swing = rk32_edp_get_adjust_request_voltage(
616 adjust_request, lane);
617 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
618 adjust_request, lane);
619 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
620 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
622 if (voltage_swing == VOLTAGE_LEVEL_3)
623 training_lane |= DPCD_MAX_SWING_REACHED;
624 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
625 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
627 edp->link_train.training_lane[lane] = training_lane;
629 rk32_edp_set_lane_link_training(edp,
630 edp->link_train.training_lane[lane],
634 retval = rk32_edp_write_byte_to_dpcd(edp,
635 DPCD_TRAINING_PATTERN_SET,
636 DPCD_SCRAMBLING_DISABLED |
637 DPCD_TRAINING_PATTERN_2);
639 dev_err(edp->dev, "failed to set training pattern 2!\n");
643 retval = rk32_edp_write_bytes_to_dpcd(edp,
644 DPCD_TRAINING_LANE0_SET,
646 edp->link_train.training_lane);
648 dev_err(edp->dev, "failed to set training lane!\n");
652 dev_info(edp->dev, "Link Training Clock Recovery success\n");
653 edp->link_train.lt_state = LT_EQ_TRAINING;
655 for (lane = 0; lane < lane_count; lane++) {
656 training_lane = rk32_edp_get_lane_link_training(
658 retval = rk32_edp_read_bytes_from_dpcd(edp,
659 DPCD_ADJUST_REQUEST_LANE0_1,
662 dev_err(edp->dev, "failed to read adjust request!\n");
666 voltage_swing = rk32_edp_get_adjust_request_voltage(
667 adjust_request, lane);
668 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
669 adjust_request, lane);
671 if (voltage_swing == VOLTAGE_LEVEL_3 ||
672 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
673 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
674 goto reduce_link_rate;
677 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
679 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
681 edp->link_train.cr_loop[lane]++;
682 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
683 dev_err(edp->dev, "CR Max loop\n");
684 goto reduce_link_rate;
688 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
689 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
691 if (voltage_swing == VOLTAGE_LEVEL_3)
692 training_lane |= DPCD_MAX_SWING_REACHED;
693 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
694 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
696 edp->link_train.training_lane[lane] = training_lane;
698 rk32_edp_set_lane_link_training(edp,
699 edp->link_train.training_lane[lane], lane);
702 retval = rk32_edp_write_bytes_to_dpcd(edp,
703 DPCD_TRAINING_LANE0_SET,
705 edp->link_train.training_lane);
707 dev_err(edp->dev, "failed to set training lane!\n");
715 rk32_edp_reduce_link_rate(edp);
719 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
727 u8 adjust_request[2];
735 lane_count = edp->link_train.lane_count;
737 retval = rk32_edp_read_bytes_from_dpcd(edp,
741 dev_err(edp->dev, "failed to read lane status!\n");
745 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
746 link_align[0] = link_status[0];
747 link_align[1] = link_status[1];
749 retval = rk32_edp_read_byte_from_dpcd(edp,
750 DPCD_LANE_ALIGN_STATUS_UPDATED,
753 dev_err(edp->dev, "failed to read lane aligne status!\n");
757 for (lane = 0; lane < lane_count; lane++) {
758 retval = rk32_edp_read_bytes_from_dpcd(edp,
759 DPCD_ADJUST_REQUEST_LANE0_1,
762 dev_err(edp->dev, "failed to read adjust request!\n");
766 voltage_swing = rk32_edp_get_adjust_request_voltage(
767 adjust_request, lane);
768 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
769 adjust_request, lane);
770 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
771 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
773 if (voltage_swing == VOLTAGE_LEVEL_3)
774 training_lane |= DPCD_MAX_SWING_REACHED;
775 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
776 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
778 edp->link_train.training_lane[lane] = training_lane;
781 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
782 /* traing pattern Set to Normal */
783 retval = rk32_edp_training_pattern_dis(edp);
785 dev_err(edp->dev, "failed to disable training pattern!\n");
789 dev_info(edp->dev, "Link Training success!\n");
791 rk32_edp_get_link_bandwidth(edp, ®);
792 edp->link_train.link_rate = reg;
793 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
794 edp->link_train.link_rate);
796 rk32_edp_get_lane_count(edp, ®);
797 edp->link_train.lane_count = reg;
798 dev_dbg(edp->dev, "final lane count = %.2x\n",
799 edp->link_train.lane_count);
801 edp->link_train.lt_state = FINISHED;
804 edp->link_train.eq_loop++;
806 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
807 dev_err(edp->dev, "EQ Max loop\n");
808 goto reduce_link_rate;
811 for (lane = 0; lane < lane_count; lane++)
812 rk32_edp_set_lane_link_training(edp,
813 edp->link_train.training_lane[lane],
816 retval = rk32_edp_write_bytes_to_dpcd(edp,
817 DPCD_TRAINING_LANE0_SET,
819 edp->link_train.training_lane);
821 dev_err(edp->dev, "failed to set training lane!\n");
826 goto reduce_link_rate;
832 rk32_edp_reduce_link_rate(edp);
836 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
843 * For DP rev.1.1, Maximum link rate of Main Link lanes
844 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
846 retval = rk32_edp_read_byte_from_dpcd(edp,
847 DPCD_MAX_LINK_RATE, &data);
856 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
863 * For DP rev.1.1, Maximum number of Main Link lanes
864 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
866 retval = rk32_edp_read_byte_from_dpcd(edp,
867 DPCD_MAX_LANE_CNT, &data);
871 *lane_count = DPCD_MAX_LANE_COUNT(data);
875 static int rk32_edp_init_training(struct rk32_edp *edp)
880 * MACRO_RST must be applied after the PLL_LOCK to avoid
881 * the DP inter pair skew issue for at least 10 us
883 rk32_edp_reset_macro(edp);
886 retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
887 retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
888 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
889 edp->link_train.link_rate * 27/100,
890 edp->link_train.link_rate*27%100,
891 edp->link_train.lane_count);
893 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
894 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
895 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
896 "use default link rate:%d.%dGps\n",
897 edp->link_train.link_rate,
898 edp->video_info.link_rate*27/100,
899 edp->video_info.link_rate*27%100);
900 edp->link_train.link_rate = edp->video_info.link_rate;
903 if (edp->link_train.lane_count == 0) {
904 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
905 "use default lanes:%d\n",
906 edp->link_train.lane_count,
907 edp->video_info.lane_count);
908 edp->link_train.lane_count = edp->video_info.lane_count;
911 rk32_edp_analog_power_ctr(edp, 1);
917 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
920 int training_finished = 0;
922 edp->link_train.lt_state = LT_START;
925 while (!training_finished) {
926 switch (edp->link_train.lt_state) {
928 retval = rk32_edp_link_start(edp);
930 dev_err(edp->dev, "LT Start failed\n");
932 case LT_CLK_RECOVERY:
933 retval = rk32_edp_process_clock_recovery(edp);
935 dev_err(edp->dev, "LT CR failed\n");
938 retval = rk32_edp_process_equalizer_training(edp);
940 dev_err(edp->dev, "LT EQ failed\n");
943 training_finished = 1;
954 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
958 /* Set link rate and count as you want to establish*/
959 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
960 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
961 rk32_edp_hw_link_training_en(edp);
962 val = rk32_edp_wait_hw_lt_done(edp);
965 dev_err(edp->dev, "hw lt timeout");
969 val = rk32_edp_wait_hw_lt_done(edp);
972 val = rk32_edp_get_hw_lt_status(edp);
974 dev_err(edp->dev, "hw lt err:%d\n", val);
978 static int rk32_edp_set_link_train(struct rk32_edp *edp)
982 retval = rk32_edp_init_training(edp);
984 dev_err(edp->dev, "DP LT init failed!\n");
986 retval = rk32_edp_sw_link_training(edp);
988 retval = rk32_edp_hw_link_training(edp);
994 static int rk32_edp_config_video(struct rk32_edp *edp,
995 struct video_info *video_info)
998 int timeout_loop = 0;
1001 rk32_edp_config_video_slave_mode(edp, video_info);
1003 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1004 video_info->color_space,
1005 video_info->dynamic_range,
1006 video_info->ycbcr_coeff);
1008 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1009 dev_err(edp->dev, "PLL is not locked yet.\n");
1015 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1017 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1018 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1025 /* Set to use the register calculated M/N video */
1026 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1028 /* For video bist, Video timing must be generated by register */
1029 #ifndef EDP_BIST_MODE
1030 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1032 /* Disable video mute */
1033 rk32_edp_enable_video_mute(edp, 0);
1035 /* Configure video slave mode */
1036 rk32_edp_enable_video_master(edp, 0);
1039 rk32_edp_start_video(edp);
1045 if (rk32_edp_is_video_stream_on(edp) == 0) {
1047 if (done_count > 10)
1049 } else if (done_count) {
1052 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1053 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1057 usleep_range(1000, 1000);
1061 dev_err(edp->dev, "Video stream is not detected!\n");
1066 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1072 rk32_edp_enable_scrambling(edp);
1074 retval = rk32_edp_read_byte_from_dpcd(edp,
1075 DPCD_TRAINING_PATTERN_SET,
1080 retval = rk32_edp_write_byte_to_dpcd(edp,
1081 DPCD_TRAINING_PATTERN_SET,
1082 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1086 rk32_edp_disable_scrambling(edp);
1088 retval = rk32_edp_read_byte_from_dpcd(edp,
1089 DPCD_TRAINING_PATTERN_SET,
1094 retval = rk32_edp_write_byte_to_dpcd(edp,
1095 DPCD_TRAINING_PATTERN_SET,
1096 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1104 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1106 struct rk32_edp *edp = arg;
1107 enum dp_irq_type irq_type;
1109 irq_type = rk32_edp_get_irq_type(edp);
1111 case DP_IRQ_TYPE_HP_CABLE_IN:
1112 dev_info(edp->dev, "Received irq - cable in\n");
1113 rk32_edp_clear_hotplug_interrupts(edp);
1115 case DP_IRQ_TYPE_HP_CABLE_OUT:
1116 dev_info(edp->dev, "Received irq - cable out\n");
1117 rk32_edp_clear_hotplug_interrupts(edp);
1119 case DP_IRQ_TYPE_HP_CHANGE:
1121 * We get these change notifications once in a while, but there
1122 * is nothing we can do with them. Just ignore it for now and
1123 * only handle cable changes.
1125 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1126 rk32_edp_clear_hotplug_interrupts(edp);
1129 dev_err(edp->dev, "Received irq - unknown type!\n");
1135 static int rk32_edp_enable(void)
1138 struct rk32_edp *edp = rk32_edp;
1141 rk32_edp_clk_enable(edp);
1142 rk32_edp_pre_init();
1143 rk32_edp_init_edp(edp);
1144 enable_irq(edp->irq);
1145 /*ret = rk32_edp_handle_edid(edp);
1147 dev_err(edp->dev, "unable to handle edid\n");
1152 ret = rk32_edp_enable_scramble(edp, 0);
1154 dev_err(edp->dev, "unable to set scramble\n");
1158 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1160 dev_err(edp->dev, "unable to set enhanced mode\n");
1163 rk32_edp_enable_enhanced_mode(edp, 1);*/
1165 ret = rk32_edp_set_link_train(edp);
1167 dev_err(edp->dev, "link train failed!\n");
1169 dev_info(edp->dev, "link training success.\n");
1171 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1172 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1173 rk32_edp_init_video(edp);
1175 #ifdef EDP_BIST_MODE
1176 rk32_edp_bist_cfg(edp);
1178 ret = rk32_edp_config_video(edp, &edp->video_info);
1180 dev_err(edp->dev, "unable to config video\n");
1188 static int rk32_edp_disable(void )
1190 struct rk32_edp *edp = rk32_edp;
1192 disable_irq(edp->irq);
1193 rk32_edp_reset(edp);
1194 rk32_edp_analog_power_ctr(edp, 0);
1195 rk32_edp_clk_disable(edp);
1201 static struct rk_fb_trsm_ops trsm_edp_ops = {
1202 .enable = rk32_edp_enable,
1203 .disable = rk32_edp_disable,
1207 #if defined(CONFIG_DEBUG_FS)
1209 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1212 unsigned char buf[12];
1213 struct rk32_edp *edp = s->private;
1215 dev_err(edp->dev, "no edp device!\n");
1220 rk32_edp_read_bytes_from_dpcd(edp,
1221 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1222 for (i=0;i< 12;i++) {
1223 seq_printf(s,"0x%02x>>0x%02x\n",0x210 + i, buf[i]);
1228 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1231 unsigned char buf[12];
1232 struct rk32_edp *edp = s->private;
1234 dev_err(edp->dev, "no edp device!\n");
1237 seq_printf(s,"edid");
1241 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1244 struct rk32_edp *edp = s->private;
1246 dev_err(edp->dev, "no edp device!\n");
1250 for (i = 0; i < 0x284; i++) {
1252 seq_printf(s, "\n%08x: ", i*4);
1253 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1259 #define EDP_DEBUG_ENTRY(name) \
1260 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1262 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1265 static const struct file_operations edp_##name##_debugfs_fops = { \
1266 .owner = THIS_MODULE, \
1267 .open = edp_##name##_debugfs_open, \
1269 .llseek = seq_lseek, \
1270 .release = single_release, \
1273 EDP_DEBUG_ENTRY(dpcd);
1274 EDP_DEBUG_ENTRY(edid);
1275 EDP_DEBUG_ENTRY(reg);
1279 static int rk32_edp_probe(struct platform_device *pdev)
1281 struct rk32_edp *edp;
1282 struct resource *res;
1283 struct device_node *np = pdev->dev.of_node;
1287 dev_err(&pdev->dev, "Missing device tree node.\n");
1291 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1293 dev_err(&pdev->dev, "no memory for state\n");
1296 edp->dev = &pdev->dev;
1297 edp->video_info.h_sync_polarity = 0;
1298 edp->video_info.v_sync_polarity = 0;
1299 edp->video_info.interlaced = 0;
1300 edp->video_info.color_space = CS_RGB;
1301 edp->video_info.dynamic_range = VESA;
1302 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1303 edp->video_info.color_depth = COLOR_8;
1305 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1306 edp->video_info.lane_count = LANE_CNT4;
1307 rk_fb_get_prmry_screen(&edp->screen);
1308 if (edp->screen.type != SCREEN_EDP) {
1309 dev_err(&pdev->dev, "screen is not edp!\n");
1312 platform_set_drvdata(pdev, edp);
1313 dev_set_name(edp->dev, "rk32-edp");
1315 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1317 if (IS_ERR(edp->regs)) {
1318 dev_err(&pdev->dev, "ioremap reg failed\n");
1319 return PTR_ERR(edp->regs);
1322 edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1323 if (IS_ERR(edp->clk_edp)) {
1324 dev_err(&pdev->dev, "cannot get clk_edp\n");
1325 return PTR_ERR(edp->clk_edp);
1328 edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1329 if (IS_ERR(edp->clk_24m)) {
1330 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1331 return PTR_ERR(edp->clk_24m);
1334 edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1335 if (IS_ERR(edp->pclk)) {
1336 dev_err(&pdev->dev, "cannot get pclk\n");
1337 return PTR_ERR(edp->pclk);
1340 clk_prepare(edp->pclk);
1341 clk_prepare(edp->clk_edp);
1342 clk_prepare(edp->clk_24m);
1343 rk32_edp_clk_enable(edp);
1344 if (!support_uboot_display())
1345 rk32_edp_pre_init();
1346 edp->irq = platform_get_irq(pdev, 0);
1348 dev_err(&pdev->dev, "cannot find IRQ\n");
1351 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1352 dev_name(&pdev->dev), edp);
1354 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1357 disable_irq_nosync(edp->irq);
1358 if (!support_uboot_display())
1359 rk32_edp_clk_disable(edp);
1361 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1362 #if defined(CONFIG_DEBUG_FS)
1363 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1364 if (IS_ERR(edp->debugfs_dir)) {
1365 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1367 debugfs_create_file("dpcd", S_IRUSR,edp->debugfs_dir,
1368 edp, &edp_dpcd_debugfs_fops);
1369 debugfs_create_file("edid", S_IRUSR,edp->debugfs_dir,
1370 edp, &edp_edid_debugfs_fops);
1371 debugfs_create_file("reg", S_IRUSR,edp->debugfs_dir,
1372 edp, &edp_reg_debugfs_fops);
1376 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1381 static void rk32_edp_shutdown(struct platform_device *pdev)
1386 #if defined(CONFIG_OF)
1387 static const struct of_device_id rk32_edp_dt_ids[] = {
1388 {.compatible = "rockchip,rk32-edp",},
1392 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1395 static struct platform_driver rk32_edp_driver = {
1396 .probe = rk32_edp_probe,
1399 .owner = THIS_MODULE,
1400 #if defined(CONFIG_OF)
1401 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1404 .shutdown = rk32_edp_shutdown,
1407 static int __init rk32_edp_module_init(void)
1409 return platform_driver_register(&rk32_edp_driver);
1412 static void __exit rk32_edp_module_exit(void)
1417 fs_initcall(rk32_edp_module_init);
1418 module_exit(rk32_edp_module_exit);