drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 #if defined(CONFIG_DEBUG_FS)
  35 #include <linux/fs.h>
  36 #include <linux/debugfs.h>
  37 #include <linux/seq_file.h>
  38 #endif
  39
  40 /*#define EDP_BIST_MODE*/
  41
  42 static struct rk32_edp *rk32_edp;
  43
  44 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  45 {
  46         if (!edp->clk_on) {
  47                 clk_enable(edp->pd);
  48                 clk_enable(edp->pclk);
  49                 clk_enable(edp->clk_edp);
  50                 clk_enable(edp->clk_24m);
  51                 edp->clk_on = true;
  52         }
  53
  54         return 0;
  55 }
  56
  57 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  58 {
  59         if (edp->clk_on) {
  60                 clk_disable(edp->pclk);
  61                 clk_disable(edp->clk_edp);
  62                 clk_disable(edp->clk_24m);
  63                 clk_disable(edp->pd);
  64                 edp->clk_on = false;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static int rk32_edp_pre_init(void)
  71 {
  72         u32 val;
  73         val = GRF_EDP_REF_CLK_SEL_INTER | (GRF_EDP_REF_CLK_SEL_INTER << 16);
  74         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  75
  76         val = 0x80008000;
  77         writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
  78         dsb();
  79         val = 0x80008000;
  80         writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  81         dsb();
  82         udelay(1);
  83         val = 0x80000000;
  84         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  85         dsb();
  86         udelay(1);
  87         return 0;
  88 }
  89
  90 static int rk32_edp_init_edp(struct rk32_edp *edp)
  91 {
  92         struct rk_screen *screen = &edp->screen;
  93         u32 val = 0;
  94
  95         screen->lcdc_id = 1;
  96         if (screen->lcdc_id == 1)  /*select lcdc*/
  97                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  98         else
  99                 val = EDP_SEL_VOP_LIT << 16;
 100         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 101
 102         rk32_edp_reset(edp);
 103         rk32_edp_init_refclk(edp);
 104         rk32_edp_init_interrupt(edp);
 105         rk32_edp_enable_sw_function(edp);
 106         rk32_edp_init_analog_func(edp);
 107         rk32_edp_init_hpd(edp);
 108         rk32_edp_init_aux(edp);
 109
 110         return 0;
 111 }
 112
 113 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 114 {
 115         int timeout_loop = 0;
 116
 117         rk32_edp_init_hpd(edp);
 118
 119         udelay(200);
 120
 121         while (rk32_edp_get_plug_in_status(edp) != 0) {
 122                 timeout_loop++;
 123                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 124                         dev_err(edp->dev, "failed to get hpd plug status\n");
 125                         return -ETIMEDOUT;
 126                 }
 127                 udelay(10);
 128         }
 129
 130         return 0;
 131 }
 132
 133 static int rk32_edp_read_edid(struct rk32_edp *edp)
 134 {
 135         unsigned char edid[EDID_LENGTH * 2];
 136         unsigned int extend_block = 0;
 137         unsigned char sum;
 138         unsigned char test_vector;
 139         int retval;
 140
 141         /*
 142          * EDID device address is 0x50.
 143          * However, if necessary, you must have set upper address
 144          * into E-EDID in I2C device, 0x30.
 145          */
 146
 147         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 148         retval = rk32_edp_read_byte_from_i2c(edp,
 149                 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
 150         if (retval < 0) {
 151                 dev_err(edp->dev, "EDID extension flag failed!\n");
 152                 return -EIO;
 153         }
 154
 155         if (extend_block > 0) {
 156                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 157
 158                 /* Read EDID data */
 159                 retval = rk32_edp_read_bytes_from_i2c(edp,
 160                                 EDID_ADDR, EDID_HEADER,
 161                                 EDID_LENGTH, &edid[EDID_HEADER]);
 162                 if (retval != 0) {
 163                         dev_err(edp->dev, "EDID Read failed!\n");
 164                         return -EIO;
 165                 }
 166                 sum = edp_calc_edid_check_sum(edid);
 167                 if (sum != 0) {
 168                         dev_warn(edp->dev, "EDID bad checksum!\n");
 169                         return 0;
 170                 }
 171
 172                 /* Read additional EDID data */
 173                 retval = rk32_edp_read_bytes_from_i2c(edp,
 174                                 EDID_ADDR, EDID_LENGTH,
 175                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 176                 if (retval != 0) {
 177                         dev_err(edp->dev, "EDID Read failed!\n");
 178                         return -EIO;
 179                 }
 180                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 181                 if (sum != 0) {
 182                         dev_warn(edp->dev, "EDID bad checksum!\n");
 183                         return 0;
 184                 }
 185
 186                 retval = rk32_edp_read_byte_from_dpcd(edp,
 187                                 DPCD_TEST_REQUEST, &test_vector);
 188                 if (retval < 0) {
 189                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 190                         return retval;
 191                 }
 192
 193                 if (test_vector & DPCD_TEST_EDID_READ) {
 194                         retval = rk32_edp_write_byte_to_dpcd(edp,
 195                                         DPCD_TEST_EDID_CHECKSUM,
 196                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 197                         if (retval < 0) {
 198                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 199                                 return retval;
 200                         }
 201                         retval = rk32_edp_write_byte_to_dpcd(edp,
 202                                         DPCD_TEST_RESPONSE,
 203                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 204                         if (retval < 0) {
 205                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 206                                 return retval;
 207                         }
 208                 }
 209         } else {
 210                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 211
 212                 /* Read EDID data */
 213                 retval = rk32_edp_read_bytes_from_i2c(edp,
 214                                 EDID_ADDR, EDID_HEADER,
 215                                 EDID_LENGTH, &edid[EDID_HEADER]);
 216                 if (retval != 0) {
 217                         dev_err(edp->dev, "EDID Read failed!\n");
 218                         return -EIO;
 219                 }
 220                 sum = edp_calc_edid_check_sum(edid);
 221                 if (sum != 0) {
 222                         dev_warn(edp->dev, "EDID bad checksum!\n");
 223                         return 0;
 224                 }
 225
 226                 retval = rk32_edp_read_byte_from_dpcd(edp,
 227                                 DPCD_TEST_REQUEST, &test_vector);
 228                 if (retval < 0) {
 229                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 230                         return retval;
 231                 }
 232
 233                 if (test_vector & DPCD_TEST_EDID_READ) {
 234                         retval = rk32_edp_write_byte_to_dpcd(edp,
 235                                         DPCD_TEST_EDID_CHECKSUM,
 236                                         edid[EDID_CHECKSUM]);
 237                         if (retval < 0) {
 238                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 239                                 return retval;
 240                         }
 241                         retval = rk32_edp_write_byte_to_dpcd(edp,
 242                                         DPCD_TEST_RESPONSE,
 243                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 244                         if (retval < 0) {
 245                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 246                                 return retval;
 247                         }
 248                 }
 249         }
 250         fb_edid_to_monspecs(edid, &edp->specs);
 251         dev_err(edp->dev, "EDID Read success!\n");
 252         return 0;
 253 }
 254
 255 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 256 {
 257         u8 buf[12];
 258         int i;
 259         int retval;
 260
 261         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 262         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 263         if (retval < 0)
 264                 return retval;
 265
 266         for (i = 0; i < 12; i++)
 267                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 268         /* Read EDID */
 269         for (i = 0; i < 3; i++) {
 270                 retval = rk32_edp_read_edid(edp);
 271                 if (retval == 0)
 272                         break;
 273         }
 274
 275         return retval;
 276 }
 277
 278 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 279                                                 bool enable)
 280 {
 281         u8 data;
 282         int retval;
 283
 284         retval = rk32_edp_read_byte_from_dpcd(edp,
 285                         DPCD_LANE_CNT_SET, &data);
 286         if (retval < 0)
 287                 return retval;
 288
 289         if (enable) {
 290                 retval = rk32_edp_write_byte_to_dpcd(edp,
 291                                 DPCD_LANE_CNT_SET,
 292                                 DPCD_ENHANCED_FRAME_EN |
 293                                 DPCD_LANE_COUNT_SET(data));
 294         } else {
 295                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 296                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 297
 298                 retval = rk32_edp_write_byte_to_dpcd(edp,
 299                                 DPCD_LANE_CNT_SET,
 300                                 DPCD_LANE_COUNT_SET(data));
 301         }
 302
 303         return retval;
 304 }
 305
 306 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 307 {
 308         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 309         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 310
 311         if (enable) {
 312                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 313                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 314         } else {
 315                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 316         }*/
 317 }
 318
 319 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 320 {
 321         u8 data;
 322         int retval;
 323
 324         retval = rk32_edp_read_byte_from_dpcd(edp,
 325                         DPCD_MAX_LANE_CNT, &data);
 326         if (retval < 0)
 327                 return retval;
 328
 329         return DPCD_ENHANCED_FRAME_CAP(data);
 330 }
 331
 332 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 333 {
 334         /*rk32_edp_write_byte_to_dpcd(edp,
 335                         DPCD_ADDR_USER_DEFINED1, 0);
 336         rk32_edp_write_byte_to_dpcd(edp,
 337                         DPCD_ADDR_USER_DEFINED2, 0x83);
 338         rk32_edp_write_byte_to_dpcd(edp,
 339                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 340 }
 341
 342 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 343 {
 344         u8 data;
 345         int retval;
 346
 347         retval = rk32_edp_is_enhanced_mode_available(edp);
 348         if (retval < 0)
 349                 return retval;
 350
 351         data = (u8)retval;
 352         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 353         if (retval < 0)
 354                 return retval;
 355
 356         rk32_edp_enable_enhanced_mode(edp, data);
 357
 358         return 0;
 359 }
 360
 361 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 362 {
 363         int retval;
 364
 365         rk32_edp_set_training_pattern(edp, DP_NONE);
 366
 367         retval = rk32_edp_write_byte_to_dpcd(edp,
 368                         DPCD_TRAINING_PATTERN_SET,
 369                         DPCD_TRAINING_PATTERN_DISABLED);
 370         if (retval < 0)
 371                 return retval;
 372
 373         return 0;
 374 }
 375
 376 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 377                                         int pre_emphasis, int lane)
 378 {
 379         switch (lane) {
 380         case 0:
 381                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 382                 break;
 383         case 1:
 384                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 385                 break;
 386
 387         case 2:
 388                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 389                 break;
 390
 391         case 3:
 392                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 393                 break;
 394         }
 395 }
 396
 397 static int rk32_edp_link_start(struct rk32_edp *edp)
 398 {
 399         u8 buf[4];
 400         int lane;
 401         int lane_count;
 402         int retval;
 403
 404         lane_count = edp->link_train.lane_count;
 405
 406         edp->link_train.lt_state = LT_CLK_RECOVERY;
 407         edp->link_train.eq_loop = 0;
 408
 409         for (lane = 0; lane < lane_count; lane++)
 410                 edp->link_train.cr_loop[lane] = 0;
 411
 412         /* Set sink to D0 (Sink Not Ready) mode. */
 413         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 414                                 DPCD_SET_POWER_STATE_D0);
 415         if (retval < 0) {
 416                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 417                 return retval;
 418         }
 419
 420         /* Set link rate and count as you want to establish*/
 421         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 422         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 423
 424         /* Setup RX configuration */
 425         buf[0] = edp->link_train.link_rate;
 426         buf[1] = edp->link_train.lane_count;
 427         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 428                                         2, buf);
 429         if (retval < 0) {
 430                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 431                 return retval;
 432         }
 433
 434         /* Set TX pre-emphasis to level1 */
 435         for (lane = 0; lane < lane_count; lane++)
 436                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 437                         PRE_EMPHASIS_LEVEL_1, lane);
 438
 439         /* Set training pattern 1 */
 440         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 441
 442         /* Set RX training pattern */
 443         retval = rk32_edp_write_byte_to_dpcd(edp,
 444                         DPCD_TRAINING_PATTERN_SET,
 445                         DPCD_SCRAMBLING_DISABLED |
 446                         DPCD_TRAINING_PATTERN_1);
 447         if (retval < 0) {
 448                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 449                 return retval;
 450         }
 451
 452         for (lane = 0; lane < lane_count; lane++)
 453                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 454                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 455         retval = rk32_edp_write_bytes_to_dpcd(edp,
 456                         DPCD_TRAINING_LANE0_SET,
 457                         lane_count, buf);
 458         if (retval < 0) {
 459                 dev_err(edp->dev, "failed to set training lane!\n");
 460                 return retval;
 461         }
 462
 463         return 0;
 464 }
 465
 466 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 467 {
 468         int shift = (lane & 1) * 4;
 469         u8 link_value = link_status[lane>>1];
 470
 471         return (link_value >> shift) & 0xf;
 472 }
 473
 474 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 475 {
 476         int lane;
 477         u8 lane_status;
 478
 479         for (lane = 0; lane < lane_count; lane++) {
 480                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 481                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 482                         return -EINVAL;
 483         }
 484         return 0;
 485 }
 486
 487 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 488 {
 489         int lane;
 490         u8 lane_align;
 491         u8 lane_status;
 492
 493         lane_align = link_align[2];
 494         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 495                 return -EINVAL;
 496
 497         for (lane = 0; lane < lane_count; lane++) {
 498                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 499                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 500                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 501                         return -EINVAL;
 502         }
 503
 504         return 0;
 505 }
 506
 507 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 508                                                         int lane)
 509 {
 510         int shift = (lane & 1) * 4;
 511         u8 link_value = adjust_request[lane>>1];
 512
 513         return (link_value >> shift) & 0x3;
 514 }
 515
 516 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 517                                         u8 adjust_request[2],
 518                                         int lane)
 519 {
 520         int shift = (lane & 1) * 4;
 521         u8 link_value = adjust_request[lane>>1];
 522
 523         return ((link_value >> shift) & 0xc) >> 2;
 524 }
 525
 526 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 527                                         u8 training_lane_set, int lane)
 528 {
 529         switch (lane) {
 530         case 0:
 531                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 532                 break;
 533         case 1:
 534                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 535                 break;
 536
 537         case 2:
 538                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 539                 break;
 540
 541         case 3:
 542                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 543                 break;
 544         }
 545 }
 546
 547 static unsigned int rk32_edp_get_lane_link_training(
 548                                 struct rk32_edp *edp,
 549                                 int lane)
 550 {
 551         u32 reg;
 552
 553         switch (lane) {
 554         case 0:
 555                 reg = rk32_edp_get_lane0_link_training(edp);
 556                 break;
 557         case 1:
 558                 reg = rk32_edp_get_lane1_link_training(edp);
 559                 break;
 560         case 2:
 561                 reg = rk32_edp_get_lane2_link_training(edp);
 562                 break;
 563         case 3:
 564                 reg = rk32_edp_get_lane3_link_training(edp);
 565                 break;
 566         }
 567
 568         return reg;
 569 }
 570
 571 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 572 {
 573         rk32_edp_training_pattern_dis(edp);
 574
 575         edp->link_train.lt_state = FAILED;
 576 }
 577
 578 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 579 {
 580         u8 link_status[2];
 581         int lane;
 582         int lane_count;
 583
 584         u8 adjust_request[2];
 585         u8 voltage_swing;
 586         u8 pre_emphasis;
 587         u8 training_lane;
 588         int retval;
 589
 590         udelay(100);
 591
 592         lane_count = edp->link_train.lane_count;
 593
 594         retval = rk32_edp_read_bytes_from_dpcd(edp,
 595                         DPCD_LANE0_1_STATUS,
 596                         2, link_status);
 597         if (retval < 0) {
 598                 dev_err(edp->dev, "failed to read lane status!\n");
 599                 return retval;
 600         }
 601
 602         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 603                 /* set training pattern 2 for EQ */
 604                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 605
 606                 for (lane = 0; lane < lane_count; lane++) {
 607                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 608                                         DPCD_ADJUST_REQUEST_LANE0_1,
 609                                         2, adjust_request);
 610                         if (retval < 0) {
 611                                 dev_err(edp->dev, "failed to read adjust request!\n");
 612                                 return retval;
 613                         }
 614
 615                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 616                                                         adjust_request, lane);
 617                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 618                                                         adjust_request, lane);
 619                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 620                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 621
 622                         if (voltage_swing == VOLTAGE_LEVEL_3)
 623                                 training_lane |= DPCD_MAX_SWING_REACHED;
 624                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 625                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 626
 627                         edp->link_train.training_lane[lane] = training_lane;
 628
 629                         rk32_edp_set_lane_link_training(edp,
 630                                 edp->link_train.training_lane[lane],
 631                                 lane);
 632                 }
 633
 634                 retval = rk32_edp_write_byte_to_dpcd(edp,
 635                                 DPCD_TRAINING_PATTERN_SET,
 636                                 DPCD_SCRAMBLING_DISABLED |
 637                                 DPCD_TRAINING_PATTERN_2);
 638                 if (retval < 0) {
 639                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 640                         return retval;
 641                 }
 642
 643                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 644                                 DPCD_TRAINING_LANE0_SET,
 645                                 lane_count,
 646                                 edp->link_train.training_lane);
 647                 if (retval < 0) {
 648                         dev_err(edp->dev, "failed to set training lane!\n");
 649                         return retval;
 650                 }
 651
 652                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 653                 edp->link_train.lt_state = LT_EQ_TRAINING;
 654         } else {
 655                 for (lane = 0; lane < lane_count; lane++) {
 656                         training_lane = rk32_edp_get_lane_link_training(
 657                                                         edp, lane);
 658                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 659                                         DPCD_ADJUST_REQUEST_LANE0_1,
 660                                         2, adjust_request);
 661                         if (retval < 0) {
 662                                 dev_err(edp->dev, "failed to read adjust request!\n");
 663                                 return retval;
 664                         }
 665
 666                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 667                                                         adjust_request, lane);
 668                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 669                                                         adjust_request, lane);
 670
 671                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 672                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 673                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 674                                 goto reduce_link_rate;
 675                         }
 676
 677                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 678                                         voltage_swing) &&
 679                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 680                                         pre_emphasis)) {
 681                                 edp->link_train.cr_loop[lane]++;
 682                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 683                                         dev_err(edp->dev, "CR Max loop\n");
 684                                         goto reduce_link_rate;
 685                                 }
 686                         }
 687
 688                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 689                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 690
 691                         if (voltage_swing == VOLTAGE_LEVEL_3)
 692                                 training_lane |= DPCD_MAX_SWING_REACHED;
 693                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 694                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 695
 696                         edp->link_train.training_lane[lane] = training_lane;
 697
 698                         rk32_edp_set_lane_link_training(edp,
 699                                 edp->link_train.training_lane[lane], lane);
 700                 }
 701
 702                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 703                                 DPCD_TRAINING_LANE0_SET,
 704                                 lane_count,
 705                                 edp->link_train.training_lane);
 706                 if (retval < 0) {
 707                         dev_err(edp->dev, "failed to set training lane!\n");
 708                         return retval;
 709                 }
 710         }
 711
 712         return 0;
 713
 714 reduce_link_rate:
 715         rk32_edp_reduce_link_rate(edp);
 716         return -EIO;
 717 }
 718
 719 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 720 {
 721         u8 link_status[2];
 722         u8 link_align[3];
 723         int lane;
 724         int lane_count;
 725         u32 reg;
 726
 727         u8 adjust_request[2];
 728         u8 voltage_swing;
 729         u8 pre_emphasis;
 730         u8 training_lane;
 731         int retval;
 732
 733         udelay(400);
 734
 735         lane_count = edp->link_train.lane_count;
 736
 737         retval = rk32_edp_read_bytes_from_dpcd(edp,
 738                         DPCD_LANE0_1_STATUS,
 739                         2, link_status);
 740         if (retval < 0) {
 741                 dev_err(edp->dev, "failed to read lane status!\n");
 742                 return retval;
 743         }
 744
 745         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 746                 link_align[0] = link_status[0];
 747                 link_align[1] = link_status[1];
 748
 749                 retval = rk32_edp_read_byte_from_dpcd(edp,
 750                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 751                                 &link_align[2]);
 752                 if (retval < 0) {
 753                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 754                         return retval;
 755                 }
 756
 757                 for (lane = 0; lane < lane_count; lane++) {
 758                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 759                                         DPCD_ADJUST_REQUEST_LANE0_1,
 760                                         2, adjust_request);
 761                         if (retval < 0) {
 762                                 dev_err(edp->dev, "failed to read adjust request!\n");
 763                                 return retval;
 764                         }
 765
 766                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 767                                                         adjust_request, lane);
 768                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 769                                                         adjust_request, lane);
 770                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 771                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 772
 773                         if (voltage_swing == VOLTAGE_LEVEL_3)
 774                                 training_lane |= DPCD_MAX_SWING_REACHED;
 775                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 776                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 777
 778                         edp->link_train.training_lane[lane] = training_lane;
 779                 }
 780
 781                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 782                         /* traing pattern Set to Normal */
 783                         retval = rk32_edp_training_pattern_dis(edp);
 784                         if (retval < 0) {
 785                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 786                                 return retval;
 787                         }
 788
 789                         dev_info(edp->dev, "Link Training success!\n");
 790
 791                         rk32_edp_get_link_bandwidth(edp, &reg);
 792                         edp->link_train.link_rate = reg;
 793                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 794                                 edp->link_train.link_rate);
 795
 796                         rk32_edp_get_lane_count(edp, &reg);
 797                         edp->link_train.lane_count = reg;
 798                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 799                                 edp->link_train.lane_count);
 800
 801                         edp->link_train.lt_state = FINISHED;
 802                 } else {
 803                         /* not all locked */
 804                         edp->link_train.eq_loop++;
 805
 806                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 807                                 dev_err(edp->dev, "EQ Max loop\n");
 808                                 goto reduce_link_rate;
 809                         }
 810
 811                         for (lane = 0; lane < lane_count; lane++)
 812                                 rk32_edp_set_lane_link_training(edp,
 813                                         edp->link_train.training_lane[lane],
 814                                         lane);
 815
 816                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 817                                         DPCD_TRAINING_LANE0_SET,
 818                                         lane_count,
 819                                         edp->link_train.training_lane);
 820                         if (retval < 0) {
 821                                 dev_err(edp->dev, "failed to set training lane!\n");
 822                                 return retval;
 823                         }
 824                 }
 825         } else {
 826                 goto reduce_link_rate;
 827         }
 828
 829         return 0;
 830
 831 reduce_link_rate:
 832         rk32_edp_reduce_link_rate(edp);
 833         return -EIO;
 834 }
 835
 836 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 837                                         u8 *bandwidth)
 838 {
 839         u8 data;
 840         int retval = 0;
 841
 842         /*
 843          * For DP rev.1.1, Maximum link rate of Main Link lanes
 844          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 845          */
 846         retval = rk32_edp_read_byte_from_dpcd(edp,
 847                         DPCD_MAX_LINK_RATE, &data);
 848         if (retval < 0)
 849                 *bandwidth = 0;
 850         else
 851                 *bandwidth = data;
 852         return retval;
 853
 854 }
 855
 856 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 857                                         u8 *lane_count)
 858 {
 859         u8 data;
 860         int retval;
 861
 862         /*
 863          * For DP rev.1.1, Maximum number of Main Link lanes
 864          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 865          */
 866         retval = rk32_edp_read_byte_from_dpcd(edp,
 867                         DPCD_MAX_LANE_CNT, &data);
 868         if (retval < 0)
 869                 *lane_count = 0;
 870         else
 871                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 872         return retval;
 873 }
 874
 875 static int rk32_edp_init_training(struct rk32_edp *edp)
 876 {
 877         int retval;
 878
 879         /*
 880          * MACRO_RST must be applied after the PLL_LOCK to avoid
 881          * the DP inter pair skew issue for at least 10 us
 882          */
 883         rk32_edp_reset_macro(edp);
 884
 885
 886         retval = rk32_edp_get_max_rx_bandwidth(edp,
 887                                 &edp->link_train.link_rate);
 888         retval = rk32_edp_get_max_rx_lane_count(edp,
 889                                 &edp->link_train.lane_count);
 890         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 891                         edp->link_train.link_rate * 27/100,
 892                         edp->link_train.link_rate*27%100,
 893                         edp->link_train.lane_count);
 894
 895         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 896            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 897                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 898                         "use default link rate:%d.%dGps\n",
 899                         edp->link_train.link_rate,
 900                         edp->video_info.link_rate*27/100,
 901                         edp->video_info.link_rate*27%100);
 902                 edp->link_train.link_rate = edp->video_info.link_rate;
 903         }
 904
 905         if (edp->link_train.lane_count == 0) {
 906                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 907                         "use default lanes:%d\n",
 908                         edp->link_train.lane_count,
 909                         edp->video_info.lane_count);
 910                 edp->link_train.lane_count = edp->video_info.lane_count;
 911         }
 912
 913         rk32_edp_analog_power_ctr(edp, 1);
 914
 915
 916         return 0;
 917 }
 918
 919 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 920 {
 921         int retval = 0;
 922         int training_finished = 0;
 923
 924         edp->link_train.lt_state = LT_START;
 925
 926         /* Process here */
 927         while (!training_finished) {
 928                 switch (edp->link_train.lt_state) {
 929                 case LT_START:
 930                         retval = rk32_edp_link_start(edp);
 931                         if (retval)
 932                                 dev_err(edp->dev, "LT Start failed\n");
 933                         break;
 934                 case LT_CLK_RECOVERY:
 935                         retval = rk32_edp_process_clock_recovery(edp);
 936                         if (retval)
 937                                 dev_err(edp->dev, "LT CR failed\n");
 938                         break;
 939                 case LT_EQ_TRAINING:
 940                         retval = rk32_edp_process_equalizer_training(edp);
 941                         if (retval)
 942                                 dev_err(edp->dev, "LT EQ failed\n");
 943                         break;
 944                 case FINISHED:
 945                         training_finished = 1;
 946                         break;
 947                 case FAILED:
 948                         return -EREMOTEIO;
 949                 }
 950         }
 951
 952         return retval;
 953 }
 954
 955
 956 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 957 {
 958         u32 cnt = 50;
 959         u32 val;
 960         /* Set link rate and count as you want to establish*/
 961         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 962         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 963         rk32_edp_hw_link_training_en(edp);
 964         val = rk32_edp_wait_hw_lt_done(edp);
 965         while (val) {
 966                 if (cnt-- <= 0) {
 967                         dev_err(edp->dev, "hw lt timeout");
 968                         return -ETIMEDOUT;
 969                 }
 970                 mdelay(1);
 971                 val = rk32_edp_wait_hw_lt_done(edp);
 972         }
 973
 974         val = rk32_edp_get_hw_lt_status(edp);
 975         if (val)
 976                 dev_err(edp->dev, "hw lt err:%d\n", val);
 977         return val;
 978
 979 }
 980 static int rk32_edp_set_link_train(struct rk32_edp *edp)
 981 {
 982         int retval;
 983
 984         retval = rk32_edp_init_training(edp);
 985         if (retval < 0)
 986                 dev_err(edp->dev, "DP LT init failed!\n");
 987 #if 0
 988         retval = rk32_edp_sw_link_training(edp);
 989 #else
 990         retval = rk32_edp_hw_link_training(edp);
 991 #endif
 992
 993         return retval;
 994 }
 995
 996 static int rk32_edp_config_video(struct rk32_edp *edp,
 997                         struct video_info *video_info)
 998 {
 999         int retval = 0;
1000         int timeout_loop = 0;
1001         int done_count = 0;
1002
1003         rk32_edp_config_video_slave_mode(edp, video_info);
1004
1005         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1006                         video_info->color_space,
1007                         video_info->dynamic_range,
1008                         video_info->ycbcr_coeff);
1009
1010         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1011                 dev_err(edp->dev, "PLL is not locked yet.\n");
1012                 return -EINVAL;
1013         }
1014
1015         for (;;) {
1016                 timeout_loop++;
1017                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1018                         break;
1019                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1020                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1021                         return -ETIMEDOUT;
1022                 }
1023
1024                 udelay(1);
1025         }
1026
1027         /* Set to use the register calculated M/N video */
1028         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1029
1030         /* For video bist, Video timing must be generated by register */
1031 #ifndef EDP_BIST_MODE
1032         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1033 #endif
1034         /* Disable video mute */
1035         rk32_edp_enable_video_mute(edp, 0);
1036
1037         /* Configure video slave mode */
1038         rk32_edp_enable_video_master(edp, 0);
1039
1040         /* Enable video */
1041         rk32_edp_start_video(edp);
1042
1043         timeout_loop = 0;
1044
1045         for (;;) {
1046                 timeout_loop++;
1047                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1048                         done_count++;
1049                         if (done_count > 10)
1050                                 break;
1051                 } else if (done_count) {
1052                         done_count = 0;
1053                 }
1054                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1055                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1056                         return -ETIMEDOUT;
1057                 }
1058
1059                 mdelay(1);
1060         }
1061
1062         if (retval != 0)
1063                 dev_err(edp->dev, "Video stream is not detected!\n");
1064
1065         return retval;
1066 }
1067
1068 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1069 {
1070         u8 data;
1071         int retval;
1072
1073         if (enable) {
1074                 rk32_edp_enable_scrambling(edp);
1075
1076                 retval = rk32_edp_read_byte_from_dpcd(edp,
1077                                 DPCD_TRAINING_PATTERN_SET,
1078                                 &data);
1079                 if (retval < 0)
1080                         return retval;
1081
1082                 retval = rk32_edp_write_byte_to_dpcd(edp,
1083                                 DPCD_TRAINING_PATTERN_SET,
1084                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1085                 if (retval < 0)
1086                         return retval;
1087         } else {
1088                 rk32_edp_disable_scrambling(edp);
1089
1090                 retval = rk32_edp_read_byte_from_dpcd(edp,
1091                                 DPCD_TRAINING_PATTERN_SET,
1092                                 &data);
1093                 if (retval < 0)
1094                         return retval;
1095
1096                 retval = rk32_edp_write_byte_to_dpcd(edp,
1097                                 DPCD_TRAINING_PATTERN_SET,
1098                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1099                 if (retval < 0)
1100                         return retval;
1101         }
1102
1103         return 0;
1104 }
1105
1106 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1107 {
1108         struct rk32_edp *edp = arg;
1109         enum dp_irq_type irq_type;
1110
1111         irq_type = rk32_edp_get_irq_type(edp);
1112         switch (irq_type) {
1113         case DP_IRQ_TYPE_HP_CABLE_IN:
1114                 dev_info(edp->dev, "Received irq - cable in\n");
1115                 rk32_edp_clear_hotplug_interrupts(edp);
1116                 break;
1117         case DP_IRQ_TYPE_HP_CABLE_OUT:
1118                 dev_info(edp->dev, "Received irq - cable out\n");
1119                 rk32_edp_clear_hotplug_interrupts(edp);
1120                 break;
1121         case DP_IRQ_TYPE_HP_CHANGE:
1122                 /*
1123                  * We get these change notifications once in a while, but there
1124                  * is nothing we can do with them. Just ignore it for now and
1125                  * only handle cable changes.
1126                  */
1127                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1128                 rk32_edp_clear_hotplug_interrupts(edp);
1129                 break;
1130         default:
1131                 dev_err(edp->dev, "Received irq - unknown type!\n");
1132                 break;
1133         }
1134         return IRQ_HANDLED;
1135 }
1136
1137 static int rk32_edp_enable(void)
1138 {
1139         int ret = 0;
1140         struct rk32_edp *edp = rk32_edp;
1141
1142
1143         rk32_edp_clk_enable(edp);
1144         rk32_edp_pre_init();
1145         rk32_edp_init_edp(edp);
1146         enable_irq(edp->irq);
1147         /*ret = rk32_edp_handle_edid(edp);
1148         if (ret) {
1149                 dev_err(edp->dev, "unable to handle edid\n");
1150                 //goto out;
1151         }
1152
1153
1154         ret = rk32_edp_enable_scramble(edp, 0);
1155         if (ret) {
1156                 dev_err(edp->dev, "unable to set scramble\n");
1157                 //goto out;
1158         }
1159
1160         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1161         if (ret) {
1162                 dev_err(edp->dev, "unable to set enhanced mode\n");
1163                 //goto out;
1164         }
1165         rk32_edp_enable_enhanced_mode(edp, 1);*/
1166
1167         ret = rk32_edp_set_link_train(edp);
1168         if (ret)
1169                 dev_err(edp->dev, "link train failed!\n");
1170         else
1171                 dev_info(edp->dev, "link training success.\n");
1172
1173         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1174         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1175         rk32_edp_init_video(edp);
1176
1177 #ifdef EDP_BIST_MODE
1178         rk32_edp_bist_cfg(edp);
1179 #endif
1180         ret = rk32_edp_config_video(edp, &edp->video_info);
1181         if (ret)
1182                 dev_err(edp->dev, "unable to config video\n");
1183
1184         return ret;
1185
1186
1187
1188 }
1189
1190 static int  rk32_edp_disable(void)
1191 {
1192         struct rk32_edp *edp = rk32_edp;
1193
1194         disable_irq(edp->irq);
1195         rk32_edp_reset(edp);
1196         rk32_edp_analog_power_ctr(edp, 0);
1197         rk32_edp_clk_disable(edp);
1198
1199         return 0;
1200 }
1201
1202
1203 static struct rk_fb_trsm_ops trsm_edp_ops = {
1204         .enable = rk32_edp_enable,
1205         .disable = rk32_edp_disable,
1206 };
1207
1208
1209 #if defined(CONFIG_DEBUG_FS)
1210
1211 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1212 {
1213         int i = 0;
1214         unsigned char buf[12];
1215         struct rk32_edp *edp = s->private;
1216         if (!edp) {
1217                 dev_err(edp->dev, "no edp device!\n");
1218                 return -ENODEV;
1219         }
1220
1221
1222         rk32_edp_read_bytes_from_dpcd(edp,
1223                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1224         for (i = 0; i < 12; i++)
1225                 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);
1226         return 0;
1227 }
1228
1229 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1230 {
1231         struct rk32_edp *edp = s->private;
1232         if (!edp) {
1233                 dev_err(edp->dev, "no edp device!\n");
1234                 return -ENODEV;
1235         }
1236         rk32_edp_read_edid(edp);
1237         seq_puts(s, "edid");
1238         return 0;
1239 }
1240
1241 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1242 {
1243         int i = 0;
1244         struct rk32_edp *edp = s->private;
1245         if (!edp) {
1246                 dev_err(edp->dev, "no edp device!\n");
1247                 return -ENODEV;
1248         }
1249
1250         for (i = 0; i < 0x284; i++) {
1251                 if (!(i%4))
1252                         seq_printf(s, "\n%08x:  ", i*4);
1253                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1254         }
1255         return 0;
1256 }
1257
1258
1259 #define EDP_DEBUG_ENTRY(name) \
1260 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1261 { \
1262         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1263 } \
1264 \
1265 static const struct file_operations edp_##name##_debugfs_fops = { \
1266         .owner = THIS_MODULE, \
1267         .open = edp_##name##_debugfs_open, \
1268         .read = seq_read, \
1269         .llseek = seq_lseek, \
1270         .release = single_release, \
1271 }
1272
1273 EDP_DEBUG_ENTRY(dpcd);
1274 EDP_DEBUG_ENTRY(edid);
1275 EDP_DEBUG_ENTRY(reg);
1276
1277 #endif
1278
1279 static int rk32_edp_probe(struct platform_device *pdev)
1280 {
1281         struct rk32_edp *edp;
1282         struct resource *res;
1283         struct device_node *np = pdev->dev.of_node;
1284         int ret;
1285
1286         if (!np) {
1287                 dev_err(&pdev->dev, "Missing device tree node.\n");
1288                 return -EINVAL;
1289         }
1290
1291         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1292         if (!edp) {
1293                 dev_err(&pdev->dev, "no memory for state\n");
1294                 return -ENOMEM;
1295         }
1296         edp->dev = &pdev->dev;
1297         edp->video_info.h_sync_polarity = 0;
1298         edp->video_info.v_sync_polarity = 0;
1299         edp->video_info.interlaced      = 0;
1300         edp->video_info.color_space     = CS_RGB;
1301         edp->video_info.dynamic_range   = VESA;
1302         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1303         edp->video_info.color_depth     = COLOR_8;
1304
1305         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1306         edp->video_info.lane_count      = LANE_CNT4;
1307         rk_fb_get_prmry_screen(&edp->screen);
1308         if (edp->screen.type != SCREEN_EDP) {
1309                 dev_err(&pdev->dev, "screen is not edp!\n");
1310                 return -EINVAL;
1311         }
1312         platform_set_drvdata(pdev, edp);
1313         dev_set_name(edp->dev, "rk32-edp");
1314
1315         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1316         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1317         if (IS_ERR(edp->regs)) {
1318                 dev_err(&pdev->dev, "ioremap reg failed\n");
1319                 return PTR_ERR(edp->regs);
1320         }
1321
1322         edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1323         if (IS_ERR(edp->pd))
1324                 dev_err(&pdev->dev, "cannot get pd\n");
1325         edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1326         if (IS_ERR(edp->clk_edp)) {
1327                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1328                 return PTR_ERR(edp->clk_edp);
1329         }
1330
1331         edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1332         if (IS_ERR(edp->clk_24m)) {
1333                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1334                 return PTR_ERR(edp->clk_24m);
1335         }
1336
1337         edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1338         if (IS_ERR(edp->pclk)) {
1339                 dev_err(&pdev->dev, "cannot get pclk\n");
1340                 return PTR_ERR(edp->pclk);
1341         }
1342         clk_prepare(edp->pd);
1343         clk_prepare(edp->pclk);
1344         clk_prepare(edp->clk_edp);
1345         clk_prepare(edp->clk_24m);
1346         rk32_edp_clk_enable(edp);
1347         if (!support_uboot_display())
1348                 rk32_edp_pre_init();
1349         edp->irq = platform_get_irq(pdev, 0);
1350         if (edp->irq < 0) {
1351                 dev_err(&pdev->dev, "cannot find IRQ\n");
1352                 return edp->irq;
1353         }
1354         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1355                         dev_name(&pdev->dev), edp);
1356         if (ret) {
1357                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1358                 return ret;
1359         }
1360         disable_irq_nosync(edp->irq);
1361         if (!support_uboot_display())
1362                 rk32_edp_clk_disable(edp);
1363         rk32_edp = edp;
1364         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1365 #if defined(CONFIG_DEBUG_FS)
1366         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1367         if (IS_ERR(edp->debugfs_dir)) {
1368                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1369         } else {
1370                 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1371                                         edp, &edp_dpcd_debugfs_fops);
1372                 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1373                                         edp, &edp_edid_debugfs_fops);
1374                 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1375                                         edp, &edp_reg_debugfs_fops);
1376         }
1377
1378 #endif
1379         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1380
1381         return 0;
1382 }
1383
1384 static void rk32_edp_shutdown(struct platform_device *pdev)
1385 {
1386
1387 }
1388
1389 #if defined(CONFIG_OF)
1390 static const struct of_device_id rk32_edp_dt_ids[] = {
1391         {.compatible = "rockchip,rk32-edp",},
1392         {}
1393 };
1394
1395 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1396 #endif
1397
1398 static struct platform_driver rk32_edp_driver = {
1399         .probe = rk32_edp_probe,
1400         .driver = {
1401                    .name = "rk32-edp",
1402                    .owner = THIS_MODULE,
1403 #if defined(CONFIG_OF)
1404                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1405 #endif
1406         },
1407         .shutdown = rk32_edp_shutdown,
1408 };
1409
1410 static int __init rk32_edp_module_init(void)
1411 {
1412         return platform_driver_register(&rk32_edp_driver);
1413 }
1414
1415 static void __exit rk32_edp_module_exit(void)
1416 {
1417
1418 }
1419
1420 fs_initcall(rk32_edp_module_init);
1421 module_exit(rk32_edp_module_exit);