drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rk_fb.h>
  27 #include "rk32_dp.h"
  28 #include "../../../arch/arm/mach-rockchip/iomap.h"
  29 #include "../../../arch/arm/mach-rockchip/grf.h"
  30
  31 #if defined(CONFIG_OF)
  32 #include <linux/of.h>
  33 #endif
  34
  35 /*#define BIST_MODE*/
  36
  37 static int rk32_edp_init_edp(struct rk32_edp *edp)
  38 {
  39         rk32_edp_reset(edp);
  40         rk32_edp_init_analog_param(edp);
  41         rk32_edp_init_interrupt(edp);
  42
  43         rk32_edp_enable_sw_function(edp);
  44
  45         rk32_edp_init_analog_func(edp);
  46
  47         rk32_edp_init_hpd(edp);
  48         rk32_edp_init_aux(edp);
  49
  50         return 0;
  51 }
  52
  53 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  54 {
  55         int timeout_loop = 0;
  56
  57         rk32_edp_init_hpd(edp);
  58
  59         udelay(200);
  60
  61         while (rk32_edp_get_plug_in_status(edp) != 0) {
  62                 timeout_loop++;
  63                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  64                         dev_err(edp->dev, "failed to get hpd plug status\n");
  65                         return -ETIMEDOUT;
  66                 }
  67                 udelay(10);
  68         }
  69
  70         return 0;
  71 }
  72
  73 static unsigned char rk32_edp_calc_edid_check_sum(unsigned char *edid_data)
  74 {
  75         int i;
  76         unsigned char sum = 0;
  77
  78         for (i = 0; i < EDID_BLOCK_LENGTH; i++)
  79                 sum = sum + edid_data[i];
  80
  81         return sum;
  82 }
  83
  84 static int rk32_edp_read_edid(struct rk32_edp *edp)
  85 {
  86         unsigned char edid[EDID_BLOCK_LENGTH * 2];
  87         unsigned int extend_block = 0;
  88         unsigned char sum;
  89         unsigned char test_vector;
  90         int retval;
  91
  92         /*
  93          * EDID device address is 0x50.
  94          * However, if necessary, you must have set upper address
  95          * into E-EDID in I2C device, 0x30.
  96          */
  97
  98         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  99         retval = rk32_edp_read_byte_from_i2c(edp, I2C_EDID_DEVICE_ADDR,
 100                                 EDID_EXTENSION_FLAG,
 101                                 &extend_block);
 102         if (retval < 0) {
 103                 dev_err(edp->dev, "EDID extension flag failed!\n");
 104                 return -EIO;
 105         }
 106
 107         if (extend_block > 0) {
 108                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 109
 110                 /* Read EDID data */
 111                 retval = rk32_edp_read_bytes_from_i2c(edp, I2C_EDID_DEVICE_ADDR,
 112                                                 EDID_HEADER_PATTERN,
 113                                                 EDID_BLOCK_LENGTH,
 114                                                 &edid[EDID_HEADER_PATTERN]);
 115                 if (retval != 0) {
 116                         dev_err(edp->dev, "EDID Read failed!\n");
 117                         return -EIO;
 118                 }
 119                 sum = rk32_edp_calc_edid_check_sum(edid);
 120                 if (sum != 0) {
 121                         dev_warn(edp->dev, "EDID bad checksum!\n");
 122                         return 0;
 123                 }
 124
 125                 /* Read additional EDID data */
 126                 retval = rk32_edp_read_bytes_from_i2c(edp,
 127                                 I2C_EDID_DEVICE_ADDR,
 128                                 EDID_BLOCK_LENGTH,
 129                                 EDID_BLOCK_LENGTH,
 130                                 &edid[EDID_BLOCK_LENGTH]);
 131                 if (retval != 0) {
 132                         dev_err(edp->dev, "EDID Read failed!\n");
 133                         return -EIO;
 134                 }
 135                 sum = rk32_edp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
 136                 if (sum != 0) {
 137                         dev_warn(edp->dev, "EDID bad checksum!\n");
 138                         return 0;
 139                 }
 140
 141                 retval = rk32_edp_read_byte_from_dpcd(edp,
 142                                 DPCD_ADDR_TEST_REQUEST,
 143                                 &test_vector);
 144                 if (retval < 0) {
 145                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 146                         return retval;
 147                 }
 148
 149                 if (test_vector & DPCD_TEST_EDID_READ) {
 150                         retval = rk32_edp_write_byte_to_dpcd(edp,
 151                                         DPCD_ADDR_TEST_EDID_CHECKSUM,
 152                                         edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
 153                         if (retval < 0) {
 154                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 155                                 return retval;
 156                         }
 157                         retval = rk32_edp_write_byte_to_dpcd(edp,
 158                                         DPCD_ADDR_TEST_RESPONSE,
 159                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 160                         if (retval < 0) {
 161                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 162                                 return retval;
 163                         }
 164                 }
 165         } else {
 166                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 167
 168                 /* Read EDID data */
 169                 retval = rk32_edp_read_bytes_from_i2c(edp,
 170                                 I2C_EDID_DEVICE_ADDR,
 171                                 EDID_HEADER_PATTERN,
 172                                 EDID_BLOCK_LENGTH,
 173                                 &edid[EDID_HEADER_PATTERN]);
 174                 if (retval != 0) {
 175                         dev_err(edp->dev, "EDID Read failed!\n");
 176                         return -EIO;
 177                 }
 178                 sum = rk32_edp_calc_edid_check_sum(edid);
 179                 if (sum != 0) {
 180                         dev_warn(edp->dev, "EDID bad checksum!\n");
 181                         return 0;
 182                 }
 183
 184                 retval = rk32_edp_read_byte_from_dpcd(edp,
 185                                 DPCD_ADDR_TEST_REQUEST,
 186                                 &test_vector);
 187                 if (retval < 0) {
 188                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 189                         return retval;
 190                 }
 191
 192                 if (test_vector & DPCD_TEST_EDID_READ) {
 193                         retval = rk32_edp_write_byte_to_dpcd(edp,
 194                                         DPCD_ADDR_TEST_EDID_CHECKSUM,
 195                                         edid[EDID_CHECKSUM]);
 196                         if (retval < 0) {
 197                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 198                                 return retval;
 199                         }
 200                         retval = rk32_edp_write_byte_to_dpcd(edp,
 201                                         DPCD_ADDR_TEST_RESPONSE,
 202                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 203                         if (retval < 0) {
 204                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 205                                 return retval;
 206                         }
 207                 }
 208         }
 209
 210         dev_err(edp->dev, "EDID Read success!\n");
 211         return 0;
 212 }
 213
 214 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 215 {
 216         u8 buf[12];
 217         int i;
 218         int retval;
 219
 220         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 221         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_ADDR_DPCD_REV,
 222                                         12, buf);
 223         if (retval < 0)
 224                 return retval;
 225
 226         /* Read EDID */
 227         for (i = 0; i < 3; i++) {
 228                 retval = rk32_edp_read_edid(edp);
 229                 if (retval == 0)
 230                         break;
 231         }
 232
 233         return retval;
 234 }
 235
 236 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 237                                                 bool enable)
 238 {
 239         u8 data;
 240         int retval;
 241
 242         retval = rk32_edp_read_byte_from_dpcd(edp,
 243                         DPCD_ADDR_LANE_COUNT_SET, &data);
 244         if (retval < 0)
 245                 return retval;
 246
 247         if (enable) {
 248                 retval = rk32_edp_write_byte_to_dpcd(edp,
 249                                 DPCD_ADDR_LANE_COUNT_SET,
 250                                 DPCD_ENHANCED_FRAME_EN |
 251                                 DPCD_LANE_COUNT_SET(data));
 252         } else {
 253                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 254                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 255
 256                 retval = rk32_edp_write_byte_to_dpcd(edp,
 257                                 DPCD_ADDR_LANE_COUNT_SET,
 258                                 DPCD_LANE_COUNT_SET(data));
 259         }
 260
 261         return retval;
 262 }
 263
 264 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 265 {
 266         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 267         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 268
 269         if (enable) {
 270                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 271                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 272         } else {
 273                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 274         }*/
 275 }
 276
 277 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 278 {
 279         u8 data;
 280         int retval;
 281
 282         retval = rk32_edp_read_byte_from_dpcd(edp,
 283                         DPCD_ADDR_MAX_LANE_COUNT, &data);
 284         if (retval < 0)
 285                 return retval;
 286
 287         return DPCD_ENHANCED_FRAME_CAP(data);
 288 }
 289
 290 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 291 {
 292         /*rk32_edp_write_byte_to_dpcd(edp,
 293                         DPCD_ADDR_USER_DEFINED1, 0);
 294         rk32_edp_write_byte_to_dpcd(edp,
 295                         DPCD_ADDR_USER_DEFINED2, 0x83);
 296         rk32_edp_write_byte_to_dpcd(edp,
 297                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 298 }
 299
 300 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 301 {
 302         u8 data;
 303         int retval;
 304
 305         retval = rk32_edp_is_enhanced_mode_available(edp);
 306         if (retval < 0)
 307                 return retval;
 308
 309         data = (u8)retval;
 310         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 311         if (retval < 0)
 312                 return retval;
 313
 314         rk32_edp_enable_enhanced_mode(edp, data);
 315
 316         return 0;
 317 }
 318
 319 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 320 {
 321         int retval;
 322
 323         rk32_edp_set_training_pattern(edp, DP_NONE);
 324
 325         retval = rk32_edp_write_byte_to_dpcd(edp,
 326                         DPCD_ADDR_TRAINING_PATTERN_SET,
 327                         DPCD_TRAINING_PATTERN_DISABLED);
 328         if (retval < 0)
 329                 return retval;
 330
 331         return 0;
 332 }
 333
 334 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 335                                         int pre_emphasis, int lane)
 336 {
 337         switch (lane) {
 338         case 0:
 339                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 340                 break;
 341         case 1:
 342                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 343                 break;
 344
 345         case 2:
 346                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 347                 break;
 348
 349         case 3:
 350                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 351                 break;
 352         }
 353 }
 354
 355 static int rk32_edp_link_start(struct rk32_edp *edp)
 356 {
 357         u8 buf[4];
 358         int lane;
 359         int lane_count;
 360         int retval;
 361
 362         lane_count = edp->link_train.lane_count;
 363
 364         edp->link_train.lt_state = LT_CLK_RECOVERY;
 365         edp->link_train.eq_loop = 0;
 366
 367         for (lane = 0; lane < lane_count; lane++)
 368                 edp->link_train.cr_loop[lane] = 0;
 369
 370         /* Set sink to D0 (Sink Not Ready) mode. */
 371         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_SINK_POWER_STATE,
 372                                 DPCD_SET_POWER_STATE_D0);
 373         if (retval < 0) {
 374                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 375                 return retval;
 376         }
 377
 378         /* Set link rate and count as you want to establish*/
 379         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 380         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 381
 382         /* Setup RX configuration */
 383         buf[0] = edp->link_train.link_rate;
 384         buf[1] = edp->link_train.lane_count;
 385         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_ADDR_LINK_BW_SET,
 386                                         2, buf);
 387         if (retval < 0) {
 388                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 389                 return retval;
 390         }
 391
 392         /* Set TX pre-emphasis to level1 */
 393         for (lane = 0; lane < lane_count; lane++)
 394                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 395                         PRE_EMPHASIS_LEVEL_1, lane);
 396
 397         /* Set training pattern 1 */
 398         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 399
 400         /* Set RX training pattern */
 401         retval = rk32_edp_write_byte_to_dpcd(edp,
 402                         DPCD_ADDR_TRAINING_PATTERN_SET,
 403                         DPCD_SCRAMBLING_DISABLED |
 404                         DPCD_TRAINING_PATTERN_1);
 405         if (retval < 0) {
 406                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 407                 return retval;
 408         }
 409
 410         for (lane = 0; lane < lane_count; lane++)
 411                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 412                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 413         retval = rk32_edp_write_bytes_to_dpcd(edp,
 414                         DPCD_ADDR_TRAINING_LANE0_SET,
 415                         lane_count, buf);
 416         if (retval < 0) {
 417                 dev_err(edp->dev, "failed to set training lane!\n");
 418                 return retval;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 425 {
 426         int shift = (lane & 1) * 4;
 427         u8 link_value = link_status[lane>>1];
 428
 429         return (link_value >> shift) & 0xf;
 430 }
 431
 432 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 433 {
 434         int lane;
 435         u8 lane_status;
 436
 437         for (lane = 0; lane < lane_count; lane++) {
 438                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 439                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 440                         return -EINVAL;
 441         }
 442         return 0;
 443 }
 444
 445 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 446 {
 447         int lane;
 448         u8 lane_align;
 449         u8 lane_status;
 450
 451         lane_align = link_align[2];
 452         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 453                 return -EINVAL;
 454
 455         for (lane = 0; lane < lane_count; lane++) {
 456                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 457                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 458                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 459                         return -EINVAL;
 460         }
 461
 462         return 0;
 463 }
 464
 465 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 466                                                         int lane)
 467 {
 468         int shift = (lane & 1) * 4;
 469         u8 link_value = adjust_request[lane>>1];
 470
 471         return (link_value >> shift) & 0x3;
 472 }
 473
 474 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 475                                         u8 adjust_request[2],
 476                                         int lane)
 477 {
 478         int shift = (lane & 1) * 4;
 479         u8 link_value = adjust_request[lane>>1];
 480
 481         return ((link_value >> shift) & 0xc) >> 2;
 482 }
 483
 484 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 485                                         u8 training_lane_set, int lane)
 486 {
 487         switch (lane) {
 488         case 0:
 489                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 490                 break;
 491         case 1:
 492                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 493                 break;
 494
 495         case 2:
 496                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 497                 break;
 498
 499         case 3:
 500                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 501                 break;
 502         }
 503 }
 504
 505 static unsigned int rk32_edp_get_lane_link_training(
 506                                 struct rk32_edp *edp,
 507                                 int lane)
 508 {
 509         u32 reg;
 510
 511         switch (lane) {
 512         case 0:
 513                 reg = rk32_edp_get_lane0_link_training(edp);
 514                 break;
 515         case 1:
 516                 reg = rk32_edp_get_lane1_link_training(edp);
 517                 break;
 518         case 2:
 519                 reg = rk32_edp_get_lane2_link_training(edp);
 520                 break;
 521         case 3:
 522                 reg = rk32_edp_get_lane3_link_training(edp);
 523                 break;
 524         }
 525
 526         return reg;
 527 }
 528
 529 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 530 {
 531         rk32_edp_training_pattern_dis(edp);
 532
 533         edp->link_train.lt_state = FAILED;
 534 }
 535
 536 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 537 {
 538         u8 link_status[2];
 539         int lane;
 540         int lane_count;
 541
 542         u8 adjust_request[2];
 543         u8 voltage_swing;
 544         u8 pre_emphasis;
 545         u8 training_lane;
 546         int retval;
 547
 548         udelay(100);
 549
 550         lane_count = edp->link_train.lane_count;
 551
 552         retval = rk32_edp_read_bytes_from_dpcd(edp,
 553                         DPCD_ADDR_LANE0_1_STATUS,
 554                         2, link_status);
 555         if (retval < 0) {
 556                 dev_err(edp->dev, "failed to read lane status!\n");
 557                 return retval;
 558         }
 559
 560         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 561                 /* set training pattern 2 for EQ */
 562                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 563
 564                 for (lane = 0; lane < lane_count; lane++) {
 565                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 566                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 567                                         2, adjust_request);
 568                         if (retval < 0) {
 569                                 dev_err(edp->dev, "failed to read adjust request!\n");
 570                                 return retval;
 571                         }
 572
 573                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 574                                                         adjust_request, lane);
 575                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 576                                                         adjust_request, lane);
 577                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 578                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 579
 580                         if (voltage_swing == VOLTAGE_LEVEL_3)
 581                                 training_lane |= DPCD_MAX_SWING_REACHED;
 582                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 583                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 584
 585                         edp->link_train.training_lane[lane] = training_lane;
 586
 587                         rk32_edp_set_lane_link_training(edp,
 588                                 edp->link_train.training_lane[lane],
 589                                 lane);
 590                 }
 591
 592                 retval = rk32_edp_write_byte_to_dpcd(edp,
 593                                 DPCD_ADDR_TRAINING_PATTERN_SET,
 594                                 DPCD_SCRAMBLING_DISABLED |
 595                                 DPCD_TRAINING_PATTERN_2);
 596                 if (retval < 0) {
 597                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 598                         return retval;
 599                 }
 600
 601                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 602                                 DPCD_ADDR_TRAINING_LANE0_SET,
 603                                 lane_count,
 604                                 edp->link_train.training_lane);
 605                 if (retval < 0) {
 606                         dev_err(edp->dev, "failed to set training lane!\n");
 607                         return retval;
 608                 }
 609
 610                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 611                 edp->link_train.lt_state = LT_EQ_TRAINING;
 612         } else {
 613                 for (lane = 0; lane < lane_count; lane++) {
 614                         training_lane = rk32_edp_get_lane_link_training(
 615                                                         edp, lane);
 616                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 617                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 618                                         2, adjust_request);
 619                         if (retval < 0) {
 620                                 dev_err(edp->dev, "failed to read adjust request!\n");
 621                                 return retval;
 622                         }
 623
 624                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 625                                                         adjust_request, lane);
 626                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 627                                                         adjust_request, lane);
 628
 629                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 630                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 631                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 632                                 goto reduce_link_rate;
 633                         }
 634
 635                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 636                                         voltage_swing) &&
 637                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 638                                         pre_emphasis)) {
 639                                 edp->link_train.cr_loop[lane]++;
 640                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 641                                         dev_err(edp->dev, "CR Max loop\n");
 642                                         goto reduce_link_rate;
 643                                 }
 644                         }
 645
 646                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 647                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 648
 649                         if (voltage_swing == VOLTAGE_LEVEL_3)
 650                                 training_lane |= DPCD_MAX_SWING_REACHED;
 651                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 652                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 653
 654                         edp->link_train.training_lane[lane] = training_lane;
 655
 656                         rk32_edp_set_lane_link_training(edp,
 657                                 edp->link_train.training_lane[lane], lane);
 658                 }
 659
 660                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 661                                 DPCD_ADDR_TRAINING_LANE0_SET,
 662                                 lane_count,
 663                                 edp->link_train.training_lane);
 664                 if (retval < 0) {
 665                         dev_err(edp->dev, "failed to set training lane!\n");
 666                         return retval;
 667                 }
 668         }
 669
 670         return 0;
 671
 672 reduce_link_rate:
 673         rk32_edp_reduce_link_rate(edp);
 674         return -EIO;
 675 }
 676
 677 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 678 {
 679         u8 link_status[2];
 680         u8 link_align[3];
 681         int lane;
 682         int lane_count;
 683         u32 reg;
 684
 685         u8 adjust_request[2];
 686         u8 voltage_swing;
 687         u8 pre_emphasis;
 688         u8 training_lane;
 689         int retval;
 690
 691         udelay(400);
 692
 693         lane_count = edp->link_train.lane_count;
 694
 695         retval = rk32_edp_read_bytes_from_dpcd(edp,
 696                         DPCD_ADDR_LANE0_1_STATUS,
 697                         2, link_status);
 698         if (retval < 0) {
 699                 dev_err(edp->dev, "failed to read lane status!\n");
 700                 return retval;
 701         }
 702
 703         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 704                 link_align[0] = link_status[0];
 705                 link_align[1] = link_status[1];
 706
 707                 retval = rk32_edp_read_byte_from_dpcd(edp,
 708                                 DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED,
 709                                 &link_align[2]);
 710                 if (retval < 0) {
 711                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 712                         return retval;
 713                 }
 714
 715                 for (lane = 0; lane < lane_count; lane++) {
 716                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 717                                         DPCD_ADDR_ADJUST_REQUEST_LANE0_1,
 718                                         2, adjust_request);
 719                         if (retval < 0) {
 720                                 dev_err(edp->dev, "failed to read adjust request!\n");
 721                                 return retval;
 722                         }
 723
 724                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 725                                                         adjust_request, lane);
 726                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 727                                                         adjust_request, lane);
 728                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 729                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 730
 731                         if (voltage_swing == VOLTAGE_LEVEL_3)
 732                                 training_lane |= DPCD_MAX_SWING_REACHED;
 733                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 734                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 735
 736                         edp->link_train.training_lane[lane] = training_lane;
 737                 }
 738
 739                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 740                         /* traing pattern Set to Normal */
 741                         retval = rk32_edp_training_pattern_dis(edp);
 742                         if (retval < 0) {
 743                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 744                                 return retval;
 745                         }
 746
 747                         dev_info(edp->dev, "Link Training success!\n");
 748
 749                         rk32_edp_get_link_bandwidth(edp, &reg);
 750                         edp->link_train.link_rate = reg;
 751                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 752                                 edp->link_train.link_rate);
 753
 754                         rk32_edp_get_lane_count(edp, &reg);
 755                         edp->link_train.lane_count = reg;
 756                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 757                                 edp->link_train.lane_count);
 758
 759                         edp->link_train.lt_state = FINISHED;
 760                 } else {
 761                         /* not all locked */
 762                         edp->link_train.eq_loop++;
 763
 764                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 765                                 dev_err(edp->dev, "EQ Max loop\n");
 766                                 goto reduce_link_rate;
 767                         }
 768
 769                         for (lane = 0; lane < lane_count; lane++)
 770                                 rk32_edp_set_lane_link_training(edp,
 771                                         edp->link_train.training_lane[lane],
 772                                         lane);
 773
 774                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 775                                         DPCD_ADDR_TRAINING_LANE0_SET,
 776                                         lane_count,
 777                                         edp->link_train.training_lane);
 778                         if (retval < 0) {
 779                                 dev_err(edp->dev, "failed to set training lane!\n");
 780                                 return retval;
 781                         }
 782                 }
 783         } else {
 784                 goto reduce_link_rate;
 785         }
 786
 787         return 0;
 788
 789 reduce_link_rate:
 790         rk32_edp_reduce_link_rate(edp);
 791         return -EIO;
 792 }
 793
 794 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 795                                         u8 *bandwidth)
 796 {
 797         u8 data;
 798         int retval;
 799
 800         /*
 801          * For DP rev.1.1, Maximum link rate of Main Link lanes
 802          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 803          */
 804         retval = rk32_edp_read_byte_from_dpcd(edp,
 805                         DPCD_ADDR_MAX_LINK_RATE, &data);
 806         if (retval < 0)
 807                 return retval;
 808
 809         *bandwidth = data;
 810         return 0;
 811 }
 812
 813 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 814                                         u8 *lane_count)
 815 {
 816         u8 data;
 817         int retval;
 818
 819         /*
 820          * For DP rev.1.1, Maximum number of Main Link lanes
 821          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 822          */
 823         retval = rk32_edp_read_byte_from_dpcd(edp,
 824                         DPCD_ADDR_MAX_LANE_COUNT, &data);
 825         if (retval < 0)
 826                 return retval;
 827
 828         *lane_count = DPCD_MAX_LANE_COUNT(data);
 829         return 0;
 830 }
 831
 832 static int rk32_edp_init_training(struct rk32_edp *edp,
 833                         enum link_lane_count_type max_lane,
 834                         u32 max_rate)
 835 {
 836         int retval;
 837
 838         /*
 839          * MACRO_RST must be applied after the PLL_LOCK to avoid
 840          * the DP inter pair skew issue for at least 10 us
 841          */
 842         rk32_edp_reset_macro(edp);
 843
 844
 845         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 846         if (retval < 0)
 847                 return retval;
 848
 849         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 850         if (retval < 0)
 851                 return retval;
 852
 853         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 854            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 855                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 856                         edp->link_train.link_rate);
 857                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 858         }
 859
 860         if (edp->link_train.lane_count == 0) {
 861                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 862                         edp->link_train.lane_count);
 863                 edp->link_train.lane_count = (u8)LANE_CNT1;
 864         }
 865
 866
 867         if (edp->link_train.lane_count > max_lane)
 868                 edp->link_train.lane_count = max_lane;
 869         if (edp->link_train.link_rate > max_rate)
 870                 edp->link_train.link_rate = max_rate;
 871
 872
 873         rk32_edp_analog_power_ctr(edp, 1);
 874
 875         return 0;
 876 }
 877
 878 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 879 {
 880         int retval = 0;
 881         int training_finished = 0;
 882
 883         edp->link_train.lt_state = LT_START;
 884
 885         /* Process here */
 886         while (!training_finished) {
 887                 switch (edp->link_train.lt_state) {
 888                 case LT_START:
 889                         retval = rk32_edp_link_start(edp);
 890                         if (retval)
 891                                 dev_err(edp->dev, "LT Start failed\n");
 892                         break;
 893                 case LT_CLK_RECOVERY:
 894                         retval = rk32_edp_process_clock_recovery(edp);
 895                         if (retval)
 896                                 dev_err(edp->dev, "LT CR failed\n");
 897                         break;
 898                 case LT_EQ_TRAINING:
 899                         retval = rk32_edp_process_equalizer_training(edp);
 900                         if (retval)
 901                                 dev_err(edp->dev, "LT EQ failed\n");
 902                         break;
 903                 case FINISHED:
 904                         training_finished = 1;
 905                         break;
 906                 case FAILED:
 907                         return -EREMOTEIO;
 908                 }
 909         }
 910
 911         return retval;
 912 }
 913
 914 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 915                                 u32 count,
 916                                 u32 bwtype)
 917 {
 918         int retval;
 919
 920         retval = rk32_edp_init_training(edp, count, bwtype);
 921         if (retval < 0)
 922                 dev_err(edp->dev, "DP LT init failed!\n");
 923
 924         retval = rk32_edp_sw_link_training(edp);
 925         if (retval < 0)
 926                 dev_err(edp->dev, "DP LT failed!\n");
 927
 928         return retval;
 929 }
 930
 931 static int rk32_edp_config_video(struct rk32_edp *edp,
 932                         struct video_info *video_info)
 933 {
 934         int retval = 0;
 935         int timeout_loop = 0;
 936         int done_count = 0;
 937
 938         rk32_edp_config_video_slave_mode(edp, video_info);
 939
 940         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 941                         video_info->color_space,
 942                         video_info->dynamic_range,
 943                         video_info->ycbcr_coeff);
 944
 945         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 946                 dev_err(edp->dev, "PLL is not locked yet.\n");
 947                 return -EINVAL;
 948         }
 949
 950         for (;;) {
 951                 timeout_loop++;
 952                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 953                         break;
 954                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 955                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 956                         return -ETIMEDOUT;
 957                 }
 958
 959                 usleep_range(1, 1);
 960         }
 961
 962         /* Set to use the register calculated M/N video */
 963         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 964
 965         /* For video bist, Video timing must be generated by register */
 966         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 967
 968         /* Disable video mute */
 969         rk32_edp_enable_video_mute(edp, 0);
 970
 971         /* Configure video slave mode */
 972         rk32_edp_enable_video_master(edp, 0);
 973
 974         /* Enable video */
 975         rk32_edp_start_video(edp);
 976
 977         timeout_loop = 0;
 978
 979         for (;;) {
 980                 timeout_loop++;
 981                 if (rk32_edp_is_video_stream_on(edp) == 0) {
 982                         done_count++;
 983                         if (done_count > 10)
 984                                 break;
 985                 } else if (done_count) {
 986                         done_count = 0;
 987                 }
 988                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 989                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 990                         return -ETIMEDOUT;
 991                 }
 992
 993                 usleep_range(1000, 1000);
 994         }
 995
 996         if (retval != 0)
 997                 dev_err(edp->dev, "Video stream is not detected!\n");
 998
 999         return retval;
1000 }
1001
1002 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1003 {
1004         u8 data;
1005         int retval;
1006
1007         if (enable) {
1008                 rk32_edp_enable_scrambling(edp);
1009
1010                 retval = rk32_edp_read_byte_from_dpcd(edp,
1011                                 DPCD_ADDR_TRAINING_PATTERN_SET,
1012                                 &data);
1013                 if (retval < 0)
1014                         return retval;
1015
1016                 retval = rk32_edp_write_byte_to_dpcd(edp,
1017                                 DPCD_ADDR_TRAINING_PATTERN_SET,
1018                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1019                 if (retval < 0)
1020                         return retval;
1021         } else {
1022                 rk32_edp_disable_scrambling(edp);
1023
1024                 retval = rk32_edp_read_byte_from_dpcd(edp,
1025                                 DPCD_ADDR_TRAINING_PATTERN_SET,
1026                                 &data);
1027                 if (retval < 0)
1028                         return retval;
1029
1030                 retval = rk32_edp_write_byte_to_dpcd(edp,
1031                                 DPCD_ADDR_TRAINING_PATTERN_SET,
1032                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1033                 if (retval < 0)
1034                         return retval;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static irqreturn_t rk32_edp_irq_handler(int irq, void *arg)
1041 {
1042         struct rk32_edp *edp = arg;
1043
1044         dev_err(edp->dev, "rk32_edp_irq_handler\n");
1045         return IRQ_HANDLED;
1046 }
1047
1048 static int rk32_edp_enable(struct rk32_edp *edp)
1049 {
1050         int ret = 0;
1051         int retry = 0;
1052
1053         if (edp->enabled)
1054                 goto out;
1055
1056         edp->enabled = 1;
1057         clk_prepare_enable(edp->clk_edp);
1058         clk_prepare_enable(edp->clk_24m);
1059 edp_phy_init:
1060
1061
1062         rk32_edp_init_edp(edp);
1063
1064
1065         ret = rk32_edp_handle_edid(edp);
1066         if (ret) {
1067                 dev_err(edp->dev, "unable to handle edid\n");
1068                 goto out;
1069         }
1070
1071         rk32_edp_disable_rx_zmux(edp);
1072
1073
1074         ret = rk32_edp_enable_scramble(edp, 0);
1075         if (ret) {
1076                 dev_err(edp->dev, "unable to set scramble\n");
1077                 goto out;
1078         }
1079
1080         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1081         if (ret) {
1082                 dev_err(edp->dev, "unable to set enhanced mode\n");
1083                 goto out;
1084         }
1085         rk32_edp_enable_enhanced_mode(edp, 0);
1086
1087
1088         rk32_edp_rx_control(edp,0);
1089
1090        /* Link Training */
1091         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1092         if (ret) {
1093                 dev_err(edp->dev, "unable to do link train\n");
1094                 goto out;
1095         }
1096
1097         /* Rx data enable */
1098         rk32_edp_rx_control(edp,1);
1099
1100         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1101         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1102
1103         rk32_edp_init_video(edp);
1104         ret = rk32_edp_config_video(edp, &edp->video_info);
1105         if (ret) {
1106                 dev_err(edp->dev, "unable to config video\n");
1107                 goto out;
1108         }
1109
1110         return 0;
1111
1112 out:
1113
1114         if (retry < 3) {
1115                 retry++;
1116                 goto edp_phy_init;
1117         }
1118
1119         dev_err(edp->dev, "DP LT exceeds max retry count");
1120
1121         return ret;
1122 }
1123
1124 static void rk32_edp_disable(struct rk32_edp *edp)
1125 {
1126         if (!edp->enabled)
1127                 return ;
1128
1129         edp->enabled = 0;
1130
1131         rk32_edp_reset(edp);
1132         rk32_edp_analog_power_ctr(edp, 0);
1133
1134         clk_disable(edp->clk_24m);
1135         clk_disable(edp->clk_edp);
1136 }
1137
1138
1139
1140 static void rk32_edp_init(struct rk32_edp *edp)
1141 {
1142
1143         rk32_edp_enable(edp);
1144 }
1145 static int rk32_edp_probe(struct platform_device *pdev)
1146 {
1147         struct rk32_edp *edp;
1148         struct resource *res;
1149         struct device_node *np = pdev->dev.of_node;
1150         u32 version;
1151
1152         if (!np) {
1153                 dev_err(&pdev->dev, "Missing device tree node.\n");
1154                 return -EINVAL;
1155         }
1156
1157         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1158         if (!edp) {
1159                 dev_err(&pdev->dev, "no memory for state\n");
1160                 return -ENOMEM;
1161         }
1162         edp->dev = &pdev->dev;
1163         edp->video_info.h_sync_polarity = 0;
1164         edp->video_info.v_sync_polarity = 0;
1165         edp->video_info.interlaced      = 0;
1166         edp->video_info.color_space     = CS_RGB;
1167         edp->video_info.dynamic_range   = VESA;
1168         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1169         edp->video_info.color_depth     = COLOR_8;
1170
1171         edp->video_info.link_rate       = LINK_RATE_2_70GBPS;
1172         edp->video_info.lane_count      = LANE_CNT4;
1173
1174         platform_set_drvdata(pdev, edp);
1175         dev_set_name(edp->dev, "rk32-edp");
1176         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1177         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1178         if (IS_ERR(edp->regs)) {
1179                 dev_err(&pdev->dev, "ioremap reg failed\n");
1180                 return PTR_ERR(edp->regs);
1181         }
1182         version = readl_relaxed(edp->regs + DP_VERSION);
1183         dev_info(&pdev->dev, "edp version:0x%08x\n", version);
1184         rk32_edp_init(edp);
1185         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1186
1187         return 0;
1188 }
1189
1190 static void rk32_edp_shutdown(struct platform_device *pdev)
1191 {
1192
1193 }
1194
1195 #if defined(CONFIG_OF)
1196 static const struct of_device_id rk32_edp_dt_ids[] = {
1197         {.compatible = "rockchip, rk32-edp",},
1198         {}
1199 };
1200
1201 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1202 #endif
1203
1204 static struct platform_driver rk32_edp_driver = {
1205         .probe = rk32_edp_probe,
1206         .driver = {
1207                    .name = "rk32-edp",
1208                    .owner = THIS_MODULE,
1209 #if defined(CONFIG_OF)
1210                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1211 #endif
1212         },
1213         .shutdown = rk32_edp_shutdown,
1214 };
1215
1216 static int __init rk32_edp_module_init(void)
1217 {
1218         return platform_driver_register(&rk32_edp_driver);
1219 }
1220
1221 static void __exit rk32_edp_module_exit(void)
1222 {
1223
1224 }
1225
1226 fs_initcall(rk32_edp_module_init);
1227 module_exit(rk32_edp_module_exit);