drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 //#define EDP_BIST_MODE
  35
  36 static struct rk32_edp *rk32_edp;
  37 static int lcdc_probed = 0;
  38 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  39 {
  40         if (!edp->clk_on) {
  41                 clk_enable(edp->pclk);
  42                 clk_enable(edp->clk_edp);
  43                 clk_enable(edp->clk_24m);
  44                 edp->clk_on = true;
  45         }
  46
  47         return 0;
  48 }
  49
  50 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  51 {
  52         if (edp->clk_on) {
  53                 clk_disable(edp->pclk);
  54                 clk_disable(edp->clk_edp);
  55                 clk_disable(edp->clk_24m);
  56                 edp->clk_on = false;
  57         }
  58
  59         return 0;
  60 }
  61
  62 static int rk32_edp_pre_init(void)
  63 {
  64         u32 val;
  65         val = GRF_EDP_REF_CLK_SEL_INTER |
  66                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  67         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  68
  69         val = 0x80008000;
  70         writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
  71
  72         val = 0x80008000;
  73         writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  74         udelay(1);
  75         val = 0x80000000;
  76         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  77         udelay(1);
  78         return 0;
  79 }
  80
  81 static int rk32_edp_init_edp(struct rk32_edp *edp)
  82 {
  83         struct rk_screen *screen = &edp->screen;
  84         u32 val = 0;
  85
  86         screen->lcdc_id = 1;
  87         if (screen->lcdc_id == 1)  /*select lcdc*/
  88                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  89         else
  90                 val = EDP_SEL_VOP_LIT << 16;
  91         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  92
  93
  94         rk32_edp_reset(edp);
  95         rk32_edp_init_refclk(edp);
  96         rk32_edp_init_interrupt(edp);
  97
  98         rk32_edp_enable_sw_function(edp);
  99
 100         rk32_edp_init_analog_func(edp);
 101
 102         rk32_edp_init_hpd(edp);
 103         rk32_edp_init_aux(edp);
 104
 105         return 0;
 106 }
 107
 108 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 109 {
 110         int timeout_loop = 0;
 111
 112         rk32_edp_init_hpd(edp);
 113
 114         udelay(200);
 115
 116         while (rk32_edp_get_plug_in_status(edp) != 0) {
 117                 timeout_loop++;
 118                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 119                         dev_err(edp->dev, "failed to get hpd plug status\n");
 120                         return -ETIMEDOUT;
 121                 }
 122                 udelay(10);
 123         }
 124
 125         return 0;
 126 }
 127
 128 static int rk32_edp_read_edid(struct rk32_edp *edp)
 129 {
 130         unsigned char edid[EDID_LENGTH * 2];
 131         unsigned int extend_block = 0;
 132         unsigned char sum;
 133         unsigned char test_vector;
 134         int retval;
 135
 136         /*
 137          * EDID device address is 0x50.
 138          * However, if necessary, you must have set upper address
 139          * into E-EDID in I2C device, 0x30.
 140          */
 141
 142         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 143         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 144                                                 &extend_block);
 145         if (retval < 0) {
 146                 dev_err(edp->dev, "EDID extension flag failed!\n");
 147                 return -EIO;
 148         }
 149
 150         if (extend_block > 0) {
 151                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 152
 153                 /* Read EDID data */
 154                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 155                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 156                 if (retval != 0) {
 157                         dev_err(edp->dev, "EDID Read failed!\n");
 158                         return -EIO;
 159                 }
 160                 sum = edp_calc_edid_check_sum(edid);
 161                 if (sum != 0) {
 162                         dev_warn(edp->dev, "EDID bad checksum!\n");
 163                         return 0;
 164                 }
 165
 166                 /* Read additional EDID data */
 167                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 168                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 169                 if (retval != 0) {
 170                         dev_err(edp->dev, "EDID Read failed!\n");
 171                         return -EIO;
 172                 }
 173                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 174                 if (sum != 0) {
 175                         dev_warn(edp->dev, "EDID bad checksum!\n");
 176                         return 0;
 177                 }
 178
 179                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 180                                         &test_vector);
 181                 if (retval < 0) {
 182                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 183                         return retval;
 184                 }
 185
 186                 if (test_vector & DPCD_TEST_EDID_READ) {
 187                         retval = rk32_edp_write_byte_to_dpcd(edp,
 188                                         DPCD_TEST_EDID_CHECKSUM,
 189                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 190                         if (retval < 0) {
 191                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 192                                 return retval;
 193                         }
 194                         retval = rk32_edp_write_byte_to_dpcd(edp,
 195                                         DPCD_TEST_RESPONSE,
 196                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 197                         if (retval < 0) {
 198                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 199                                 return retval;
 200                         }
 201                 }
 202         } else {
 203                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 204
 205                 /* Read EDID data */
 206                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 207                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 208                 if (retval != 0) {
 209                         dev_err(edp->dev, "EDID Read failed!\n");
 210                         return -EIO;
 211                 }
 212                 sum = edp_calc_edid_check_sum(edid);
 213                 if (sum != 0) {
 214                         dev_warn(edp->dev, "EDID bad checksum!\n");
 215                         return 0;
 216                 }
 217
 218                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 219                                                 &test_vector);
 220                 if (retval < 0) {
 221                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 222                         return retval;
 223                 }
 224
 225                 if (test_vector & DPCD_TEST_EDID_READ) {
 226                         retval = rk32_edp_write_byte_to_dpcd(edp,
 227                                         DPCD_TEST_EDID_CHECKSUM,
 228                                         edid[EDID_CHECKSUM]);
 229                         if (retval < 0) {
 230                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 231                                 return retval;
 232                         }
 233                         retval = rk32_edp_write_byte_to_dpcd(edp,
 234                                         DPCD_TEST_RESPONSE,
 235                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 236                         if (retval < 0) {
 237                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 238                                 return retval;
 239                         }
 240                 }
 241         }
 242         fb_edid_to_monspecs(edid, &edp->specs);
 243         dev_err(edp->dev, "EDID Read success!\n");
 244         return 0;
 245 }
 246
 247 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 248 {
 249         u8 buf[12];
 250         int i;
 251         int retval;
 252
 253         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 254         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 255         if (retval < 0)
 256                 return retval;
 257
 258         for (i=0 ;i < 12; i++)
 259                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 260         /* Read EDID */
 261         for (i = 0; i < 3; i++) {
 262                 retval = rk32_edp_read_edid(edp);
 263                 if (retval == 0)
 264                         break;
 265         }
 266
 267         return retval;
 268 }
 269
 270 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 271                                                 bool enable)
 272 {
 273         u8 data;
 274         int retval;
 275
 276         retval = rk32_edp_read_byte_from_dpcd(edp,
 277                         DPCD_LANE_CNT_SET, &data);
 278         if (retval < 0)
 279                 return retval;
 280
 281         if (enable) {
 282                 retval = rk32_edp_write_byte_to_dpcd(edp,
 283                                 DPCD_LANE_CNT_SET,
 284                                 DPCD_ENHANCED_FRAME_EN |
 285                                 DPCD_LANE_COUNT_SET(data));
 286         } else {
 287                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 288                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 289
 290                 retval = rk32_edp_write_byte_to_dpcd(edp,
 291                                 DPCD_LANE_CNT_SET,
 292                                 DPCD_LANE_COUNT_SET(data));
 293         }
 294
 295         return retval;
 296 }
 297
 298 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 299 {
 300         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 301         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 302
 303         if (enable) {
 304                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 305                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 306         } else {
 307                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 308         }*/
 309 }
 310
 311 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 312 {
 313         u8 data;
 314         int retval;
 315
 316         retval = rk32_edp_read_byte_from_dpcd(edp,
 317                         DPCD_MAX_LANE_CNT, &data);
 318         if (retval < 0)
 319                 return retval;
 320
 321         return DPCD_ENHANCED_FRAME_CAP(data);
 322 }
 323
 324 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 325 {
 326         /*rk32_edp_write_byte_to_dpcd(edp,
 327                         DPCD_ADDR_USER_DEFINED1, 0);
 328         rk32_edp_write_byte_to_dpcd(edp,
 329                         DPCD_ADDR_USER_DEFINED2, 0x83);
 330         rk32_edp_write_byte_to_dpcd(edp,
 331                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 332 }
 333
 334 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 335 {
 336         u8 data;
 337         int retval;
 338
 339         retval = rk32_edp_is_enhanced_mode_available(edp);
 340         if (retval < 0)
 341                 return retval;
 342
 343         data = (u8)retval;
 344         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 345         if (retval < 0)
 346                 return retval;
 347
 348         rk32_edp_enable_enhanced_mode(edp, data);
 349
 350         return 0;
 351 }
 352
 353 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 354 {
 355         int retval;
 356
 357         rk32_edp_set_training_pattern(edp, DP_NONE);
 358
 359         retval = rk32_edp_write_byte_to_dpcd(edp,
 360                         DPCD_TRAINING_PATTERN_SET,
 361                         DPCD_TRAINING_PATTERN_DISABLED);
 362         if (retval < 0)
 363                 return retval;
 364
 365         return 0;
 366 }
 367
 368 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 369                                         int pre_emphasis, int lane)
 370 {
 371         switch (lane) {
 372         case 0:
 373                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 374                 break;
 375         case 1:
 376                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 377                 break;
 378
 379         case 2:
 380                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 381                 break;
 382
 383         case 3:
 384                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 385                 break;
 386         }
 387 }
 388
 389 static int rk32_edp_link_start(struct rk32_edp *edp)
 390 {
 391         u8 buf[4];
 392         int lane;
 393         int lane_count;
 394         int retval;
 395
 396         lane_count = edp->link_train.lane_count;
 397
 398         edp->link_train.lt_state = LT_CLK_RECOVERY;
 399         edp->link_train.eq_loop = 0;
 400
 401         for (lane = 0; lane < lane_count; lane++)
 402                 edp->link_train.cr_loop[lane] = 0;
 403
 404         /* Set sink to D0 (Sink Not Ready) mode. */
 405         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 406                                 DPCD_SET_POWER_STATE_D0);
 407         if (retval < 0) {
 408                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 409                 return retval;
 410         }
 411
 412         /* Set link rate and count as you want to establish*/
 413         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 414         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 415
 416         /* Setup RX configuration */
 417         buf[0] = edp->link_train.link_rate;
 418         buf[1] = edp->link_train.lane_count;
 419         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 420                                         2, buf);
 421         if (retval < 0) {
 422                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 423                 return retval;
 424         }
 425
 426         /* Set TX pre-emphasis to level1 */
 427         for (lane = 0; lane < lane_count; lane++)
 428                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 429                         PRE_EMPHASIS_LEVEL_1, lane);
 430
 431         /* Set training pattern 1 */
 432         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 433
 434         /* Set RX training pattern */
 435         retval = rk32_edp_write_byte_to_dpcd(edp,
 436                         DPCD_TRAINING_PATTERN_SET,
 437                         DPCD_SCRAMBLING_DISABLED |
 438                         DPCD_TRAINING_PATTERN_1);
 439         if (retval < 0) {
 440                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 441                 return retval;
 442         }
 443
 444         for (lane = 0; lane < lane_count; lane++)
 445                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 446                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 447         retval = rk32_edp_write_bytes_to_dpcd(edp,
 448                         DPCD_TRAINING_LANE0_SET,
 449                         lane_count, buf);
 450         if (retval < 0) {
 451                 dev_err(edp->dev, "failed to set training lane!\n");
 452                 return retval;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 459 {
 460         int shift = (lane & 1) * 4;
 461         u8 link_value = link_status[lane>>1];
 462
 463         return (link_value >> shift) & 0xf;
 464 }
 465
 466 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 467 {
 468         int lane;
 469         u8 lane_status;
 470
 471         for (lane = 0; lane < lane_count; lane++) {
 472                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 473                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 474                         return -EINVAL;
 475         }
 476         return 0;
 477 }
 478
 479 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 480 {
 481         int lane;
 482         u8 lane_align;
 483         u8 lane_status;
 484
 485         lane_align = link_align[2];
 486         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 487                 return -EINVAL;
 488
 489         for (lane = 0; lane < lane_count; lane++) {
 490                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 491                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 492                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 493                         return -EINVAL;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 500                                                         int lane)
 501 {
 502         int shift = (lane & 1) * 4;
 503         u8 link_value = adjust_request[lane>>1];
 504
 505         return (link_value >> shift) & 0x3;
 506 }
 507
 508 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 509                                         u8 adjust_request[2],
 510                                         int lane)
 511 {
 512         int shift = (lane & 1) * 4;
 513         u8 link_value = adjust_request[lane>>1];
 514
 515         return ((link_value >> shift) & 0xc) >> 2;
 516 }
 517
 518 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 519                                         u8 training_lane_set, int lane)
 520 {
 521         switch (lane) {
 522         case 0:
 523                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 524                 break;
 525         case 1:
 526                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 527                 break;
 528
 529         case 2:
 530                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 531                 break;
 532
 533         case 3:
 534                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 535                 break;
 536         }
 537 }
 538
 539 static unsigned int rk32_edp_get_lane_link_training(
 540                                 struct rk32_edp *edp,
 541                                 int lane)
 542 {
 543         u32 reg;
 544
 545         switch (lane) {
 546         case 0:
 547                 reg = rk32_edp_get_lane0_link_training(edp);
 548                 break;
 549         case 1:
 550                 reg = rk32_edp_get_lane1_link_training(edp);
 551                 break;
 552         case 2:
 553                 reg = rk32_edp_get_lane2_link_training(edp);
 554                 break;
 555         case 3:
 556                 reg = rk32_edp_get_lane3_link_training(edp);
 557                 break;
 558         }
 559
 560         return reg;
 561 }
 562
 563 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 564 {
 565         rk32_edp_training_pattern_dis(edp);
 566
 567         edp->link_train.lt_state = FAILED;
 568 }
 569
 570 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 571 {
 572         u8 link_status[2];
 573         int lane;
 574         int lane_count;
 575
 576         u8 adjust_request[2];
 577         u8 voltage_swing;
 578         u8 pre_emphasis;
 579         u8 training_lane;
 580         int retval;
 581
 582         udelay(100);
 583
 584         lane_count = edp->link_train.lane_count;
 585
 586         retval = rk32_edp_read_bytes_from_dpcd(edp,
 587                         DPCD_LANE0_1_STATUS,
 588                         2, link_status);
 589         if (retval < 0) {
 590                 dev_err(edp->dev, "failed to read lane status!\n");
 591                 return retval;
 592         }
 593
 594         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 595                 /* set training pattern 2 for EQ */
 596                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 597
 598                 for (lane = 0; lane < lane_count; lane++) {
 599                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 600                                         DPCD_ADJUST_REQUEST_LANE0_1,
 601                                         2, adjust_request);
 602                         if (retval < 0) {
 603                                 dev_err(edp->dev, "failed to read adjust request!\n");
 604                                 return retval;
 605                         }
 606
 607                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 608                                                         adjust_request, lane);
 609                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 610                                                         adjust_request, lane);
 611                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 612                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 613
 614                         if (voltage_swing == VOLTAGE_LEVEL_3)
 615                                 training_lane |= DPCD_MAX_SWING_REACHED;
 616                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 617                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 618
 619                         edp->link_train.training_lane[lane] = training_lane;
 620
 621                         rk32_edp_set_lane_link_training(edp,
 622                                 edp->link_train.training_lane[lane],
 623                                 lane);
 624                 }
 625
 626                 retval = rk32_edp_write_byte_to_dpcd(edp,
 627                                 DPCD_TRAINING_PATTERN_SET,
 628                                 DPCD_SCRAMBLING_DISABLED |
 629                                 DPCD_TRAINING_PATTERN_2);
 630                 if (retval < 0) {
 631                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 632                         return retval;
 633                 }
 634
 635                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 636                                 DPCD_TRAINING_LANE0_SET,
 637                                 lane_count,
 638                                 edp->link_train.training_lane);
 639                 if (retval < 0) {
 640                         dev_err(edp->dev, "failed to set training lane!\n");
 641                         return retval;
 642                 }
 643
 644                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 645                 edp->link_train.lt_state = LT_EQ_TRAINING;
 646         } else {
 647                 for (lane = 0; lane < lane_count; lane++) {
 648                         training_lane = rk32_edp_get_lane_link_training(
 649                                                         edp, lane);
 650                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 651                                         DPCD_ADJUST_REQUEST_LANE0_1,
 652                                         2, adjust_request);
 653                         if (retval < 0) {
 654                                 dev_err(edp->dev, "failed to read adjust request!\n");
 655                                 return retval;
 656                         }
 657
 658                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 659                                                         adjust_request, lane);
 660                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 661                                                         adjust_request, lane);
 662
 663                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 664                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 665                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 666                                 goto reduce_link_rate;
 667                         }
 668
 669                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 670                                         voltage_swing) &&
 671                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 672                                         pre_emphasis)) {
 673                                 edp->link_train.cr_loop[lane]++;
 674                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 675                                         dev_err(edp->dev, "CR Max loop\n");
 676                                         goto reduce_link_rate;
 677                                 }
 678                         }
 679
 680                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 681                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 682
 683                         if (voltage_swing == VOLTAGE_LEVEL_3)
 684                                 training_lane |= DPCD_MAX_SWING_REACHED;
 685                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 686                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 687
 688                         edp->link_train.training_lane[lane] = training_lane;
 689
 690                         rk32_edp_set_lane_link_training(edp,
 691                                 edp->link_train.training_lane[lane], lane);
 692                 }
 693
 694                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 695                                 DPCD_TRAINING_LANE0_SET,
 696                                 lane_count,
 697                                 edp->link_train.training_lane);
 698                 if (retval < 0) {
 699                         dev_err(edp->dev, "failed to set training lane!\n");
 700                         return retval;
 701                 }
 702         }
 703
 704         return 0;
 705
 706 reduce_link_rate:
 707         rk32_edp_reduce_link_rate(edp);
 708         return -EIO;
 709 }
 710
 711 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 712 {
 713         u8 link_status[2];
 714         u8 link_align[3];
 715         int lane;
 716         int lane_count;
 717         u32 reg;
 718
 719         u8 adjust_request[2];
 720         u8 voltage_swing;
 721         u8 pre_emphasis;
 722         u8 training_lane;
 723         int retval;
 724
 725         udelay(400);
 726
 727         lane_count = edp->link_train.lane_count;
 728
 729         retval = rk32_edp_read_bytes_from_dpcd(edp,
 730                         DPCD_LANE0_1_STATUS,
 731                         2, link_status);
 732         if (retval < 0) {
 733                 dev_err(edp->dev, "failed to read lane status!\n");
 734                 return retval;
 735         }
 736
 737         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 738                 link_align[0] = link_status[0];
 739                 link_align[1] = link_status[1];
 740
 741                 retval = rk32_edp_read_byte_from_dpcd(edp,
 742                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 743                                 &link_align[2]);
 744                 if (retval < 0) {
 745                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 746                         return retval;
 747                 }
 748
 749                 for (lane = 0; lane < lane_count; lane++) {
 750                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 751                                         DPCD_ADJUST_REQUEST_LANE0_1,
 752                                         2, adjust_request);
 753                         if (retval < 0) {
 754                                 dev_err(edp->dev, "failed to read adjust request!\n");
 755                                 return retval;
 756                         }
 757
 758                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 759                                                         adjust_request, lane);
 760                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 761                                                         adjust_request, lane);
 762                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 763                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 764
 765                         if (voltage_swing == VOLTAGE_LEVEL_3)
 766                                 training_lane |= DPCD_MAX_SWING_REACHED;
 767                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 768                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 769
 770                         edp->link_train.training_lane[lane] = training_lane;
 771                 }
 772
 773                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 774                         /* traing pattern Set to Normal */
 775                         retval = rk32_edp_training_pattern_dis(edp);
 776                         if (retval < 0) {
 777                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 778                                 return retval;
 779                         }
 780
 781                         dev_info(edp->dev, "Link Training success!\n");
 782
 783                         rk32_edp_get_link_bandwidth(edp, &reg);
 784                         edp->link_train.link_rate = reg;
 785                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 786                                 edp->link_train.link_rate);
 787
 788                         rk32_edp_get_lane_count(edp, &reg);
 789                         edp->link_train.lane_count = reg;
 790                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 791                                 edp->link_train.lane_count);
 792
 793                         edp->link_train.lt_state = FINISHED;
 794                 } else {
 795                         /* not all locked */
 796                         edp->link_train.eq_loop++;
 797
 798                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 799                                 dev_err(edp->dev, "EQ Max loop\n");
 800                                 goto reduce_link_rate;
 801                         }
 802
 803                         for (lane = 0; lane < lane_count; lane++)
 804                                 rk32_edp_set_lane_link_training(edp,
 805                                         edp->link_train.training_lane[lane],
 806                                         lane);
 807
 808                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 809                                         DPCD_TRAINING_LANE0_SET,
 810                                         lane_count,
 811                                         edp->link_train.training_lane);
 812                         if (retval < 0) {
 813                                 dev_err(edp->dev, "failed to set training lane!\n");
 814                                 return retval;
 815                         }
 816                 }
 817         } else {
 818                 goto reduce_link_rate;
 819         }
 820
 821         return 0;
 822
 823 reduce_link_rate:
 824         rk32_edp_reduce_link_rate(edp);
 825         return -EIO;
 826 }
 827
 828 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 829                                         u8 *bandwidth)
 830 {
 831         u8 data;
 832         int retval;
 833
 834         /*
 835          * For DP rev.1.1, Maximum link rate of Main Link lanes
 836          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 837          */
 838         retval = rk32_edp_read_byte_from_dpcd(edp,
 839                         DPCD_MAX_LINK_RATE, &data);
 840         if (retval < 0)
 841                 return retval;
 842
 843         *bandwidth = data;
 844         return 0;
 845 }
 846
 847 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 848                                         u8 *lane_count)
 849 {
 850         u8 data;
 851         int retval;
 852
 853         /*
 854          * For DP rev.1.1, Maximum number of Main Link lanes
 855          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 856          */
 857         retval = rk32_edp_read_byte_from_dpcd(edp,
 858                         DPCD_MAX_LANE_CNT, &data);
 859         if (retval < 0)
 860                 return retval;
 861
 862         *lane_count = DPCD_MAX_LANE_COUNT(data);
 863         return 0;
 864 }
 865
 866 static int rk32_edp_init_training(struct rk32_edp *edp)
 867 {
 868         int retval;
 869
 870         /*
 871          * MACRO_RST must be applied after the PLL_LOCK to avoid
 872          * the DP inter pair skew issue for at least 10 us
 873          */
 874         rk32_edp_reset_macro(edp);
 875
 876
 877         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 878         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 879         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 880                         edp->link_train.link_rate * 27/100,
 881                         edp->link_train.link_rate*27%100,
 882                         edp->link_train.lane_count);
 883
 884         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 885            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 886                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 887                         "use default link rate:%d.%dGps\n",
 888                         edp->link_train.link_rate,
 889                         edp->video_info.link_rate*27/100,
 890                         edp->video_info.link_rate*27%100);
 891                 edp->link_train.link_rate = edp->video_info.link_rate;
 892         }
 893
 894         if (edp->link_train.lane_count == 0) {
 895                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 896                         "use default lanes:%d\n",
 897                         edp->link_train.lane_count,
 898                         edp->video_info.lane_count);
 899                 edp->link_train.lane_count = edp->video_info.lane_count;
 900         }
 901
 902         rk32_edp_analog_power_ctr(edp, 1);
 903
 904
 905         return 0;
 906 }
 907
 908 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 909 {
 910         int retval = 0;
 911         int training_finished = 0;
 912
 913         edp->link_train.lt_state = LT_START;
 914
 915         /* Process here */
 916         while (!training_finished) {
 917                 switch (edp->link_train.lt_state) {
 918                 case LT_START:
 919                         retval = rk32_edp_link_start(edp);
 920                         if (retval)
 921                                 dev_err(edp->dev, "LT Start failed\n");
 922                         break;
 923                 case LT_CLK_RECOVERY:
 924                         retval = rk32_edp_process_clock_recovery(edp);
 925                         if (retval)
 926                                 dev_err(edp->dev, "LT CR failed\n");
 927                         break;
 928                 case LT_EQ_TRAINING:
 929                         retval = rk32_edp_process_equalizer_training(edp);
 930                         if (retval)
 931                                 dev_err(edp->dev, "LT EQ failed\n");
 932                         break;
 933                 case FINISHED:
 934                         training_finished = 1;
 935                         break;
 936                 case FAILED:
 937                         return -EREMOTEIO;
 938                 }
 939         }
 940
 941         return retval;
 942 }
 943
 944
 945 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 946 {
 947         u32 cnt = 50;
 948         u32 val;
 949         /* Set link rate and count as you want to establish*/
 950         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 951         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 952         rk32_edp_hw_link_training_en(edp);
 953         val = rk32_edp_wait_hw_lt_done(edp);
 954         while (val) {
 955                 if (cnt-- <= 0) {
 956                         dev_err(edp->dev, "hw lt timeout");
 957                         return -ETIMEDOUT;
 958                 }
 959                 mdelay(1);
 960                 val = rk32_edp_wait_hw_lt_done(edp);
 961         }
 962
 963         val = rk32_edp_get_hw_lt_status(edp);
 964         if (val)
 965                 dev_err(edp->dev, "hw lt err:%d\n", val);
 966         return val;
 967
 968 }
 969 static int rk32_edp_set_link_train(struct rk32_edp *edp)
 970 {
 971         int retval;
 972
 973         retval = rk32_edp_init_training(edp);
 974         if (retval < 0)
 975                 dev_err(edp->dev, "DP LT init failed!\n");
 976 #if 0
 977         retval = rk32_edp_sw_link_training(edp);
 978 #else
 979         retval = rk32_edp_hw_link_training(edp);
 980 #endif
 981
 982         return retval;
 983 }
 984
 985 static int rk32_edp_config_video(struct rk32_edp *edp,
 986                         struct video_info *video_info)
 987 {
 988         int retval = 0;
 989         int timeout_loop = 0;
 990         int done_count = 0;
 991
 992         rk32_edp_config_video_slave_mode(edp, video_info);
 993
 994         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 995                         video_info->color_space,
 996                         video_info->dynamic_range,
 997                         video_info->ycbcr_coeff);
 998
 999         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1000                 dev_err(edp->dev, "PLL is not locked yet.\n");
1001                 return -EINVAL;
1002         }
1003
1004         for (;;) {
1005                 timeout_loop++;
1006                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1007                         break;
1008                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1009                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1010                         return -ETIMEDOUT;
1011                 }
1012
1013                 usleep_range(1, 1);
1014         }
1015
1016         /* Set to use the register calculated M/N video */
1017         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1018
1019         /* For video bist, Video timing must be generated by register */
1020         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1021
1022         /* Disable video mute */
1023         rk32_edp_enable_video_mute(edp, 0);
1024
1025         /* Configure video slave mode */
1026         rk32_edp_enable_video_master(edp, 0);
1027
1028         /* Enable video */
1029         rk32_edp_start_video(edp);
1030
1031         timeout_loop = 0;
1032
1033         for (;;) {
1034                 timeout_loop++;
1035                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1036                         done_count++;
1037                         if (done_count > 10)
1038                                 break;
1039                 } else if (done_count) {
1040                         done_count = 0;
1041                 }
1042                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1043                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1044                         return -ETIMEDOUT;
1045                 }
1046
1047                 usleep_range(1000, 1000);
1048         }
1049
1050         if (retval != 0)
1051                 dev_err(edp->dev, "Video stream is not detected!\n");
1052
1053         return retval;
1054 }
1055
1056 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1057 {
1058         u8 data;
1059         int retval;
1060
1061         if (enable) {
1062                 rk32_edp_enable_scrambling(edp);
1063
1064                 retval = rk32_edp_read_byte_from_dpcd(edp,
1065                                 DPCD_TRAINING_PATTERN_SET,
1066                                 &data);
1067                 if (retval < 0)
1068                         return retval;
1069
1070                 retval = rk32_edp_write_byte_to_dpcd(edp,
1071                                 DPCD_TRAINING_PATTERN_SET,
1072                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1073                 if (retval < 0)
1074                         return retval;
1075         } else {
1076                 rk32_edp_disable_scrambling(edp);
1077
1078                 retval = rk32_edp_read_byte_from_dpcd(edp,
1079                                 DPCD_TRAINING_PATTERN_SET,
1080                                 &data);
1081                 if (retval < 0)
1082                         return retval;
1083
1084                 retval = rk32_edp_write_byte_to_dpcd(edp,
1085                                 DPCD_TRAINING_PATTERN_SET,
1086                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1087                 if (retval < 0)
1088                         return retval;
1089         }
1090
1091         return 0;
1092 }
1093
1094 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1095 {
1096         struct rk32_edp *edp = arg;
1097         enum dp_irq_type irq_type;
1098
1099         if (!lcdc_probed) {
1100                 disable_irq_nosync(edp->irq);
1101                 return 0;
1102         }
1103
1104         irq_type = rk32_edp_get_irq_type(edp);
1105         switch (irq_type) {
1106         case DP_IRQ_TYPE_HP_CABLE_IN:
1107                 dev_info(edp->dev, "Received irq - cable in\n");
1108                 rk32_edp_clear_hotplug_interrupts(edp);
1109                 break;
1110         case DP_IRQ_TYPE_HP_CABLE_OUT:
1111                 dev_info(edp->dev, "Received irq - cable out\n");
1112                 rk32_edp_clear_hotplug_interrupts(edp);
1113                 break;
1114         case DP_IRQ_TYPE_HP_CHANGE:
1115                 /*
1116                  * We get these change notifications once in a while, but there
1117                  * is nothing we can do with them. Just ignore it for now and
1118                  * only handle cable changes.
1119                  */
1120                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1121                 rk32_edp_clear_hotplug_interrupts(edp);
1122                 break;
1123         default:
1124                 dev_err(edp->dev, "Received irq - unknown type!\n");
1125                 break;
1126         }
1127         return IRQ_HANDLED;
1128 }
1129
1130 static int rk32_edp_enable(void)
1131 {
1132         int ret = 0;
1133         struct rk32_edp *edp = rk32_edp;
1134
1135
1136         rk32_edp_clk_enable(edp);
1137         rk32_edp_pre_init();
1138         lcdc_probed = 1;
1139         rk32_edp_init_edp(edp);
1140         enable_irq(edp->irq);
1141         /*ret = rk32_edp_handle_edid(edp);
1142         if (ret) {
1143                 dev_err(edp->dev, "unable to handle edid\n");
1144                 //goto out;
1145         }
1146
1147
1148         ret = rk32_edp_enable_scramble(edp, 0);
1149         if (ret) {
1150                 dev_err(edp->dev, "unable to set scramble\n");
1151                 //goto out;
1152         }
1153
1154         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1155         if (ret) {
1156                 dev_err(edp->dev, "unable to set enhanced mode\n");
1157                 //goto out;
1158         }
1159         rk32_edp_enable_enhanced_mode(edp, 1);*/
1160
1161         ret = rk32_edp_set_link_train(edp);
1162         if (ret)
1163                 dev_err(edp->dev, "link train failed!\n");
1164         else
1165                 dev_info(edp->dev, "link training success.\n");
1166
1167         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1168         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1169
1170 #ifdef EDP_BIST_MODE
1171         rk32_edp_bist_cfg(edp);
1172 #else
1173         rk32_edp_init_video(edp);
1174         ret = rk32_edp_config_video(edp, &edp->video_info);
1175         if (ret)
1176                 dev_err(edp->dev, "unable to config video\n");
1177 #endif
1178         return ret;
1179
1180
1181
1182 }
1183
1184 static int  rk32_edp_disable(void )
1185 {
1186         struct rk32_edp *edp = rk32_edp;
1187
1188         disable_irq(edp->irq);
1189         rk32_edp_reset(edp);
1190         rk32_edp_analog_power_ctr(edp, 0);
1191         rk32_edp_clk_disable(edp);
1192
1193         return 0;
1194 }
1195
1196
1197 static struct rk_fb_trsm_ops trsm_edp_ops = {
1198         .enable = rk32_edp_enable,
1199         .disable = rk32_edp_disable,
1200 };
1201 static int rk32_edp_probe(struct platform_device *pdev)
1202 {
1203         struct rk32_edp *edp;
1204         struct resource *res;
1205         struct device_node *np = pdev->dev.of_node;
1206         int ret;
1207
1208         if (!np) {
1209                 dev_err(&pdev->dev, "Missing device tree node.\n");
1210                 return -EINVAL;
1211         }
1212
1213         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1214         if (!edp) {
1215                 dev_err(&pdev->dev, "no memory for state\n");
1216                 return -ENOMEM;
1217         }
1218         edp->dev = &pdev->dev;
1219         edp->video_info.h_sync_polarity = 0;
1220         edp->video_info.v_sync_polarity = 0;
1221         edp->video_info.interlaced      = 0;
1222         edp->video_info.color_space     = CS_RGB;
1223         edp->video_info.dynamic_range   = VESA;
1224         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1225         edp->video_info.color_depth     = COLOR_6;
1226
1227         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1228         edp->video_info.lane_count      = LANE_CNT4;
1229         rk_fb_get_prmry_screen(&edp->screen);
1230         if (edp->screen.type != SCREEN_EDP) {
1231                 dev_err(&pdev->dev, "screen is not edp!\n");
1232                 return -EINVAL;
1233         }
1234         platform_set_drvdata(pdev, edp);
1235         dev_set_name(edp->dev, "rk32-edp");
1236
1237         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1238         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1239         if (IS_ERR(edp->regs)) {
1240                 dev_err(&pdev->dev, "ioremap reg failed\n");
1241                 return PTR_ERR(edp->regs);
1242         }
1243
1244         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1245         if (IS_ERR(edp->clk_edp)) {
1246                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1247                 return PTR_ERR(edp->clk_edp);
1248         }
1249
1250         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1251         if (IS_ERR(edp->clk_24m)) {
1252                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1253                 return PTR_ERR(edp->clk_24m);
1254         }
1255
1256         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1257         if (IS_ERR(edp->pclk)) {
1258                 dev_err(&pdev->dev, "cannot get pclk\n");
1259                 return PTR_ERR(edp->pclk);
1260         }
1261
1262         clk_prepare(edp->pclk);
1263         clk_prepare(edp->clk_edp);
1264         clk_prepare(edp->clk_24m);
1265         edp->irq = platform_get_irq(pdev, 0);
1266         if (edp->irq < 0) {
1267                 dev_err(&pdev->dev, "cannot find IRQ\n");
1268                 return edp->irq;
1269         }
1270         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1271                         dev_name(&pdev->dev), edp);
1272         if (ret) {
1273                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1274                 return ret;
1275         }
1276         disable_irq_nosync(edp->irq);
1277         rk32_edp = edp;
1278         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1279         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1280
1281         return 0;
1282 }
1283
1284 static void rk32_edp_shutdown(struct platform_device *pdev)
1285 {
1286
1287 }
1288
1289 #if defined(CONFIG_OF)
1290 static const struct of_device_id rk32_edp_dt_ids[] = {
1291         {.compatible = "rockchip,rk32-edp",},
1292         {}
1293 };
1294
1295 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1296 #endif
1297
1298 static struct platform_driver rk32_edp_driver = {
1299         .probe = rk32_edp_probe,
1300         .driver = {
1301                    .name = "rk32-edp",
1302                    .owner = THIS_MODULE,
1303 #if defined(CONFIG_OF)
1304                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1305 #endif
1306         },
1307         .shutdown = rk32_edp_shutdown,
1308 };
1309
1310 static int __init rk32_edp_module_init(void)
1311 {
1312         return platform_driver_register(&rk32_edp_driver);
1313 }
1314
1315 static void __exit rk32_edp_module_exit(void)
1316 {
1317
1318 }
1319
1320 subsys_initcall_sync(rk32_edp_module_init);
1321 module_exit(rk32_edp_module_exit);