drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 /*#define EDP_BIST_MODE*/
  35
  36 static int rk32_edp_init_edp(struct rk32_edp *edp)
  37 {
  38         struct rk_screen *screen = &edp->screen;
  39         u32 val = 0;
  40 #ifndef CONFIG_RK_FPGA
  41         if (screen->lcdc_id == 0)  /*select lcdc*/
  42                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  43         else
  44                 val = EDP_SEL_VOP_LIT << 16;
  45         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  46 #endif
  47         rk32_edp_reset(edp);
  48         rk32_edp_init_refclk(edp);
  49         rk32_edp_init_interrupt(edp);
  50
  51         rk32_edp_enable_sw_function(edp);
  52
  53         rk32_edp_init_analog_func(edp);
  54
  55         rk32_edp_init_hpd(edp);
  56         rk32_edp_init_aux(edp);
  57
  58         return 0;
  59 }
  60
  61 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  62 {
  63         int timeout_loop = 0;
  64
  65         rk32_edp_init_hpd(edp);
  66
  67         udelay(200);
  68
  69         while (rk32_edp_get_plug_in_status(edp) != 0) {
  70                 timeout_loop++;
  71                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  72                         dev_err(edp->dev, "failed to get hpd plug status\n");
  73                         return -ETIMEDOUT;
  74                 }
  75                 udelay(10);
  76         }
  77
  78         return 0;
  79 }
  80
  81 static int rk32_edp_read_edid(struct rk32_edp *edp)
  82 {
  83         unsigned char edid[EDID_LENGTH * 2];
  84         unsigned int extend_block = 0;
  85         unsigned char sum;
  86         unsigned char test_vector;
  87         int retval;
  88
  89         /*
  90          * EDID device address is 0x50.
  91          * However, if necessary, you must have set upper address
  92          * into E-EDID in I2C device, 0x30.
  93          */
  94
  95         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  96         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
  97                                                 &extend_block);
  98         if (retval < 0) {
  99                 dev_err(edp->dev, "EDID extension flag failed!\n");
 100                 return -EIO;
 101         }
 102
 103         if (extend_block > 0) {
 104                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 105
 106                 /* Read EDID data */
 107                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 108                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 109                 if (retval != 0) {
 110                         dev_err(edp->dev, "EDID Read failed!\n");
 111                         return -EIO;
 112                 }
 113                 sum = edp_calc_edid_check_sum(edid);
 114                 if (sum != 0) {
 115                         dev_warn(edp->dev, "EDID bad checksum!\n");
 116                         return 0;
 117                 }
 118
 119                 /* Read additional EDID data */
 120                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 121                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 122                 if (retval != 0) {
 123                         dev_err(edp->dev, "EDID Read failed!\n");
 124                         return -EIO;
 125                 }
 126                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 127                 if (sum != 0) {
 128                         dev_warn(edp->dev, "EDID bad checksum!\n");
 129                         return 0;
 130                 }
 131
 132                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 133                                         &test_vector);
 134                 if (retval < 0) {
 135                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 136                         return retval;
 137                 }
 138
 139                 if (test_vector & DPCD_TEST_EDID_READ) {
 140                         retval = rk32_edp_write_byte_to_dpcd(edp,
 141                                         DPCD_TEST_EDID_CHECKSUM,
 142                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 143                         if (retval < 0) {
 144                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 145                                 return retval;
 146                         }
 147                         retval = rk32_edp_write_byte_to_dpcd(edp,
 148                                         DPCD_TEST_RESPONSE,
 149                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 150                         if (retval < 0) {
 151                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 152                                 return retval;
 153                         }
 154                 }
 155         } else {
 156                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 157
 158                 /* Read EDID data */
 159                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 160                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 161                 if (retval != 0) {
 162                         dev_err(edp->dev, "EDID Read failed!\n");
 163                         return -EIO;
 164                 }
 165                 sum = edp_calc_edid_check_sum(edid);
 166                 if (sum != 0) {
 167                         dev_warn(edp->dev, "EDID bad checksum!\n");
 168                         return 0;
 169                 }
 170
 171                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 172                                                 &test_vector);
 173                 if (retval < 0) {
 174                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 175                         return retval;
 176                 }
 177
 178                 if (test_vector & DPCD_TEST_EDID_READ) {
 179                         retval = rk32_edp_write_byte_to_dpcd(edp,
 180                                         DPCD_TEST_EDID_CHECKSUM,
 181                                         edid[EDID_CHECKSUM]);
 182                         if (retval < 0) {
 183                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 184                                 return retval;
 185                         }
 186                         retval = rk32_edp_write_byte_to_dpcd(edp,
 187                                         DPCD_TEST_RESPONSE,
 188                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 189                         if (retval < 0) {
 190                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 191                                 return retval;
 192                         }
 193                 }
 194         }
 195
 196         dev_err(edp->dev, "EDID Read success!\n");
 197         return 0;
 198 }
 199
 200 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 201 {
 202         u8 buf[12];
 203         int i;
 204         int retval;
 205
 206         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 207         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 208         if (retval < 0)
 209                 return retval;
 210
 211         /* Read EDID */
 212         for (i = 0; i < 3; i++) {
 213                 retval = rk32_edp_read_edid(edp);
 214                 if (retval == 0)
 215                         break;
 216         }
 217
 218         return retval;
 219 }
 220
 221 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 222                                                 bool enable)
 223 {
 224         u8 data;
 225         int retval;
 226
 227         retval = rk32_edp_read_byte_from_dpcd(edp,
 228                         DPCD_LANE_CNT_SET, &data);
 229         if (retval < 0)
 230                 return retval;
 231
 232         if (enable) {
 233                 retval = rk32_edp_write_byte_to_dpcd(edp,
 234                                 DPCD_LANE_CNT_SET,
 235                                 DPCD_ENHANCED_FRAME_EN |
 236                                 DPCD_LANE_COUNT_SET(data));
 237         } else {
 238                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 239                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 240
 241                 retval = rk32_edp_write_byte_to_dpcd(edp,
 242                                 DPCD_LANE_CNT_SET,
 243                                 DPCD_LANE_COUNT_SET(data));
 244         }
 245
 246         return retval;
 247 }
 248
 249 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 250 {
 251         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 252         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 253
 254         if (enable) {
 255                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 256                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 257         } else {
 258                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 259         }*/
 260 }
 261
 262 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 263 {
 264         u8 data;
 265         int retval;
 266
 267         retval = rk32_edp_read_byte_from_dpcd(edp,
 268                         DPCD_MAX_LANE_CNT, &data);
 269         if (retval < 0)
 270                 return retval;
 271
 272         return DPCD_ENHANCED_FRAME_CAP(data);
 273 }
 274
 275 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 276 {
 277         /*rk32_edp_write_byte_to_dpcd(edp,
 278                         DPCD_ADDR_USER_DEFINED1, 0);
 279         rk32_edp_write_byte_to_dpcd(edp,
 280                         DPCD_ADDR_USER_DEFINED2, 0x83);
 281         rk32_edp_write_byte_to_dpcd(edp,
 282                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 283 }
 284
 285 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 286 {
 287         u8 data;
 288         int retval;
 289
 290         retval = rk32_edp_is_enhanced_mode_available(edp);
 291         if (retval < 0)
 292                 return retval;
 293
 294         data = (u8)retval;
 295         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 296         if (retval < 0)
 297                 return retval;
 298
 299         rk32_edp_enable_enhanced_mode(edp, data);
 300
 301         return 0;
 302 }
 303
 304 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 305 {
 306         int retval;
 307
 308         rk32_edp_set_training_pattern(edp, DP_NONE);
 309
 310         retval = rk32_edp_write_byte_to_dpcd(edp,
 311                         DPCD_TRAINING_PATTERN_SET,
 312                         DPCD_TRAINING_PATTERN_DISABLED);
 313         if (retval < 0)
 314                 return retval;
 315
 316         return 0;
 317 }
 318
 319 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 320                                         int pre_emphasis, int lane)
 321 {
 322         switch (lane) {
 323         case 0:
 324                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 325                 break;
 326         case 1:
 327                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 328                 break;
 329
 330         case 2:
 331                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 332                 break;
 333
 334         case 3:
 335                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 336                 break;
 337         }
 338 }
 339
 340 static int rk32_edp_link_start(struct rk32_edp *edp)
 341 {
 342         u8 buf[4];
 343         int lane;
 344         int lane_count;
 345         int retval;
 346
 347         lane_count = edp->link_train.lane_count;
 348
 349         edp->link_train.lt_state = LT_CLK_RECOVERY;
 350         edp->link_train.eq_loop = 0;
 351
 352         for (lane = 0; lane < lane_count; lane++)
 353                 edp->link_train.cr_loop[lane] = 0;
 354
 355         /* Set sink to D0 (Sink Not Ready) mode. */
 356         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 357                                 DPCD_SET_POWER_STATE_D0);
 358         if (retval < 0) {
 359                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 360                 return retval;
 361         }
 362
 363         /* Set link rate and count as you want to establish*/
 364         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 365         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 366
 367         /* Setup RX configuration */
 368         buf[0] = edp->link_train.link_rate;
 369         buf[1] = edp->link_train.lane_count;
 370         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 371                                         2, buf);
 372         if (retval < 0) {
 373                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 374                 return retval;
 375         }
 376
 377         /* Set TX pre-emphasis to level1 */
 378         for (lane = 0; lane < lane_count; lane++)
 379                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 380                         PRE_EMPHASIS_LEVEL_1, lane);
 381
 382         /* Set training pattern 1 */
 383         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 384
 385         /* Set RX training pattern */
 386         retval = rk32_edp_write_byte_to_dpcd(edp,
 387                         DPCD_TRAINING_PATTERN_SET,
 388                         DPCD_SCRAMBLING_DISABLED |
 389                         DPCD_TRAINING_PATTERN_1);
 390         if (retval < 0) {
 391                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 392                 return retval;
 393         }
 394
 395         for (lane = 0; lane < lane_count; lane++)
 396                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 397                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 398         retval = rk32_edp_write_bytes_to_dpcd(edp,
 399                         DPCD_TRAINING_LANE0_SET,
 400                         lane_count, buf);
 401         if (retval < 0) {
 402                 dev_err(edp->dev, "failed to set training lane!\n");
 403                 return retval;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 410 {
 411         int shift = (lane & 1) * 4;
 412         u8 link_value = link_status[lane>>1];
 413
 414         return (link_value >> shift) & 0xf;
 415 }
 416
 417 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 418 {
 419         int lane;
 420         u8 lane_status;
 421
 422         for (lane = 0; lane < lane_count; lane++) {
 423                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 424                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 425                         return -EINVAL;
 426         }
 427         return 0;
 428 }
 429
 430 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 431 {
 432         int lane;
 433         u8 lane_align;
 434         u8 lane_status;
 435
 436         lane_align = link_align[2];
 437         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 438                 return -EINVAL;
 439
 440         for (lane = 0; lane < lane_count; lane++) {
 441                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 442                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 443                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 444                         return -EINVAL;
 445         }
 446
 447         return 0;
 448 }
 449
 450 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 451                                                         int lane)
 452 {
 453         int shift = (lane & 1) * 4;
 454         u8 link_value = adjust_request[lane>>1];
 455
 456         return (link_value >> shift) & 0x3;
 457 }
 458
 459 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 460                                         u8 adjust_request[2],
 461                                         int lane)
 462 {
 463         int shift = (lane & 1) * 4;
 464         u8 link_value = adjust_request[lane>>1];
 465
 466         return ((link_value >> shift) & 0xc) >> 2;
 467 }
 468
 469 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 470                                         u8 training_lane_set, int lane)
 471 {
 472         switch (lane) {
 473         case 0:
 474                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 475                 break;
 476         case 1:
 477                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 478                 break;
 479
 480         case 2:
 481                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 482                 break;
 483
 484         case 3:
 485                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 486                 break;
 487         }
 488 }
 489
 490 static unsigned int rk32_edp_get_lane_link_training(
 491                                 struct rk32_edp *edp,
 492                                 int lane)
 493 {
 494         u32 reg;
 495
 496         switch (lane) {
 497         case 0:
 498                 reg = rk32_edp_get_lane0_link_training(edp);
 499                 break;
 500         case 1:
 501                 reg = rk32_edp_get_lane1_link_training(edp);
 502                 break;
 503         case 2:
 504                 reg = rk32_edp_get_lane2_link_training(edp);
 505                 break;
 506         case 3:
 507                 reg = rk32_edp_get_lane3_link_training(edp);
 508                 break;
 509         }
 510
 511         return reg;
 512 }
 513
 514 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 515 {
 516         rk32_edp_training_pattern_dis(edp);
 517
 518         edp->link_train.lt_state = FAILED;
 519 }
 520
 521 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 522 {
 523         u8 link_status[2];
 524         int lane;
 525         int lane_count;
 526
 527         u8 adjust_request[2];
 528         u8 voltage_swing;
 529         u8 pre_emphasis;
 530         u8 training_lane;
 531         int retval;
 532
 533         udelay(100);
 534
 535         lane_count = edp->link_train.lane_count;
 536
 537         retval = rk32_edp_read_bytes_from_dpcd(edp,
 538                         DPCD_LANE0_1_STATUS,
 539                         2, link_status);
 540         if (retval < 0) {
 541                 dev_err(edp->dev, "failed to read lane status!\n");
 542                 return retval;
 543         }
 544
 545         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 546                 /* set training pattern 2 for EQ */
 547                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 548
 549                 for (lane = 0; lane < lane_count; lane++) {
 550                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 551                                         DPCD_ADJUST_REQUEST_LANE0_1,
 552                                         2, adjust_request);
 553                         if (retval < 0) {
 554                                 dev_err(edp->dev, "failed to read adjust request!\n");
 555                                 return retval;
 556                         }
 557
 558                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 559                                                         adjust_request, lane);
 560                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 561                                                         adjust_request, lane);
 562                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 563                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 564
 565                         if (voltage_swing == VOLTAGE_LEVEL_3)
 566                                 training_lane |= DPCD_MAX_SWING_REACHED;
 567                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 568                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 569
 570                         edp->link_train.training_lane[lane] = training_lane;
 571
 572                         rk32_edp_set_lane_link_training(edp,
 573                                 edp->link_train.training_lane[lane],
 574                                 lane);
 575                 }
 576
 577                 retval = rk32_edp_write_byte_to_dpcd(edp,
 578                                 DPCD_TRAINING_PATTERN_SET,
 579                                 DPCD_SCRAMBLING_DISABLED |
 580                                 DPCD_TRAINING_PATTERN_2);
 581                 if (retval < 0) {
 582                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 583                         return retval;
 584                 }
 585
 586                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 587                                 DPCD_TRAINING_LANE0_SET,
 588                                 lane_count,
 589                                 edp->link_train.training_lane);
 590                 if (retval < 0) {
 591                         dev_err(edp->dev, "failed to set training lane!\n");
 592                         return retval;
 593                 }
 594
 595                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 596                 edp->link_train.lt_state = LT_EQ_TRAINING;
 597         } else {
 598                 for (lane = 0; lane < lane_count; lane++) {
 599                         training_lane = rk32_edp_get_lane_link_training(
 600                                                         edp, lane);
 601                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 602                                         DPCD_ADJUST_REQUEST_LANE0_1,
 603                                         2, adjust_request);
 604                         if (retval < 0) {
 605                                 dev_err(edp->dev, "failed to read adjust request!\n");
 606                                 return retval;
 607                         }
 608
 609                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 610                                                         adjust_request, lane);
 611                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 612                                                         adjust_request, lane);
 613
 614                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 615                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 616                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 617                                 goto reduce_link_rate;
 618                         }
 619
 620                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 621                                         voltage_swing) &&
 622                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 623                                         pre_emphasis)) {
 624                                 edp->link_train.cr_loop[lane]++;
 625                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 626                                         dev_err(edp->dev, "CR Max loop\n");
 627                                         goto reduce_link_rate;
 628                                 }
 629                         }
 630
 631                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 632                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 633
 634                         if (voltage_swing == VOLTAGE_LEVEL_3)
 635                                 training_lane |= DPCD_MAX_SWING_REACHED;
 636                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 637                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 638
 639                         edp->link_train.training_lane[lane] = training_lane;
 640
 641                         rk32_edp_set_lane_link_training(edp,
 642                                 edp->link_train.training_lane[lane], lane);
 643                 }
 644
 645                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 646                                 DPCD_TRAINING_LANE0_SET,
 647                                 lane_count,
 648                                 edp->link_train.training_lane);
 649                 if (retval < 0) {
 650                         dev_err(edp->dev, "failed to set training lane!\n");
 651                         return retval;
 652                 }
 653         }
 654
 655         return 0;
 656
 657 reduce_link_rate:
 658         rk32_edp_reduce_link_rate(edp);
 659         return -EIO;
 660 }
 661
 662 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 663 {
 664         u8 link_status[2];
 665         u8 link_align[3];
 666         int lane;
 667         int lane_count;
 668         u32 reg;
 669
 670         u8 adjust_request[2];
 671         u8 voltage_swing;
 672         u8 pre_emphasis;
 673         u8 training_lane;
 674         int retval;
 675
 676         udelay(400);
 677
 678         lane_count = edp->link_train.lane_count;
 679
 680         retval = rk32_edp_read_bytes_from_dpcd(edp,
 681                         DPCD_LANE0_1_STATUS,
 682                         2, link_status);
 683         if (retval < 0) {
 684                 dev_err(edp->dev, "failed to read lane status!\n");
 685                 return retval;
 686         }
 687
 688         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 689                 link_align[0] = link_status[0];
 690                 link_align[1] = link_status[1];
 691
 692                 retval = rk32_edp_read_byte_from_dpcd(edp,
 693                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 694                                 &link_align[2]);
 695                 if (retval < 0) {
 696                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 697                         return retval;
 698                 }
 699
 700                 for (lane = 0; lane < lane_count; lane++) {
 701                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 702                                         DPCD_ADJUST_REQUEST_LANE0_1,
 703                                         2, adjust_request);
 704                         if (retval < 0) {
 705                                 dev_err(edp->dev, "failed to read adjust request!\n");
 706                                 return retval;
 707                         }
 708
 709                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 710                                                         adjust_request, lane);
 711                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 712                                                         adjust_request, lane);
 713                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 714                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 715
 716                         if (voltage_swing == VOLTAGE_LEVEL_3)
 717                                 training_lane |= DPCD_MAX_SWING_REACHED;
 718                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 719                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 720
 721                         edp->link_train.training_lane[lane] = training_lane;
 722                 }
 723
 724                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 725                         /* traing pattern Set to Normal */
 726                         retval = rk32_edp_training_pattern_dis(edp);
 727                         if (retval < 0) {
 728                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 729                                 return retval;
 730                         }
 731
 732                         dev_info(edp->dev, "Link Training success!\n");
 733
 734                         rk32_edp_get_link_bandwidth(edp, &reg);
 735                         edp->link_train.link_rate = reg;
 736                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 737                                 edp->link_train.link_rate);
 738
 739                         rk32_edp_get_lane_count(edp, &reg);
 740                         edp->link_train.lane_count = reg;
 741                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 742                                 edp->link_train.lane_count);
 743
 744                         edp->link_train.lt_state = FINISHED;
 745                 } else {
 746                         /* not all locked */
 747                         edp->link_train.eq_loop++;
 748
 749                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 750                                 dev_err(edp->dev, "EQ Max loop\n");
 751                                 goto reduce_link_rate;
 752                         }
 753
 754                         for (lane = 0; lane < lane_count; lane++)
 755                                 rk32_edp_set_lane_link_training(edp,
 756                                         edp->link_train.training_lane[lane],
 757                                         lane);
 758
 759                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 760                                         DPCD_TRAINING_LANE0_SET,
 761                                         lane_count,
 762                                         edp->link_train.training_lane);
 763                         if (retval < 0) {
 764                                 dev_err(edp->dev, "failed to set training lane!\n");
 765                                 return retval;
 766                         }
 767                 }
 768         } else {
 769                 goto reduce_link_rate;
 770         }
 771
 772         return 0;
 773
 774 reduce_link_rate:
 775         rk32_edp_reduce_link_rate(edp);
 776         return -EIO;
 777 }
 778
 779 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 780                                         u8 *bandwidth)
 781 {
 782         u8 data;
 783         int retval;
 784
 785         /*
 786          * For DP rev.1.1, Maximum link rate of Main Link lanes
 787          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 788          */
 789         retval = rk32_edp_read_byte_from_dpcd(edp,
 790                         DPCD_MAX_LINK_RATE, &data);
 791         if (retval < 0)
 792                 return retval;
 793
 794         *bandwidth = data;
 795         return 0;
 796 }
 797
 798 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 799                                         u8 *lane_count)
 800 {
 801         u8 data;
 802         int retval;
 803
 804         /*
 805          * For DP rev.1.1, Maximum number of Main Link lanes
 806          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 807          */
 808         retval = rk32_edp_read_byte_from_dpcd(edp,
 809                         DPCD_MAX_LANE_CNT, &data);
 810         if (retval < 0)
 811                 return retval;
 812
 813         *lane_count = DPCD_MAX_LANE_COUNT(data);
 814         return 0;
 815 }
 816
 817 static int rk32_edp_init_training(struct rk32_edp *edp,
 818                         enum link_lane_count_type max_lane,
 819                         u32 max_rate)
 820 {
 821         int retval;
 822
 823         /*
 824          * MACRO_RST must be applied after the PLL_LOCK to avoid
 825          * the DP inter pair skew issue for at least 10 us
 826          */
 827         rk32_edp_reset_macro(edp);
 828
 829
 830         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 831         if (retval < 0)
 832                 return retval;
 833
 834         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 835         if (retval < 0)
 836                 return retval;
 837         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 838                         edp->link_train.link_rate * 27/100,
 839                         edp->link_train.link_rate*27%100,
 840                         edp->link_train.lane_count);
 841
 842         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 843            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 844                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 845                         edp->link_train.link_rate);
 846                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 847         }
 848
 849         if (edp->link_train.lane_count == 0) {
 850                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 851                         edp->link_train.lane_count);
 852                 edp->link_train.lane_count = (u8)LANE_CNT1;
 853         }
 854
 855
 856         if (edp->link_train.lane_count > max_lane)
 857                 edp->link_train.lane_count = max_lane;
 858         if (edp->link_train.link_rate > max_rate)
 859                 edp->link_train.link_rate = max_rate;
 860
 861
 862         rk32_edp_analog_power_ctr(edp, 1);
 863
 864         return 0;
 865 }
 866
 867 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 868 {
 869         int retval = 0;
 870         int training_finished = 0;
 871
 872         edp->link_train.lt_state = LT_START;
 873
 874         /* Process here */
 875         while (!training_finished) {
 876                 switch (edp->link_train.lt_state) {
 877                 case LT_START:
 878                         retval = rk32_edp_link_start(edp);
 879                         if (retval)
 880                                 dev_err(edp->dev, "LT Start failed\n");
 881                         break;
 882                 case LT_CLK_RECOVERY:
 883                         retval = rk32_edp_process_clock_recovery(edp);
 884                         if (retval)
 885                                 dev_err(edp->dev, "LT CR failed\n");
 886                         break;
 887                 case LT_EQ_TRAINING:
 888                         retval = rk32_edp_process_equalizer_training(edp);
 889                         if (retval)
 890                                 dev_err(edp->dev, "LT EQ failed\n");
 891                         break;
 892                 case FINISHED:
 893                         training_finished = 1;
 894                         break;
 895                 case FAILED:
 896                         return -EREMOTEIO;
 897                 }
 898         }
 899
 900         return retval;
 901 }
 902
 903
 904 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 905 {
 906         u32 cnt = 50;
 907         u32 val;
 908         /* Set link rate and count as you want to establish*/
 909         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 910         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 911         rk32_edp_hw_link_training_en(edp);
 912         mdelay(1);
 913         val = rk32_edp_wait_hw_lt_done(edp);
 914         while (val) {
 915                 if (cnt-- <= 0) {
 916                         dev_err(edp->dev, "hw lt timeout");
 917                         return -ETIMEDOUT;
 918                 }
 919                 mdelay(1);
 920                 val = rk32_edp_wait_hw_lt_done(edp);
 921         }
 922
 923         val = rk32_edp_get_hw_lt_status(edp);
 924         if (val)
 925                 dev_err(edp->dev, "hw lt err:%d\n", val);
 926         return val;
 927
 928 }
 929 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 930                                 u32 count,
 931                                 u32 bwtype)
 932 {
 933         int retval;
 934
 935         retval = rk32_edp_init_training(edp, count, bwtype);
 936         if (retval < 0)
 937                 dev_err(edp->dev, "DP LT init failed!\n");
 938 #if 0
 939         retval = rk32_edp_sw_link_training(edp);
 940 #else
 941         retval = rk32_edp_hw_link_training(edp);
 942 #endif
 943
 944         return retval;
 945 }
 946
 947 static int rk32_edp_config_video(struct rk32_edp *edp,
 948                         struct video_info *video_info)
 949 {
 950         int retval = 0;
 951         int timeout_loop = 0;
 952         int done_count = 0;
 953
 954         rk32_edp_config_video_slave_mode(edp, video_info);
 955
 956         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 957                         video_info->color_space,
 958                         video_info->dynamic_range,
 959                         video_info->ycbcr_coeff);
 960
 961         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 962                 dev_err(edp->dev, "PLL is not locked yet.\n");
 963                 return -EINVAL;
 964         }
 965
 966         for (;;) {
 967                 timeout_loop++;
 968                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 969                         break;
 970                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 971                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 972                         return -ETIMEDOUT;
 973                 }
 974
 975                 usleep_range(1, 1);
 976         }
 977
 978         /* Set to use the register calculated M/N video */
 979         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 980
 981         /* For video bist, Video timing must be generated by register */
 982         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 983
 984         /* Disable video mute */
 985         rk32_edp_enable_video_mute(edp, 0);
 986
 987         /* Configure video slave mode */
 988         rk32_edp_enable_video_master(edp, 0);
 989
 990         /* Enable video */
 991         rk32_edp_start_video(edp);
 992
 993         timeout_loop = 0;
 994
 995         for (;;) {
 996                 timeout_loop++;
 997                 if (rk32_edp_is_video_stream_on(edp) == 0) {
 998                         done_count++;
 999                         if (done_count > 10)
1000                                 break;
1001                 } else if (done_count) {
1002                         done_count = 0;
1003                 }
1004                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1005                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1006                         return -ETIMEDOUT;
1007                 }
1008
1009                 usleep_range(1000, 1000);
1010         }
1011
1012         if (retval != 0)
1013                 dev_err(edp->dev, "Video stream is not detected!\n");
1014
1015         return retval;
1016 }
1017
1018 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1019 {
1020         u8 data;
1021         int retval;
1022
1023         if (enable) {
1024                 rk32_edp_enable_scrambling(edp);
1025
1026                 retval = rk32_edp_read_byte_from_dpcd(edp,
1027                                 DPCD_TRAINING_PATTERN_SET,
1028                                 &data);
1029                 if (retval < 0)
1030                         return retval;
1031
1032                 retval = rk32_edp_write_byte_to_dpcd(edp,
1033                                 DPCD_TRAINING_PATTERN_SET,
1034                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1035                 if (retval < 0)
1036                         return retval;
1037         } else {
1038                 rk32_edp_disable_scrambling(edp);
1039
1040                 retval = rk32_edp_read_byte_from_dpcd(edp,
1041                                 DPCD_TRAINING_PATTERN_SET,
1042                                 &data);
1043                 if (retval < 0)
1044                         return retval;
1045
1046                 retval = rk32_edp_write_byte_to_dpcd(edp,
1047                                 DPCD_TRAINING_PATTERN_SET,
1048                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1049                 if (retval < 0)
1050                         return retval;
1051         }
1052
1053         return 0;
1054 }
1055
1056 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1057 {
1058         struct rk32_edp *edp = arg;
1059
1060         dev_info(edp->dev, "rk32_edp_isr\n");
1061         return IRQ_HANDLED;
1062 }
1063
1064 static int rk32_edp_enable(struct rk32_edp *edp)
1065 {
1066         int ret = 0;
1067         int retry = 0;
1068
1069         if (edp->enabled)
1070                 goto out;
1071
1072         edp->enabled = 1;
1073         clk_prepare_enable(edp->clk_edp);
1074         clk_prepare_enable(edp->clk_24m);
1075 edp_phy_init:
1076
1077
1078         rk32_edp_init_edp(edp);
1079
1080
1081         ret = rk32_edp_handle_edid(edp);
1082         if (ret) {
1083                 dev_err(edp->dev, "unable to handle edid\n");
1084                 goto out;
1085         }
1086
1087
1088         ret = rk32_edp_enable_scramble(edp, 0);
1089         if (ret) {
1090                 dev_err(edp->dev, "unable to set scramble\n");
1091                 goto out;
1092         }
1093
1094         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1095         if (ret) {
1096                 dev_err(edp->dev, "unable to set enhanced mode\n");
1097                 goto out;
1098         }
1099         rk32_edp_enable_enhanced_mode(edp, 0);
1100
1101        /* Link Training */
1102         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1103         if (ret) {
1104                 dev_err(edp->dev, "link train failed\n");
1105                 goto out;
1106         }
1107
1108         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1109         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1110
1111 #ifdef EDP_BIST_MODE
1112         rk32_edp_bist_cfg(edp);
1113 #else
1114         rk32_edp_init_video(edp);
1115         ret = rk32_edp_config_video(edp, &edp->video_info);
1116         if (ret) {
1117                 dev_err(edp->dev, "unable to config video\n");
1118                 goto out;
1119         }
1120 #endif
1121
1122         return 0;
1123
1124 out:
1125
1126         if (retry < 3) {
1127                 retry++;
1128                 goto edp_phy_init;
1129         }
1130
1131         dev_err(edp->dev, "DP LT exceeds max retry count");
1132
1133         return ret;
1134 }
1135
1136 static void rk32_edp_disable(struct rk32_edp *edp)
1137 {
1138         if (!edp->enabled)
1139                 return ;
1140
1141         edp->enabled = 0;
1142
1143         rk32_edp_reset(edp);
1144         rk32_edp_analog_power_ctr(edp, 0);
1145
1146         clk_disable(edp->clk_24m);
1147         clk_disable(edp->clk_edp);
1148 }
1149
1150
1151
1152 static void rk32_edp_init(struct rk32_edp *edp)
1153 {
1154
1155         rk32_edp_enable(edp);
1156 }
1157 static int rk32_edp_probe(struct platform_device *pdev)
1158 {
1159         struct rk32_edp *edp;
1160         struct resource *res;
1161         struct device_node *np = pdev->dev.of_node;
1162         int ret;
1163
1164         if (!np) {
1165                 dev_err(&pdev->dev, "Missing device tree node.\n");
1166                 return -EINVAL;
1167         }
1168
1169         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1170         if (!edp) {
1171                 dev_err(&pdev->dev, "no memory for state\n");
1172                 return -ENOMEM;
1173         }
1174         edp->dev = &pdev->dev;
1175         edp->video_info.h_sync_polarity = 0;
1176         edp->video_info.v_sync_polarity = 0;
1177         edp->video_info.interlaced      = 0;
1178         edp->video_info.color_space     = CS_RGB;
1179         edp->video_info.dynamic_range   = VESA;
1180         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1181         edp->video_info.color_depth     = COLOR_8;
1182
1183         edp->video_info.link_rate       = LINK_RATE_2_70GBPS;
1184         edp->video_info.lane_count      = LANE_CNT4;
1185         rk_fb_get_prmry_screen(&edp->screen);
1186         if (edp->screen.type != SCREEN_EDP) {
1187                 dev_err(&pdev->dev, "screen is not edp!\n");
1188                 return -EINVAL;
1189         }
1190         platform_set_drvdata(pdev, edp);
1191         dev_set_name(edp->dev, "rk32-edp");
1192
1193         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1194         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1195         if (IS_ERR(edp->regs)) {
1196                 dev_err(&pdev->dev, "ioremap reg failed\n");
1197                 return PTR_ERR(edp->regs);
1198         }
1199
1200
1201         edp->irq = platform_get_irq(pdev, 0);
1202         if (edp->irq < 0) {
1203                 dev_err(&pdev->dev, "cannot find IRQ\n");
1204                 return edp->irq;
1205         }
1206         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1207                         dev_name(&pdev->dev), edp);
1208         if (ret) {
1209                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1210                 return ret;
1211         }
1212
1213         rk32_edp_init(edp);
1214         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1215
1216         return 0;
1217 }
1218
1219 static void rk32_edp_shutdown(struct platform_device *pdev)
1220 {
1221
1222 }
1223
1224 #if defined(CONFIG_OF)
1225 static const struct of_device_id rk32_edp_dt_ids[] = {
1226         {.compatible = "rockchip, rk32-edp",},
1227         {}
1228 };
1229
1230 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1231 #endif
1232
1233 static struct platform_driver rk32_edp_driver = {
1234         .probe = rk32_edp_probe,
1235         .driver = {
1236                    .name = "rk32-edp",
1237                    .owner = THIS_MODULE,
1238 #if defined(CONFIG_OF)
1239                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1240 #endif
1241         },
1242         .shutdown = rk32_edp_shutdown,
1243 };
1244
1245 static int __init rk32_edp_module_init(void)
1246 {
1247         return platform_driver_register(&rk32_edp_driver);
1248 }
1249
1250 static void __exit rk32_edp_module_exit(void)
1251 {
1252
1253 }
1254
1255 fs_initcall(rk32_edp_module_init);
1256 module_exit(rk32_edp_module_exit);