drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include "rk32_dp.h"
  27 #include "../../../arch/arm/mach-rockchip/iomap.h"
  28 #include "../../../arch/arm/mach-rockchip/grf.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 /*#define EDP_BIST_MODE*/
  35
  36 static int rk32_edp_init_edp(struct rk32_edp *edp)
  37 {
  38         rk32_edp_reset(edp);
  39         rk32_edp_init_analog_param(edp);
  40         rk32_edp_init_interrupt(edp);
  41
  42         rk32_edp_enable_sw_function(edp);
  43
  44         rk32_edp_init_analog_func(edp);
  45
  46         rk32_edp_init_hpd(edp);
  47         rk32_edp_init_aux(edp);
  48
  49         return 0;
  50 }
  51
  52 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  53 {
  54         int timeout_loop = 0;
  55
  56         rk32_edp_init_hpd(edp);
  57
  58         udelay(200);
  59
  60         while (rk32_edp_get_plug_in_status(edp) != 0) {
  61                 timeout_loop++;
  62                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  63                         dev_err(edp->dev, "failed to get hpd plug status\n");
  64                         return -ETIMEDOUT;
  65                 }
  66                 udelay(10);
  67         }
  68
  69         return 0;
  70 }
  71
  72 static int rk32_edp_read_edid(struct rk32_edp *edp)
  73 {
  74         unsigned char edid[EDID_LENGTH * 2];
  75         unsigned int extend_block = 0;
  76         unsigned char sum;
  77         unsigned char test_vector;
  78         int retval;
  79
  80         /*
  81          * EDID device address is 0x50.
  82          * However, if necessary, you must have set upper address
  83          * into E-EDID in I2C device, 0x30.
  84          */
  85
  86         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  87         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
  88                                                 &extend_block);
  89         if (retval < 0) {
  90                 dev_err(edp->dev, "EDID extension flag failed!\n");
  91                 return -EIO;
  92         }
  93
  94         if (extend_block > 0) {
  95                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
  96
  97                 /* Read EDID data */
  98                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
  99                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 100                 if (retval != 0) {
 101                         dev_err(edp->dev, "EDID Read failed!\n");
 102                         return -EIO;
 103                 }
 104                 sum = edp_calc_edid_check_sum(edid);
 105                 if (sum != 0) {
 106                         dev_warn(edp->dev, "EDID bad checksum!\n");
 107                         return 0;
 108                 }
 109
 110                 /* Read additional EDID data */
 111                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 112                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 113                 if (retval != 0) {
 114                         dev_err(edp->dev, "EDID Read failed!\n");
 115                         return -EIO;
 116                 }
 117                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 118                 if (sum != 0) {
 119                         dev_warn(edp->dev, "EDID bad checksum!\n");
 120                         return 0;
 121                 }
 122
 123                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 124                                         &test_vector);
 125                 if (retval < 0) {
 126                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 127                         return retval;
 128                 }
 129
 130                 if (test_vector & DPCD_TEST_EDID_READ) {
 131                         retval = rk32_edp_write_byte_to_dpcd(edp,
 132                                         DPCD_TEST_EDID_CHECKSUM,
 133                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 134                         if (retval < 0) {
 135                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 136                                 return retval;
 137                         }
 138                         retval = rk32_edp_write_byte_to_dpcd(edp,
 139                                         DPCD_TEST_RESPONSE,
 140                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 141                         if (retval < 0) {
 142                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 143                                 return retval;
 144                         }
 145                 }
 146         } else {
 147                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 148
 149                 /* Read EDID data */
 150                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 151                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 152                 if (retval != 0) {
 153                         dev_err(edp->dev, "EDID Read failed!\n");
 154                         return -EIO;
 155                 }
 156                 sum = edp_calc_edid_check_sum(edid);
 157                 if (sum != 0) {
 158                         dev_warn(edp->dev, "EDID bad checksum!\n");
 159                         return 0;
 160                 }
 161
 162                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 163                                                 &test_vector);
 164                 if (retval < 0) {
 165                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 166                         return retval;
 167                 }
 168
 169                 if (test_vector & DPCD_TEST_EDID_READ) {
 170                         retval = rk32_edp_write_byte_to_dpcd(edp,
 171                                         DPCD_TEST_EDID_CHECKSUM,
 172                                         edid[EDID_CHECKSUM]);
 173                         if (retval < 0) {
 174                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 175                                 return retval;
 176                         }
 177                         retval = rk32_edp_write_byte_to_dpcd(edp,
 178                                         DPCD_TEST_RESPONSE,
 179                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 180                         if (retval < 0) {
 181                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 182                                 return retval;
 183                         }
 184                 }
 185         }
 186
 187         dev_err(edp->dev, "EDID Read success!\n");
 188         return 0;
 189 }
 190
 191 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 192 {
 193         u8 buf[12];
 194         int i;
 195         int retval;
 196
 197         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 198         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 199         if (retval < 0)
 200                 return retval;
 201
 202         /* Read EDID */
 203         for (i = 0; i < 3; i++) {
 204                 retval = rk32_edp_read_edid(edp);
 205                 if (retval == 0)
 206                         break;
 207         }
 208
 209         return retval;
 210 }
 211
 212 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 213                                                 bool enable)
 214 {
 215         u8 data;
 216         int retval;
 217
 218         retval = rk32_edp_read_byte_from_dpcd(edp,
 219                         DPCD_LANE_CNT_SET, &data);
 220         if (retval < 0)
 221                 return retval;
 222
 223         if (enable) {
 224                 retval = rk32_edp_write_byte_to_dpcd(edp,
 225                                 DPCD_LANE_CNT_SET,
 226                                 DPCD_ENHANCED_FRAME_EN |
 227                                 DPCD_LANE_COUNT_SET(data));
 228         } else {
 229                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 230                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 231
 232                 retval = rk32_edp_write_byte_to_dpcd(edp,
 233                                 DPCD_LANE_CNT_SET,
 234                                 DPCD_LANE_COUNT_SET(data));
 235         }
 236
 237         return retval;
 238 }
 239
 240 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 241 {
 242         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 243         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 244
 245         if (enable) {
 246                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 247                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 248         } else {
 249                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 250         }*/
 251 }
 252
 253 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 254 {
 255         u8 data;
 256         int retval;
 257
 258         retval = rk32_edp_read_byte_from_dpcd(edp,
 259                         DPCD_MAX_LANE_CNT, &data);
 260         if (retval < 0)
 261                 return retval;
 262
 263         return DPCD_ENHANCED_FRAME_CAP(data);
 264 }
 265
 266 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 267 {
 268         /*rk32_edp_write_byte_to_dpcd(edp,
 269                         DPCD_ADDR_USER_DEFINED1, 0);
 270         rk32_edp_write_byte_to_dpcd(edp,
 271                         DPCD_ADDR_USER_DEFINED2, 0x83);
 272         rk32_edp_write_byte_to_dpcd(edp,
 273                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 274 }
 275
 276 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 277 {
 278         u8 data;
 279         int retval;
 280
 281         retval = rk32_edp_is_enhanced_mode_available(edp);
 282         if (retval < 0)
 283                 return retval;
 284
 285         data = (u8)retval;
 286         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 287         if (retval < 0)
 288                 return retval;
 289
 290         rk32_edp_enable_enhanced_mode(edp, data);
 291
 292         return 0;
 293 }
 294
 295 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 296 {
 297         int retval;
 298
 299         rk32_edp_set_training_pattern(edp, DP_NONE);
 300
 301         retval = rk32_edp_write_byte_to_dpcd(edp,
 302                         DPCD_TRAINING_PATTERN_SET,
 303                         DPCD_TRAINING_PATTERN_DISABLED);
 304         if (retval < 0)
 305                 return retval;
 306
 307         return 0;
 308 }
 309
 310 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 311                                         int pre_emphasis, int lane)
 312 {
 313         switch (lane) {
 314         case 0:
 315                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 316                 break;
 317         case 1:
 318                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 319                 break;
 320
 321         case 2:
 322                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 323                 break;
 324
 325         case 3:
 326                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 327                 break;
 328         }
 329 }
 330
 331 static int rk32_edp_link_start(struct rk32_edp *edp)
 332 {
 333         u8 buf[4];
 334         int lane;
 335         int lane_count;
 336         int retval;
 337
 338         lane_count = edp->link_train.lane_count;
 339
 340         edp->link_train.lt_state = LT_CLK_RECOVERY;
 341         edp->link_train.eq_loop = 0;
 342
 343         for (lane = 0; lane < lane_count; lane++)
 344                 edp->link_train.cr_loop[lane] = 0;
 345
 346         /* Set sink to D0 (Sink Not Ready) mode. */
 347         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 348                                 DPCD_SET_POWER_STATE_D0);
 349         if (retval < 0) {
 350                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 351                 return retval;
 352         }
 353
 354         /* Set link rate and count as you want to establish*/
 355         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 356         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 357
 358         /* Setup RX configuration */
 359         buf[0] = edp->link_train.link_rate;
 360         buf[1] = edp->link_train.lane_count;
 361         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 362                                         2, buf);
 363         if (retval < 0) {
 364                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 365                 return retval;
 366         }
 367
 368         /* Set TX pre-emphasis to level1 */
 369         for (lane = 0; lane < lane_count; lane++)
 370                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 371                         PRE_EMPHASIS_LEVEL_1, lane);
 372
 373         /* Set training pattern 1 */
 374         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 375
 376         /* Set RX training pattern */
 377         retval = rk32_edp_write_byte_to_dpcd(edp,
 378                         DPCD_TRAINING_PATTERN_SET,
 379                         DPCD_SCRAMBLING_DISABLED |
 380                         DPCD_TRAINING_PATTERN_1);
 381         if (retval < 0) {
 382                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 383                 return retval;
 384         }
 385
 386         for (lane = 0; lane < lane_count; lane++)
 387                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 388                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 389         retval = rk32_edp_write_bytes_to_dpcd(edp,
 390                         DPCD_TRAINING_LANE0_SET,
 391                         lane_count, buf);
 392         if (retval < 0) {
 393                 dev_err(edp->dev, "failed to set training lane!\n");
 394                 return retval;
 395         }
 396
 397         return 0;
 398 }
 399
 400 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 401 {
 402         int shift = (lane & 1) * 4;
 403         u8 link_value = link_status[lane>>1];
 404
 405         return (link_value >> shift) & 0xf;
 406 }
 407
 408 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 409 {
 410         int lane;
 411         u8 lane_status;
 412
 413         for (lane = 0; lane < lane_count; lane++) {
 414                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 415                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 416                         return -EINVAL;
 417         }
 418         return 0;
 419 }
 420
 421 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 422 {
 423         int lane;
 424         u8 lane_align;
 425         u8 lane_status;
 426
 427         lane_align = link_align[2];
 428         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 429                 return -EINVAL;
 430
 431         for (lane = 0; lane < lane_count; lane++) {
 432                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 433                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 434                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 435                         return -EINVAL;
 436         }
 437
 438         return 0;
 439 }
 440
 441 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 442                                                         int lane)
 443 {
 444         int shift = (lane & 1) * 4;
 445         u8 link_value = adjust_request[lane>>1];
 446
 447         return (link_value >> shift) & 0x3;
 448 }
 449
 450 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 451                                         u8 adjust_request[2],
 452                                         int lane)
 453 {
 454         int shift = (lane & 1) * 4;
 455         u8 link_value = adjust_request[lane>>1];
 456
 457         return ((link_value >> shift) & 0xc) >> 2;
 458 }
 459
 460 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 461                                         u8 training_lane_set, int lane)
 462 {
 463         switch (lane) {
 464         case 0:
 465                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 466                 break;
 467         case 1:
 468                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 469                 break;
 470
 471         case 2:
 472                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 473                 break;
 474
 475         case 3:
 476                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 477                 break;
 478         }
 479 }
 480
 481 static unsigned int rk32_edp_get_lane_link_training(
 482                                 struct rk32_edp *edp,
 483                                 int lane)
 484 {
 485         u32 reg;
 486
 487         switch (lane) {
 488         case 0:
 489                 reg = rk32_edp_get_lane0_link_training(edp);
 490                 break;
 491         case 1:
 492                 reg = rk32_edp_get_lane1_link_training(edp);
 493                 break;
 494         case 2:
 495                 reg = rk32_edp_get_lane2_link_training(edp);
 496                 break;
 497         case 3:
 498                 reg = rk32_edp_get_lane3_link_training(edp);
 499                 break;
 500         }
 501
 502         return reg;
 503 }
 504
 505 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 506 {
 507         rk32_edp_training_pattern_dis(edp);
 508
 509         edp->link_train.lt_state = FAILED;
 510 }
 511
 512 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 513 {
 514         u8 link_status[2];
 515         int lane;
 516         int lane_count;
 517
 518         u8 adjust_request[2];
 519         u8 voltage_swing;
 520         u8 pre_emphasis;
 521         u8 training_lane;
 522         int retval;
 523
 524         udelay(100);
 525
 526         lane_count = edp->link_train.lane_count;
 527
 528         retval = rk32_edp_read_bytes_from_dpcd(edp,
 529                         DPCD_LANE0_1_STATUS,
 530                         2, link_status);
 531         if (retval < 0) {
 532                 dev_err(edp->dev, "failed to read lane status!\n");
 533                 return retval;
 534         }
 535
 536         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 537                 /* set training pattern 2 for EQ */
 538                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 539
 540                 for (lane = 0; lane < lane_count; lane++) {
 541                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 542                                         DPCD_ADJUST_REQUEST_LANE0_1,
 543                                         2, adjust_request);
 544                         if (retval < 0) {
 545                                 dev_err(edp->dev, "failed to read adjust request!\n");
 546                                 return retval;
 547                         }
 548
 549                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 550                                                         adjust_request, lane);
 551                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 552                                                         adjust_request, lane);
 553                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 554                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 555
 556                         if (voltage_swing == VOLTAGE_LEVEL_3)
 557                                 training_lane |= DPCD_MAX_SWING_REACHED;
 558                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 559                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 560
 561                         edp->link_train.training_lane[lane] = training_lane;
 562
 563                         rk32_edp_set_lane_link_training(edp,
 564                                 edp->link_train.training_lane[lane],
 565                                 lane);
 566                 }
 567
 568                 retval = rk32_edp_write_byte_to_dpcd(edp,
 569                                 DPCD_TRAINING_PATTERN_SET,
 570                                 DPCD_SCRAMBLING_DISABLED |
 571                                 DPCD_TRAINING_PATTERN_2);
 572                 if (retval < 0) {
 573                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 574                         return retval;
 575                 }
 576
 577                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 578                                 DPCD_TRAINING_LANE0_SET,
 579                                 lane_count,
 580                                 edp->link_train.training_lane);
 581                 if (retval < 0) {
 582                         dev_err(edp->dev, "failed to set training lane!\n");
 583                         return retval;
 584                 }
 585
 586                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 587                 edp->link_train.lt_state = LT_EQ_TRAINING;
 588         } else {
 589                 for (lane = 0; lane < lane_count; lane++) {
 590                         training_lane = rk32_edp_get_lane_link_training(
 591                                                         edp, lane);
 592                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 593                                         DPCD_ADJUST_REQUEST_LANE0_1,
 594                                         2, adjust_request);
 595                         if (retval < 0) {
 596                                 dev_err(edp->dev, "failed to read adjust request!\n");
 597                                 return retval;
 598                         }
 599
 600                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 601                                                         adjust_request, lane);
 602                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 603                                                         adjust_request, lane);
 604
 605                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 606                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 607                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 608                                 goto reduce_link_rate;
 609                         }
 610
 611                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 612                                         voltage_swing) &&
 613                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 614                                         pre_emphasis)) {
 615                                 edp->link_train.cr_loop[lane]++;
 616                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 617                                         dev_err(edp->dev, "CR Max loop\n");
 618                                         goto reduce_link_rate;
 619                                 }
 620                         }
 621
 622                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 623                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 624
 625                         if (voltage_swing == VOLTAGE_LEVEL_3)
 626                                 training_lane |= DPCD_MAX_SWING_REACHED;
 627                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 628                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 629
 630                         edp->link_train.training_lane[lane] = training_lane;
 631
 632                         rk32_edp_set_lane_link_training(edp,
 633                                 edp->link_train.training_lane[lane], lane);
 634                 }
 635
 636                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 637                                 DPCD_TRAINING_LANE0_SET,
 638                                 lane_count,
 639                                 edp->link_train.training_lane);
 640                 if (retval < 0) {
 641                         dev_err(edp->dev, "failed to set training lane!\n");
 642                         return retval;
 643                 }
 644         }
 645
 646         return 0;
 647
 648 reduce_link_rate:
 649         rk32_edp_reduce_link_rate(edp);
 650         return -EIO;
 651 }
 652
 653 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 654 {
 655         u8 link_status[2];
 656         u8 link_align[3];
 657         int lane;
 658         int lane_count;
 659         u32 reg;
 660
 661         u8 adjust_request[2];
 662         u8 voltage_swing;
 663         u8 pre_emphasis;
 664         u8 training_lane;
 665         int retval;
 666
 667         udelay(400);
 668
 669         lane_count = edp->link_train.lane_count;
 670
 671         retval = rk32_edp_read_bytes_from_dpcd(edp,
 672                         DPCD_LANE0_1_STATUS,
 673                         2, link_status);
 674         if (retval < 0) {
 675                 dev_err(edp->dev, "failed to read lane status!\n");
 676                 return retval;
 677         }
 678
 679         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 680                 link_align[0] = link_status[0];
 681                 link_align[1] = link_status[1];
 682
 683                 retval = rk32_edp_read_byte_from_dpcd(edp,
 684                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 685                                 &link_align[2]);
 686                 if (retval < 0) {
 687                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 688                         return retval;
 689                 }
 690
 691                 for (lane = 0; lane < lane_count; lane++) {
 692                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 693                                         DPCD_ADJUST_REQUEST_LANE0_1,
 694                                         2, adjust_request);
 695                         if (retval < 0) {
 696                                 dev_err(edp->dev, "failed to read adjust request!\n");
 697                                 return retval;
 698                         }
 699
 700                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 701                                                         adjust_request, lane);
 702                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 703                                                         adjust_request, lane);
 704                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 705                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 706
 707                         if (voltage_swing == VOLTAGE_LEVEL_3)
 708                                 training_lane |= DPCD_MAX_SWING_REACHED;
 709                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 710                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 711
 712                         edp->link_train.training_lane[lane] = training_lane;
 713                 }
 714
 715                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 716                         /* traing pattern Set to Normal */
 717                         retval = rk32_edp_training_pattern_dis(edp);
 718                         if (retval < 0) {
 719                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 720                                 return retval;
 721                         }
 722
 723                         dev_info(edp->dev, "Link Training success!\n");
 724
 725                         rk32_edp_get_link_bandwidth(edp, &reg);
 726                         edp->link_train.link_rate = reg;
 727                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 728                                 edp->link_train.link_rate);
 729
 730                         rk32_edp_get_lane_count(edp, &reg);
 731                         edp->link_train.lane_count = reg;
 732                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 733                                 edp->link_train.lane_count);
 734
 735                         edp->link_train.lt_state = FINISHED;
 736                 } else {
 737                         /* not all locked */
 738                         edp->link_train.eq_loop++;
 739
 740                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 741                                 dev_err(edp->dev, "EQ Max loop\n");
 742                                 goto reduce_link_rate;
 743                         }
 744
 745                         for (lane = 0; lane < lane_count; lane++)
 746                                 rk32_edp_set_lane_link_training(edp,
 747                                         edp->link_train.training_lane[lane],
 748                                         lane);
 749
 750                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 751                                         DPCD_TRAINING_LANE0_SET,
 752                                         lane_count,
 753                                         edp->link_train.training_lane);
 754                         if (retval < 0) {
 755                                 dev_err(edp->dev, "failed to set training lane!\n");
 756                                 return retval;
 757                         }
 758                 }
 759         } else {
 760                 goto reduce_link_rate;
 761         }
 762
 763         return 0;
 764
 765 reduce_link_rate:
 766         rk32_edp_reduce_link_rate(edp);
 767         return -EIO;
 768 }
 769
 770 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 771                                         u8 *bandwidth)
 772 {
 773         u8 data;
 774         int retval;
 775
 776         /*
 777          * For DP rev.1.1, Maximum link rate of Main Link lanes
 778          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 779          */
 780         retval = rk32_edp_read_byte_from_dpcd(edp,
 781                         DPCD_MAX_LINK_RATE, &data);
 782         if (retval < 0)
 783                 return retval;
 784
 785         *bandwidth = data;
 786         return 0;
 787 }
 788
 789 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 790                                         u8 *lane_count)
 791 {
 792         u8 data;
 793         int retval;
 794
 795         /*
 796          * For DP rev.1.1, Maximum number of Main Link lanes
 797          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 798          */
 799         retval = rk32_edp_read_byte_from_dpcd(edp,
 800                         DPCD_MAX_LANE_CNT, &data);
 801         if (retval < 0)
 802                 return retval;
 803
 804         *lane_count = DPCD_MAX_LANE_COUNT(data);
 805         return 0;
 806 }
 807
 808 static int rk32_edp_init_training(struct rk32_edp *edp,
 809                         enum link_lane_count_type max_lane,
 810                         u32 max_rate)
 811 {
 812         int retval;
 813
 814         /*
 815          * MACRO_RST must be applied after the PLL_LOCK to avoid
 816          * the DP inter pair skew issue for at least 10 us
 817          */
 818         rk32_edp_reset_macro(edp);
 819
 820
 821         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 822         if (retval < 0)
 823                 return retval;
 824
 825         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 826         if (retval < 0)
 827                 return retval;
 828         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 829                         edp->link_train.link_rate * 27/100,
 830                         edp->link_train.link_rate*27%100,
 831                         edp->link_train.lane_count);
 832
 833         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 834            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 835                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 836                         edp->link_train.link_rate);
 837                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 838         }
 839
 840         if (edp->link_train.lane_count == 0) {
 841                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 842                         edp->link_train.lane_count);
 843                 edp->link_train.lane_count = (u8)LANE_CNT1;
 844         }
 845
 846
 847         if (edp->link_train.lane_count > max_lane)
 848                 edp->link_train.lane_count = max_lane;
 849         if (edp->link_train.link_rate > max_rate)
 850                 edp->link_train.link_rate = max_rate;
 851
 852
 853         rk32_edp_analog_power_ctr(edp, 1);
 854
 855         return 0;
 856 }
 857
 858 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 859 {
 860         int retval = 0;
 861         int training_finished = 0;
 862
 863         edp->link_train.lt_state = LT_START;
 864
 865         /* Process here */
 866         while (!training_finished) {
 867                 switch (edp->link_train.lt_state) {
 868                 case LT_START:
 869                         retval = rk32_edp_link_start(edp);
 870                         if (retval)
 871                                 dev_err(edp->dev, "LT Start failed\n");
 872                         break;
 873                 case LT_CLK_RECOVERY:
 874                         retval = rk32_edp_process_clock_recovery(edp);
 875                         if (retval)
 876                                 dev_err(edp->dev, "LT CR failed\n");
 877                         break;
 878                 case LT_EQ_TRAINING:
 879                         retval = rk32_edp_process_equalizer_training(edp);
 880                         if (retval)
 881                                 dev_err(edp->dev, "LT EQ failed\n");
 882                         break;
 883                 case FINISHED:
 884                         training_finished = 1;
 885                         break;
 886                 case FAILED:
 887                         return -EREMOTEIO;
 888                 }
 889         }
 890
 891         return retval;
 892 }
 893
 894
 895 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 896 {
 897         u32 cnt = 50;
 898         u32 val;
 899         /* Set link rate and count as you want to establish*/
 900         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 901         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 902         rk32_edp_hw_link_training_en(edp);
 903         mdelay(1);
 904         val = rk32_edp_wait_hw_lt_done(edp);
 905         while (val) {
 906                 if (cnt-- <= 0) {
 907                         dev_err(edp->dev, "hw lt timeout");
 908                         return -ETIMEDOUT;
 909                 }
 910                 mdelay(1);
 911                 val = rk32_edp_wait_hw_lt_done(edp);
 912         }
 913
 914         val = rk32_edp_get_hw_lt_status(edp);
 915         if (val)
 916                 dev_err(edp->dev, "hw lt err:%d\n", val);
 917         return val;
 918
 919 }
 920 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 921                                 u32 count,
 922                                 u32 bwtype)
 923 {
 924         int retval;
 925
 926         retval = rk32_edp_init_training(edp, count, bwtype);
 927         if (retval < 0)
 928                 dev_err(edp->dev, "DP LT init failed!\n");
 929 #if 0
 930         retval = rk32_edp_sw_link_training(edp);
 931 #else
 932         retval = rk32_edp_hw_link_training(edp);
 933 #endif
 934
 935         return retval;
 936 }
 937
 938 static int rk32_edp_config_video(struct rk32_edp *edp,
 939                         struct video_info *video_info)
 940 {
 941         int retval = 0;
 942         int timeout_loop = 0;
 943         int done_count = 0;
 944
 945         rk32_edp_config_video_slave_mode(edp, video_info);
 946
 947         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 948                         video_info->color_space,
 949                         video_info->dynamic_range,
 950                         video_info->ycbcr_coeff);
 951
 952         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 953                 dev_err(edp->dev, "PLL is not locked yet.\n");
 954                 return -EINVAL;
 955         }
 956
 957         for (;;) {
 958                 timeout_loop++;
 959                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 960                         break;
 961                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 962                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 963                         return -ETIMEDOUT;
 964                 }
 965
 966                 usleep_range(1, 1);
 967         }
 968
 969         /* Set to use the register calculated M/N video */
 970         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 971
 972         /* For video bist, Video timing must be generated by register */
 973         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 974
 975         /* Disable video mute */
 976         rk32_edp_enable_video_mute(edp, 0);
 977
 978         /* Configure video slave mode */
 979         rk32_edp_enable_video_master(edp, 0);
 980
 981         /* Enable video */
 982         rk32_edp_start_video(edp);
 983
 984         timeout_loop = 0;
 985
 986         for (;;) {
 987                 timeout_loop++;
 988                 if (rk32_edp_is_video_stream_on(edp) == 0) {
 989                         done_count++;
 990                         if (done_count > 10)
 991                                 break;
 992                 } else if (done_count) {
 993                         done_count = 0;
 994                 }
 995                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 996                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 997                         return -ETIMEDOUT;
 998                 }
 999
1000                 usleep_range(1000, 1000);
1001         }
1002
1003         if (retval != 0)
1004                 dev_err(edp->dev, "Video stream is not detected!\n");
1005
1006         return retval;
1007 }
1008
1009 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1010 {
1011         u8 data;
1012         int retval;
1013
1014         if (enable) {
1015                 rk32_edp_enable_scrambling(edp);
1016
1017                 retval = rk32_edp_read_byte_from_dpcd(edp,
1018                                 DPCD_TRAINING_PATTERN_SET,
1019                                 &data);
1020                 if (retval < 0)
1021                         return retval;
1022
1023                 retval = rk32_edp_write_byte_to_dpcd(edp,
1024                                 DPCD_TRAINING_PATTERN_SET,
1025                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1026                 if (retval < 0)
1027                         return retval;
1028         } else {
1029                 rk32_edp_disable_scrambling(edp);
1030
1031                 retval = rk32_edp_read_byte_from_dpcd(edp,
1032                                 DPCD_TRAINING_PATTERN_SET,
1033                                 &data);
1034                 if (retval < 0)
1035                         return retval;
1036
1037                 retval = rk32_edp_write_byte_to_dpcd(edp,
1038                                 DPCD_TRAINING_PATTERN_SET,
1039                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1040                 if (retval < 0)
1041                         return retval;
1042         }
1043
1044         return 0;
1045 }
1046
1047 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1048 {
1049         struct rk32_edp *edp = arg;
1050
1051         dev_info(edp->dev, "rk32_edp_isr\n");
1052         return IRQ_HANDLED;
1053 }
1054
1055 static int rk32_edp_enable(struct rk32_edp *edp)
1056 {
1057         int ret = 0;
1058         int retry = 0;
1059
1060         if (edp->enabled)
1061                 goto out;
1062
1063         edp->enabled = 1;
1064         clk_prepare_enable(edp->clk_edp);
1065         clk_prepare_enable(edp->clk_24m);
1066 edp_phy_init:
1067
1068
1069         rk32_edp_init_edp(edp);
1070
1071
1072         ret = rk32_edp_handle_edid(edp);
1073         if (ret) {
1074                 dev_err(edp->dev, "unable to handle edid\n");
1075                 goto out;
1076         }
1077
1078         rk32_edp_disable_rx_zmux(edp);
1079
1080
1081         ret = rk32_edp_enable_scramble(edp, 0);
1082         if (ret) {
1083                 dev_err(edp->dev, "unable to set scramble\n");
1084                 goto out;
1085         }
1086
1087         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1088         if (ret) {
1089                 dev_err(edp->dev, "unable to set enhanced mode\n");
1090                 goto out;
1091         }
1092         rk32_edp_enable_enhanced_mode(edp, 0);
1093
1094
1095         rk32_edp_rx_control(edp,0);
1096
1097        /* Link Training */
1098         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1099         if (ret) {
1100                 dev_err(edp->dev, "link train failed\n");
1101                 goto out;
1102         }
1103
1104         /* Rx data enable */
1105         rk32_edp_rx_control(edp,1);
1106
1107         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1108         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1109
1110 #ifdef EDP_BIST_MODE
1111         rk32_edp_bist_cfg(edp);
1112 #else
1113         rk32_edp_init_video(edp);
1114         ret = rk32_edp_config_video(edp, &edp->video_info);
1115         if (ret) {
1116                 dev_err(edp->dev, "unable to config video\n");
1117                 goto out;
1118         }
1119 #endif
1120
1121         return 0;
1122
1123 out:
1124
1125         if (retry < 3) {
1126                 retry++;
1127                 goto edp_phy_init;
1128         }
1129
1130         dev_err(edp->dev, "DP LT exceeds max retry count");
1131
1132         return ret;
1133 }
1134
1135 static void rk32_edp_disable(struct rk32_edp *edp)
1136 {
1137         if (!edp->enabled)
1138                 return ;
1139
1140         edp->enabled = 0;
1141
1142         rk32_edp_reset(edp);
1143         rk32_edp_analog_power_ctr(edp, 0);
1144
1145         clk_disable(edp->clk_24m);
1146         clk_disable(edp->clk_edp);
1147 }
1148
1149
1150
1151 static void rk32_edp_init(struct rk32_edp *edp)
1152 {
1153
1154         rk32_edp_enable(edp);
1155 }
1156 static int rk32_edp_probe(struct platform_device *pdev)
1157 {
1158         struct rk32_edp *edp;
1159         struct resource *res;
1160         struct device_node *np = pdev->dev.of_node;
1161         int ret;
1162
1163         if (!np) {
1164                 dev_err(&pdev->dev, "Missing device tree node.\n");
1165                 return -EINVAL;
1166         }
1167
1168         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1169         if (!edp) {
1170                 dev_err(&pdev->dev, "no memory for state\n");
1171                 return -ENOMEM;
1172         }
1173         edp->dev = &pdev->dev;
1174         edp->video_info.h_sync_polarity = 0;
1175         edp->video_info.v_sync_polarity = 0;
1176         edp->video_info.interlaced      = 0;
1177         edp->video_info.color_space     = CS_RGB;
1178         edp->video_info.dynamic_range   = VESA;
1179         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1180         edp->video_info.color_depth     = COLOR_8;
1181
1182         edp->video_info.link_rate       = LINK_RATE_2_70GBPS;
1183         edp->video_info.lane_count      = LANE_CNT4;
1184         rk_fb_get_prmry_screen(&edp->screen);
1185         if (edp->screen.type != SCREEN_EDP) {
1186                 dev_err(&pdev->dev, "screen is not edp!\n");
1187                 return -EINVAL;
1188         }
1189         platform_set_drvdata(pdev, edp);
1190         dev_set_name(edp->dev, "rk32-edp");
1191         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1193         if (IS_ERR(edp->regs)) {
1194                 dev_err(&pdev->dev, "ioremap reg failed\n");
1195                 return PTR_ERR(edp->regs);
1196         }
1197         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1198                         dev_name(&pdev->dev), edp);
1199         if (ret) {
1200                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1201                 return ret;
1202         }
1203
1204         rk32_edp_init(edp);
1205         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1206
1207         return 0;
1208 }
1209
1210 static void rk32_edp_shutdown(struct platform_device *pdev)
1211 {
1212
1213 }
1214
1215 #if defined(CONFIG_OF)
1216 static const struct of_device_id rk32_edp_dt_ids[] = {
1217         {.compatible = "rockchip, rk32-edp",},
1218         {}
1219 };
1220
1221 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1222 #endif
1223
1224 static struct platform_driver rk32_edp_driver = {
1225         .probe = rk32_edp_probe,
1226         .driver = {
1227                    .name = "rk32-edp",
1228                    .owner = THIS_MODULE,
1229 #if defined(CONFIG_OF)
1230                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1231 #endif
1232         },
1233         .shutdown = rk32_edp_shutdown,
1234 };
1235
1236 static int __init rk32_edp_module_init(void)
1237 {
1238         return platform_driver_register(&rk32_edp_driver);
1239 }
1240
1241 static void __exit rk32_edp_module_exit(void)
1242 {
1243
1244 }
1245
1246 fs_initcall(rk32_edp_module_init);
1247 module_exit(rk32_edp_module_exit);