drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 //#define EDP_BIST_MODE
  35
  36 static struct rk32_edp *rk32_edp;
  37 static int rk32_edp_init_edp(struct rk32_edp *edp)
  38 {
  39         struct rk_screen *screen = &edp->screen;
  40         u32 val = 0;
  41
  42         screen->lcdc_id = 1;
  43         if (screen->lcdc_id == 1)  /*select lcdc*/
  44                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  45         else
  46                 val = EDP_SEL_VOP_LIT << 16;
  47         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  48
  49         val = GRF_EDP_REF_CLK_SEL_INTER |
  50                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  51         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  52
  53         val = 0x80008000;
  54         writel_relaxed(val, RK_CRU_VIRT + 0x0d0);
  55
  56         rk32_edp_reset(edp);
  57         rk32_edp_init_refclk(edp);
  58         rk32_edp_init_interrupt(edp);
  59
  60         rk32_edp_enable_sw_function(edp);
  61
  62         rk32_edp_init_analog_func(edp);
  63
  64         rk32_edp_init_hpd(edp);
  65         rk32_edp_init_aux(edp);
  66
  67         return 0;
  68 }
  69
  70 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  71 {
  72         int timeout_loop = 0;
  73
  74         rk32_edp_init_hpd(edp);
  75
  76         udelay(200);
  77
  78         while (rk32_edp_get_plug_in_status(edp) != 0) {
  79                 timeout_loop++;
  80                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  81                         dev_err(edp->dev, "failed to get hpd plug status\n");
  82                         return -ETIMEDOUT;
  83                 }
  84                 udelay(10);
  85         }
  86
  87         return 0;
  88 }
  89
  90 static int rk32_edp_read_edid(struct rk32_edp *edp)
  91 {
  92         unsigned char edid[EDID_LENGTH * 2];
  93         unsigned int extend_block = 0;
  94         unsigned char sum;
  95         unsigned char test_vector;
  96         int retval;
  97
  98         /*
  99          * EDID device address is 0x50.
 100          * However, if necessary, you must have set upper address
 101          * into E-EDID in I2C device, 0x30.
 102          */
 103
 104         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 105         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 106                                                 &extend_block);
 107         if (retval < 0) {
 108                 dev_err(edp->dev, "EDID extension flag failed!\n");
 109                 return -EIO;
 110         }
 111
 112         if (extend_block > 0) {
 113                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 114
 115                 /* Read EDID data */
 116                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 117                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 118                 if (retval != 0) {
 119                         dev_err(edp->dev, "EDID Read failed!\n");
 120                         return -EIO;
 121                 }
 122                 sum = edp_calc_edid_check_sum(edid);
 123                 if (sum != 0) {
 124                         dev_warn(edp->dev, "EDID bad checksum!\n");
 125                         return 0;
 126                 }
 127
 128                 /* Read additional EDID data */
 129                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 130                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 131                 if (retval != 0) {
 132                         dev_err(edp->dev, "EDID Read failed!\n");
 133                         return -EIO;
 134                 }
 135                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 136                 if (sum != 0) {
 137                         dev_warn(edp->dev, "EDID bad checksum!\n");
 138                         return 0;
 139                 }
 140
 141                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 142                                         &test_vector);
 143                 if (retval < 0) {
 144                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 145                         return retval;
 146                 }
 147
 148                 if (test_vector & DPCD_TEST_EDID_READ) {
 149                         retval = rk32_edp_write_byte_to_dpcd(edp,
 150                                         DPCD_TEST_EDID_CHECKSUM,
 151                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 152                         if (retval < 0) {
 153                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 154                                 return retval;
 155                         }
 156                         retval = rk32_edp_write_byte_to_dpcd(edp,
 157                                         DPCD_TEST_RESPONSE,
 158                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 159                         if (retval < 0) {
 160                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 161                                 return retval;
 162                         }
 163                 }
 164         } else {
 165                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 166
 167                 /* Read EDID data */
 168                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 169                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 170                 if (retval != 0) {
 171                         dev_err(edp->dev, "EDID Read failed!\n");
 172                         return -EIO;
 173                 }
 174                 sum = edp_calc_edid_check_sum(edid);
 175                 if (sum != 0) {
 176                         dev_warn(edp->dev, "EDID bad checksum!\n");
 177                         return 0;
 178                 }
 179
 180                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 181                                                 &test_vector);
 182                 if (retval < 0) {
 183                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 184                         return retval;
 185                 }
 186
 187                 if (test_vector & DPCD_TEST_EDID_READ) {
 188                         retval = rk32_edp_write_byte_to_dpcd(edp,
 189                                         DPCD_TEST_EDID_CHECKSUM,
 190                                         edid[EDID_CHECKSUM]);
 191                         if (retval < 0) {
 192                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 193                                 return retval;
 194                         }
 195                         retval = rk32_edp_write_byte_to_dpcd(edp,
 196                                         DPCD_TEST_RESPONSE,
 197                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 198                         if (retval < 0) {
 199                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 200                                 return retval;
 201                         }
 202                 }
 203         }
 204         fb_edid_to_monspecs(edid, &edp->specs);
 205         dev_err(edp->dev, "EDID Read success!\n");
 206         return 0;
 207 }
 208
 209 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 210 {
 211         u8 buf[12];
 212         int i;
 213         int retval;
 214
 215         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 216         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 217         if (retval < 0)
 218                 return retval;
 219
 220         for (i=0 ;i < 12; i++)
 221                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 222         /* Read EDID */
 223         for (i = 0; i < 3; i++) {
 224                 retval = rk32_edp_read_edid(edp);
 225                 if (retval == 0)
 226                         break;
 227         }
 228
 229         return retval;
 230 }
 231
 232 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 233                                                 bool enable)
 234 {
 235         u8 data;
 236         int retval;
 237
 238         retval = rk32_edp_read_byte_from_dpcd(edp,
 239                         DPCD_LANE_CNT_SET, &data);
 240         if (retval < 0)
 241                 return retval;
 242
 243         if (enable) {
 244                 retval = rk32_edp_write_byte_to_dpcd(edp,
 245                                 DPCD_LANE_CNT_SET,
 246                                 DPCD_ENHANCED_FRAME_EN |
 247                                 DPCD_LANE_COUNT_SET(data));
 248         } else {
 249                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 250                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 251
 252                 retval = rk32_edp_write_byte_to_dpcd(edp,
 253                                 DPCD_LANE_CNT_SET,
 254                                 DPCD_LANE_COUNT_SET(data));
 255         }
 256
 257         return retval;
 258 }
 259
 260 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 261 {
 262         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 263         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 264
 265         if (enable) {
 266                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 267                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 268         } else {
 269                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 270         }*/
 271 }
 272
 273 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 274 {
 275         u8 data;
 276         int retval;
 277
 278         retval = rk32_edp_read_byte_from_dpcd(edp,
 279                         DPCD_MAX_LANE_CNT, &data);
 280         if (retval < 0)
 281                 return retval;
 282
 283         return DPCD_ENHANCED_FRAME_CAP(data);
 284 }
 285
 286 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 287 {
 288         /*rk32_edp_write_byte_to_dpcd(edp,
 289                         DPCD_ADDR_USER_DEFINED1, 0);
 290         rk32_edp_write_byte_to_dpcd(edp,
 291                         DPCD_ADDR_USER_DEFINED2, 0x83);
 292         rk32_edp_write_byte_to_dpcd(edp,
 293                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 294 }
 295
 296 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 297 {
 298         u8 data;
 299         int retval;
 300
 301         retval = rk32_edp_is_enhanced_mode_available(edp);
 302         if (retval < 0)
 303                 return retval;
 304
 305         data = (u8)retval;
 306         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 307         if (retval < 0)
 308                 return retval;
 309
 310         rk32_edp_enable_enhanced_mode(edp, data);
 311
 312         return 0;
 313 }
 314
 315 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 316 {
 317         int retval;
 318
 319         rk32_edp_set_training_pattern(edp, DP_NONE);
 320
 321         retval = rk32_edp_write_byte_to_dpcd(edp,
 322                         DPCD_TRAINING_PATTERN_SET,
 323                         DPCD_TRAINING_PATTERN_DISABLED);
 324         if (retval < 0)
 325                 return retval;
 326
 327         return 0;
 328 }
 329
 330 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 331                                         int pre_emphasis, int lane)
 332 {
 333         switch (lane) {
 334         case 0:
 335                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 336                 break;
 337         case 1:
 338                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 339                 break;
 340
 341         case 2:
 342                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 343                 break;
 344
 345         case 3:
 346                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 347                 break;
 348         }
 349 }
 350
 351 static int rk32_edp_link_start(struct rk32_edp *edp)
 352 {
 353         u8 buf[4];
 354         int lane;
 355         int lane_count;
 356         int retval;
 357
 358         lane_count = edp->link_train.lane_count;
 359
 360         edp->link_train.lt_state = LT_CLK_RECOVERY;
 361         edp->link_train.eq_loop = 0;
 362
 363         for (lane = 0; lane < lane_count; lane++)
 364                 edp->link_train.cr_loop[lane] = 0;
 365
 366         /* Set sink to D0 (Sink Not Ready) mode. */
 367         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 368                                 DPCD_SET_POWER_STATE_D0);
 369         if (retval < 0) {
 370                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 371                 return retval;
 372         }
 373
 374         /* Set link rate and count as you want to establish*/
 375         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 376         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 377
 378         /* Setup RX configuration */
 379         buf[0] = edp->link_train.link_rate;
 380         buf[1] = edp->link_train.lane_count;
 381         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 382                                         2, buf);
 383         if (retval < 0) {
 384                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 385                 return retval;
 386         }
 387
 388         /* Set TX pre-emphasis to level1 */
 389         for (lane = 0; lane < lane_count; lane++)
 390                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 391                         PRE_EMPHASIS_LEVEL_1, lane);
 392
 393         /* Set training pattern 1 */
 394         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 395
 396         /* Set RX training pattern */
 397         retval = rk32_edp_write_byte_to_dpcd(edp,
 398                         DPCD_TRAINING_PATTERN_SET,
 399                         DPCD_SCRAMBLING_DISABLED |
 400                         DPCD_TRAINING_PATTERN_1);
 401         if (retval < 0) {
 402                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 403                 return retval;
 404         }
 405
 406         for (lane = 0; lane < lane_count; lane++)
 407                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 408                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 409         retval = rk32_edp_write_bytes_to_dpcd(edp,
 410                         DPCD_TRAINING_LANE0_SET,
 411                         lane_count, buf);
 412         if (retval < 0) {
 413                 dev_err(edp->dev, "failed to set training lane!\n");
 414                 return retval;
 415         }
 416
 417         return 0;
 418 }
 419
 420 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 421 {
 422         int shift = (lane & 1) * 4;
 423         u8 link_value = link_status[lane>>1];
 424
 425         return (link_value >> shift) & 0xf;
 426 }
 427
 428 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 429 {
 430         int lane;
 431         u8 lane_status;
 432
 433         for (lane = 0; lane < lane_count; lane++) {
 434                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 435                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 436                         return -EINVAL;
 437         }
 438         return 0;
 439 }
 440
 441 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 442 {
 443         int lane;
 444         u8 lane_align;
 445         u8 lane_status;
 446
 447         lane_align = link_align[2];
 448         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 449                 return -EINVAL;
 450
 451         for (lane = 0; lane < lane_count; lane++) {
 452                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 453                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 454                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 455                         return -EINVAL;
 456         }
 457
 458         return 0;
 459 }
 460
 461 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 462                                                         int lane)
 463 {
 464         int shift = (lane & 1) * 4;
 465         u8 link_value = adjust_request[lane>>1];
 466
 467         return (link_value >> shift) & 0x3;
 468 }
 469
 470 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 471                                         u8 adjust_request[2],
 472                                         int lane)
 473 {
 474         int shift = (lane & 1) * 4;
 475         u8 link_value = adjust_request[lane>>1];
 476
 477         return ((link_value >> shift) & 0xc) >> 2;
 478 }
 479
 480 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 481                                         u8 training_lane_set, int lane)
 482 {
 483         switch (lane) {
 484         case 0:
 485                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 486                 break;
 487         case 1:
 488                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 489                 break;
 490
 491         case 2:
 492                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 493                 break;
 494
 495         case 3:
 496                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 497                 break;
 498         }
 499 }
 500
 501 static unsigned int rk32_edp_get_lane_link_training(
 502                                 struct rk32_edp *edp,
 503                                 int lane)
 504 {
 505         u32 reg;
 506
 507         switch (lane) {
 508         case 0:
 509                 reg = rk32_edp_get_lane0_link_training(edp);
 510                 break;
 511         case 1:
 512                 reg = rk32_edp_get_lane1_link_training(edp);
 513                 break;
 514         case 2:
 515                 reg = rk32_edp_get_lane2_link_training(edp);
 516                 break;
 517         case 3:
 518                 reg = rk32_edp_get_lane3_link_training(edp);
 519                 break;
 520         }
 521
 522         return reg;
 523 }
 524
 525 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 526 {
 527         rk32_edp_training_pattern_dis(edp);
 528
 529         edp->link_train.lt_state = FAILED;
 530 }
 531
 532 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 533 {
 534         u8 link_status[2];
 535         int lane;
 536         int lane_count;
 537
 538         u8 adjust_request[2];
 539         u8 voltage_swing;
 540         u8 pre_emphasis;
 541         u8 training_lane;
 542         int retval;
 543
 544         udelay(100);
 545
 546         lane_count = edp->link_train.lane_count;
 547
 548         retval = rk32_edp_read_bytes_from_dpcd(edp,
 549                         DPCD_LANE0_1_STATUS,
 550                         2, link_status);
 551         if (retval < 0) {
 552                 dev_err(edp->dev, "failed to read lane status!\n");
 553                 return retval;
 554         }
 555
 556         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 557                 /* set training pattern 2 for EQ */
 558                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 559
 560                 for (lane = 0; lane < lane_count; lane++) {
 561                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 562                                         DPCD_ADJUST_REQUEST_LANE0_1,
 563                                         2, adjust_request);
 564                         if (retval < 0) {
 565                                 dev_err(edp->dev, "failed to read adjust request!\n");
 566                                 return retval;
 567                         }
 568
 569                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 570                                                         adjust_request, lane);
 571                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 572                                                         adjust_request, lane);
 573                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 574                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 575
 576                         if (voltage_swing == VOLTAGE_LEVEL_3)
 577                                 training_lane |= DPCD_MAX_SWING_REACHED;
 578                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 579                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 580
 581                         edp->link_train.training_lane[lane] = training_lane;
 582
 583                         rk32_edp_set_lane_link_training(edp,
 584                                 edp->link_train.training_lane[lane],
 585                                 lane);
 586                 }
 587
 588                 retval = rk32_edp_write_byte_to_dpcd(edp,
 589                                 DPCD_TRAINING_PATTERN_SET,
 590                                 DPCD_SCRAMBLING_DISABLED |
 591                                 DPCD_TRAINING_PATTERN_2);
 592                 if (retval < 0) {
 593                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 594                         return retval;
 595                 }
 596
 597                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 598                                 DPCD_TRAINING_LANE0_SET,
 599                                 lane_count,
 600                                 edp->link_train.training_lane);
 601                 if (retval < 0) {
 602                         dev_err(edp->dev, "failed to set training lane!\n");
 603                         return retval;
 604                 }
 605
 606                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 607                 edp->link_train.lt_state = LT_EQ_TRAINING;
 608         } else {
 609                 for (lane = 0; lane < lane_count; lane++) {
 610                         training_lane = rk32_edp_get_lane_link_training(
 611                                                         edp, lane);
 612                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 613                                         DPCD_ADJUST_REQUEST_LANE0_1,
 614                                         2, adjust_request);
 615                         if (retval < 0) {
 616                                 dev_err(edp->dev, "failed to read adjust request!\n");
 617                                 return retval;
 618                         }
 619
 620                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 621                                                         adjust_request, lane);
 622                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 623                                                         adjust_request, lane);
 624
 625                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 626                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 627                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 628                                 goto reduce_link_rate;
 629                         }
 630
 631                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 632                                         voltage_swing) &&
 633                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 634                                         pre_emphasis)) {
 635                                 edp->link_train.cr_loop[lane]++;
 636                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 637                                         dev_err(edp->dev, "CR Max loop\n");
 638                                         goto reduce_link_rate;
 639                                 }
 640                         }
 641
 642                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 643                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 644
 645                         if (voltage_swing == VOLTAGE_LEVEL_3)
 646                                 training_lane |= DPCD_MAX_SWING_REACHED;
 647                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 648                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 649
 650                         edp->link_train.training_lane[lane] = training_lane;
 651
 652                         rk32_edp_set_lane_link_training(edp,
 653                                 edp->link_train.training_lane[lane], lane);
 654                 }
 655
 656                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 657                                 DPCD_TRAINING_LANE0_SET,
 658                                 lane_count,
 659                                 edp->link_train.training_lane);
 660                 if (retval < 0) {
 661                         dev_err(edp->dev, "failed to set training lane!\n");
 662                         return retval;
 663                 }
 664         }
 665
 666         return 0;
 667
 668 reduce_link_rate:
 669         rk32_edp_reduce_link_rate(edp);
 670         return -EIO;
 671 }
 672
 673 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 674 {
 675         u8 link_status[2];
 676         u8 link_align[3];
 677         int lane;
 678         int lane_count;
 679         u32 reg;
 680
 681         u8 adjust_request[2];
 682         u8 voltage_swing;
 683         u8 pre_emphasis;
 684         u8 training_lane;
 685         int retval;
 686
 687         udelay(400);
 688
 689         lane_count = edp->link_train.lane_count;
 690
 691         retval = rk32_edp_read_bytes_from_dpcd(edp,
 692                         DPCD_LANE0_1_STATUS,
 693                         2, link_status);
 694         if (retval < 0) {
 695                 dev_err(edp->dev, "failed to read lane status!\n");
 696                 return retval;
 697         }
 698
 699         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 700                 link_align[0] = link_status[0];
 701                 link_align[1] = link_status[1];
 702
 703                 retval = rk32_edp_read_byte_from_dpcd(edp,
 704                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 705                                 &link_align[2]);
 706                 if (retval < 0) {
 707                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 708                         return retval;
 709                 }
 710
 711                 for (lane = 0; lane < lane_count; lane++) {
 712                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 713                                         DPCD_ADJUST_REQUEST_LANE0_1,
 714                                         2, adjust_request);
 715                         if (retval < 0) {
 716                                 dev_err(edp->dev, "failed to read adjust request!\n");
 717                                 return retval;
 718                         }
 719
 720                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 721                                                         adjust_request, lane);
 722                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 723                                                         adjust_request, lane);
 724                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 725                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 726
 727                         if (voltage_swing == VOLTAGE_LEVEL_3)
 728                                 training_lane |= DPCD_MAX_SWING_REACHED;
 729                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 730                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 731
 732                         edp->link_train.training_lane[lane] = training_lane;
 733                 }
 734
 735                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 736                         /* traing pattern Set to Normal */
 737                         retval = rk32_edp_training_pattern_dis(edp);
 738                         if (retval < 0) {
 739                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 740                                 return retval;
 741                         }
 742
 743                         dev_info(edp->dev, "Link Training success!\n");
 744
 745                         rk32_edp_get_link_bandwidth(edp, &reg);
 746                         edp->link_train.link_rate = reg;
 747                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 748                                 edp->link_train.link_rate);
 749
 750                         rk32_edp_get_lane_count(edp, &reg);
 751                         edp->link_train.lane_count = reg;
 752                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 753                                 edp->link_train.lane_count);
 754
 755                         edp->link_train.lt_state = FINISHED;
 756                 } else {
 757                         /* not all locked */
 758                         edp->link_train.eq_loop++;
 759
 760                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 761                                 dev_err(edp->dev, "EQ Max loop\n");
 762                                 goto reduce_link_rate;
 763                         }
 764
 765                         for (lane = 0; lane < lane_count; lane++)
 766                                 rk32_edp_set_lane_link_training(edp,
 767                                         edp->link_train.training_lane[lane],
 768                                         lane);
 769
 770                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 771                                         DPCD_TRAINING_LANE0_SET,
 772                                         lane_count,
 773                                         edp->link_train.training_lane);
 774                         if (retval < 0) {
 775                                 dev_err(edp->dev, "failed to set training lane!\n");
 776                                 return retval;
 777                         }
 778                 }
 779         } else {
 780                 goto reduce_link_rate;
 781         }
 782
 783         return 0;
 784
 785 reduce_link_rate:
 786         rk32_edp_reduce_link_rate(edp);
 787         return -EIO;
 788 }
 789
 790 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 791                                         u8 *bandwidth)
 792 {
 793         u8 data;
 794         int retval;
 795
 796         /*
 797          * For DP rev.1.1, Maximum link rate of Main Link lanes
 798          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 799          */
 800         retval = rk32_edp_read_byte_from_dpcd(edp,
 801                         DPCD_MAX_LINK_RATE, &data);
 802         if (retval < 0)
 803                 return retval;
 804
 805         *bandwidth = data;
 806         return 0;
 807 }
 808
 809 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 810                                         u8 *lane_count)
 811 {
 812         u8 data;
 813         int retval;
 814
 815         /*
 816          * For DP rev.1.1, Maximum number of Main Link lanes
 817          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 818          */
 819         retval = rk32_edp_read_byte_from_dpcd(edp,
 820                         DPCD_MAX_LANE_CNT, &data);
 821         if (retval < 0)
 822                 return retval;
 823
 824         *lane_count = DPCD_MAX_LANE_COUNT(data);
 825         return 0;
 826 }
 827
 828 static int rk32_edp_init_training(struct rk32_edp *edp,
 829                         enum link_lane_count_type max_lane,
 830                         u32 max_rate)
 831 {
 832         int retval;
 833
 834         /*
 835          * MACRO_RST must be applied after the PLL_LOCK to avoid
 836          * the DP inter pair skew issue for at least 10 us
 837          */
 838         rk32_edp_reset_macro(edp);
 839
 840
 841         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 842         if (retval < 0)
 843                 return retval;
 844
 845         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 846         if (retval < 0)
 847                 return retval;
 848         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 849                         edp->link_train.link_rate * 27/100,
 850                         edp->link_train.link_rate*27%100,
 851                         edp->link_train.lane_count);
 852
 853         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 854            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 855                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 856                         edp->link_train.link_rate);
 857                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 858         }
 859
 860         if (edp->link_train.lane_count == 0) {
 861                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 862                         edp->link_train.lane_count);
 863                 edp->link_train.lane_count = (u8)LANE_CNT1;
 864         }
 865
 866
 867         if (edp->link_train.lane_count > max_lane)
 868                 edp->link_train.lane_count = max_lane;
 869         if (edp->link_train.link_rate > max_rate)
 870                 edp->link_train.link_rate = max_rate;
 871
 872
 873         rk32_edp_analog_power_ctr(edp, 1);
 874
 875         return 0;
 876 }
 877
 878 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 879 {
 880         int retval = 0;
 881         int training_finished = 0;
 882
 883         edp->link_train.lt_state = LT_START;
 884
 885         /* Process here */
 886         while (!training_finished) {
 887                 switch (edp->link_train.lt_state) {
 888                 case LT_START:
 889                         retval = rk32_edp_link_start(edp);
 890                         if (retval)
 891                                 dev_err(edp->dev, "LT Start failed\n");
 892                         break;
 893                 case LT_CLK_RECOVERY:
 894                         retval = rk32_edp_process_clock_recovery(edp);
 895                         if (retval)
 896                                 dev_err(edp->dev, "LT CR failed\n");
 897                         break;
 898                 case LT_EQ_TRAINING:
 899                         retval = rk32_edp_process_equalizer_training(edp);
 900                         if (retval)
 901                                 dev_err(edp->dev, "LT EQ failed\n");
 902                         break;
 903                 case FINISHED:
 904                         training_finished = 1;
 905                         break;
 906                 case FAILED:
 907                         return -EREMOTEIO;
 908                 }
 909         }
 910
 911         return retval;
 912 }
 913
 914
 915 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 916 {
 917         u32 cnt = 50;
 918         u32 val;
 919         /* Set link rate and count as you want to establish*/
 920         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 921         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 922         rk32_edp_hw_link_training_en(edp);
 923         mdelay(1);
 924         val = rk32_edp_wait_hw_lt_done(edp);
 925         while (val) {
 926                 if (cnt-- <= 0) {
 927                         dev_err(edp->dev, "hw lt timeout");
 928                         return -ETIMEDOUT;
 929                 }
 930                 mdelay(1);
 931                 val = rk32_edp_wait_hw_lt_done(edp);
 932         }
 933
 934         val = rk32_edp_get_hw_lt_status(edp);
 935         if (val)
 936                 dev_err(edp->dev, "hw lt err:%d\n", val);
 937         return val;
 938
 939 }
 940 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 941                                 u32 count,
 942                                 u32 bwtype)
 943 {
 944         int retval;
 945
 946         retval = rk32_edp_init_training(edp, count, bwtype);
 947         if (retval < 0)
 948                 dev_err(edp->dev, "DP LT init failed!\n");
 949 #if 0
 950         retval = rk32_edp_sw_link_training(edp);
 951 #else
 952         retval = rk32_edp_hw_link_training(edp);
 953 #endif
 954
 955         return retval;
 956 }
 957
 958 static int rk32_edp_config_video(struct rk32_edp *edp,
 959                         struct video_info *video_info)
 960 {
 961         int retval = 0;
 962         int timeout_loop = 0;
 963         int done_count = 0;
 964
 965         rk32_edp_config_video_slave_mode(edp, video_info);
 966
 967         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 968                         video_info->color_space,
 969                         video_info->dynamic_range,
 970                         video_info->ycbcr_coeff);
 971
 972         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 973                 dev_err(edp->dev, "PLL is not locked yet.\n");
 974                 return -EINVAL;
 975         }
 976
 977         for (;;) {
 978                 timeout_loop++;
 979                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 980                         break;
 981                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 982                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 983                         return -ETIMEDOUT;
 984                 }
 985
 986                 usleep_range(1, 1);
 987         }
 988
 989         /* Set to use the register calculated M/N video */
 990         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 991
 992         /* For video bist, Video timing must be generated by register */
 993         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 994
 995         /* Disable video mute */
 996         rk32_edp_enable_video_mute(edp, 0);
 997
 998         /* Configure video slave mode */
 999         rk32_edp_enable_video_master(edp, 0);
1000
1001         /* Enable video */
1002         rk32_edp_start_video(edp);
1003
1004         timeout_loop = 0;
1005
1006         for (;;) {
1007                 timeout_loop++;
1008                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1009                         done_count++;
1010                         if (done_count > 10)
1011                                 break;
1012                 } else if (done_count) {
1013                         done_count = 0;
1014                 }
1015                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1016                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1017                         return -ETIMEDOUT;
1018                 }
1019
1020                 usleep_range(1000, 1000);
1021         }
1022
1023         if (retval != 0)
1024                 dev_err(edp->dev, "Video stream is not detected!\n");
1025
1026         return retval;
1027 }
1028
1029 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1030 {
1031         u8 data;
1032         int retval;
1033
1034         if (enable) {
1035                 rk32_edp_enable_scrambling(edp);
1036
1037                 retval = rk32_edp_read_byte_from_dpcd(edp,
1038                                 DPCD_TRAINING_PATTERN_SET,
1039                                 &data);
1040                 if (retval < 0)
1041                         return retval;
1042
1043                 retval = rk32_edp_write_byte_to_dpcd(edp,
1044                                 DPCD_TRAINING_PATTERN_SET,
1045                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1046                 if (retval < 0)
1047                         return retval;
1048         } else {
1049                 rk32_edp_disable_scrambling(edp);
1050
1051                 retval = rk32_edp_read_byte_from_dpcd(edp,
1052                                 DPCD_TRAINING_PATTERN_SET,
1053                                 &data);
1054                 if (retval < 0)
1055                         return retval;
1056
1057                 retval = rk32_edp_write_byte_to_dpcd(edp,
1058                                 DPCD_TRAINING_PATTERN_SET,
1059                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1060                 if (retval < 0)
1061                         return retval;
1062         }
1063
1064         return 0;
1065 }
1066
1067 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1068 {
1069         struct rk32_edp *edp = arg;
1070
1071         //dev_info(edp->dev, "rk32_edp_isr\n");
1072         return IRQ_HANDLED;
1073 }
1074
1075 static int rk32_edp_enable(void)
1076 {
1077         int ret = 0;
1078         int retry = 0;
1079         struct rk32_edp *edp = rk32_edp;
1080         if (edp->enabled)
1081                 goto out;
1082
1083         edp->enabled = 1;
1084         clk_enable(edp->pclk);
1085         clk_enable(edp->clk_edp);
1086         clk_enable(edp->clk_24m);
1087 edp_phy_init:
1088
1089
1090         rk32_edp_init_edp(edp);
1091
1092         ret = rk32_edp_handle_edid(edp);
1093         if (ret) {
1094                 dev_err(edp->dev, "unable to handle edid\n");
1095                 //goto out;
1096         }
1097
1098
1099         ret = rk32_edp_enable_scramble(edp, 0);
1100         if (ret) {
1101                 dev_err(edp->dev, "unable to set scramble\n");
1102                 //goto out;
1103         }
1104
1105         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1106         if (ret) {
1107                 dev_err(edp->dev, "unable to set enhanced mode\n");
1108                 //goto out;
1109         }
1110         rk32_edp_enable_enhanced_mode(edp, 0);
1111
1112        /* Link Training */
1113         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_1_62GBPS);
1114         if (ret) {
1115                 dev_err(edp->dev, "link train failed\n");
1116                 //goto out;
1117         }
1118
1119         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1120         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1121
1122 #ifdef EDP_BIST_MODE
1123         rk32_edp_bist_cfg(edp);
1124 #else
1125         rk32_edp_init_video(edp);
1126         ret = rk32_edp_config_video(edp, &edp->video_info);
1127         if (ret) {
1128                 dev_err(edp->dev, "unable to config video\n");
1129                 //goto out;
1130         }
1131 #endif
1132         return 0;
1133
1134 out:
1135
1136         if (retry < 3) {
1137                 retry++;
1138                 goto edp_phy_init;
1139         }
1140
1141         dev_err(edp->dev, "DP LT exceeds max retry count");
1142         return ret;
1143 }
1144
1145 static int  rk32_edp_disable(void )
1146 {
1147         struct rk32_edp *edp = rk32_edp;
1148
1149         if (!edp->enabled)
1150                 return 0;
1151
1152         edp->enabled = 0;
1153
1154         rk32_edp_reset(edp);
1155         rk32_edp_analog_power_ctr(edp, 0);
1156
1157         clk_disable(edp->clk_24m);
1158         clk_disable(edp->clk_edp);
1159         clk_disable(edp->pclk);
1160
1161         return 0;
1162 }
1163
1164
1165 static struct rk_fb_trsm_ops trsm_edp_ops = {
1166         .enable = rk32_edp_enable,
1167         .disable = rk32_edp_disable,
1168 };
1169 static int rk32_edp_probe(struct platform_device *pdev)
1170 {
1171         struct rk32_edp *edp;
1172         struct resource *res;
1173         struct device_node *np = pdev->dev.of_node;
1174         int ret;
1175
1176         if (!np) {
1177                 dev_err(&pdev->dev, "Missing device tree node.\n");
1178                 return -EINVAL;
1179         }
1180
1181         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1182         if (!edp) {
1183                 dev_err(&pdev->dev, "no memory for state\n");
1184                 return -ENOMEM;
1185         }
1186         edp->dev = &pdev->dev;
1187         edp->video_info.h_sync_polarity = 0;
1188         edp->video_info.v_sync_polarity = 0;
1189         edp->video_info.interlaced      = 0;
1190         edp->video_info.color_space     = CS_RGB;
1191         edp->video_info.dynamic_range   = VESA;
1192         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1193         edp->video_info.color_depth     = COLOR_8;
1194
1195         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1196         edp->video_info.lane_count      = LANE_CNT4;
1197         rk_fb_get_prmry_screen(&edp->screen);
1198         if (edp->screen.type != SCREEN_EDP) {
1199                 dev_err(&pdev->dev, "screen is not edp!\n");
1200                 return -EINVAL;
1201         }
1202         platform_set_drvdata(pdev, edp);
1203         dev_set_name(edp->dev, "rk32-edp");
1204
1205         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1206         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1207         if (IS_ERR(edp->regs)) {
1208                 dev_err(&pdev->dev, "ioremap reg failed\n");
1209                 return PTR_ERR(edp->regs);
1210         }
1211
1212         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1213         if (IS_ERR(edp->clk_edp)) {
1214                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1215                 return PTR_ERR(edp->clk_edp);
1216         }
1217
1218         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1219         if (IS_ERR(edp->clk_24m)) {
1220                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1221                 return PTR_ERR(edp->clk_24m);
1222         }
1223
1224         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1225         if (IS_ERR(edp->pclk)) {
1226                 dev_err(&pdev->dev, "cannot get pclk\n");
1227                 return PTR_ERR(edp->pclk);
1228         }
1229
1230         /*edp->irq = platform_get_irq(pdev, 0);
1231         if (edp->irq < 0) {
1232                 dev_err(&pdev->dev, "cannot find IRQ\n");
1233                 return edp->irq;
1234         }
1235         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1236                         dev_name(&pdev->dev), edp);
1237         if (ret) {
1238                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1239                 return ret;
1240         }
1241         disable_irq(edp->irq);*/
1242         rk32_edp = edp;
1243         clk_prepare(edp->pclk);
1244         clk_prepare(edp->clk_edp);
1245         clk_prepare(edp->clk_24m);
1246         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1247         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1248
1249         return 0;
1250 }
1251
1252 static void rk32_edp_shutdown(struct platform_device *pdev)
1253 {
1254
1255 }
1256
1257 #if defined(CONFIG_OF)
1258 static const struct of_device_id rk32_edp_dt_ids[] = {
1259         {.compatible = "rockchip, rk32-edp",},
1260         {}
1261 };
1262
1263 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1264 #endif
1265
1266 static struct platform_driver rk32_edp_driver = {
1267         .probe = rk32_edp_probe,
1268         .driver = {
1269                    .name = "rk32-edp",
1270                    .owner = THIS_MODULE,
1271 #if defined(CONFIG_OF)
1272                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1273 #endif
1274         },
1275         .shutdown = rk32_edp_shutdown,
1276 };
1277
1278 static int __init rk32_edp_module_init(void)
1279 {
1280         return platform_driver_register(&rk32_edp_driver);
1281 }
1282
1283 static void __exit rk32_edp_module_exit(void)
1284 {
1285
1286 }
1287
1288 subsys_initcall_sync(rk32_edp_module_init);
1289 module_exit(rk32_edp_module_exit);