drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 //#define EDP_BIST_MODE
  35
  36 static struct rk32_edp *rk32_edp;
  37 static int rk32_edp_init_edp(struct rk32_edp *edp)
  38 {
  39         struct rk_screen *screen = &edp->screen;
  40         u32 val = 0;
  41         int i= 0;
  42         screen->lcdc_id = 1;
  43         if (screen->lcdc_id == 1)  /*select lcdc*/
  44                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  45         else
  46                 val = EDP_SEL_VOP_LIT << 16;
  47         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  48
  49         val = GRF_EDP_REF_CLK_SEL_INTER |
  50                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  51         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  52
  53         val = 0x80008000;
  54         writel_relaxed(val, RK_CRU_VIRT + 0x0d0);
  55
  56         val = 0x80008000;
  57         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  58         mdelay(12);
  59         val = 0x80000000;
  60         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  61         mdelay(12);
  62         rk32_edp_reset(edp);
  63         rk32_edp_init_refclk(edp);
  64         rk32_edp_init_interrupt(edp);
  65
  66         rk32_edp_enable_sw_function(edp);
  67
  68         rk32_edp_init_analog_func(edp);
  69
  70         rk32_edp_init_hpd(edp);
  71         rk32_edp_init_aux(edp);
  72
  73         return 0;
  74 }
  75
  76 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  77 {
  78         int timeout_loop = 0;
  79
  80         rk32_edp_init_hpd(edp);
  81
  82         udelay(200);
  83
  84         while (rk32_edp_get_plug_in_status(edp) != 0) {
  85                 timeout_loop++;
  86                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  87                         dev_err(edp->dev, "failed to get hpd plug status\n");
  88                         return -ETIMEDOUT;
  89                 }
  90                 udelay(10);
  91         }
  92
  93         return 0;
  94 }
  95
  96 static int rk32_edp_read_edid(struct rk32_edp *edp)
  97 {
  98         unsigned char edid[EDID_LENGTH * 2];
  99         unsigned int extend_block = 0;
 100         unsigned char sum;
 101         unsigned char test_vector;
 102         int retval;
 103
 104         /*
 105          * EDID device address is 0x50.
 106          * However, if necessary, you must have set upper address
 107          * into E-EDID in I2C device, 0x30.
 108          */
 109
 110         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 111         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 112                                                 &extend_block);
 113         if (retval < 0) {
 114                 dev_err(edp->dev, "EDID extension flag failed!\n");
 115                 return -EIO;
 116         }
 117
 118         if (extend_block > 0) {
 119                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 120
 121                 /* Read EDID data */
 122                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 123                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 124                 if (retval != 0) {
 125                         dev_err(edp->dev, "EDID Read failed!\n");
 126                         return -EIO;
 127                 }
 128                 sum = edp_calc_edid_check_sum(edid);
 129                 if (sum != 0) {
 130                         dev_warn(edp->dev, "EDID bad checksum!\n");
 131                         return 0;
 132                 }
 133
 134                 /* Read additional EDID data */
 135                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 136                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 137                 if (retval != 0) {
 138                         dev_err(edp->dev, "EDID Read failed!\n");
 139                         return -EIO;
 140                 }
 141                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 142                 if (sum != 0) {
 143                         dev_warn(edp->dev, "EDID bad checksum!\n");
 144                         return 0;
 145                 }
 146
 147                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 148                                         &test_vector);
 149                 if (retval < 0) {
 150                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 151                         return retval;
 152                 }
 153
 154                 if (test_vector & DPCD_TEST_EDID_READ) {
 155                         retval = rk32_edp_write_byte_to_dpcd(edp,
 156                                         DPCD_TEST_EDID_CHECKSUM,
 157                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 158                         if (retval < 0) {
 159                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 160                                 return retval;
 161                         }
 162                         retval = rk32_edp_write_byte_to_dpcd(edp,
 163                                         DPCD_TEST_RESPONSE,
 164                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 165                         if (retval < 0) {
 166                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 167                                 return retval;
 168                         }
 169                 }
 170         } else {
 171                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 172
 173                 /* Read EDID data */
 174                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 175                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 176                 if (retval != 0) {
 177                         dev_err(edp->dev, "EDID Read failed!\n");
 178                         return -EIO;
 179                 }
 180                 sum = edp_calc_edid_check_sum(edid);
 181                 if (sum != 0) {
 182                         dev_warn(edp->dev, "EDID bad checksum!\n");
 183                         return 0;
 184                 }
 185
 186                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 187                                                 &test_vector);
 188                 if (retval < 0) {
 189                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 190                         return retval;
 191                 }
 192
 193                 if (test_vector & DPCD_TEST_EDID_READ) {
 194                         retval = rk32_edp_write_byte_to_dpcd(edp,
 195                                         DPCD_TEST_EDID_CHECKSUM,
 196                                         edid[EDID_CHECKSUM]);
 197                         if (retval < 0) {
 198                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 199                                 return retval;
 200                         }
 201                         retval = rk32_edp_write_byte_to_dpcd(edp,
 202                                         DPCD_TEST_RESPONSE,
 203                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 204                         if (retval < 0) {
 205                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 206                                 return retval;
 207                         }
 208                 }
 209         }
 210         fb_edid_to_monspecs(edid, &edp->specs);
 211         dev_err(edp->dev, "EDID Read success!\n");
 212         return 0;
 213 }
 214
 215 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 216 {
 217         u8 buf[12];
 218         int i;
 219         int retval;
 220
 221         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 222         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 223         if (retval < 0)
 224                 return retval;
 225
 226         for (i=0 ;i < 12; i++)
 227                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 228         /* Read EDID */
 229         for (i = 0; i < 3; i++) {
 230                 retval = rk32_edp_read_edid(edp);
 231                 if (retval == 0)
 232                         break;
 233         }
 234
 235         return retval;
 236 }
 237
 238 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 239                                                 bool enable)
 240 {
 241         u8 data;
 242         int retval;
 243
 244         retval = rk32_edp_read_byte_from_dpcd(edp,
 245                         DPCD_LANE_CNT_SET, &data);
 246         if (retval < 0)
 247                 return retval;
 248
 249         if (enable) {
 250                 retval = rk32_edp_write_byte_to_dpcd(edp,
 251                                 DPCD_LANE_CNT_SET,
 252                                 DPCD_ENHANCED_FRAME_EN |
 253                                 DPCD_LANE_COUNT_SET(data));
 254         } else {
 255                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 256                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 257
 258                 retval = rk32_edp_write_byte_to_dpcd(edp,
 259                                 DPCD_LANE_CNT_SET,
 260                                 DPCD_LANE_COUNT_SET(data));
 261         }
 262
 263         return retval;
 264 }
 265
 266 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 267 {
 268         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 269         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 270
 271         if (enable) {
 272                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 273                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 274         } else {
 275                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 276         }*/
 277 }
 278
 279 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 280 {
 281         u8 data;
 282         int retval;
 283
 284         retval = rk32_edp_read_byte_from_dpcd(edp,
 285                         DPCD_MAX_LANE_CNT, &data);
 286         if (retval < 0)
 287                 return retval;
 288
 289         return DPCD_ENHANCED_FRAME_CAP(data);
 290 }
 291
 292 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 293 {
 294         /*rk32_edp_write_byte_to_dpcd(edp,
 295                         DPCD_ADDR_USER_DEFINED1, 0);
 296         rk32_edp_write_byte_to_dpcd(edp,
 297                         DPCD_ADDR_USER_DEFINED2, 0x83);
 298         rk32_edp_write_byte_to_dpcd(edp,
 299                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 300 }
 301
 302 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 303 {
 304         u8 data;
 305         int retval;
 306
 307         retval = rk32_edp_is_enhanced_mode_available(edp);
 308         if (retval < 0)
 309                 return retval;
 310
 311         data = (u8)retval;
 312         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 313         if (retval < 0)
 314                 return retval;
 315
 316         rk32_edp_enable_enhanced_mode(edp, data);
 317
 318         return 0;
 319 }
 320
 321 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 322 {
 323         int retval;
 324
 325         rk32_edp_set_training_pattern(edp, DP_NONE);
 326
 327         retval = rk32_edp_write_byte_to_dpcd(edp,
 328                         DPCD_TRAINING_PATTERN_SET,
 329                         DPCD_TRAINING_PATTERN_DISABLED);
 330         if (retval < 0)
 331                 return retval;
 332
 333         return 0;
 334 }
 335
 336 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 337                                         int pre_emphasis, int lane)
 338 {
 339         switch (lane) {
 340         case 0:
 341                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 342                 break;
 343         case 1:
 344                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 345                 break;
 346
 347         case 2:
 348                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 349                 break;
 350
 351         case 3:
 352                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 353                 break;
 354         }
 355 }
 356
 357 static int rk32_edp_link_start(struct rk32_edp *edp)
 358 {
 359         u8 buf[4];
 360         int lane;
 361         int lane_count;
 362         int retval;
 363
 364         lane_count = edp->link_train.lane_count;
 365
 366         edp->link_train.lt_state = LT_CLK_RECOVERY;
 367         edp->link_train.eq_loop = 0;
 368
 369         for (lane = 0; lane < lane_count; lane++)
 370                 edp->link_train.cr_loop[lane] = 0;
 371
 372         /* Set sink to D0 (Sink Not Ready) mode. */
 373         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 374                                 DPCD_SET_POWER_STATE_D0);
 375         if (retval < 0) {
 376                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 377                 return retval;
 378         }
 379
 380         /* Set link rate and count as you want to establish*/
 381         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 382         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 383
 384         /* Setup RX configuration */
 385         buf[0] = edp->link_train.link_rate;
 386         buf[1] = edp->link_train.lane_count;
 387         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 388                                         2, buf);
 389         if (retval < 0) {
 390                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 391                 return retval;
 392         }
 393
 394         /* Set TX pre-emphasis to level1 */
 395         for (lane = 0; lane < lane_count; lane++)
 396                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 397                         PRE_EMPHASIS_LEVEL_1, lane);
 398
 399         /* Set training pattern 1 */
 400         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 401
 402         /* Set RX training pattern */
 403         retval = rk32_edp_write_byte_to_dpcd(edp,
 404                         DPCD_TRAINING_PATTERN_SET,
 405                         DPCD_SCRAMBLING_DISABLED |
 406                         DPCD_TRAINING_PATTERN_1);
 407         if (retval < 0) {
 408                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 409                 return retval;
 410         }
 411
 412         for (lane = 0; lane < lane_count; lane++)
 413                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 414                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 415         retval = rk32_edp_write_bytes_to_dpcd(edp,
 416                         DPCD_TRAINING_LANE0_SET,
 417                         lane_count, buf);
 418         if (retval < 0) {
 419                 dev_err(edp->dev, "failed to set training lane!\n");
 420                 return retval;
 421         }
 422
 423         return 0;
 424 }
 425
 426 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 427 {
 428         int shift = (lane & 1) * 4;
 429         u8 link_value = link_status[lane>>1];
 430
 431         return (link_value >> shift) & 0xf;
 432 }
 433
 434 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 435 {
 436         int lane;
 437         u8 lane_status;
 438
 439         for (lane = 0; lane < lane_count; lane++) {
 440                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 441                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 442                         return -EINVAL;
 443         }
 444         return 0;
 445 }
 446
 447 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 448 {
 449         int lane;
 450         u8 lane_align;
 451         u8 lane_status;
 452
 453         lane_align = link_align[2];
 454         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 455                 return -EINVAL;
 456
 457         for (lane = 0; lane < lane_count; lane++) {
 458                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 459                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 460                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 461                         return -EINVAL;
 462         }
 463
 464         return 0;
 465 }
 466
 467 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 468                                                         int lane)
 469 {
 470         int shift = (lane & 1) * 4;
 471         u8 link_value = adjust_request[lane>>1];
 472
 473         return (link_value >> shift) & 0x3;
 474 }
 475
 476 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 477                                         u8 adjust_request[2],
 478                                         int lane)
 479 {
 480         int shift = (lane & 1) * 4;
 481         u8 link_value = adjust_request[lane>>1];
 482
 483         return ((link_value >> shift) & 0xc) >> 2;
 484 }
 485
 486 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 487                                         u8 training_lane_set, int lane)
 488 {
 489         switch (lane) {
 490         case 0:
 491                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 492                 break;
 493         case 1:
 494                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 495                 break;
 496
 497         case 2:
 498                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 499                 break;
 500
 501         case 3:
 502                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 503                 break;
 504         }
 505 }
 506
 507 static unsigned int rk32_edp_get_lane_link_training(
 508                                 struct rk32_edp *edp,
 509                                 int lane)
 510 {
 511         u32 reg;
 512
 513         switch (lane) {
 514         case 0:
 515                 reg = rk32_edp_get_lane0_link_training(edp);
 516                 break;
 517         case 1:
 518                 reg = rk32_edp_get_lane1_link_training(edp);
 519                 break;
 520         case 2:
 521                 reg = rk32_edp_get_lane2_link_training(edp);
 522                 break;
 523         case 3:
 524                 reg = rk32_edp_get_lane3_link_training(edp);
 525                 break;
 526         }
 527
 528         return reg;
 529 }
 530
 531 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 532 {
 533         rk32_edp_training_pattern_dis(edp);
 534
 535         edp->link_train.lt_state = FAILED;
 536 }
 537
 538 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 539 {
 540         u8 link_status[2];
 541         int lane;
 542         int lane_count;
 543
 544         u8 adjust_request[2];
 545         u8 voltage_swing;
 546         u8 pre_emphasis;
 547         u8 training_lane;
 548         int retval;
 549
 550         udelay(100);
 551
 552         lane_count = edp->link_train.lane_count;
 553
 554         retval = rk32_edp_read_bytes_from_dpcd(edp,
 555                         DPCD_LANE0_1_STATUS,
 556                         2, link_status);
 557         if (retval < 0) {
 558                 dev_err(edp->dev, "failed to read lane status!\n");
 559                 return retval;
 560         }
 561
 562         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 563                 /* set training pattern 2 for EQ */
 564                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 565
 566                 for (lane = 0; lane < lane_count; lane++) {
 567                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 568                                         DPCD_ADJUST_REQUEST_LANE0_1,
 569                                         2, adjust_request);
 570                         if (retval < 0) {
 571                                 dev_err(edp->dev, "failed to read adjust request!\n");
 572                                 return retval;
 573                         }
 574
 575                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 576                                                         adjust_request, lane);
 577                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 578                                                         adjust_request, lane);
 579                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 580                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 581
 582                         if (voltage_swing == VOLTAGE_LEVEL_3)
 583                                 training_lane |= DPCD_MAX_SWING_REACHED;
 584                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 585                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 586
 587                         edp->link_train.training_lane[lane] = training_lane;
 588
 589                         rk32_edp_set_lane_link_training(edp,
 590                                 edp->link_train.training_lane[lane],
 591                                 lane);
 592                 }
 593
 594                 retval = rk32_edp_write_byte_to_dpcd(edp,
 595                                 DPCD_TRAINING_PATTERN_SET,
 596                                 DPCD_SCRAMBLING_DISABLED |
 597                                 DPCD_TRAINING_PATTERN_2);
 598                 if (retval < 0) {
 599                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 600                         return retval;
 601                 }
 602
 603                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 604                                 DPCD_TRAINING_LANE0_SET,
 605                                 lane_count,
 606                                 edp->link_train.training_lane);
 607                 if (retval < 0) {
 608                         dev_err(edp->dev, "failed to set training lane!\n");
 609                         return retval;
 610                 }
 611
 612                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 613                 edp->link_train.lt_state = LT_EQ_TRAINING;
 614         } else {
 615                 for (lane = 0; lane < lane_count; lane++) {
 616                         training_lane = rk32_edp_get_lane_link_training(
 617                                                         edp, lane);
 618                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 619                                         DPCD_ADJUST_REQUEST_LANE0_1,
 620                                         2, adjust_request);
 621                         if (retval < 0) {
 622                                 dev_err(edp->dev, "failed to read adjust request!\n");
 623                                 return retval;
 624                         }
 625
 626                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 627                                                         adjust_request, lane);
 628                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 629                                                         adjust_request, lane);
 630
 631                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 632                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 633                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 634                                 goto reduce_link_rate;
 635                         }
 636
 637                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 638                                         voltage_swing) &&
 639                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 640                                         pre_emphasis)) {
 641                                 edp->link_train.cr_loop[lane]++;
 642                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 643                                         dev_err(edp->dev, "CR Max loop\n");
 644                                         goto reduce_link_rate;
 645                                 }
 646                         }
 647
 648                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 649                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 650
 651                         if (voltage_swing == VOLTAGE_LEVEL_3)
 652                                 training_lane |= DPCD_MAX_SWING_REACHED;
 653                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 654                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 655
 656                         edp->link_train.training_lane[lane] = training_lane;
 657
 658                         rk32_edp_set_lane_link_training(edp,
 659                                 edp->link_train.training_lane[lane], lane);
 660                 }
 661
 662                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 663                                 DPCD_TRAINING_LANE0_SET,
 664                                 lane_count,
 665                                 edp->link_train.training_lane);
 666                 if (retval < 0) {
 667                         dev_err(edp->dev, "failed to set training lane!\n");
 668                         return retval;
 669                 }
 670         }
 671
 672         return 0;
 673
 674 reduce_link_rate:
 675         rk32_edp_reduce_link_rate(edp);
 676         return -EIO;
 677 }
 678
 679 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 680 {
 681         u8 link_status[2];
 682         u8 link_align[3];
 683         int lane;
 684         int lane_count;
 685         u32 reg;
 686
 687         u8 adjust_request[2];
 688         u8 voltage_swing;
 689         u8 pre_emphasis;
 690         u8 training_lane;
 691         int retval;
 692
 693         udelay(400);
 694
 695         lane_count = edp->link_train.lane_count;
 696
 697         retval = rk32_edp_read_bytes_from_dpcd(edp,
 698                         DPCD_LANE0_1_STATUS,
 699                         2, link_status);
 700         if (retval < 0) {
 701                 dev_err(edp->dev, "failed to read lane status!\n");
 702                 return retval;
 703         }
 704
 705         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 706                 link_align[0] = link_status[0];
 707                 link_align[1] = link_status[1];
 708
 709                 retval = rk32_edp_read_byte_from_dpcd(edp,
 710                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 711                                 &link_align[2]);
 712                 if (retval < 0) {
 713                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 714                         return retval;
 715                 }
 716
 717                 for (lane = 0; lane < lane_count; lane++) {
 718                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 719                                         DPCD_ADJUST_REQUEST_LANE0_1,
 720                                         2, adjust_request);
 721                         if (retval < 0) {
 722                                 dev_err(edp->dev, "failed to read adjust request!\n");
 723                                 return retval;
 724                         }
 725
 726                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 727                                                         adjust_request, lane);
 728                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 729                                                         adjust_request, lane);
 730                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 731                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 732
 733                         if (voltage_swing == VOLTAGE_LEVEL_3)
 734                                 training_lane |= DPCD_MAX_SWING_REACHED;
 735                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 736                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 737
 738                         edp->link_train.training_lane[lane] = training_lane;
 739                 }
 740
 741                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 742                         /* traing pattern Set to Normal */
 743                         retval = rk32_edp_training_pattern_dis(edp);
 744                         if (retval < 0) {
 745                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 746                                 return retval;
 747                         }
 748
 749                         dev_info(edp->dev, "Link Training success!\n");
 750
 751                         rk32_edp_get_link_bandwidth(edp, &reg);
 752                         edp->link_train.link_rate = reg;
 753                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 754                                 edp->link_train.link_rate);
 755
 756                         rk32_edp_get_lane_count(edp, &reg);
 757                         edp->link_train.lane_count = reg;
 758                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 759                                 edp->link_train.lane_count);
 760
 761                         edp->link_train.lt_state = FINISHED;
 762                 } else {
 763                         /* not all locked */
 764                         edp->link_train.eq_loop++;
 765
 766                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 767                                 dev_err(edp->dev, "EQ Max loop\n");
 768                                 goto reduce_link_rate;
 769                         }
 770
 771                         for (lane = 0; lane < lane_count; lane++)
 772                                 rk32_edp_set_lane_link_training(edp,
 773                                         edp->link_train.training_lane[lane],
 774                                         lane);
 775
 776                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 777                                         DPCD_TRAINING_LANE0_SET,
 778                                         lane_count,
 779                                         edp->link_train.training_lane);
 780                         if (retval < 0) {
 781                                 dev_err(edp->dev, "failed to set training lane!\n");
 782                                 return retval;
 783                         }
 784                 }
 785         } else {
 786                 goto reduce_link_rate;
 787         }
 788
 789         return 0;
 790
 791 reduce_link_rate:
 792         rk32_edp_reduce_link_rate(edp);
 793         return -EIO;
 794 }
 795
 796 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 797                                         u8 *bandwidth)
 798 {
 799         u8 data;
 800         int retval;
 801
 802         /*
 803          * For DP rev.1.1, Maximum link rate of Main Link lanes
 804          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 805          */
 806         retval = rk32_edp_read_byte_from_dpcd(edp,
 807                         DPCD_MAX_LINK_RATE, &data);
 808         if (retval < 0)
 809                 return retval;
 810
 811         *bandwidth = data;
 812         return 0;
 813 }
 814
 815 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 816                                         u8 *lane_count)
 817 {
 818         u8 data;
 819         int retval;
 820
 821         /*
 822          * For DP rev.1.1, Maximum number of Main Link lanes
 823          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 824          */
 825         retval = rk32_edp_read_byte_from_dpcd(edp,
 826                         DPCD_MAX_LANE_CNT, &data);
 827         if (retval < 0)
 828                 return retval;
 829
 830         *lane_count = DPCD_MAX_LANE_COUNT(data);
 831         return 0;
 832 }
 833
 834 static int rk32_edp_init_training(struct rk32_edp *edp)
 835 {
 836         int retval;
 837
 838         /*
 839          * MACRO_RST must be applied after the PLL_LOCK to avoid
 840          * the DP inter pair skew issue for at least 10 us
 841          */
 842         rk32_edp_reset_macro(edp);
 843
 844
 845         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 846         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 847         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 848                         edp->link_train.link_rate * 27/100,
 849                         edp->link_train.link_rate*27%100,
 850                         edp->link_train.lane_count);
 851
 852         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 853            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 854                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 855                         "use default link rate:%d.%dGps\n",
 856                         edp->link_train.link_rate,
 857                         edp->video_info.link_rate*27/100,
 858                         edp->video_info.link_rate*27%100);
 859                 edp->link_train.link_rate = edp->video_info.link_rate;
 860         }
 861
 862         if (edp->link_train.lane_count == 0) {
 863                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 864                         "use default lanes:%d\n",
 865                         edp->link_train.lane_count,
 866                         edp->video_info.lane_count);
 867                 edp->link_train.lane_count = edp->video_info.lane_count;
 868         }
 869
 870         rk32_edp_analog_power_ctr(edp, 1);
 871
 872
 873         return 0;
 874 }
 875
 876 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 877 {
 878         int retval = 0;
 879         int training_finished = 0;
 880
 881         edp->link_train.lt_state = LT_START;
 882
 883         /* Process here */
 884         while (!training_finished) {
 885                 switch (edp->link_train.lt_state) {
 886                 case LT_START:
 887                         retval = rk32_edp_link_start(edp);
 888                         if (retval)
 889                                 dev_err(edp->dev, "LT Start failed\n");
 890                         break;
 891                 case LT_CLK_RECOVERY:
 892                         retval = rk32_edp_process_clock_recovery(edp);
 893                         if (retval)
 894                                 dev_err(edp->dev, "LT CR failed\n");
 895                         break;
 896                 case LT_EQ_TRAINING:
 897                         retval = rk32_edp_process_equalizer_training(edp);
 898                         if (retval)
 899                                 dev_err(edp->dev, "LT EQ failed\n");
 900                         break;
 901                 case FINISHED:
 902                         training_finished = 1;
 903                         break;
 904                 case FAILED:
 905                         return -EREMOTEIO;
 906                 }
 907         }
 908
 909         return retval;
 910 }
 911
 912
 913 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 914 {
 915         u32 cnt = 50;
 916         u32 val;
 917         /* Set link rate and count as you want to establish*/
 918         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 919         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 920         rk32_edp_hw_link_training_en(edp);
 921         mdelay(10);
 922         val = rk32_edp_wait_hw_lt_done(edp);
 923         while (val) {
 924                 if (cnt-- <= 0) {
 925                         dev_err(edp->dev, "hw lt timeout");
 926                         return -ETIMEDOUT;
 927                 }
 928                 mdelay(1);
 929                 val = rk32_edp_wait_hw_lt_done(edp);
 930         }
 931
 932         val = rk32_edp_get_hw_lt_status(edp);
 933         if (val)
 934                 dev_err(edp->dev, "hw lt err:%d\n", val);
 935         return val;
 936
 937 }
 938 static int rk32_edp_set_link_train(struct rk32_edp *edp)
 939 {
 940         int retval;
 941
 942         retval = rk32_edp_init_training(edp);
 943         if (retval < 0)
 944                 dev_err(edp->dev, "DP LT init failed!\n");
 945 #if 0
 946         retval = rk32_edp_sw_link_training(edp);
 947 #else
 948         retval = rk32_edp_hw_link_training(edp);
 949 #endif
 950
 951         return retval;
 952 }
 953
 954 static int rk32_edp_config_video(struct rk32_edp *edp,
 955                         struct video_info *video_info)
 956 {
 957         int retval = 0;
 958         int timeout_loop = 0;
 959         int done_count = 0;
 960
 961         rk32_edp_config_video_slave_mode(edp, video_info);
 962
 963         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 964                         video_info->color_space,
 965                         video_info->dynamic_range,
 966                         video_info->ycbcr_coeff);
 967
 968         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 969                 dev_err(edp->dev, "PLL is not locked yet.\n");
 970                 return -EINVAL;
 971         }
 972
 973         for (;;) {
 974                 timeout_loop++;
 975                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 976                         break;
 977                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 978                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 979                         return -ETIMEDOUT;
 980                 }
 981
 982                 usleep_range(1, 1);
 983         }
 984
 985         /* Set to use the register calculated M/N video */
 986         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 987
 988         /* For video bist, Video timing must be generated by register */
 989         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 990
 991         /* Disable video mute */
 992         rk32_edp_enable_video_mute(edp, 0);
 993
 994         /* Configure video slave mode */
 995         rk32_edp_enable_video_master(edp, 0);
 996
 997         /* Enable video */
 998         rk32_edp_start_video(edp);
 999
1000         timeout_loop = 0;
1001
1002         for (;;) {
1003                 timeout_loop++;
1004                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1005                         done_count++;
1006                         if (done_count > 10)
1007                                 break;
1008                 } else if (done_count) {
1009                         done_count = 0;
1010                 }
1011                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1012                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1013                         return -ETIMEDOUT;
1014                 }
1015
1016                 usleep_range(1000, 1000);
1017         }
1018
1019         if (retval != 0)
1020                 dev_err(edp->dev, "Video stream is not detected!\n");
1021
1022         return retval;
1023 }
1024
1025 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1026 {
1027         u8 data;
1028         int retval;
1029
1030         if (enable) {
1031                 rk32_edp_enable_scrambling(edp);
1032
1033                 retval = rk32_edp_read_byte_from_dpcd(edp,
1034                                 DPCD_TRAINING_PATTERN_SET,
1035                                 &data);
1036                 if (retval < 0)
1037                         return retval;
1038
1039                 retval = rk32_edp_write_byte_to_dpcd(edp,
1040                                 DPCD_TRAINING_PATTERN_SET,
1041                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1042                 if (retval < 0)
1043                         return retval;
1044         } else {
1045                 rk32_edp_disable_scrambling(edp);
1046
1047                 retval = rk32_edp_read_byte_from_dpcd(edp,
1048                                 DPCD_TRAINING_PATTERN_SET,
1049                                 &data);
1050                 if (retval < 0)
1051                         return retval;
1052
1053                 retval = rk32_edp_write_byte_to_dpcd(edp,
1054                                 DPCD_TRAINING_PATTERN_SET,
1055                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1056                 if (retval < 0)
1057                         return retval;
1058         }
1059
1060         return 0;
1061 }
1062
1063 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1064 {
1065         struct rk32_edp *edp = arg;
1066         enum dp_irq_type irq_type;
1067
1068         irq_type = rk32_edp_get_irq_type(edp);
1069
1070         return IRQ_HANDLED;
1071 }
1072
1073 static int rk32_edp_enable(void)
1074 {
1075         int ret = 0;
1076         int i;
1077         struct rk32_edp *edp = rk32_edp;
1078
1079         clk_enable(edp->pclk);
1080         clk_enable(edp->clk_edp);
1081         clk_enable(edp->clk_24m);
1082
1083         rk32_edp_init_edp(edp);
1084
1085         /*ret = rk32_edp_handle_edid(edp);
1086         if (ret) {
1087                 dev_err(edp->dev, "unable to handle edid\n");
1088                 //goto out;
1089         }
1090
1091
1092         ret = rk32_edp_enable_scramble(edp, 0);
1093         if (ret) {
1094                 dev_err(edp->dev, "unable to set scramble\n");
1095                 //goto out;
1096         }
1097
1098         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1099         if (ret) {
1100                 dev_err(edp->dev, "unable to set enhanced mode\n");
1101                 //goto out;
1102         }
1103         rk32_edp_enable_enhanced_mode(edp, 1);*/
1104
1105         ret = rk32_edp_set_link_train(edp);
1106         if (ret)
1107                 dev_err(edp->dev, "link train failed>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
1108         else
1109                 dev_info(edp->dev, "link training success.\n");
1110
1111         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1112         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1113
1114 #ifdef EDP_BIST_MODE
1115         rk32_edp_bist_cfg(edp);
1116 #else
1117         rk32_edp_init_video(edp);
1118         ret = rk32_edp_config_video(edp, &edp->video_info);
1119         if (ret)
1120                 dev_err(edp->dev, "unable to config video\n");
1121 #endif
1122         return ret;
1123
1124
1125
1126 }
1127
1128 static int  rk32_edp_disable(void )
1129 {
1130         struct rk32_edp *edp = rk32_edp;
1131
1132         rk32_edp_reset(edp);
1133         rk32_edp_analog_power_ctr(edp, 0);
1134
1135         clk_disable(edp->clk_24m);
1136         clk_disable(edp->clk_edp);
1137         clk_disable(edp->pclk);
1138
1139         return 0;
1140 }
1141
1142
1143 static struct rk_fb_trsm_ops trsm_edp_ops = {
1144         .enable = rk32_edp_enable,
1145         .disable = rk32_edp_disable,
1146 };
1147 static int rk32_edp_probe(struct platform_device *pdev)
1148 {
1149         struct rk32_edp *edp;
1150         struct resource *res;
1151         struct device_node *np = pdev->dev.of_node;
1152         int ret;
1153
1154         if (!np) {
1155                 dev_err(&pdev->dev, "Missing device tree node.\n");
1156                 return -EINVAL;
1157         }
1158
1159         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1160         if (!edp) {
1161                 dev_err(&pdev->dev, "no memory for state\n");
1162                 return -ENOMEM;
1163         }
1164         edp->dev = &pdev->dev;
1165         edp->video_info.h_sync_polarity = 0;
1166         edp->video_info.v_sync_polarity = 0;
1167         edp->video_info.interlaced      = 0;
1168         edp->video_info.color_space     = CS_RGB;
1169         edp->video_info.dynamic_range   = VESA;
1170         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1171         edp->video_info.color_depth     = COLOR_8;
1172
1173         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1174         edp->video_info.lane_count      = LANE_CNT4;
1175         rk_fb_get_prmry_screen(&edp->screen);
1176         if (edp->screen.type != SCREEN_EDP) {
1177                 dev_err(&pdev->dev, "screen is not edp!\n");
1178                 return -EINVAL;
1179         }
1180         platform_set_drvdata(pdev, edp);
1181         dev_set_name(edp->dev, "rk32-edp");
1182
1183         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1184         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1185         if (IS_ERR(edp->regs)) {
1186                 dev_err(&pdev->dev, "ioremap reg failed\n");
1187                 return PTR_ERR(edp->regs);
1188         }
1189
1190         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1191         if (IS_ERR(edp->clk_edp)) {
1192                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1193                 return PTR_ERR(edp->clk_edp);
1194         }
1195
1196         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1197         if (IS_ERR(edp->clk_24m)) {
1198                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1199                 return PTR_ERR(edp->clk_24m);
1200         }
1201
1202         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1203         if (IS_ERR(edp->pclk)) {
1204                 dev_err(&pdev->dev, "cannot get pclk\n");
1205                 return PTR_ERR(edp->pclk);
1206         }
1207
1208         /*edp->irq = platform_get_irq(pdev, 0);
1209         if (edp->irq < 0) {
1210                 dev_err(&pdev->dev, "cannot find IRQ\n");
1211                 return edp->irq;
1212         }
1213         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1214                         dev_name(&pdev->dev), edp);
1215         if (ret) {
1216                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1217                 return ret;
1218         }
1219         disable_irq(edp->irq);*/
1220         rk32_edp = edp;
1221         clk_prepare(edp->pclk);
1222         clk_prepare(edp->clk_edp);
1223         clk_prepare(edp->clk_24m);
1224         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1225         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1226
1227         return 0;
1228 }
1229
1230 static void rk32_edp_shutdown(struct platform_device *pdev)
1231 {
1232
1233 }
1234
1235 #if defined(CONFIG_OF)
1236 static const struct of_device_id rk32_edp_dt_ids[] = {
1237         {.compatible = "rockchip, rk32-edp",},
1238         {}
1239 };
1240
1241 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1242 #endif
1243
1244 static struct platform_driver rk32_edp_driver = {
1245         .probe = rk32_edp_probe,
1246         .driver = {
1247                    .name = "rk32-edp",
1248                    .owner = THIS_MODULE,
1249 #if defined(CONFIG_OF)
1250                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1251 #endif
1252         },
1253         .shutdown = rk32_edp_shutdown,
1254 };
1255
1256 static int __init rk32_edp_module_init(void)
1257 {
1258         return platform_driver_register(&rk32_edp_driver);
1259 }
1260
1261 static void __exit rk32_edp_module_exit(void)
1262 {
1263
1264 }
1265
1266 subsys_initcall_sync(rk32_edp_module_init);
1267 module_exit(rk32_edp_module_exit);