drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 //#define EDP_BIST_MODE
  35
  36 static struct rk32_edp *rk32_edp;
  37 static int rk32_edp_init_edp(struct rk32_edp *edp)
  38 {
  39         struct rk_screen *screen = &edp->screen;
  40         u32 val = 0;
  41
  42         screen->lcdc_id = 1;
  43         if (screen->lcdc_id == 1)  /*select lcdc*/
  44                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  45         else
  46                 val = EDP_SEL_VOP_LIT << 16;
  47         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  48
  49         val = GRF_EDP_REF_CLK_SEL_INTER |
  50                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  51         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  52
  53         val = 0x80008000;
  54         writel_relaxed(val, RK_CRU_VIRT + 0x0d0);
  55         rk32_edp_reset(edp);
  56         rk32_edp_init_refclk(edp);
  57         rk32_edp_init_interrupt(edp);
  58
  59         rk32_edp_enable_sw_function(edp);
  60
  61         rk32_edp_init_analog_func(edp);
  62
  63         rk32_edp_init_hpd(edp);
  64         rk32_edp_init_aux(edp);
  65
  66         return 0;
  67 }
  68
  69 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  70 {
  71         int timeout_loop = 0;
  72
  73         rk32_edp_init_hpd(edp);
  74
  75         udelay(200);
  76
  77         while (rk32_edp_get_plug_in_status(edp) != 0) {
  78                 timeout_loop++;
  79                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  80                         dev_err(edp->dev, "failed to get hpd plug status\n");
  81                         return -ETIMEDOUT;
  82                 }
  83                 udelay(10);
  84         }
  85
  86         return 0;
  87 }
  88
  89 static int rk32_edp_read_edid(struct rk32_edp *edp)
  90 {
  91         unsigned char edid[EDID_LENGTH * 2];
  92         unsigned int extend_block = 0;
  93         unsigned char sum;
  94         unsigned char test_vector;
  95         int retval;
  96
  97         /*
  98          * EDID device address is 0x50.
  99          * However, if necessary, you must have set upper address
 100          * into E-EDID in I2C device, 0x30.
 101          */
 102
 103         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 104         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 105                                                 &extend_block);
 106         if (retval < 0) {
 107                 dev_err(edp->dev, "EDID extension flag failed!\n");
 108                 return -EIO;
 109         }
 110
 111         if (extend_block > 0) {
 112                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 113
 114                 /* Read EDID data */
 115                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 116                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 117                 if (retval != 0) {
 118                         dev_err(edp->dev, "EDID Read failed!\n");
 119                         return -EIO;
 120                 }
 121                 sum = edp_calc_edid_check_sum(edid);
 122                 if (sum != 0) {
 123                         dev_warn(edp->dev, "EDID bad checksum!\n");
 124                         return 0;
 125                 }
 126
 127                 /* Read additional EDID data */
 128                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 129                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 130                 if (retval != 0) {
 131                         dev_err(edp->dev, "EDID Read failed!\n");
 132                         return -EIO;
 133                 }
 134                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 135                 if (sum != 0) {
 136                         dev_warn(edp->dev, "EDID bad checksum!\n");
 137                         return 0;
 138                 }
 139
 140                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 141                                         &test_vector);
 142                 if (retval < 0) {
 143                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 144                         return retval;
 145                 }
 146
 147                 if (test_vector & DPCD_TEST_EDID_READ) {
 148                         retval = rk32_edp_write_byte_to_dpcd(edp,
 149                                         DPCD_TEST_EDID_CHECKSUM,
 150                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 151                         if (retval < 0) {
 152                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 153                                 return retval;
 154                         }
 155                         retval = rk32_edp_write_byte_to_dpcd(edp,
 156                                         DPCD_TEST_RESPONSE,
 157                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 158                         if (retval < 0) {
 159                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 160                                 return retval;
 161                         }
 162                 }
 163         } else {
 164                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 165
 166                 /* Read EDID data */
 167                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 168                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 169                 if (retval != 0) {
 170                         dev_err(edp->dev, "EDID Read failed!\n");
 171                         return -EIO;
 172                 }
 173                 sum = edp_calc_edid_check_sum(edid);
 174                 if (sum != 0) {
 175                         dev_warn(edp->dev, "EDID bad checksum!\n");
 176                         return 0;
 177                 }
 178
 179                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 180                                                 &test_vector);
 181                 if (retval < 0) {
 182                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 183                         return retval;
 184                 }
 185
 186                 if (test_vector & DPCD_TEST_EDID_READ) {
 187                         retval = rk32_edp_write_byte_to_dpcd(edp,
 188                                         DPCD_TEST_EDID_CHECKSUM,
 189                                         edid[EDID_CHECKSUM]);
 190                         if (retval < 0) {
 191                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 192                                 return retval;
 193                         }
 194                         retval = rk32_edp_write_byte_to_dpcd(edp,
 195                                         DPCD_TEST_RESPONSE,
 196                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 197                         if (retval < 0) {
 198                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 199                                 return retval;
 200                         }
 201                 }
 202         }
 203
 204         dev_err(edp->dev, "EDID Read success!\n");
 205         return 0;
 206 }
 207
 208 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 209 {
 210         u8 buf[12];
 211         int i;
 212         int retval;
 213
 214         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 215         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 216         if (retval < 0)
 217                 return retval;
 218
 219         /* Read EDID */
 220         for (i = 0; i < 3; i++) {
 221                 retval = rk32_edp_read_edid(edp);
 222                 if (retval == 0)
 223                         break;
 224         }
 225
 226         return retval;
 227 }
 228
 229 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 230                                                 bool enable)
 231 {
 232         u8 data;
 233         int retval;
 234
 235         retval = rk32_edp_read_byte_from_dpcd(edp,
 236                         DPCD_LANE_CNT_SET, &data);
 237         if (retval < 0)
 238                 return retval;
 239
 240         if (enable) {
 241                 retval = rk32_edp_write_byte_to_dpcd(edp,
 242                                 DPCD_LANE_CNT_SET,
 243                                 DPCD_ENHANCED_FRAME_EN |
 244                                 DPCD_LANE_COUNT_SET(data));
 245         } else {
 246                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 247                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 248
 249                 retval = rk32_edp_write_byte_to_dpcd(edp,
 250                                 DPCD_LANE_CNT_SET,
 251                                 DPCD_LANE_COUNT_SET(data));
 252         }
 253
 254         return retval;
 255 }
 256
 257 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 258 {
 259         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 260         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 261
 262         if (enable) {
 263                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 264                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 265         } else {
 266                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 267         }*/
 268 }
 269
 270 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 271 {
 272         u8 data;
 273         int retval;
 274
 275         retval = rk32_edp_read_byte_from_dpcd(edp,
 276                         DPCD_MAX_LANE_CNT, &data);
 277         if (retval < 0)
 278                 return retval;
 279
 280         return DPCD_ENHANCED_FRAME_CAP(data);
 281 }
 282
 283 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 284 {
 285         /*rk32_edp_write_byte_to_dpcd(edp,
 286                         DPCD_ADDR_USER_DEFINED1, 0);
 287         rk32_edp_write_byte_to_dpcd(edp,
 288                         DPCD_ADDR_USER_DEFINED2, 0x83);
 289         rk32_edp_write_byte_to_dpcd(edp,
 290                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 291 }
 292
 293 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 294 {
 295         u8 data;
 296         int retval;
 297
 298         retval = rk32_edp_is_enhanced_mode_available(edp);
 299         if (retval < 0)
 300                 return retval;
 301
 302         data = (u8)retval;
 303         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 304         if (retval < 0)
 305                 return retval;
 306
 307         rk32_edp_enable_enhanced_mode(edp, data);
 308
 309         return 0;
 310 }
 311
 312 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 313 {
 314         int retval;
 315
 316         rk32_edp_set_training_pattern(edp, DP_NONE);
 317
 318         retval = rk32_edp_write_byte_to_dpcd(edp,
 319                         DPCD_TRAINING_PATTERN_SET,
 320                         DPCD_TRAINING_PATTERN_DISABLED);
 321         if (retval < 0)
 322                 return retval;
 323
 324         return 0;
 325 }
 326
 327 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 328                                         int pre_emphasis, int lane)
 329 {
 330         switch (lane) {
 331         case 0:
 332                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 333                 break;
 334         case 1:
 335                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 336                 break;
 337
 338         case 2:
 339                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 340                 break;
 341
 342         case 3:
 343                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 344                 break;
 345         }
 346 }
 347
 348 static int rk32_edp_link_start(struct rk32_edp *edp)
 349 {
 350         u8 buf[4];
 351         int lane;
 352         int lane_count;
 353         int retval;
 354
 355         lane_count = edp->link_train.lane_count;
 356
 357         edp->link_train.lt_state = LT_CLK_RECOVERY;
 358         edp->link_train.eq_loop = 0;
 359
 360         for (lane = 0; lane < lane_count; lane++)
 361                 edp->link_train.cr_loop[lane] = 0;
 362
 363         /* Set sink to D0 (Sink Not Ready) mode. */
 364         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 365                                 DPCD_SET_POWER_STATE_D0);
 366         if (retval < 0) {
 367                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 368                 return retval;
 369         }
 370
 371         /* Set link rate and count as you want to establish*/
 372         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 373         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 374
 375         /* Setup RX configuration */
 376         buf[0] = edp->link_train.link_rate;
 377         buf[1] = edp->link_train.lane_count;
 378         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 379                                         2, buf);
 380         if (retval < 0) {
 381                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 382                 return retval;
 383         }
 384
 385         /* Set TX pre-emphasis to level1 */
 386         for (lane = 0; lane < lane_count; lane++)
 387                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 388                         PRE_EMPHASIS_LEVEL_1, lane);
 389
 390         /* Set training pattern 1 */
 391         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 392
 393         /* Set RX training pattern */
 394         retval = rk32_edp_write_byte_to_dpcd(edp,
 395                         DPCD_TRAINING_PATTERN_SET,
 396                         DPCD_SCRAMBLING_DISABLED |
 397                         DPCD_TRAINING_PATTERN_1);
 398         if (retval < 0) {
 399                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 400                 return retval;
 401         }
 402
 403         for (lane = 0; lane < lane_count; lane++)
 404                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 405                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 406         retval = rk32_edp_write_bytes_to_dpcd(edp,
 407                         DPCD_TRAINING_LANE0_SET,
 408                         lane_count, buf);
 409         if (retval < 0) {
 410                 dev_err(edp->dev, "failed to set training lane!\n");
 411                 return retval;
 412         }
 413
 414         return 0;
 415 }
 416
 417 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 418 {
 419         int shift = (lane & 1) * 4;
 420         u8 link_value = link_status[lane>>1];
 421
 422         return (link_value >> shift) & 0xf;
 423 }
 424
 425 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 426 {
 427         int lane;
 428         u8 lane_status;
 429
 430         for (lane = 0; lane < lane_count; lane++) {
 431                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 432                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 433                         return -EINVAL;
 434         }
 435         return 0;
 436 }
 437
 438 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 439 {
 440         int lane;
 441         u8 lane_align;
 442         u8 lane_status;
 443
 444         lane_align = link_align[2];
 445         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 446                 return -EINVAL;
 447
 448         for (lane = 0; lane < lane_count; lane++) {
 449                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 450                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 451                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 452                         return -EINVAL;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 459                                                         int lane)
 460 {
 461         int shift = (lane & 1) * 4;
 462         u8 link_value = adjust_request[lane>>1];
 463
 464         return (link_value >> shift) & 0x3;
 465 }
 466
 467 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 468                                         u8 adjust_request[2],
 469                                         int lane)
 470 {
 471         int shift = (lane & 1) * 4;
 472         u8 link_value = adjust_request[lane>>1];
 473
 474         return ((link_value >> shift) & 0xc) >> 2;
 475 }
 476
 477 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 478                                         u8 training_lane_set, int lane)
 479 {
 480         switch (lane) {
 481         case 0:
 482                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 483                 break;
 484         case 1:
 485                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 486                 break;
 487
 488         case 2:
 489                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 490                 break;
 491
 492         case 3:
 493                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 494                 break;
 495         }
 496 }
 497
 498 static unsigned int rk32_edp_get_lane_link_training(
 499                                 struct rk32_edp *edp,
 500                                 int lane)
 501 {
 502         u32 reg;
 503
 504         switch (lane) {
 505         case 0:
 506                 reg = rk32_edp_get_lane0_link_training(edp);
 507                 break;
 508         case 1:
 509                 reg = rk32_edp_get_lane1_link_training(edp);
 510                 break;
 511         case 2:
 512                 reg = rk32_edp_get_lane2_link_training(edp);
 513                 break;
 514         case 3:
 515                 reg = rk32_edp_get_lane3_link_training(edp);
 516                 break;
 517         }
 518
 519         return reg;
 520 }
 521
 522 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 523 {
 524         rk32_edp_training_pattern_dis(edp);
 525
 526         edp->link_train.lt_state = FAILED;
 527 }
 528
 529 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 530 {
 531         u8 link_status[2];
 532         int lane;
 533         int lane_count;
 534
 535         u8 adjust_request[2];
 536         u8 voltage_swing;
 537         u8 pre_emphasis;
 538         u8 training_lane;
 539         int retval;
 540
 541         udelay(100);
 542
 543         lane_count = edp->link_train.lane_count;
 544
 545         retval = rk32_edp_read_bytes_from_dpcd(edp,
 546                         DPCD_LANE0_1_STATUS,
 547                         2, link_status);
 548         if (retval < 0) {
 549                 dev_err(edp->dev, "failed to read lane status!\n");
 550                 return retval;
 551         }
 552
 553         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 554                 /* set training pattern 2 for EQ */
 555                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 556
 557                 for (lane = 0; lane < lane_count; lane++) {
 558                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 559                                         DPCD_ADJUST_REQUEST_LANE0_1,
 560                                         2, adjust_request);
 561                         if (retval < 0) {
 562                                 dev_err(edp->dev, "failed to read adjust request!\n");
 563                                 return retval;
 564                         }
 565
 566                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 567                                                         adjust_request, lane);
 568                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 569                                                         adjust_request, lane);
 570                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 571                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 572
 573                         if (voltage_swing == VOLTAGE_LEVEL_3)
 574                                 training_lane |= DPCD_MAX_SWING_REACHED;
 575                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 576                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 577
 578                         edp->link_train.training_lane[lane] = training_lane;
 579
 580                         rk32_edp_set_lane_link_training(edp,
 581                                 edp->link_train.training_lane[lane],
 582                                 lane);
 583                 }
 584
 585                 retval = rk32_edp_write_byte_to_dpcd(edp,
 586                                 DPCD_TRAINING_PATTERN_SET,
 587                                 DPCD_SCRAMBLING_DISABLED |
 588                                 DPCD_TRAINING_PATTERN_2);
 589                 if (retval < 0) {
 590                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 591                         return retval;
 592                 }
 593
 594                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 595                                 DPCD_TRAINING_LANE0_SET,
 596                                 lane_count,
 597                                 edp->link_train.training_lane);
 598                 if (retval < 0) {
 599                         dev_err(edp->dev, "failed to set training lane!\n");
 600                         return retval;
 601                 }
 602
 603                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 604                 edp->link_train.lt_state = LT_EQ_TRAINING;
 605         } else {
 606                 for (lane = 0; lane < lane_count; lane++) {
 607                         training_lane = rk32_edp_get_lane_link_training(
 608                                                         edp, lane);
 609                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 610                                         DPCD_ADJUST_REQUEST_LANE0_1,
 611                                         2, adjust_request);
 612                         if (retval < 0) {
 613                                 dev_err(edp->dev, "failed to read adjust request!\n");
 614                                 return retval;
 615                         }
 616
 617                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 618                                                         adjust_request, lane);
 619                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 620                                                         adjust_request, lane);
 621
 622                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 623                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 624                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 625                                 goto reduce_link_rate;
 626                         }
 627
 628                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 629                                         voltage_swing) &&
 630                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 631                                         pre_emphasis)) {
 632                                 edp->link_train.cr_loop[lane]++;
 633                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 634                                         dev_err(edp->dev, "CR Max loop\n");
 635                                         goto reduce_link_rate;
 636                                 }
 637                         }
 638
 639                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 640                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 641
 642                         if (voltage_swing == VOLTAGE_LEVEL_3)
 643                                 training_lane |= DPCD_MAX_SWING_REACHED;
 644                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 645                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 646
 647                         edp->link_train.training_lane[lane] = training_lane;
 648
 649                         rk32_edp_set_lane_link_training(edp,
 650                                 edp->link_train.training_lane[lane], lane);
 651                 }
 652
 653                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 654                                 DPCD_TRAINING_LANE0_SET,
 655                                 lane_count,
 656                                 edp->link_train.training_lane);
 657                 if (retval < 0) {
 658                         dev_err(edp->dev, "failed to set training lane!\n");
 659                         return retval;
 660                 }
 661         }
 662
 663         return 0;
 664
 665 reduce_link_rate:
 666         rk32_edp_reduce_link_rate(edp);
 667         return -EIO;
 668 }
 669
 670 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 671 {
 672         u8 link_status[2];
 673         u8 link_align[3];
 674         int lane;
 675         int lane_count;
 676         u32 reg;
 677
 678         u8 adjust_request[2];
 679         u8 voltage_swing;
 680         u8 pre_emphasis;
 681         u8 training_lane;
 682         int retval;
 683
 684         udelay(400);
 685
 686         lane_count = edp->link_train.lane_count;
 687
 688         retval = rk32_edp_read_bytes_from_dpcd(edp,
 689                         DPCD_LANE0_1_STATUS,
 690                         2, link_status);
 691         if (retval < 0) {
 692                 dev_err(edp->dev, "failed to read lane status!\n");
 693                 return retval;
 694         }
 695
 696         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 697                 link_align[0] = link_status[0];
 698                 link_align[1] = link_status[1];
 699
 700                 retval = rk32_edp_read_byte_from_dpcd(edp,
 701                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 702                                 &link_align[2]);
 703                 if (retval < 0) {
 704                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 705                         return retval;
 706                 }
 707
 708                 for (lane = 0; lane < lane_count; lane++) {
 709                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 710                                         DPCD_ADJUST_REQUEST_LANE0_1,
 711                                         2, adjust_request);
 712                         if (retval < 0) {
 713                                 dev_err(edp->dev, "failed to read adjust request!\n");
 714                                 return retval;
 715                         }
 716
 717                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 718                                                         adjust_request, lane);
 719                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 720                                                         adjust_request, lane);
 721                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 722                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 723
 724                         if (voltage_swing == VOLTAGE_LEVEL_3)
 725                                 training_lane |= DPCD_MAX_SWING_REACHED;
 726                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 727                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 728
 729                         edp->link_train.training_lane[lane] = training_lane;
 730                 }
 731
 732                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 733                         /* traing pattern Set to Normal */
 734                         retval = rk32_edp_training_pattern_dis(edp);
 735                         if (retval < 0) {
 736                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 737                                 return retval;
 738                         }
 739
 740                         dev_info(edp->dev, "Link Training success!\n");
 741
 742                         rk32_edp_get_link_bandwidth(edp, &reg);
 743                         edp->link_train.link_rate = reg;
 744                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 745                                 edp->link_train.link_rate);
 746
 747                         rk32_edp_get_lane_count(edp, &reg);
 748                         edp->link_train.lane_count = reg;
 749                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 750                                 edp->link_train.lane_count);
 751
 752                         edp->link_train.lt_state = FINISHED;
 753                 } else {
 754                         /* not all locked */
 755                         edp->link_train.eq_loop++;
 756
 757                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 758                                 dev_err(edp->dev, "EQ Max loop\n");
 759                                 goto reduce_link_rate;
 760                         }
 761
 762                         for (lane = 0; lane < lane_count; lane++)
 763                                 rk32_edp_set_lane_link_training(edp,
 764                                         edp->link_train.training_lane[lane],
 765                                         lane);
 766
 767                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 768                                         DPCD_TRAINING_LANE0_SET,
 769                                         lane_count,
 770                                         edp->link_train.training_lane);
 771                         if (retval < 0) {
 772                                 dev_err(edp->dev, "failed to set training lane!\n");
 773                                 return retval;
 774                         }
 775                 }
 776         } else {
 777                 goto reduce_link_rate;
 778         }
 779
 780         return 0;
 781
 782 reduce_link_rate:
 783         rk32_edp_reduce_link_rate(edp);
 784         return -EIO;
 785 }
 786
 787 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 788                                         u8 *bandwidth)
 789 {
 790         u8 data;
 791         int retval;
 792
 793         /*
 794          * For DP rev.1.1, Maximum link rate of Main Link lanes
 795          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 796          */
 797         retval = rk32_edp_read_byte_from_dpcd(edp,
 798                         DPCD_MAX_LINK_RATE, &data);
 799         if (retval < 0)
 800                 return retval;
 801
 802         *bandwidth = data;
 803         return 0;
 804 }
 805
 806 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 807                                         u8 *lane_count)
 808 {
 809         u8 data;
 810         int retval;
 811
 812         /*
 813          * For DP rev.1.1, Maximum number of Main Link lanes
 814          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 815          */
 816         retval = rk32_edp_read_byte_from_dpcd(edp,
 817                         DPCD_MAX_LANE_CNT, &data);
 818         if (retval < 0)
 819                 return retval;
 820
 821         *lane_count = DPCD_MAX_LANE_COUNT(data);
 822         return 0;
 823 }
 824
 825 static int rk32_edp_init_training(struct rk32_edp *edp,
 826                         enum link_lane_count_type max_lane,
 827                         u32 max_rate)
 828 {
 829         int retval;
 830
 831         /*
 832          * MACRO_RST must be applied after the PLL_LOCK to avoid
 833          * the DP inter pair skew issue for at least 10 us
 834          */
 835         rk32_edp_reset_macro(edp);
 836
 837
 838         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 839         if (retval < 0)
 840                 return retval;
 841
 842         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 843         if (retval < 0)
 844                 return retval;
 845         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 846                         edp->link_train.link_rate * 27/100,
 847                         edp->link_train.link_rate*27%100,
 848                         edp->link_train.lane_count);
 849
 850         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 851            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 852                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 853                         edp->link_train.link_rate);
 854                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 855         }
 856
 857         if (edp->link_train.lane_count == 0) {
 858                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 859                         edp->link_train.lane_count);
 860                 edp->link_train.lane_count = (u8)LANE_CNT1;
 861         }
 862
 863
 864         if (edp->link_train.lane_count > max_lane)
 865                 edp->link_train.lane_count = max_lane;
 866         if (edp->link_train.link_rate > max_rate)
 867                 edp->link_train.link_rate = max_rate;
 868
 869
 870         rk32_edp_analog_power_ctr(edp, 1);
 871
 872         return 0;
 873 }
 874
 875 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 876 {
 877         int retval = 0;
 878         int training_finished = 0;
 879
 880         edp->link_train.lt_state = LT_START;
 881
 882         /* Process here */
 883         while (!training_finished) {
 884                 switch (edp->link_train.lt_state) {
 885                 case LT_START:
 886                         retval = rk32_edp_link_start(edp);
 887                         if (retval)
 888                                 dev_err(edp->dev, "LT Start failed\n");
 889                         break;
 890                 case LT_CLK_RECOVERY:
 891                         retval = rk32_edp_process_clock_recovery(edp);
 892                         if (retval)
 893                                 dev_err(edp->dev, "LT CR failed\n");
 894                         break;
 895                 case LT_EQ_TRAINING:
 896                         retval = rk32_edp_process_equalizer_training(edp);
 897                         if (retval)
 898                                 dev_err(edp->dev, "LT EQ failed\n");
 899                         break;
 900                 case FINISHED:
 901                         training_finished = 1;
 902                         break;
 903                 case FAILED:
 904                         return -EREMOTEIO;
 905                 }
 906         }
 907
 908         return retval;
 909 }
 910
 911
 912 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 913 {
 914         u32 cnt = 50;
 915         u32 val;
 916         /* Set link rate and count as you want to establish*/
 917         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 918         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 919         rk32_edp_hw_link_training_en(edp);
 920         mdelay(1);
 921         val = rk32_edp_wait_hw_lt_done(edp);
 922         while (val) {
 923                 if (cnt-- <= 0) {
 924                         dev_err(edp->dev, "hw lt timeout");
 925                         return -ETIMEDOUT;
 926                 }
 927                 mdelay(1);
 928                 val = rk32_edp_wait_hw_lt_done(edp);
 929         }
 930
 931         val = rk32_edp_get_hw_lt_status(edp);
 932         if (val)
 933                 dev_err(edp->dev, "hw lt err:%d\n", val);
 934         return val;
 935
 936 }
 937 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 938                                 u32 count,
 939                                 u32 bwtype)
 940 {
 941         int retval;
 942
 943         retval = rk32_edp_init_training(edp, count, bwtype);
 944         if (retval < 0)
 945                 dev_err(edp->dev, "DP LT init failed!\n");
 946 #if 0
 947         retval = rk32_edp_sw_link_training(edp);
 948 #else
 949         retval = rk32_edp_hw_link_training(edp);
 950 #endif
 951
 952         return retval;
 953 }
 954
 955 static int rk32_edp_config_video(struct rk32_edp *edp,
 956                         struct video_info *video_info)
 957 {
 958         int retval = 0;
 959         int timeout_loop = 0;
 960         int done_count = 0;
 961
 962         rk32_edp_config_video_slave_mode(edp, video_info);
 963
 964         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 965                         video_info->color_space,
 966                         video_info->dynamic_range,
 967                         video_info->ycbcr_coeff);
 968
 969         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 970                 dev_err(edp->dev, "PLL is not locked yet.\n");
 971                 return -EINVAL;
 972         }
 973
 974         for (;;) {
 975                 timeout_loop++;
 976                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 977                         break;
 978                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 979                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 980                         return -ETIMEDOUT;
 981                 }
 982
 983                 usleep_range(1, 1);
 984         }
 985
 986         /* Set to use the register calculated M/N video */
 987         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 988
 989         /* For video bist, Video timing must be generated by register */
 990         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 991
 992         /* Disable video mute */
 993         rk32_edp_enable_video_mute(edp, 0);
 994
 995         /* Configure video slave mode */
 996         rk32_edp_enable_video_master(edp, 0);
 997
 998         /* Enable video */
 999         rk32_edp_start_video(edp);
1000
1001         timeout_loop = 0;
1002
1003         for (;;) {
1004                 timeout_loop++;
1005                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1006                         done_count++;
1007                         if (done_count > 10)
1008                                 break;
1009                 } else if (done_count) {
1010                         done_count = 0;
1011                 }
1012                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1013                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1014                         return -ETIMEDOUT;
1015                 }
1016
1017                 usleep_range(1000, 1000);
1018         }
1019
1020         if (retval != 0)
1021                 dev_err(edp->dev, "Video stream is not detected!\n");
1022
1023         return retval;
1024 }
1025
1026 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1027 {
1028         u8 data;
1029         int retval;
1030
1031         if (enable) {
1032                 rk32_edp_enable_scrambling(edp);
1033
1034                 retval = rk32_edp_read_byte_from_dpcd(edp,
1035                                 DPCD_TRAINING_PATTERN_SET,
1036                                 &data);
1037                 if (retval < 0)
1038                         return retval;
1039
1040                 retval = rk32_edp_write_byte_to_dpcd(edp,
1041                                 DPCD_TRAINING_PATTERN_SET,
1042                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1043                 if (retval < 0)
1044                         return retval;
1045         } else {
1046                 rk32_edp_disable_scrambling(edp);
1047
1048                 retval = rk32_edp_read_byte_from_dpcd(edp,
1049                                 DPCD_TRAINING_PATTERN_SET,
1050                                 &data);
1051                 if (retval < 0)
1052                         return retval;
1053
1054                 retval = rk32_edp_write_byte_to_dpcd(edp,
1055                                 DPCD_TRAINING_PATTERN_SET,
1056                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1057                 if (retval < 0)
1058                         return retval;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1065 {
1066         struct rk32_edp *edp = arg;
1067
1068         //dev_info(edp->dev, "rk32_edp_isr\n");
1069         return IRQ_HANDLED;
1070 }
1071
1072 static int rk32_edp_enable(void)
1073 {
1074         int ret = 0;
1075         int retry = 0;
1076         struct rk32_edp *edp = rk32_edp;
1077         if (edp->enabled)
1078                 goto out;
1079
1080         edp->enabled = 1;
1081         clk_enable(edp->pclk);
1082         clk_enable(edp->clk_edp);
1083         clk_enable(edp->clk_24m);
1084 edp_phy_init:
1085
1086
1087         rk32_edp_init_edp(edp);
1088
1089         /*ret = rk32_edp_handle_edid(edp);
1090         if (ret) {
1091                 dev_err(edp->dev, "unable to handle edid\n");
1092                 //goto out;
1093         }
1094
1095
1096         ret = rk32_edp_enable_scramble(edp, 0);
1097         if (ret) {
1098                 dev_err(edp->dev, "unable to set scramble\n");
1099                 //goto out;
1100         }
1101
1102         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1103         if (ret) {
1104                 dev_err(edp->dev, "unable to set enhanced mode\n");
1105                 //goto out;
1106         }
1107         rk32_edp_enable_enhanced_mode(edp, 0);*/
1108
1109        /* Link Training */
1110         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1111         if (ret) {
1112                 dev_err(edp->dev, "link train failed\n");
1113                 //goto out;
1114         }
1115
1116         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1117         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1118
1119 #ifdef EDP_BIST_MODE
1120         rk32_edp_bist_cfg(edp);
1121 #else
1122         rk32_edp_init_video(edp);
1123         ret = rk32_edp_config_video(edp, &edp->video_info);
1124         if (ret) {
1125                 dev_err(edp->dev, "unable to config video\n");
1126                 //goto out;
1127         }
1128 #endif
1129         return 0;
1130
1131 out:
1132
1133         if (retry < 3) {
1134                 retry++;
1135                 goto edp_phy_init;
1136         }
1137
1138         dev_err(edp->dev, "DP LT exceeds max retry count");
1139         return ret;
1140 }
1141
1142 static int  rk32_edp_disable(void )
1143 {
1144         struct rk32_edp *edp = rk32_edp;
1145
1146         if (!edp->enabled)
1147                 return 0;
1148
1149         edp->enabled = 0;
1150
1151         rk32_edp_reset(edp);
1152         rk32_edp_analog_power_ctr(edp, 0);
1153
1154         clk_disable(edp->clk_24m);
1155         clk_disable(edp->clk_edp);
1156         clk_disable(edp->pclk);
1157
1158         return 0;
1159 }
1160
1161
1162 static struct rk_fb_trsm_ops trsm_edp_ops = {
1163         .enable = rk32_edp_enable,
1164         .disable = rk32_edp_disable,
1165 };
1166 static int rk32_edp_probe(struct platform_device *pdev)
1167 {
1168         struct rk32_edp *edp;
1169         struct resource *res;
1170         struct device_node *np = pdev->dev.of_node;
1171         int ret;
1172
1173         if (!np) {
1174                 dev_err(&pdev->dev, "Missing device tree node.\n");
1175                 return -EINVAL;
1176         }
1177
1178         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1179         if (!edp) {
1180                 dev_err(&pdev->dev, "no memory for state\n");
1181                 return -ENOMEM;
1182         }
1183         edp->dev = &pdev->dev;
1184         edp->video_info.h_sync_polarity = 0;
1185         edp->video_info.v_sync_polarity = 0;
1186         edp->video_info.interlaced      = 0;
1187         edp->video_info.color_space     = CS_RGB;
1188         edp->video_info.dynamic_range   = VESA;
1189         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1190         edp->video_info.color_depth     = COLOR_8;
1191
1192         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1193         edp->video_info.lane_count      = LANE_CNT4;
1194         rk_fb_get_prmry_screen(&edp->screen);
1195         if (edp->screen.type != SCREEN_EDP) {
1196                 dev_err(&pdev->dev, "screen is not edp!\n");
1197                 return -EINVAL;
1198         }
1199         platform_set_drvdata(pdev, edp);
1200         dev_set_name(edp->dev, "rk32-edp");
1201
1202         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1203         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1204         if (IS_ERR(edp->regs)) {
1205                 dev_err(&pdev->dev, "ioremap reg failed\n");
1206                 return PTR_ERR(edp->regs);
1207         }
1208
1209         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1210         if (IS_ERR(edp->clk_edp)) {
1211                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1212                 return PTR_ERR(edp->clk_edp);
1213         }
1214
1215         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1216         if (IS_ERR(edp->clk_24m)) {
1217                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1218                 return PTR_ERR(edp->clk_24m);
1219         }
1220
1221         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1222         if (IS_ERR(edp->pclk)) {
1223                 dev_err(&pdev->dev, "cannot get pclk\n");
1224                 return PTR_ERR(edp->pclk);
1225         }
1226
1227         /*edp->irq = platform_get_irq(pdev, 0);
1228         if (edp->irq < 0) {
1229                 dev_err(&pdev->dev, "cannot find IRQ\n");
1230                 return edp->irq;
1231         }
1232         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1233                         dev_name(&pdev->dev), edp);
1234         if (ret) {
1235                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1236                 return ret;
1237         }
1238         disable_irq(edp->irq);*/
1239         rk32_edp = edp;
1240         clk_prepare(edp->pclk);
1241         clk_prepare(edp->clk_edp);
1242         clk_prepare(edp->clk_24m);
1243         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1244         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1245
1246         return 0;
1247 }
1248
1249 static void rk32_edp_shutdown(struct platform_device *pdev)
1250 {
1251
1252 }
1253
1254 #if defined(CONFIG_OF)
1255 static const struct of_device_id rk32_edp_dt_ids[] = {
1256         {.compatible = "rockchip, rk32-edp",},
1257         {}
1258 };
1259
1260 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1261 #endif
1262
1263 static struct platform_driver rk32_edp_driver = {
1264         .probe = rk32_edp_probe,
1265         .driver = {
1266                    .name = "rk32-edp",
1267                    .owner = THIS_MODULE,
1268 #if defined(CONFIG_OF)
1269                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1270 #endif
1271         },
1272         .shutdown = rk32_edp_shutdown,
1273 };
1274
1275 static int __init rk32_edp_module_init(void)
1276 {
1277         return platform_driver_register(&rk32_edp_driver);
1278 }
1279
1280 static void __exit rk32_edp_module_exit(void)
1281 {
1282
1283 }
1284
1285 subsys_initcall_sync(rk32_edp_module_init);
1286 module_exit(rk32_edp_module_exit);