2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/clk.h>
24 #include <linux/platform_device.h>
25 #include <linux/uaccess.h>
26 #include <linux/rockchip/iomap.h>
27 #include <linux/rockchip/grf.h>
30 #if defined(CONFIG_OF)
34 /*#define EDP_BIST_MODE*/
36 static int rk32_edp_init_edp(struct rk32_edp *edp)
39 rk32_edp_init_analog_param(edp);
40 rk32_edp_init_interrupt(edp);
42 rk32_edp_enable_sw_function(edp);
44 rk32_edp_init_analog_func(edp);
46 rk32_edp_init_hpd(edp);
47 rk32_edp_init_aux(edp);
52 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
56 rk32_edp_init_hpd(edp);
60 while (rk32_edp_get_plug_in_status(edp) != 0) {
62 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
63 dev_err(edp->dev, "failed to get hpd plug status\n");
72 static int rk32_edp_read_edid(struct rk32_edp *edp)
74 unsigned char edid[EDID_LENGTH * 2];
75 unsigned int extend_block = 0;
77 unsigned char test_vector;
81 * EDID device address is 0x50.
82 * However, if necessary, you must have set upper address
83 * into E-EDID in I2C device, 0x30.
86 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
87 retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
90 dev_err(edp->dev, "EDID extension flag failed!\n");
94 if (extend_block > 0) {
95 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
98 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
99 EDID_LENGTH, &edid[EDID_HEADER]);
101 dev_err(edp->dev, "EDID Read failed!\n");
104 sum = edp_calc_edid_check_sum(edid);
106 dev_warn(edp->dev, "EDID bad checksum!\n");
110 /* Read additional EDID data */
111 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
112 EDID_LENGTH, &edid[EDID_LENGTH]);
114 dev_err(edp->dev, "EDID Read failed!\n");
117 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
119 dev_warn(edp->dev, "EDID bad checksum!\n");
123 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
126 dev_err(edp->dev, "DPCD EDID Read failed!\n");
130 if (test_vector & DPCD_TEST_EDID_READ) {
131 retval = rk32_edp_write_byte_to_dpcd(edp,
132 DPCD_TEST_EDID_CHECKSUM,
133 edid[EDID_LENGTH + EDID_CHECKSUM]);
135 dev_err(edp->dev, "DPCD EDID Write failed!\n");
138 retval = rk32_edp_write_byte_to_dpcd(edp,
140 DPCD_TEST_EDID_CHECKSUM_WRITE);
142 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
147 dev_info(edp->dev, "EDID data does not include any extensions.\n");
150 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
151 EDID_LENGTH, &edid[EDID_HEADER]);
153 dev_err(edp->dev, "EDID Read failed!\n");
156 sum = edp_calc_edid_check_sum(edid);
158 dev_warn(edp->dev, "EDID bad checksum!\n");
162 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
165 dev_err(edp->dev, "DPCD EDID Read failed!\n");
169 if (test_vector & DPCD_TEST_EDID_READ) {
170 retval = rk32_edp_write_byte_to_dpcd(edp,
171 DPCD_TEST_EDID_CHECKSUM,
172 edid[EDID_CHECKSUM]);
174 dev_err(edp->dev, "DPCD EDID Write failed!\n");
177 retval = rk32_edp_write_byte_to_dpcd(edp,
179 DPCD_TEST_EDID_CHECKSUM_WRITE);
181 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
187 dev_err(edp->dev, "EDID Read success!\n");
191 static int rk32_edp_handle_edid(struct rk32_edp *edp)
197 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
198 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
203 for (i = 0; i < 3; i++) {
204 retval = rk32_edp_read_edid(edp);
212 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
218 retval = rk32_edp_read_byte_from_dpcd(edp,
219 DPCD_LANE_CNT_SET, &data);
224 retval = rk32_edp_write_byte_to_dpcd(edp,
226 DPCD_ENHANCED_FRAME_EN |
227 DPCD_LANE_COUNT_SET(data));
229 /*retval = rk32_edp_write_byte_to_dpcd(edp,
230 DPCD_ADDR_CONFIGURATION_SET, 0);*/
232 retval = rk32_edp_write_byte_to_dpcd(edp,
234 DPCD_LANE_COUNT_SET(data));
240 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
242 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
243 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
246 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
247 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
249 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
253 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
258 retval = rk32_edp_read_byte_from_dpcd(edp,
259 DPCD_MAX_LANE_CNT, &data);
263 return DPCD_ENHANCED_FRAME_CAP(data);
266 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
268 /*rk32_edp_write_byte_to_dpcd(edp,
269 DPCD_ADDR_USER_DEFINED1, 0);
270 rk32_edp_write_byte_to_dpcd(edp,
271 DPCD_ADDR_USER_DEFINED2, 0x83);
272 rk32_edp_write_byte_to_dpcd(edp,
273 DPCD_ADDR_USER_DEFINED3, 0x27);*/
276 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
281 retval = rk32_edp_is_enhanced_mode_available(edp);
286 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
290 rk32_edp_enable_enhanced_mode(edp, data);
295 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
299 rk32_edp_set_training_pattern(edp, DP_NONE);
301 retval = rk32_edp_write_byte_to_dpcd(edp,
302 DPCD_TRAINING_PATTERN_SET,
303 DPCD_TRAINING_PATTERN_DISABLED);
310 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
311 int pre_emphasis, int lane)
315 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
318 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
322 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
326 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
331 static int rk32_edp_link_start(struct rk32_edp *edp)
338 lane_count = edp->link_train.lane_count;
340 edp->link_train.lt_state = LT_CLK_RECOVERY;
341 edp->link_train.eq_loop = 0;
343 for (lane = 0; lane < lane_count; lane++)
344 edp->link_train.cr_loop[lane] = 0;
346 /* Set sink to D0 (Sink Not Ready) mode. */
347 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
348 DPCD_SET_POWER_STATE_D0);
350 dev_err(edp->dev, "failed to set sink device to D0!\n");
354 /* Set link rate and count as you want to establish*/
355 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
356 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
358 /* Setup RX configuration */
359 buf[0] = edp->link_train.link_rate;
360 buf[1] = edp->link_train.lane_count;
361 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
364 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
368 /* Set TX pre-emphasis to level1 */
369 for (lane = 0; lane < lane_count; lane++)
370 rk32_edp_set_lane_lane_pre_emphasis(edp,
371 PRE_EMPHASIS_LEVEL_1, lane);
373 /* Set training pattern 1 */
374 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
376 /* Set RX training pattern */
377 retval = rk32_edp_write_byte_to_dpcd(edp,
378 DPCD_TRAINING_PATTERN_SET,
379 DPCD_SCRAMBLING_DISABLED |
380 DPCD_TRAINING_PATTERN_1);
382 dev_err(edp->dev, "failed to set training pattern 1!\n");
386 for (lane = 0; lane < lane_count; lane++)
387 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
388 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
389 retval = rk32_edp_write_bytes_to_dpcd(edp,
390 DPCD_TRAINING_LANE0_SET,
393 dev_err(edp->dev, "failed to set training lane!\n");
400 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
402 int shift = (lane & 1) * 4;
403 u8 link_value = link_status[lane>>1];
405 return (link_value >> shift) & 0xf;
408 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
413 for (lane = 0; lane < lane_count; lane++) {
414 lane_status = rk32_edp_get_lane_status(link_status, lane);
415 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
421 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
427 lane_align = link_align[2];
428 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
431 for (lane = 0; lane < lane_count; lane++) {
432 lane_status = rk32_edp_get_lane_status(link_align, lane);
433 lane_status &= DPCD_CHANNEL_EQ_BITS;
434 if (lane_status != DPCD_CHANNEL_EQ_BITS)
441 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
444 int shift = (lane & 1) * 4;
445 u8 link_value = adjust_request[lane>>1];
447 return (link_value >> shift) & 0x3;
450 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
451 u8 adjust_request[2],
454 int shift = (lane & 1) * 4;
455 u8 link_value = adjust_request[lane>>1];
457 return ((link_value >> shift) & 0xc) >> 2;
460 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
461 u8 training_lane_set, int lane)
465 rk32_edp_set_lane0_link_training(edp, training_lane_set);
468 rk32_edp_set_lane1_link_training(edp, training_lane_set);
472 rk32_edp_set_lane2_link_training(edp, training_lane_set);
476 rk32_edp_set_lane3_link_training(edp, training_lane_set);
481 static unsigned int rk32_edp_get_lane_link_training(
482 struct rk32_edp *edp,
489 reg = rk32_edp_get_lane0_link_training(edp);
492 reg = rk32_edp_get_lane1_link_training(edp);
495 reg = rk32_edp_get_lane2_link_training(edp);
498 reg = rk32_edp_get_lane3_link_training(edp);
505 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
507 rk32_edp_training_pattern_dis(edp);
509 edp->link_train.lt_state = FAILED;
512 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
518 u8 adjust_request[2];
526 lane_count = edp->link_train.lane_count;
528 retval = rk32_edp_read_bytes_from_dpcd(edp,
532 dev_err(edp->dev, "failed to read lane status!\n");
536 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
537 /* set training pattern 2 for EQ */
538 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
540 for (lane = 0; lane < lane_count; lane++) {
541 retval = rk32_edp_read_bytes_from_dpcd(edp,
542 DPCD_ADJUST_REQUEST_LANE0_1,
545 dev_err(edp->dev, "failed to read adjust request!\n");
549 voltage_swing = rk32_edp_get_adjust_request_voltage(
550 adjust_request, lane);
551 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
552 adjust_request, lane);
553 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
554 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
556 if (voltage_swing == VOLTAGE_LEVEL_3)
557 training_lane |= DPCD_MAX_SWING_REACHED;
558 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
559 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
561 edp->link_train.training_lane[lane] = training_lane;
563 rk32_edp_set_lane_link_training(edp,
564 edp->link_train.training_lane[lane],
568 retval = rk32_edp_write_byte_to_dpcd(edp,
569 DPCD_TRAINING_PATTERN_SET,
570 DPCD_SCRAMBLING_DISABLED |
571 DPCD_TRAINING_PATTERN_2);
573 dev_err(edp->dev, "failed to set training pattern 2!\n");
577 retval = rk32_edp_write_bytes_to_dpcd(edp,
578 DPCD_TRAINING_LANE0_SET,
580 edp->link_train.training_lane);
582 dev_err(edp->dev, "failed to set training lane!\n");
586 dev_info(edp->dev, "Link Training Clock Recovery success\n");
587 edp->link_train.lt_state = LT_EQ_TRAINING;
589 for (lane = 0; lane < lane_count; lane++) {
590 training_lane = rk32_edp_get_lane_link_training(
592 retval = rk32_edp_read_bytes_from_dpcd(edp,
593 DPCD_ADJUST_REQUEST_LANE0_1,
596 dev_err(edp->dev, "failed to read adjust request!\n");
600 voltage_swing = rk32_edp_get_adjust_request_voltage(
601 adjust_request, lane);
602 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
603 adjust_request, lane);
605 if (voltage_swing == VOLTAGE_LEVEL_3 ||
606 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
607 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
608 goto reduce_link_rate;
611 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
613 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
615 edp->link_train.cr_loop[lane]++;
616 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
617 dev_err(edp->dev, "CR Max loop\n");
618 goto reduce_link_rate;
622 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
623 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
625 if (voltage_swing == VOLTAGE_LEVEL_3)
626 training_lane |= DPCD_MAX_SWING_REACHED;
627 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
628 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
630 edp->link_train.training_lane[lane] = training_lane;
632 rk32_edp_set_lane_link_training(edp,
633 edp->link_train.training_lane[lane], lane);
636 retval = rk32_edp_write_bytes_to_dpcd(edp,
637 DPCD_TRAINING_LANE0_SET,
639 edp->link_train.training_lane);
641 dev_err(edp->dev, "failed to set training lane!\n");
649 rk32_edp_reduce_link_rate(edp);
653 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
661 u8 adjust_request[2];
669 lane_count = edp->link_train.lane_count;
671 retval = rk32_edp_read_bytes_from_dpcd(edp,
675 dev_err(edp->dev, "failed to read lane status!\n");
679 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
680 link_align[0] = link_status[0];
681 link_align[1] = link_status[1];
683 retval = rk32_edp_read_byte_from_dpcd(edp,
684 DPCD_LANE_ALIGN_STATUS_UPDATED,
687 dev_err(edp->dev, "failed to read lane aligne status!\n");
691 for (lane = 0; lane < lane_count; lane++) {
692 retval = rk32_edp_read_bytes_from_dpcd(edp,
693 DPCD_ADJUST_REQUEST_LANE0_1,
696 dev_err(edp->dev, "failed to read adjust request!\n");
700 voltage_swing = rk32_edp_get_adjust_request_voltage(
701 adjust_request, lane);
702 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
703 adjust_request, lane);
704 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
705 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
707 if (voltage_swing == VOLTAGE_LEVEL_3)
708 training_lane |= DPCD_MAX_SWING_REACHED;
709 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
710 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
712 edp->link_train.training_lane[lane] = training_lane;
715 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
716 /* traing pattern Set to Normal */
717 retval = rk32_edp_training_pattern_dis(edp);
719 dev_err(edp->dev, "failed to disable training pattern!\n");
723 dev_info(edp->dev, "Link Training success!\n");
725 rk32_edp_get_link_bandwidth(edp, ®);
726 edp->link_train.link_rate = reg;
727 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
728 edp->link_train.link_rate);
730 rk32_edp_get_lane_count(edp, ®);
731 edp->link_train.lane_count = reg;
732 dev_dbg(edp->dev, "final lane count = %.2x\n",
733 edp->link_train.lane_count);
735 edp->link_train.lt_state = FINISHED;
738 edp->link_train.eq_loop++;
740 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
741 dev_err(edp->dev, "EQ Max loop\n");
742 goto reduce_link_rate;
745 for (lane = 0; lane < lane_count; lane++)
746 rk32_edp_set_lane_link_training(edp,
747 edp->link_train.training_lane[lane],
750 retval = rk32_edp_write_bytes_to_dpcd(edp,
751 DPCD_TRAINING_LANE0_SET,
753 edp->link_train.training_lane);
755 dev_err(edp->dev, "failed to set training lane!\n");
760 goto reduce_link_rate;
766 rk32_edp_reduce_link_rate(edp);
770 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
777 * For DP rev.1.1, Maximum link rate of Main Link lanes
778 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
780 retval = rk32_edp_read_byte_from_dpcd(edp,
781 DPCD_MAX_LINK_RATE, &data);
789 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
796 * For DP rev.1.1, Maximum number of Main Link lanes
797 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
799 retval = rk32_edp_read_byte_from_dpcd(edp,
800 DPCD_MAX_LANE_CNT, &data);
804 *lane_count = DPCD_MAX_LANE_COUNT(data);
808 static int rk32_edp_init_training(struct rk32_edp *edp,
809 enum link_lane_count_type max_lane,
815 * MACRO_RST must be applied after the PLL_LOCK to avoid
816 * the DP inter pair skew issue for at least 10 us
818 rk32_edp_reset_macro(edp);
821 retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
825 retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
828 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
829 edp->link_train.link_rate * 27/100,
830 edp->link_train.link_rate*27%100,
831 edp->link_train.lane_count);
833 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
834 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
835 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
836 edp->link_train.link_rate);
837 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
840 if (edp->link_train.lane_count == 0) {
841 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
842 edp->link_train.lane_count);
843 edp->link_train.lane_count = (u8)LANE_CNT1;
847 if (edp->link_train.lane_count > max_lane)
848 edp->link_train.lane_count = max_lane;
849 if (edp->link_train.link_rate > max_rate)
850 edp->link_train.link_rate = max_rate;
853 rk32_edp_analog_power_ctr(edp, 1);
858 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
861 int training_finished = 0;
863 edp->link_train.lt_state = LT_START;
866 while (!training_finished) {
867 switch (edp->link_train.lt_state) {
869 retval = rk32_edp_link_start(edp);
871 dev_err(edp->dev, "LT Start failed\n");
873 case LT_CLK_RECOVERY:
874 retval = rk32_edp_process_clock_recovery(edp);
876 dev_err(edp->dev, "LT CR failed\n");
879 retval = rk32_edp_process_equalizer_training(edp);
881 dev_err(edp->dev, "LT EQ failed\n");
884 training_finished = 1;
895 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
899 /* Set link rate and count as you want to establish*/
900 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
901 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
902 rk32_edp_hw_link_training_en(edp);
904 val = rk32_edp_wait_hw_lt_done(edp);
907 dev_err(edp->dev, "hw lt timeout");
911 val = rk32_edp_wait_hw_lt_done(edp);
914 val = rk32_edp_get_hw_lt_status(edp);
916 dev_err(edp->dev, "hw lt err:%d\n", val);
920 static int rk32_edp_set_link_train(struct rk32_edp *edp,
926 retval = rk32_edp_init_training(edp, count, bwtype);
928 dev_err(edp->dev, "DP LT init failed!\n");
930 retval = rk32_edp_sw_link_training(edp);
932 retval = rk32_edp_hw_link_training(edp);
938 static int rk32_edp_config_video(struct rk32_edp *edp,
939 struct video_info *video_info)
942 int timeout_loop = 0;
945 rk32_edp_config_video_slave_mode(edp, video_info);
947 rk32_edp_set_video_color_format(edp, video_info->color_depth,
948 video_info->color_space,
949 video_info->dynamic_range,
950 video_info->ycbcr_coeff);
952 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
953 dev_err(edp->dev, "PLL is not locked yet.\n");
959 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
961 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
962 dev_err(edp->dev, "Timeout of video streamclk ok\n");
969 /* Set to use the register calculated M/N video */
970 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
972 /* For video bist, Video timing must be generated by register */
973 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
975 /* Disable video mute */
976 rk32_edp_enable_video_mute(edp, 0);
978 /* Configure video slave mode */
979 rk32_edp_enable_video_master(edp, 0);
982 rk32_edp_start_video(edp);
988 if (rk32_edp_is_video_stream_on(edp) == 0) {
992 } else if (done_count) {
995 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
996 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1000 usleep_range(1000, 1000);
1004 dev_err(edp->dev, "Video stream is not detected!\n");
1009 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1015 rk32_edp_enable_scrambling(edp);
1017 retval = rk32_edp_read_byte_from_dpcd(edp,
1018 DPCD_TRAINING_PATTERN_SET,
1023 retval = rk32_edp_write_byte_to_dpcd(edp,
1024 DPCD_TRAINING_PATTERN_SET,
1025 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1029 rk32_edp_disable_scrambling(edp);
1031 retval = rk32_edp_read_byte_from_dpcd(edp,
1032 DPCD_TRAINING_PATTERN_SET,
1037 retval = rk32_edp_write_byte_to_dpcd(edp,
1038 DPCD_TRAINING_PATTERN_SET,
1039 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1047 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1049 struct rk32_edp *edp = arg;
1051 dev_info(edp->dev, "rk32_edp_isr\n");
1055 static int rk32_edp_enable(struct rk32_edp *edp)
1064 clk_prepare_enable(edp->clk_edp);
1065 clk_prepare_enable(edp->clk_24m);
1069 rk32_edp_init_edp(edp);
1072 ret = rk32_edp_handle_edid(edp);
1074 dev_err(edp->dev, "unable to handle edid\n");
1078 rk32_edp_disable_rx_zmux(edp);
1081 ret = rk32_edp_enable_scramble(edp, 0);
1083 dev_err(edp->dev, "unable to set scramble\n");
1087 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1089 dev_err(edp->dev, "unable to set enhanced mode\n");
1092 rk32_edp_enable_enhanced_mode(edp, 0);
1095 rk32_edp_rx_control(edp,0);
1098 ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1100 dev_err(edp->dev, "link train failed\n");
1104 /* Rx data enable */
1105 rk32_edp_rx_control(edp,1);
1107 rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1108 rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1110 #ifdef EDP_BIST_MODE
1111 rk32_edp_bist_cfg(edp);
1113 rk32_edp_init_video(edp);
1114 ret = rk32_edp_config_video(edp, &edp->video_info);
1116 dev_err(edp->dev, "unable to config video\n");
1130 dev_err(edp->dev, "DP LT exceeds max retry count");
1135 static void rk32_edp_disable(struct rk32_edp *edp)
1142 rk32_edp_reset(edp);
1143 rk32_edp_analog_power_ctr(edp, 0);
1145 clk_disable(edp->clk_24m);
1146 clk_disable(edp->clk_edp);
1151 static void rk32_edp_init(struct rk32_edp *edp)
1154 rk32_edp_enable(edp);
1156 static int rk32_edp_probe(struct platform_device *pdev)
1158 struct rk32_edp *edp;
1159 struct resource *res;
1160 struct device_node *np = pdev->dev.of_node;
1164 dev_err(&pdev->dev, "Missing device tree node.\n");
1168 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1170 dev_err(&pdev->dev, "no memory for state\n");
1173 edp->dev = &pdev->dev;
1174 edp->video_info.h_sync_polarity = 0;
1175 edp->video_info.v_sync_polarity = 0;
1176 edp->video_info.interlaced = 0;
1177 edp->video_info.color_space = CS_RGB;
1178 edp->video_info.dynamic_range = VESA;
1179 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1180 edp->video_info.color_depth = COLOR_8;
1182 edp->video_info.link_rate = LINK_RATE_2_70GBPS;
1183 edp->video_info.lane_count = LANE_CNT4;
1184 rk_fb_get_prmry_screen(&edp->screen);
1185 if (edp->screen.type != SCREEN_EDP) {
1186 dev_err(&pdev->dev, "screen is not edp!\n");
1189 platform_set_drvdata(pdev, edp);
1190 dev_set_name(edp->dev, "rk32-edp");
1191 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1192 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1193 if (IS_ERR(edp->regs)) {
1194 dev_err(&pdev->dev, "ioremap reg failed\n");
1195 return PTR_ERR(edp->regs);
1197 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1198 dev_name(&pdev->dev), edp);
1200 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1205 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1210 static void rk32_edp_shutdown(struct platform_device *pdev)
1215 #if defined(CONFIG_OF)
1216 static const struct of_device_id rk32_edp_dt_ids[] = {
1217 {.compatible = "rockchip, rk32-edp",},
1221 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1224 static struct platform_driver rk32_edp_driver = {
1225 .probe = rk32_edp_probe,
1228 .owner = THIS_MODULE,
1229 #if defined(CONFIG_OF)
1230 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1233 .shutdown = rk32_edp_shutdown,
1236 static int __init rk32_edp_module_init(void)
1238 return platform_driver_register(&rk32_edp_driver);
1241 static void __exit rk32_edp_module_exit(void)
1246 fs_initcall(rk32_edp_module_init);
1247 module_exit(rk32_edp_module_exit);