2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/clk.h>
24 #include <linux/platform_device.h>
25 #include <linux/uaccess.h>
26 #include <linux/rockchip/iomap.h>
27 #include <linux/rockchip/grf.h>
30 #if defined(CONFIG_OF)
34 #if defined(CONFIG_DEBUG_FS)
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
40 /*#define EDP_BIST_MODE*/
42 static struct rk32_edp *rk32_edp;
44 static int rk32_edp_clk_enable(struct rk32_edp *edp)
47 clk_prepare_enable(edp->pd);
48 clk_prepare_enable(edp->pclk);
49 clk_prepare_enable(edp->clk_edp);
50 clk_prepare_enable(edp->clk_24m);
57 static int rk32_edp_clk_disable(struct rk32_edp *edp)
60 clk_disable_unprepare(edp->pclk);
61 clk_disable_unprepare(edp->clk_edp);
62 clk_disable_unprepare(edp->clk_24m);
63 clk_disable_unprepare(edp->pd);
70 static int rk32_edp_pre_init(void)
73 val = GRF_EDP_REF_CLK_SEL_INTER | (GRF_EDP_REF_CLK_SEL_INTER << 16);
74 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
77 writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
80 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
84 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
90 static int rk32_edp_init_edp(struct rk32_edp *edp)
92 struct rk_screen *screen = &edp->screen;
95 rk_fb_get_prmry_screen(screen);
96 if (screen->lcdc_id == 1) /*select lcdc*/
97 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
99 val = EDP_SEL_VOP_LIT << 16;
100 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
103 rk32_edp_init_refclk(edp);
104 rk32_edp_init_interrupt(edp);
105 rk32_edp_enable_sw_function(edp);
106 rk32_edp_init_analog_func(edp);
107 rk32_edp_init_hpd(edp);
108 rk32_edp_init_aux(edp);
114 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
116 int timeout_loop = 0;
118 rk32_edp_init_hpd(edp);
122 while (rk32_edp_get_plug_in_status(edp) != 0) {
124 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
125 dev_err(edp->dev, "failed to get hpd plug status\n");
134 static int rk32_edp_read_edid(struct rk32_edp *edp)
136 unsigned char edid[EDID_LENGTH * 2];
137 unsigned int extend_block = 0;
139 unsigned char test_vector;
143 * EDID device address is 0x50.
144 * However, if necessary, you must have set upper address
145 * into E-EDID in I2C device, 0x30.
148 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
149 retval = rk32_edp_read_byte_from_i2c(edp,
150 EDID_ADDR, EDID_EXTENSION_FLAG, &extend_block);
152 dev_err(edp->dev, "EDID extension flag failed!\n");
156 if (extend_block > 0) {
157 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
160 retval = rk32_edp_read_bytes_from_i2c(edp,
161 EDID_ADDR, EDID_HEADER,
162 EDID_LENGTH, &edid[EDID_HEADER]);
164 dev_err(edp->dev, "EDID Read failed!\n");
167 sum = edp_calc_edid_check_sum(edid);
169 dev_warn(edp->dev, "EDID bad checksum!\n");
173 /* Read additional EDID data */
174 retval = rk32_edp_read_bytes_from_i2c(edp,
175 EDID_ADDR, EDID_LENGTH,
176 EDID_LENGTH, &edid[EDID_LENGTH]);
178 dev_err(edp->dev, "EDID Read failed!\n");
181 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
183 dev_warn(edp->dev, "EDID bad checksum!\n");
187 retval = rk32_edp_read_byte_from_dpcd(edp,
188 DPCD_TEST_REQUEST, &test_vector);
190 dev_err(edp->dev, "DPCD EDID Read failed!\n");
194 if (test_vector & DPCD_TEST_EDID_READ) {
195 retval = rk32_edp_write_byte_to_dpcd(edp,
196 DPCD_TEST_EDID_CHECKSUM,
197 edid[EDID_LENGTH + EDID_CHECKSUM]);
199 dev_err(edp->dev, "DPCD EDID Write failed!\n");
202 retval = rk32_edp_write_byte_to_dpcd(edp,
204 DPCD_TEST_EDID_CHECKSUM_WRITE);
206 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
211 dev_info(edp->dev, "EDID data does not include any extensions.\n");
214 retval = rk32_edp_read_bytes_from_i2c(edp,
215 EDID_ADDR, EDID_HEADER,
216 EDID_LENGTH, &edid[EDID_HEADER]);
218 dev_err(edp->dev, "EDID Read failed!\n");
221 sum = edp_calc_edid_check_sum(edid);
223 dev_warn(edp->dev, "EDID bad checksum!\n");
227 retval = rk32_edp_read_byte_from_dpcd(edp,
228 DPCD_TEST_REQUEST, &test_vector);
230 dev_err(edp->dev, "DPCD EDID Read failed!\n");
234 if (test_vector & DPCD_TEST_EDID_READ) {
235 retval = rk32_edp_write_byte_to_dpcd(edp,
236 DPCD_TEST_EDID_CHECKSUM,
237 edid[EDID_CHECKSUM]);
239 dev_err(edp->dev, "DPCD EDID Write failed!\n");
242 retval = rk32_edp_write_byte_to_dpcd(edp,
244 DPCD_TEST_EDID_CHECKSUM_WRITE);
246 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
251 fb_edid_to_monspecs(edid, &edp->specs);
252 dev_err(edp->dev, "EDID Read success!\n");
257 static int rk32_edp_handle_edid(struct rk32_edp *edp)
263 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
264 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
268 for (i = 0; i < 12; i++)
269 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
271 for (i = 0; i < 3; i++) {
272 retval = rk32_edp_read_edid(edp);
281 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
287 retval = rk32_edp_read_byte_from_dpcd(edp,
288 DPCD_LANE_CNT_SET, &data);
293 retval = rk32_edp_write_byte_to_dpcd(edp,
295 DPCD_ENHANCED_FRAME_EN |
296 DPCD_LANE_COUNT_SET(data));
298 /*retval = rk32_edp_write_byte_to_dpcd(edp,
299 DPCD_ADDR_CONFIGURATION_SET, 0);*/
301 retval = rk32_edp_write_byte_to_dpcd(edp,
303 DPCD_LANE_COUNT_SET(data));
309 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
311 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
312 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
315 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
316 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
318 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
323 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
328 retval = rk32_edp_read_byte_from_dpcd(edp,
329 DPCD_MAX_LANE_CNT, &data);
333 return DPCD_ENHANCED_FRAME_CAP(data);
337 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
339 /*rk32_edp_write_byte_to_dpcd(edp,
340 DPCD_ADDR_USER_DEFINED1, 0);
341 rk32_edp_write_byte_to_dpcd(edp,
342 DPCD_ADDR_USER_DEFINED2, 0x83);
343 rk32_edp_write_byte_to_dpcd(edp,
344 DPCD_ADDR_USER_DEFINED3, 0x27);*/
347 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
352 retval = rk32_edp_is_enhanced_mode_available(edp);
357 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
361 rk32_edp_enable_enhanced_mode(edp, data);
368 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
372 rk32_edp_set_training_pattern(edp, DP_NONE);
374 retval = rk32_edp_write_byte_to_dpcd(edp,
375 DPCD_TRAINING_PATTERN_SET,
376 DPCD_TRAINING_PATTERN_DISABLED);
383 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
384 int pre_emphasis, int lane)
388 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
391 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
395 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
399 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
404 static int rk32_edp_link_start(struct rk32_edp *edp)
411 lane_count = edp->link_train.lane_count;
413 edp->link_train.lt_state = LT_CLK_RECOVERY;
414 edp->link_train.eq_loop = 0;
416 for (lane = 0; lane < lane_count; lane++)
417 edp->link_train.cr_loop[lane] = 0;
419 /* Set sink to D0 (Sink Not Ready) mode. */
420 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
421 DPCD_SET_POWER_STATE_D0);
423 dev_err(edp->dev, "failed to set sink device to D0!\n");
427 /* Set link rate and count as you want to establish*/
428 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
429 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
431 /* Setup RX configuration */
432 buf[0] = edp->link_train.link_rate;
433 buf[1] = edp->link_train.lane_count;
434 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
437 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
441 /* Set TX pre-emphasis to level1 */
442 for (lane = 0; lane < lane_count; lane++)
443 rk32_edp_set_lane_lane_pre_emphasis(edp,
444 PRE_EMPHASIS_LEVEL_1, lane);
446 /* Set training pattern 1 */
447 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
449 /* Set RX training pattern */
450 retval = rk32_edp_write_byte_to_dpcd(edp,
451 DPCD_TRAINING_PATTERN_SET,
452 DPCD_SCRAMBLING_DISABLED |
453 DPCD_TRAINING_PATTERN_1);
455 dev_err(edp->dev, "failed to set training pattern 1!\n");
459 for (lane = 0; lane < lane_count; lane++)
460 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
461 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
462 retval = rk32_edp_write_bytes_to_dpcd(edp,
463 DPCD_TRAINING_LANE0_SET,
466 dev_err(edp->dev, "failed to set training lane!\n");
473 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
475 int shift = (lane & 1) * 4;
476 u8 link_value = link_status[lane>>1];
478 return (link_value >> shift) & 0xf;
481 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
486 for (lane = 0; lane < lane_count; lane++) {
487 lane_status = rk32_edp_get_lane_status(link_status, lane);
488 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
494 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
500 lane_align = link_align[2];
501 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
504 for (lane = 0; lane < lane_count; lane++) {
505 lane_status = rk32_edp_get_lane_status(link_align, lane);
506 lane_status &= DPCD_CHANNEL_EQ_BITS;
507 if (lane_status != DPCD_CHANNEL_EQ_BITS)
514 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
517 int shift = (lane & 1) * 4;
518 u8 link_value = adjust_request[lane>>1];
520 return (link_value >> shift) & 0x3;
523 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
524 u8 adjust_request[2],
527 int shift = (lane & 1) * 4;
528 u8 link_value = adjust_request[lane>>1];
530 return ((link_value >> shift) & 0xc) >> 2;
533 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
534 u8 training_lane_set, int lane)
538 rk32_edp_set_lane0_link_training(edp, training_lane_set);
541 rk32_edp_set_lane1_link_training(edp, training_lane_set);
545 rk32_edp_set_lane2_link_training(edp, training_lane_set);
549 rk32_edp_set_lane3_link_training(edp, training_lane_set);
554 static unsigned int rk32_edp_get_lane_link_training(
555 struct rk32_edp *edp,
562 reg = rk32_edp_get_lane0_link_training(edp);
565 reg = rk32_edp_get_lane1_link_training(edp);
568 reg = rk32_edp_get_lane2_link_training(edp);
571 reg = rk32_edp_get_lane3_link_training(edp);
578 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
580 rk32_edp_training_pattern_dis(edp);
582 edp->link_train.lt_state = FAILED;
585 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
591 u8 adjust_request[2];
599 lane_count = edp->link_train.lane_count;
601 retval = rk32_edp_read_bytes_from_dpcd(edp,
605 dev_err(edp->dev, "failed to read lane status!\n");
609 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
610 /* set training pattern 2 for EQ */
611 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
613 for (lane = 0; lane < lane_count; lane++) {
614 retval = rk32_edp_read_bytes_from_dpcd(edp,
615 DPCD_ADJUST_REQUEST_LANE0_1,
618 dev_err(edp->dev, "failed to read adjust request!\n");
622 voltage_swing = rk32_edp_get_adjust_request_voltage(
623 adjust_request, lane);
624 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
625 adjust_request, lane);
626 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
627 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
629 if (voltage_swing == VOLTAGE_LEVEL_3)
630 training_lane |= DPCD_MAX_SWING_REACHED;
631 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
632 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
634 edp->link_train.training_lane[lane] = training_lane;
636 rk32_edp_set_lane_link_training(edp,
637 edp->link_train.training_lane[lane],
641 retval = rk32_edp_write_byte_to_dpcd(edp,
642 DPCD_TRAINING_PATTERN_SET,
643 DPCD_SCRAMBLING_DISABLED |
644 DPCD_TRAINING_PATTERN_2);
646 dev_err(edp->dev, "failed to set training pattern 2!\n");
650 retval = rk32_edp_write_bytes_to_dpcd(edp,
651 DPCD_TRAINING_LANE0_SET,
653 edp->link_train.training_lane);
655 dev_err(edp->dev, "failed to set training lane!\n");
659 dev_info(edp->dev, "Link Training Clock Recovery success\n");
660 edp->link_train.lt_state = LT_EQ_TRAINING;
662 for (lane = 0; lane < lane_count; lane++) {
663 training_lane = rk32_edp_get_lane_link_training(
665 retval = rk32_edp_read_bytes_from_dpcd(edp,
666 DPCD_ADJUST_REQUEST_LANE0_1,
669 dev_err(edp->dev, "failed to read adjust request!\n");
673 voltage_swing = rk32_edp_get_adjust_request_voltage(
674 adjust_request, lane);
675 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
676 adjust_request, lane);
678 if (voltage_swing == VOLTAGE_LEVEL_3 ||
679 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
680 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
681 goto reduce_link_rate;
684 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
686 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
688 edp->link_train.cr_loop[lane]++;
689 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
690 dev_err(edp->dev, "CR Max loop\n");
691 goto reduce_link_rate;
695 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
696 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
698 if (voltage_swing == VOLTAGE_LEVEL_3)
699 training_lane |= DPCD_MAX_SWING_REACHED;
700 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
701 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
703 edp->link_train.training_lane[lane] = training_lane;
705 rk32_edp_set_lane_link_training(edp,
706 edp->link_train.training_lane[lane], lane);
709 retval = rk32_edp_write_bytes_to_dpcd(edp,
710 DPCD_TRAINING_LANE0_SET,
712 edp->link_train.training_lane);
714 dev_err(edp->dev, "failed to set training lane!\n");
722 rk32_edp_reduce_link_rate(edp);
726 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
734 u8 adjust_request[2];
742 lane_count = edp->link_train.lane_count;
744 retval = rk32_edp_read_bytes_from_dpcd(edp,
748 dev_err(edp->dev, "failed to read lane status!\n");
752 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
753 link_align[0] = link_status[0];
754 link_align[1] = link_status[1];
756 retval = rk32_edp_read_byte_from_dpcd(edp,
757 DPCD_LANE_ALIGN_STATUS_UPDATED,
760 dev_err(edp->dev, "failed to read lane aligne status!\n");
764 for (lane = 0; lane < lane_count; lane++) {
765 retval = rk32_edp_read_bytes_from_dpcd(edp,
766 DPCD_ADJUST_REQUEST_LANE0_1,
769 dev_err(edp->dev, "failed to read adjust request!\n");
773 voltage_swing = rk32_edp_get_adjust_request_voltage(
774 adjust_request, lane);
775 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
776 adjust_request, lane);
777 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
778 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
780 if (voltage_swing == VOLTAGE_LEVEL_3)
781 training_lane |= DPCD_MAX_SWING_REACHED;
782 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
783 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
785 edp->link_train.training_lane[lane] = training_lane;
788 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
789 /* traing pattern Set to Normal */
790 retval = rk32_edp_training_pattern_dis(edp);
792 dev_err(edp->dev, "failed to disable training pattern!\n");
796 dev_info(edp->dev, "Link Training success!\n");
798 rk32_edp_get_link_bandwidth(edp, ®);
799 edp->link_train.link_rate = reg;
800 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
801 edp->link_train.link_rate);
803 rk32_edp_get_lane_count(edp, ®);
804 edp->link_train.lane_count = reg;
805 dev_dbg(edp->dev, "final lane count = %.2x\n",
806 edp->link_train.lane_count);
808 edp->link_train.lt_state = FINISHED;
811 edp->link_train.eq_loop++;
813 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
814 dev_err(edp->dev, "EQ Max loop\n");
815 goto reduce_link_rate;
818 for (lane = 0; lane < lane_count; lane++)
819 rk32_edp_set_lane_link_training(edp,
820 edp->link_train.training_lane[lane],
823 retval = rk32_edp_write_bytes_to_dpcd(edp,
824 DPCD_TRAINING_LANE0_SET,
826 edp->link_train.training_lane);
828 dev_err(edp->dev, "failed to set training lane!\n");
833 goto reduce_link_rate;
839 rk32_edp_reduce_link_rate(edp);
843 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
850 * For DP rev.1.1, Maximum link rate of Main Link lanes
851 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
853 retval = rk32_edp_read_byte_from_dpcd(edp,
854 DPCD_MAX_LINK_RATE, &data);
863 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
870 * For DP rev.1.1, Maximum number of Main Link lanes
871 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
873 retval = rk32_edp_read_byte_from_dpcd(edp,
874 DPCD_MAX_LANE_CNT, &data);
878 *lane_count = DPCD_MAX_LANE_COUNT(data);
882 static int rk32_edp_init_training(struct rk32_edp *edp)
887 * MACRO_RST must be applied after the PLL_LOCK to avoid
888 * the DP inter pair skew issue for at least 10 us
890 rk32_edp_reset_macro(edp);
893 retval = rk32_edp_get_max_rx_bandwidth(edp,
894 &edp->link_train.link_rate);
895 retval = rk32_edp_get_max_rx_lane_count(edp,
896 &edp->link_train.lane_count);
897 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
898 edp->link_train.link_rate * 27/100,
899 edp->link_train.link_rate*27%100,
900 edp->link_train.lane_count);
902 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
903 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
904 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
905 "use default link rate:%d.%dGps\n",
906 edp->link_train.link_rate,
907 edp->video_info.link_rate*27/100,
908 edp->video_info.link_rate*27%100);
909 edp->link_train.link_rate = edp->video_info.link_rate;
912 if (edp->link_train.lane_count == 0) {
913 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
914 "use default lanes:%d\n",
915 edp->link_train.lane_count,
916 edp->video_info.lane_count);
917 edp->link_train.lane_count = edp->video_info.lane_count;
920 rk32_edp_analog_power_ctr(edp, 1);
927 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
930 int training_finished = 0;
932 edp->link_train.lt_state = LT_START;
935 while (!training_finished) {
936 switch (edp->link_train.lt_state) {
938 retval = rk32_edp_link_start(edp);
940 dev_err(edp->dev, "LT Start failed\n");
942 case LT_CLK_RECOVERY:
943 retval = rk32_edp_process_clock_recovery(edp);
945 dev_err(edp->dev, "LT CR failed\n");
948 retval = rk32_edp_process_equalizer_training(edp);
950 dev_err(edp->dev, "LT EQ failed\n");
953 training_finished = 1;
964 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
968 /* Set link rate and count as you want to establish*/
969 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
970 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
971 rk32_edp_hw_link_training_en(edp);
972 val = rk32_edp_wait_hw_lt_done(edp);
975 dev_err(edp->dev, "hw lt timeout");
979 val = rk32_edp_wait_hw_lt_done(edp);
982 val = rk32_edp_get_hw_lt_status(edp);
984 dev_err(edp->dev, "hw lt err:%d\n", val);
990 static int rk32_edp_set_link_train(struct rk32_edp *edp)
994 retval = rk32_edp_init_training(edp);
996 dev_err(edp->dev, "DP LT init failed!\n");
998 retval = rk32_edp_sw_link_training(edp);
1000 retval = rk32_edp_hw_link_training(edp);
1006 static int rk32_edp_config_video(struct rk32_edp *edp,
1007 struct video_info *video_info)
1010 int timeout_loop = 0;
1013 rk32_edp_config_video_slave_mode(edp, video_info);
1015 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1016 video_info->color_space,
1017 video_info->dynamic_range,
1018 video_info->ycbcr_coeff);
1020 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1021 dev_err(edp->dev, "PLL is not locked yet.\n");
1027 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1029 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1030 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1037 /* Set to use the register calculated M/N video */
1038 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1040 /* For video bist, Video timing must be generated by register */
1041 #ifndef EDP_BIST_MODE
1042 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1044 /* Disable video mute */
1045 rk32_edp_enable_video_mute(edp, 0);
1047 /* Configure video slave mode */
1048 rk32_edp_enable_video_master(edp, 0);
1051 rk32_edp_start_video(edp);
1057 if (rk32_edp_is_video_stream_on(edp) == 0) {
1059 if (done_count > 10)
1061 } else if (done_count) {
1064 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1065 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1073 dev_err(edp->dev, "Video stream is not detected!\n");
1079 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1085 rk32_edp_enable_scrambling(edp);
1087 retval = rk32_edp_read_byte_from_dpcd(edp,
1088 DPCD_TRAINING_PATTERN_SET,
1093 retval = rk32_edp_write_byte_to_dpcd(edp,
1094 DPCD_TRAINING_PATTERN_SET,
1095 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1099 rk32_edp_disable_scrambling(edp);
1101 retval = rk32_edp_read_byte_from_dpcd(edp,
1102 DPCD_TRAINING_PATTERN_SET,
1107 retval = rk32_edp_write_byte_to_dpcd(edp,
1108 DPCD_TRAINING_PATTERN_SET,
1109 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1118 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1120 struct rk32_edp *edp = arg;
1121 enum dp_irq_type irq_type;
1123 irq_type = rk32_edp_get_irq_type(edp);
1125 case DP_IRQ_TYPE_HP_CABLE_IN:
1126 dev_info(edp->dev, "Received irq - cable in\n");
1127 rk32_edp_clear_hotplug_interrupts(edp);
1129 case DP_IRQ_TYPE_HP_CABLE_OUT:
1130 dev_info(edp->dev, "Received irq - cable out\n");
1131 rk32_edp_clear_hotplug_interrupts(edp);
1133 case DP_IRQ_TYPE_HP_CHANGE:
1135 * We get these change notifications once in a while, but there
1136 * is nothing we can do with them. Just ignore it for now and
1137 * only handle cable changes.
1139 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1140 rk32_edp_clear_hotplug_interrupts(edp);
1143 dev_err(edp->dev, "Received irq - unknown type!\n");
1149 static int rk32_edp_enable(void)
1152 struct rk32_edp *edp = rk32_edp;
1155 rk32_edp_clk_enable(edp);
1156 rk32_edp_pre_init();
1157 rk32_edp_init_edp(edp);
1158 enable_irq(edp->irq);
1159 /*ret = rk32_edp_handle_edid(edp);
1161 dev_err(edp->dev, "unable to handle edid\n");
1166 ret = rk32_edp_enable_scramble(edp, 0);
1168 dev_err(edp->dev, "unable to set scramble\n");
1172 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1174 dev_err(edp->dev, "unable to set enhanced mode\n");
1177 rk32_edp_enable_enhanced_mode(edp, 1);*/
1179 ret = rk32_edp_set_link_train(edp);
1181 dev_err(edp->dev, "link train failed!\n");
1183 dev_info(edp->dev, "link training success.\n");
1185 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1186 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1187 rk32_edp_init_video(edp);
1189 #ifdef EDP_BIST_MODE
1190 rk32_edp_bist_cfg(edp);
1192 ret = rk32_edp_config_video(edp, &edp->video_info);
1194 dev_err(edp->dev, "unable to config video\n");
1202 static int rk32_edp_disable(void)
1204 struct rk32_edp *edp = rk32_edp;
1206 disable_irq(edp->irq);
1207 rk32_edp_reset(edp);
1208 rk32_edp_analog_power_ctr(edp, 0);
1209 rk32_edp_clk_disable(edp);
1215 static struct rk_fb_trsm_ops trsm_edp_ops = {
1216 .enable = rk32_edp_enable,
1217 .disable = rk32_edp_disable,
1221 #if defined(CONFIG_DEBUG_FS)
1223 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1226 unsigned char buf[12];
1227 struct rk32_edp *edp = s->private;
1229 dev_err(edp->dev, "no edp device!\n");
1234 rk32_edp_read_bytes_from_dpcd(edp,
1235 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1236 for (i = 0; i < 12; i++)
1237 seq_printf(s, "0x%02x>>0x%02x\n", 0x210 + i, buf[i]);
1241 static ssize_t edp_dpcd_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1246 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1248 struct rk32_edp *edp = s->private;
1250 dev_err(edp->dev, "no edp device!\n");
1253 rk32_edp_read_edid(edp);
1254 seq_puts(s, "edid");
1258 static ssize_t edp_edid_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1260 struct rk32_edp *edp = ((struct seq_file *)file->private_data)->private;
1262 dev_err(edp->dev, "no edp device!\n");
1270 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1273 struct rk32_edp *edp = s->private;
1275 dev_err(edp->dev, "no edp device!\n");
1279 for (i = 0; i < 0x284; i++) {
1281 seq_printf(s, "\n%08x: ", i*4);
1282 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1287 static ssize_t edp_reg_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos)
1292 #define EDP_DEBUG_ENTRY(name) \
1293 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1295 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1298 static const struct file_operations edp_##name##_debugfs_fops = { \
1299 .owner = THIS_MODULE, \
1300 .open = edp_##name##_debugfs_open, \
1302 .write = edp_##name##_write, \
1303 .llseek = seq_lseek, \
1304 .release = single_release, \
1307 EDP_DEBUG_ENTRY(dpcd);
1308 EDP_DEBUG_ENTRY(edid);
1309 EDP_DEBUG_ENTRY(reg);
1312 static int rk32_edp_probe(struct platform_device *pdev)
1314 struct rk32_edp *edp;
1315 struct resource *res;
1316 struct device_node *np = pdev->dev.of_node;
1320 dev_err(&pdev->dev, "Missing device tree node.\n");
1324 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1326 dev_err(&pdev->dev, "no memory for state\n");
1329 edp->dev = &pdev->dev;
1330 edp->video_info.h_sync_polarity = 0;
1331 edp->video_info.v_sync_polarity = 0;
1332 edp->video_info.interlaced = 0;
1333 edp->video_info.color_space = CS_RGB;
1334 edp->video_info.dynamic_range = VESA;
1335 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1336 edp->video_info.color_depth = COLOR_8;
1338 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1339 edp->video_info.lane_count = LANE_CNT4;
1340 rk_fb_get_prmry_screen(&edp->screen);
1341 if (edp->screen.type != SCREEN_EDP) {
1342 dev_err(&pdev->dev, "screen is not edp!\n");
1345 platform_set_drvdata(pdev, edp);
1346 dev_set_name(edp->dev, "rk32-edp");
1348 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1350 if (IS_ERR(edp->regs)) {
1351 dev_err(&pdev->dev, "ioremap reg failed\n");
1352 return PTR_ERR(edp->regs);
1355 edp->pd = devm_clk_get(&pdev->dev, "pd_edp");
1356 if (IS_ERR(edp->pd))
1357 dev_err(&pdev->dev, "cannot get pd\n");
1358 edp->clk_edp = devm_clk_get(&pdev->dev, "clk_edp");
1359 if (IS_ERR(edp->clk_edp)) {
1360 dev_err(&pdev->dev, "cannot get clk_edp\n");
1361 return PTR_ERR(edp->clk_edp);
1364 edp->clk_24m = devm_clk_get(&pdev->dev, "clk_edp_24m");
1365 if (IS_ERR(edp->clk_24m)) {
1366 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1367 return PTR_ERR(edp->clk_24m);
1370 edp->pclk = devm_clk_get(&pdev->dev, "pclk_edp");
1371 if (IS_ERR(edp->pclk)) {
1372 dev_err(&pdev->dev, "cannot get pclk\n");
1373 return PTR_ERR(edp->pclk);
1375 rk32_edp_clk_enable(edp);
1376 if (!support_uboot_display())
1377 rk32_edp_pre_init();
1378 edp->irq = platform_get_irq(pdev, 0);
1380 dev_err(&pdev->dev, "cannot find IRQ\n");
1383 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1384 dev_name(&pdev->dev), edp);
1386 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1389 disable_irq_nosync(edp->irq);
1390 if (!support_uboot_display())
1391 rk32_edp_clk_disable(edp);
1393 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1394 #if defined(CONFIG_DEBUG_FS)
1395 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1396 if (IS_ERR(edp->debugfs_dir)) {
1397 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1399 debugfs_create_file("dpcd", S_IRUSR, edp->debugfs_dir,
1400 edp, &edp_dpcd_debugfs_fops);
1401 debugfs_create_file("edid", S_IRUSR, edp->debugfs_dir,
1402 edp, &edp_edid_debugfs_fops);
1403 debugfs_create_file("reg", S_IRUSR, edp->debugfs_dir,
1404 edp, &edp_reg_debugfs_fops);
1408 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1413 static void rk32_edp_shutdown(struct platform_device *pdev)
1418 #if defined(CONFIG_OF)
1419 static const struct of_device_id rk32_edp_dt_ids[] = {
1420 {.compatible = "rockchip,rk32-edp",},
1424 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1427 static struct platform_driver rk32_edp_driver = {
1428 .probe = rk32_edp_probe,
1431 .owner = THIS_MODULE,
1432 #if defined(CONFIG_OF)
1433 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1436 .shutdown = rk32_edp_shutdown,
1439 static int __init rk32_edp_module_init(void)
1441 return platform_driver_register(&rk32_edp_driver);
1444 static void __exit rk32_edp_module_exit(void)
1449 fs_initcall(rk32_edp_module_init);
1450 module_exit(rk32_edp_module_exit);