drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 //#define EDP_BIST_MODE
  35
  36 static struct rk32_edp *rk32_edp;
  37
  38
  39 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  40 {
  41         if (!edp->clk_on) {
  42                 clk_enable(edp->pclk);
  43                 clk_enable(edp->clk_edp);
  44                 clk_enable(edp->clk_24m);
  45                 edp->clk_on = true;
  46         }
  47
  48         return 0;
  49 }
  50
  51 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  52 {
  53         if (edp->clk_on) {
  54                 clk_disable(edp->pclk);
  55                 clk_disable(edp->clk_edp);
  56                 clk_disable(edp->clk_24m);
  57                 edp->clk_on = false;
  58         }
  59
  60         return 0;
  61 }
  62
  63 static int rk32_edp_pre_init(void)
  64 {
  65         u32 val;
  66         val = GRF_EDP_REF_CLK_SEL_INTER |
  67                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  68         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  69
  70         val = 0x80008000;
  71         writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
  72
  73         val = 0x80008000;
  74         writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  75         udelay(1);
  76         val = 0x80000000;
  77         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  78         udelay(1);
  79
  80         return 0;
  81 }
  82
  83 static int rk32_edp_init_edp(struct rk32_edp *edp)
  84 {
  85         struct rk_screen *screen = &edp->screen;
  86         u32 val = 0;
  87
  88         screen->lcdc_id = 1;
  89         if (screen->lcdc_id == 1)  /*select lcdc*/
  90                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  91         else
  92                 val = EDP_SEL_VOP_LIT << 16;
  93         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  94
  95
  96         rk32_edp_reset(edp);
  97         rk32_edp_init_refclk(edp);
  98         rk32_edp_init_interrupt(edp);
  99
 100         rk32_edp_enable_sw_function(edp);
 101
 102         rk32_edp_init_analog_func(edp);
 103
 104         rk32_edp_init_hpd(edp);
 105         rk32_edp_init_aux(edp);
 106
 107         return 0;
 108 }
 109
 110 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 111 {
 112         int timeout_loop = 0;
 113
 114         rk32_edp_init_hpd(edp);
 115
 116         udelay(200);
 117
 118         while (rk32_edp_get_plug_in_status(edp) != 0) {
 119                 timeout_loop++;
 120                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 121                         dev_err(edp->dev, "failed to get hpd plug status\n");
 122                         return -ETIMEDOUT;
 123                 }
 124                 udelay(10);
 125         }
 126
 127         return 0;
 128 }
 129
 130 static int rk32_edp_read_edid(struct rk32_edp *edp)
 131 {
 132         unsigned char edid[EDID_LENGTH * 2];
 133         unsigned int extend_block = 0;
 134         unsigned char sum;
 135         unsigned char test_vector;
 136         int retval;
 137
 138         /*
 139          * EDID device address is 0x50.
 140          * However, if necessary, you must have set upper address
 141          * into E-EDID in I2C device, 0x30.
 142          */
 143
 144         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 145         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 146                                                 &extend_block);
 147         if (retval < 0) {
 148                 dev_err(edp->dev, "EDID extension flag failed!\n");
 149                 return -EIO;
 150         }
 151
 152         if (extend_block > 0) {
 153                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 154
 155                 /* Read EDID data */
 156                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 157                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 158                 if (retval != 0) {
 159                         dev_err(edp->dev, "EDID Read failed!\n");
 160                         return -EIO;
 161                 }
 162                 sum = edp_calc_edid_check_sum(edid);
 163                 if (sum != 0) {
 164                         dev_warn(edp->dev, "EDID bad checksum!\n");
 165                         return 0;
 166                 }
 167
 168                 /* Read additional EDID data */
 169                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 170                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 171                 if (retval != 0) {
 172                         dev_err(edp->dev, "EDID Read failed!\n");
 173                         return -EIO;
 174                 }
 175                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 176                 if (sum != 0) {
 177                         dev_warn(edp->dev, "EDID bad checksum!\n");
 178                         return 0;
 179                 }
 180
 181                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 182                                         &test_vector);
 183                 if (retval < 0) {
 184                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 185                         return retval;
 186                 }
 187
 188                 if (test_vector & DPCD_TEST_EDID_READ) {
 189                         retval = rk32_edp_write_byte_to_dpcd(edp,
 190                                         DPCD_TEST_EDID_CHECKSUM,
 191                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 192                         if (retval < 0) {
 193                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 194                                 return retval;
 195                         }
 196                         retval = rk32_edp_write_byte_to_dpcd(edp,
 197                                         DPCD_TEST_RESPONSE,
 198                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 199                         if (retval < 0) {
 200                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 201                                 return retval;
 202                         }
 203                 }
 204         } else {
 205                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 206
 207                 /* Read EDID data */
 208                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 209                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 210                 if (retval != 0) {
 211                         dev_err(edp->dev, "EDID Read failed!\n");
 212                         return -EIO;
 213                 }
 214                 sum = edp_calc_edid_check_sum(edid);
 215                 if (sum != 0) {
 216                         dev_warn(edp->dev, "EDID bad checksum!\n");
 217                         return 0;
 218                 }
 219
 220                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 221                                                 &test_vector);
 222                 if (retval < 0) {
 223                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 224                         return retval;
 225                 }
 226
 227                 if (test_vector & DPCD_TEST_EDID_READ) {
 228                         retval = rk32_edp_write_byte_to_dpcd(edp,
 229                                         DPCD_TEST_EDID_CHECKSUM,
 230                                         edid[EDID_CHECKSUM]);
 231                         if (retval < 0) {
 232                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 233                                 return retval;
 234                         }
 235                         retval = rk32_edp_write_byte_to_dpcd(edp,
 236                                         DPCD_TEST_RESPONSE,
 237                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 238                         if (retval < 0) {
 239                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 240                                 return retval;
 241                         }
 242                 }
 243         }
 244         fb_edid_to_monspecs(edid, &edp->specs);
 245         dev_err(edp->dev, "EDID Read success!\n");
 246         return 0;
 247 }
 248
 249 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 250 {
 251         u8 buf[12];
 252         int i;
 253         int retval;
 254
 255         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 256         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 257         if (retval < 0)
 258                 return retval;
 259
 260         for (i=0 ;i < 12; i++)
 261                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 262         /* Read EDID */
 263         for (i = 0; i < 3; i++) {
 264                 retval = rk32_edp_read_edid(edp);
 265                 if (retval == 0)
 266                         break;
 267         }
 268
 269         return retval;
 270 }
 271
 272 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 273                                                 bool enable)
 274 {
 275         u8 data;
 276         int retval;
 277
 278         retval = rk32_edp_read_byte_from_dpcd(edp,
 279                         DPCD_LANE_CNT_SET, &data);
 280         if (retval < 0)
 281                 return retval;
 282
 283         if (enable) {
 284                 retval = rk32_edp_write_byte_to_dpcd(edp,
 285                                 DPCD_LANE_CNT_SET,
 286                                 DPCD_ENHANCED_FRAME_EN |
 287                                 DPCD_LANE_COUNT_SET(data));
 288         } else {
 289                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 290                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 291
 292                 retval = rk32_edp_write_byte_to_dpcd(edp,
 293                                 DPCD_LANE_CNT_SET,
 294                                 DPCD_LANE_COUNT_SET(data));
 295         }
 296
 297         return retval;
 298 }
 299
 300 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 301 {
 302         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 303         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 304
 305         if (enable) {
 306                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 307                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 308         } else {
 309                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 310         }*/
 311 }
 312
 313 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 314 {
 315         u8 data;
 316         int retval;
 317
 318         retval = rk32_edp_read_byte_from_dpcd(edp,
 319                         DPCD_MAX_LANE_CNT, &data);
 320         if (retval < 0)
 321                 return retval;
 322
 323         return DPCD_ENHANCED_FRAME_CAP(data);
 324 }
 325
 326 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 327 {
 328         /*rk32_edp_write_byte_to_dpcd(edp,
 329                         DPCD_ADDR_USER_DEFINED1, 0);
 330         rk32_edp_write_byte_to_dpcd(edp,
 331                         DPCD_ADDR_USER_DEFINED2, 0x83);
 332         rk32_edp_write_byte_to_dpcd(edp,
 333                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 334 }
 335
 336 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 337 {
 338         u8 data;
 339         int retval;
 340
 341         retval = rk32_edp_is_enhanced_mode_available(edp);
 342         if (retval < 0)
 343                 return retval;
 344
 345         data = (u8)retval;
 346         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 347         if (retval < 0)
 348                 return retval;
 349
 350         rk32_edp_enable_enhanced_mode(edp, data);
 351
 352         return 0;
 353 }
 354
 355 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 356 {
 357         int retval;
 358
 359         rk32_edp_set_training_pattern(edp, DP_NONE);
 360
 361         retval = rk32_edp_write_byte_to_dpcd(edp,
 362                         DPCD_TRAINING_PATTERN_SET,
 363                         DPCD_TRAINING_PATTERN_DISABLED);
 364         if (retval < 0)
 365                 return retval;
 366
 367         return 0;
 368 }
 369
 370 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 371                                         int pre_emphasis, int lane)
 372 {
 373         switch (lane) {
 374         case 0:
 375                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 376                 break;
 377         case 1:
 378                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 379                 break;
 380
 381         case 2:
 382                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 383                 break;
 384
 385         case 3:
 386                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 387                 break;
 388         }
 389 }
 390
 391 static int rk32_edp_link_start(struct rk32_edp *edp)
 392 {
 393         u8 buf[4];
 394         int lane;
 395         int lane_count;
 396         int retval;
 397
 398         lane_count = edp->link_train.lane_count;
 399
 400         edp->link_train.lt_state = LT_CLK_RECOVERY;
 401         edp->link_train.eq_loop = 0;
 402
 403         for (lane = 0; lane < lane_count; lane++)
 404                 edp->link_train.cr_loop[lane] = 0;
 405
 406         /* Set sink to D0 (Sink Not Ready) mode. */
 407         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 408                                 DPCD_SET_POWER_STATE_D0);
 409         if (retval < 0) {
 410                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 411                 return retval;
 412         }
 413
 414         /* Set link rate and count as you want to establish*/
 415         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 416         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 417
 418         /* Setup RX configuration */
 419         buf[0] = edp->link_train.link_rate;
 420         buf[1] = edp->link_train.lane_count;
 421         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 422                                         2, buf);
 423         if (retval < 0) {
 424                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 425                 return retval;
 426         }
 427
 428         /* Set TX pre-emphasis to level1 */
 429         for (lane = 0; lane < lane_count; lane++)
 430                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 431                         PRE_EMPHASIS_LEVEL_1, lane);
 432
 433         /* Set training pattern 1 */
 434         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 435
 436         /* Set RX training pattern */
 437         retval = rk32_edp_write_byte_to_dpcd(edp,
 438                         DPCD_TRAINING_PATTERN_SET,
 439                         DPCD_SCRAMBLING_DISABLED |
 440                         DPCD_TRAINING_PATTERN_1);
 441         if (retval < 0) {
 442                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 443                 return retval;
 444         }
 445
 446         for (lane = 0; lane < lane_count; lane++)
 447                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 448                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 449         retval = rk32_edp_write_bytes_to_dpcd(edp,
 450                         DPCD_TRAINING_LANE0_SET,
 451                         lane_count, buf);
 452         if (retval < 0) {
 453                 dev_err(edp->dev, "failed to set training lane!\n");
 454                 return retval;
 455         }
 456
 457         return 0;
 458 }
 459
 460 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 461 {
 462         int shift = (lane & 1) * 4;
 463         u8 link_value = link_status[lane>>1];
 464
 465         return (link_value >> shift) & 0xf;
 466 }
 467
 468 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 469 {
 470         int lane;
 471         u8 lane_status;
 472
 473         for (lane = 0; lane < lane_count; lane++) {
 474                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 475                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 476                         return -EINVAL;
 477         }
 478         return 0;
 479 }
 480
 481 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 482 {
 483         int lane;
 484         u8 lane_align;
 485         u8 lane_status;
 486
 487         lane_align = link_align[2];
 488         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 489                 return -EINVAL;
 490
 491         for (lane = 0; lane < lane_count; lane++) {
 492                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 493                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 494                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 495                         return -EINVAL;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 502                                                         int lane)
 503 {
 504         int shift = (lane & 1) * 4;
 505         u8 link_value = adjust_request[lane>>1];
 506
 507         return (link_value >> shift) & 0x3;
 508 }
 509
 510 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 511                                         u8 adjust_request[2],
 512                                         int lane)
 513 {
 514         int shift = (lane & 1) * 4;
 515         u8 link_value = adjust_request[lane>>1];
 516
 517         return ((link_value >> shift) & 0xc) >> 2;
 518 }
 519
 520 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 521                                         u8 training_lane_set, int lane)
 522 {
 523         switch (lane) {
 524         case 0:
 525                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 526                 break;
 527         case 1:
 528                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 529                 break;
 530
 531         case 2:
 532                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 533                 break;
 534
 535         case 3:
 536                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 537                 break;
 538         }
 539 }
 540
 541 static unsigned int rk32_edp_get_lane_link_training(
 542                                 struct rk32_edp *edp,
 543                                 int lane)
 544 {
 545         u32 reg;
 546
 547         switch (lane) {
 548         case 0:
 549                 reg = rk32_edp_get_lane0_link_training(edp);
 550                 break;
 551         case 1:
 552                 reg = rk32_edp_get_lane1_link_training(edp);
 553                 break;
 554         case 2:
 555                 reg = rk32_edp_get_lane2_link_training(edp);
 556                 break;
 557         case 3:
 558                 reg = rk32_edp_get_lane3_link_training(edp);
 559                 break;
 560         }
 561
 562         return reg;
 563 }
 564
 565 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 566 {
 567         rk32_edp_training_pattern_dis(edp);
 568
 569         edp->link_train.lt_state = FAILED;
 570 }
 571
 572 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 573 {
 574         u8 link_status[2];
 575         int lane;
 576         int lane_count;
 577
 578         u8 adjust_request[2];
 579         u8 voltage_swing;
 580         u8 pre_emphasis;
 581         u8 training_lane;
 582         int retval;
 583
 584         udelay(100);
 585
 586         lane_count = edp->link_train.lane_count;
 587
 588         retval = rk32_edp_read_bytes_from_dpcd(edp,
 589                         DPCD_LANE0_1_STATUS,
 590                         2, link_status);
 591         if (retval < 0) {
 592                 dev_err(edp->dev, "failed to read lane status!\n");
 593                 return retval;
 594         }
 595
 596         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 597                 /* set training pattern 2 for EQ */
 598                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 599
 600                 for (lane = 0; lane < lane_count; lane++) {
 601                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 602                                         DPCD_ADJUST_REQUEST_LANE0_1,
 603                                         2, adjust_request);
 604                         if (retval < 0) {
 605                                 dev_err(edp->dev, "failed to read adjust request!\n");
 606                                 return retval;
 607                         }
 608
 609                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 610                                                         adjust_request, lane);
 611                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 612                                                         adjust_request, lane);
 613                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 614                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 615
 616                         if (voltage_swing == VOLTAGE_LEVEL_3)
 617                                 training_lane |= DPCD_MAX_SWING_REACHED;
 618                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 619                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 620
 621                         edp->link_train.training_lane[lane] = training_lane;
 622
 623                         rk32_edp_set_lane_link_training(edp,
 624                                 edp->link_train.training_lane[lane],
 625                                 lane);
 626                 }
 627
 628                 retval = rk32_edp_write_byte_to_dpcd(edp,
 629                                 DPCD_TRAINING_PATTERN_SET,
 630                                 DPCD_SCRAMBLING_DISABLED |
 631                                 DPCD_TRAINING_PATTERN_2);
 632                 if (retval < 0) {
 633                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 634                         return retval;
 635                 }
 636
 637                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 638                                 DPCD_TRAINING_LANE0_SET,
 639                                 lane_count,
 640                                 edp->link_train.training_lane);
 641                 if (retval < 0) {
 642                         dev_err(edp->dev, "failed to set training lane!\n");
 643                         return retval;
 644                 }
 645
 646                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 647                 edp->link_train.lt_state = LT_EQ_TRAINING;
 648         } else {
 649                 for (lane = 0; lane < lane_count; lane++) {
 650                         training_lane = rk32_edp_get_lane_link_training(
 651                                                         edp, lane);
 652                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 653                                         DPCD_ADJUST_REQUEST_LANE0_1,
 654                                         2, adjust_request);
 655                         if (retval < 0) {
 656                                 dev_err(edp->dev, "failed to read adjust request!\n");
 657                                 return retval;
 658                         }
 659
 660                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 661                                                         adjust_request, lane);
 662                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 663                                                         adjust_request, lane);
 664
 665                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 666                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 667                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 668                                 goto reduce_link_rate;
 669                         }
 670
 671                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 672                                         voltage_swing) &&
 673                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 674                                         pre_emphasis)) {
 675                                 edp->link_train.cr_loop[lane]++;
 676                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 677                                         dev_err(edp->dev, "CR Max loop\n");
 678                                         goto reduce_link_rate;
 679                                 }
 680                         }
 681
 682                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 683                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 684
 685                         if (voltage_swing == VOLTAGE_LEVEL_3)
 686                                 training_lane |= DPCD_MAX_SWING_REACHED;
 687                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 688                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 689
 690                         edp->link_train.training_lane[lane] = training_lane;
 691
 692                         rk32_edp_set_lane_link_training(edp,
 693                                 edp->link_train.training_lane[lane], lane);
 694                 }
 695
 696                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 697                                 DPCD_TRAINING_LANE0_SET,
 698                                 lane_count,
 699                                 edp->link_train.training_lane);
 700                 if (retval < 0) {
 701                         dev_err(edp->dev, "failed to set training lane!\n");
 702                         return retval;
 703                 }
 704         }
 705
 706         return 0;
 707
 708 reduce_link_rate:
 709         rk32_edp_reduce_link_rate(edp);
 710         return -EIO;
 711 }
 712
 713 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 714 {
 715         u8 link_status[2];
 716         u8 link_align[3];
 717         int lane;
 718         int lane_count;
 719         u32 reg;
 720
 721         u8 adjust_request[2];
 722         u8 voltage_swing;
 723         u8 pre_emphasis;
 724         u8 training_lane;
 725         int retval;
 726
 727         udelay(400);
 728
 729         lane_count = edp->link_train.lane_count;
 730
 731         retval = rk32_edp_read_bytes_from_dpcd(edp,
 732                         DPCD_LANE0_1_STATUS,
 733                         2, link_status);
 734         if (retval < 0) {
 735                 dev_err(edp->dev, "failed to read lane status!\n");
 736                 return retval;
 737         }
 738
 739         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 740                 link_align[0] = link_status[0];
 741                 link_align[1] = link_status[1];
 742
 743                 retval = rk32_edp_read_byte_from_dpcd(edp,
 744                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 745                                 &link_align[2]);
 746                 if (retval < 0) {
 747                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 748                         return retval;
 749                 }
 750
 751                 for (lane = 0; lane < lane_count; lane++) {
 752                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 753                                         DPCD_ADJUST_REQUEST_LANE0_1,
 754                                         2, adjust_request);
 755                         if (retval < 0) {
 756                                 dev_err(edp->dev, "failed to read adjust request!\n");
 757                                 return retval;
 758                         }
 759
 760                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 761                                                         adjust_request, lane);
 762                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 763                                                         adjust_request, lane);
 764                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 765                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 766
 767                         if (voltage_swing == VOLTAGE_LEVEL_3)
 768                                 training_lane |= DPCD_MAX_SWING_REACHED;
 769                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 770                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 771
 772                         edp->link_train.training_lane[lane] = training_lane;
 773                 }
 774
 775                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 776                         /* traing pattern Set to Normal */
 777                         retval = rk32_edp_training_pattern_dis(edp);
 778                         if (retval < 0) {
 779                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 780                                 return retval;
 781                         }
 782
 783                         dev_info(edp->dev, "Link Training success!\n");
 784
 785                         rk32_edp_get_link_bandwidth(edp, &reg);
 786                         edp->link_train.link_rate = reg;
 787                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 788                                 edp->link_train.link_rate);
 789
 790                         rk32_edp_get_lane_count(edp, &reg);
 791                         edp->link_train.lane_count = reg;
 792                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 793                                 edp->link_train.lane_count);
 794
 795                         edp->link_train.lt_state = FINISHED;
 796                 } else {
 797                         /* not all locked */
 798                         edp->link_train.eq_loop++;
 799
 800                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 801                                 dev_err(edp->dev, "EQ Max loop\n");
 802                                 goto reduce_link_rate;
 803                         }
 804
 805                         for (lane = 0; lane < lane_count; lane++)
 806                                 rk32_edp_set_lane_link_training(edp,
 807                                         edp->link_train.training_lane[lane],
 808                                         lane);
 809
 810                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 811                                         DPCD_TRAINING_LANE0_SET,
 812                                         lane_count,
 813                                         edp->link_train.training_lane);
 814                         if (retval < 0) {
 815                                 dev_err(edp->dev, "failed to set training lane!\n");
 816                                 return retval;
 817                         }
 818                 }
 819         } else {
 820                 goto reduce_link_rate;
 821         }
 822
 823         return 0;
 824
 825 reduce_link_rate:
 826         rk32_edp_reduce_link_rate(edp);
 827         return -EIO;
 828 }
 829
 830 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 831                                         u8 *bandwidth)
 832 {
 833         u8 data;
 834         int retval;
 835
 836         /*
 837          * For DP rev.1.1, Maximum link rate of Main Link lanes
 838          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 839          */
 840         retval = rk32_edp_read_byte_from_dpcd(edp,
 841                         DPCD_MAX_LINK_RATE, &data);
 842         if (retval < 0)
 843                 return retval;
 844
 845         *bandwidth = data;
 846         return 0;
 847 }
 848
 849 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 850                                         u8 *lane_count)
 851 {
 852         u8 data;
 853         int retval;
 854
 855         /*
 856          * For DP rev.1.1, Maximum number of Main Link lanes
 857          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 858          */
 859         retval = rk32_edp_read_byte_from_dpcd(edp,
 860                         DPCD_MAX_LANE_CNT, &data);
 861         if (retval < 0)
 862                 return retval;
 863
 864         *lane_count = DPCD_MAX_LANE_COUNT(data);
 865         return 0;
 866 }
 867
 868 static int rk32_edp_init_training(struct rk32_edp *edp)
 869 {
 870         int retval;
 871
 872         /*
 873          * MACRO_RST must be applied after the PLL_LOCK to avoid
 874          * the DP inter pair skew issue for at least 10 us
 875          */
 876         rk32_edp_reset_macro(edp);
 877
 878
 879         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 880         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 881         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 882                         edp->link_train.link_rate * 27/100,
 883                         edp->link_train.link_rate*27%100,
 884                         edp->link_train.lane_count);
 885
 886         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 887            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 888                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 889                         "use default link rate:%d.%dGps\n",
 890                         edp->link_train.link_rate,
 891                         edp->video_info.link_rate*27/100,
 892                         edp->video_info.link_rate*27%100);
 893                 edp->link_train.link_rate = edp->video_info.link_rate;
 894         }
 895
 896         if (edp->link_train.lane_count == 0) {
 897                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 898                         "use default lanes:%d\n",
 899                         edp->link_train.lane_count,
 900                         edp->video_info.lane_count);
 901                 edp->link_train.lane_count = edp->video_info.lane_count;
 902         }
 903
 904         rk32_edp_analog_power_ctr(edp, 1);
 905
 906
 907         return 0;
 908 }
 909
 910 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 911 {
 912         int retval = 0;
 913         int training_finished = 0;
 914
 915         edp->link_train.lt_state = LT_START;
 916
 917         /* Process here */
 918         while (!training_finished) {
 919                 switch (edp->link_train.lt_state) {
 920                 case LT_START:
 921                         retval = rk32_edp_link_start(edp);
 922                         if (retval)
 923                                 dev_err(edp->dev, "LT Start failed\n");
 924                         break;
 925                 case LT_CLK_RECOVERY:
 926                         retval = rk32_edp_process_clock_recovery(edp);
 927                         if (retval)
 928                                 dev_err(edp->dev, "LT CR failed\n");
 929                         break;
 930                 case LT_EQ_TRAINING:
 931                         retval = rk32_edp_process_equalizer_training(edp);
 932                         if (retval)
 933                                 dev_err(edp->dev, "LT EQ failed\n");
 934                         break;
 935                 case FINISHED:
 936                         training_finished = 1;
 937                         break;
 938                 case FAILED:
 939                         return -EREMOTEIO;
 940                 }
 941         }
 942
 943         return retval;
 944 }
 945
 946
 947 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 948 {
 949         u32 cnt = 50;
 950         u32 val;
 951         /* Set link rate and count as you want to establish*/
 952         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 953         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 954         rk32_edp_hw_link_training_en(edp);
 955         val = rk32_edp_wait_hw_lt_done(edp);
 956         while (val) {
 957                 if (cnt-- <= 0) {
 958                         dev_err(edp->dev, "hw lt timeout");
 959                         return -ETIMEDOUT;
 960                 }
 961                 mdelay(1);
 962                 val = rk32_edp_wait_hw_lt_done(edp);
 963         }
 964
 965         val = rk32_edp_get_hw_lt_status(edp);
 966         if (val)
 967                 dev_err(edp->dev, "hw lt err:%d\n", val);
 968         return val;
 969
 970 }
 971 static int rk32_edp_set_link_train(struct rk32_edp *edp)
 972 {
 973         int retval;
 974
 975         retval = rk32_edp_init_training(edp);
 976         if (retval < 0)
 977                 dev_err(edp->dev, "DP LT init failed!\n");
 978 #if 0
 979         retval = rk32_edp_sw_link_training(edp);
 980 #else
 981         retval = rk32_edp_hw_link_training(edp);
 982 #endif
 983
 984         return retval;
 985 }
 986
 987 static int rk32_edp_config_video(struct rk32_edp *edp,
 988                         struct video_info *video_info)
 989 {
 990         int retval = 0;
 991         int timeout_loop = 0;
 992         int done_count = 0;
 993
 994         rk32_edp_config_video_slave_mode(edp, video_info);
 995
 996         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 997                         video_info->color_space,
 998                         video_info->dynamic_range,
 999                         video_info->ycbcr_coeff);
1000
1001         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1002                 dev_err(edp->dev, "PLL is not locked yet.\n");
1003                 return -EINVAL;
1004         }
1005
1006         for (;;) {
1007                 timeout_loop++;
1008                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1009                         break;
1010                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1011                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1012                         return -ETIMEDOUT;
1013                 }
1014
1015                 usleep_range(1, 1);
1016         }
1017
1018         /* Set to use the register calculated M/N video */
1019         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1020
1021         /* For video bist, Video timing must be generated by register */
1022         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1023
1024         /* Disable video mute */
1025         rk32_edp_enable_video_mute(edp, 0);
1026
1027         /* Configure video slave mode */
1028         rk32_edp_enable_video_master(edp, 0);
1029
1030         /* Enable video */
1031         rk32_edp_start_video(edp);
1032
1033         timeout_loop = 0;
1034
1035         for (;;) {
1036                 timeout_loop++;
1037                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1038                         done_count++;
1039                         if (done_count > 10)
1040                                 break;
1041                 } else if (done_count) {
1042                         done_count = 0;
1043                 }
1044                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1045                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1046                         return -ETIMEDOUT;
1047                 }
1048
1049                 usleep_range(1000, 1000);
1050         }
1051
1052         if (retval != 0)
1053                 dev_err(edp->dev, "Video stream is not detected!\n");
1054
1055         return retval;
1056 }
1057
1058 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1059 {
1060         u8 data;
1061         int retval;
1062
1063         if (enable) {
1064                 rk32_edp_enable_scrambling(edp);
1065
1066                 retval = rk32_edp_read_byte_from_dpcd(edp,
1067                                 DPCD_TRAINING_PATTERN_SET,
1068                                 &data);
1069                 if (retval < 0)
1070                         return retval;
1071
1072                 retval = rk32_edp_write_byte_to_dpcd(edp,
1073                                 DPCD_TRAINING_PATTERN_SET,
1074                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1075                 if (retval < 0)
1076                         return retval;
1077         } else {
1078                 rk32_edp_disable_scrambling(edp);
1079
1080                 retval = rk32_edp_read_byte_from_dpcd(edp,
1081                                 DPCD_TRAINING_PATTERN_SET,
1082                                 &data);
1083                 if (retval < 0)
1084                         return retval;
1085
1086                 retval = rk32_edp_write_byte_to_dpcd(edp,
1087                                 DPCD_TRAINING_PATTERN_SET,
1088                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1089                 if (retval < 0)
1090                         return retval;
1091         }
1092
1093         return 0;
1094 }
1095
1096 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1097 {
1098         struct rk32_edp *edp = arg;
1099         enum dp_irq_type irq_type;
1100
1101         irq_type = rk32_edp_get_irq_type(edp);
1102
1103         return IRQ_HANDLED;
1104 }
1105
1106 static int rk32_edp_enable(void)
1107 {
1108         int ret = 0;
1109         struct rk32_edp *edp = rk32_edp;
1110
1111
1112         rk32_edp_clk_enable(edp);
1113         rk32_edp_pre_init();
1114         rk32_edp_init_edp(edp);
1115
1116         /*ret = rk32_edp_handle_edid(edp);
1117         if (ret) {
1118                 dev_err(edp->dev, "unable to handle edid\n");
1119                 //goto out;
1120         }
1121
1122
1123         ret = rk32_edp_enable_scramble(edp, 0);
1124         if (ret) {
1125                 dev_err(edp->dev, "unable to set scramble\n");
1126                 //goto out;
1127         }
1128
1129         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1130         if (ret) {
1131                 dev_err(edp->dev, "unable to set enhanced mode\n");
1132                 //goto out;
1133         }
1134         rk32_edp_enable_enhanced_mode(edp, 1);*/
1135
1136         ret = rk32_edp_set_link_train(edp);
1137         if (ret)
1138                 dev_err(edp->dev, "link train failed!\n");
1139         else
1140                 dev_info(edp->dev, "link training success.\n");
1141
1142         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1143         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1144
1145 #ifdef EDP_BIST_MODE
1146         rk32_edp_bist_cfg(edp);
1147 #else
1148         rk32_edp_init_video(edp);
1149         ret = rk32_edp_config_video(edp, &edp->video_info);
1150         if (ret)
1151                 dev_err(edp->dev, "unable to config video\n");
1152 #endif
1153         return ret;
1154
1155
1156
1157 }
1158
1159 static int  rk32_edp_disable(void )
1160 {
1161         struct rk32_edp *edp = rk32_edp;
1162
1163         rk32_edp_reset(edp);
1164         rk32_edp_analog_power_ctr(edp, 0);
1165         rk32_edp_clk_disable(edp);
1166
1167         return 0;
1168 }
1169
1170
1171 static struct rk_fb_trsm_ops trsm_edp_ops = {
1172         .enable = rk32_edp_enable,
1173         .disable = rk32_edp_disable,
1174 };
1175 static int rk32_edp_probe(struct platform_device *pdev)
1176 {
1177         struct rk32_edp *edp;
1178         struct resource *res;
1179         struct device_node *np = pdev->dev.of_node;
1180         int ret;
1181
1182         if (!np) {
1183                 dev_err(&pdev->dev, "Missing device tree node.\n");
1184                 return -EINVAL;
1185         }
1186
1187         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1188         if (!edp) {
1189                 dev_err(&pdev->dev, "no memory for state\n");
1190                 return -ENOMEM;
1191         }
1192         edp->dev = &pdev->dev;
1193         edp->video_info.h_sync_polarity = 0;
1194         edp->video_info.v_sync_polarity = 0;
1195         edp->video_info.interlaced      = 0;
1196         edp->video_info.color_space     = CS_RGB;
1197         edp->video_info.dynamic_range   = VESA;
1198         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1199         edp->video_info.color_depth     = COLOR_8;
1200
1201         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1202         edp->video_info.lane_count      = LANE_CNT4;
1203         rk_fb_get_prmry_screen(&edp->screen);
1204         if (edp->screen.type != SCREEN_EDP) {
1205                 dev_err(&pdev->dev, "screen is not edp!\n");
1206                 return -EINVAL;
1207         }
1208         platform_set_drvdata(pdev, edp);
1209         dev_set_name(edp->dev, "rk32-edp");
1210
1211         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1213         if (IS_ERR(edp->regs)) {
1214                 dev_err(&pdev->dev, "ioremap reg failed\n");
1215                 return PTR_ERR(edp->regs);
1216         }
1217
1218         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1219         if (IS_ERR(edp->clk_edp)) {
1220                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1221                 return PTR_ERR(edp->clk_edp);
1222         }
1223
1224         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1225         if (IS_ERR(edp->clk_24m)) {
1226                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1227                 return PTR_ERR(edp->clk_24m);
1228         }
1229
1230         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1231         if (IS_ERR(edp->pclk)) {
1232                 dev_err(&pdev->dev, "cannot get pclk\n");
1233                 return PTR_ERR(edp->pclk);
1234         }
1235
1236         clk_prepare(edp->pclk);
1237         clk_prepare(edp->clk_edp);
1238         clk_prepare(edp->clk_24m);
1239         rk32_edp_clk_enable(edp);
1240         rk32_edp_pre_init();
1241         edp->irq = platform_get_irq(pdev, 0);
1242         if (edp->irq < 0) {
1243                 dev_err(&pdev->dev, "cannot find IRQ\n");
1244                 return edp->irq;
1245         }
1246         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1247                         dev_name(&pdev->dev), edp);
1248         if (ret) {
1249                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1250                 return ret;
1251         }
1252         disable_irq(edp->irq);
1253         rk32_edp_clk_disable(edp);
1254         rk32_edp = edp;
1255         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1256         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1257
1258         return 0;
1259 }
1260
1261 static void rk32_edp_shutdown(struct platform_device *pdev)
1262 {
1263
1264 }
1265
1266 #if defined(CONFIG_OF)
1267 static const struct of_device_id rk32_edp_dt_ids[] = {
1268         {.compatible = "rockchip,rk32-edp",},
1269         {}
1270 };
1271
1272 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1273 #endif
1274
1275 static struct platform_driver rk32_edp_driver = {
1276         .probe = rk32_edp_probe,
1277         .driver = {
1278                    .name = "rk32-edp",
1279                    .owner = THIS_MODULE,
1280 #if defined(CONFIG_OF)
1281                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1282 #endif
1283         },
1284         .shutdown = rk32_edp_shutdown,
1285 };
1286
1287 static int __init rk32_edp_module_init(void)
1288 {
1289         return platform_driver_register(&rk32_edp_driver);
1290 }
1291
1292 static void __exit rk32_edp_module_exit(void)
1293 {
1294
1295 }
1296
1297 subsys_initcall_sync(rk32_edp_module_init);
1298 module_exit(rk32_edp_module_exit);