drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 /*#define EDP_BIST_MODE*/
  35
  36 static struct rk32_edp *rk32_edp;
  37 static int rk32_edp_init_edp(struct rk32_edp *edp)
  38 {
  39         struct rk_screen *screen = &edp->screen;
  40         u32 val = 0;
  41
  42         if (screen->lcdc_id == 1)  /*select lcdc*/
  43                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  44         else
  45                 val = EDP_SEL_VOP_LIT << 16;
  46         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
  47
  48         rk32_edp_reset(edp);
  49         rk32_edp_init_refclk(edp);
  50         rk32_edp_init_interrupt(edp);
  51
  52         rk32_edp_enable_sw_function(edp);
  53
  54         rk32_edp_init_analog_func(edp);
  55
  56         rk32_edp_init_hpd(edp);
  57         rk32_edp_init_aux(edp);
  58
  59         return 0;
  60 }
  61
  62 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
  63 {
  64         int timeout_loop = 0;
  65
  66         rk32_edp_init_hpd(edp);
  67
  68         udelay(200);
  69
  70         while (rk32_edp_get_plug_in_status(edp) != 0) {
  71                 timeout_loop++;
  72                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
  73                         dev_err(edp->dev, "failed to get hpd plug status\n");
  74                         return -ETIMEDOUT;
  75                 }
  76                 udelay(10);
  77         }
  78
  79         return 0;
  80 }
  81
  82 static int rk32_edp_read_edid(struct rk32_edp *edp)
  83 {
  84         unsigned char edid[EDID_LENGTH * 2];
  85         unsigned int extend_block = 0;
  86         unsigned char sum;
  87         unsigned char test_vector;
  88         int retval;
  89
  90         /*
  91          * EDID device address is 0x50.
  92          * However, if necessary, you must have set upper address
  93          * into E-EDID in I2C device, 0x30.
  94          */
  95
  96         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
  97         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
  98                                                 &extend_block);
  99         if (retval < 0) {
 100                 dev_err(edp->dev, "EDID extension flag failed!\n");
 101                 return -EIO;
 102         }
 103
 104         if (extend_block > 0) {
 105                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 106
 107                 /* Read EDID data */
 108                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 109                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 110                 if (retval != 0) {
 111                         dev_err(edp->dev, "EDID Read failed!\n");
 112                         return -EIO;
 113                 }
 114                 sum = edp_calc_edid_check_sum(edid);
 115                 if (sum != 0) {
 116                         dev_warn(edp->dev, "EDID bad checksum!\n");
 117                         return 0;
 118                 }
 119
 120                 /* Read additional EDID data */
 121                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 122                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 123                 if (retval != 0) {
 124                         dev_err(edp->dev, "EDID Read failed!\n");
 125                         return -EIO;
 126                 }
 127                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 128                 if (sum != 0) {
 129                         dev_warn(edp->dev, "EDID bad checksum!\n");
 130                         return 0;
 131                 }
 132
 133                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 134                                         &test_vector);
 135                 if (retval < 0) {
 136                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 137                         return retval;
 138                 }
 139
 140                 if (test_vector & DPCD_TEST_EDID_READ) {
 141                         retval = rk32_edp_write_byte_to_dpcd(edp,
 142                                         DPCD_TEST_EDID_CHECKSUM,
 143                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 144                         if (retval < 0) {
 145                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 146                                 return retval;
 147                         }
 148                         retval = rk32_edp_write_byte_to_dpcd(edp,
 149                                         DPCD_TEST_RESPONSE,
 150                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 151                         if (retval < 0) {
 152                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 153                                 return retval;
 154                         }
 155                 }
 156         } else {
 157                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 158
 159                 /* Read EDID data */
 160                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 161                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 162                 if (retval != 0) {
 163                         dev_err(edp->dev, "EDID Read failed!\n");
 164                         return -EIO;
 165                 }
 166                 sum = edp_calc_edid_check_sum(edid);
 167                 if (sum != 0) {
 168                         dev_warn(edp->dev, "EDID bad checksum!\n");
 169                         return 0;
 170                 }
 171
 172                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 173                                                 &test_vector);
 174                 if (retval < 0) {
 175                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 176                         return retval;
 177                 }
 178
 179                 if (test_vector & DPCD_TEST_EDID_READ) {
 180                         retval = rk32_edp_write_byte_to_dpcd(edp,
 181                                         DPCD_TEST_EDID_CHECKSUM,
 182                                         edid[EDID_CHECKSUM]);
 183                         if (retval < 0) {
 184                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 185                                 return retval;
 186                         }
 187                         retval = rk32_edp_write_byte_to_dpcd(edp,
 188                                         DPCD_TEST_RESPONSE,
 189                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 190                         if (retval < 0) {
 191                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 192                                 return retval;
 193                         }
 194                 }
 195         }
 196
 197         dev_err(edp->dev, "EDID Read success!\n");
 198         return 0;
 199 }
 200
 201 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 202 {
 203         u8 buf[12];
 204         int i;
 205         int retval;
 206
 207         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 208         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 209         if (retval < 0)
 210                 return retval;
 211
 212         /* Read EDID */
 213         for (i = 0; i < 3; i++) {
 214                 retval = rk32_edp_read_edid(edp);
 215                 if (retval == 0)
 216                         break;
 217         }
 218
 219         return retval;
 220 }
 221
 222 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 223                                                 bool enable)
 224 {
 225         u8 data;
 226         int retval;
 227
 228         retval = rk32_edp_read_byte_from_dpcd(edp,
 229                         DPCD_LANE_CNT_SET, &data);
 230         if (retval < 0)
 231                 return retval;
 232
 233         if (enable) {
 234                 retval = rk32_edp_write_byte_to_dpcd(edp,
 235                                 DPCD_LANE_CNT_SET,
 236                                 DPCD_ENHANCED_FRAME_EN |
 237                                 DPCD_LANE_COUNT_SET(data));
 238         } else {
 239                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 240                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 241
 242                 retval = rk32_edp_write_byte_to_dpcd(edp,
 243                                 DPCD_LANE_CNT_SET,
 244                                 DPCD_LANE_COUNT_SET(data));
 245         }
 246
 247         return retval;
 248 }
 249
 250 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 251 {
 252         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 253         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 254
 255         if (enable) {
 256                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 257                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 258         } else {
 259                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 260         }*/
 261 }
 262
 263 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 264 {
 265         u8 data;
 266         int retval;
 267
 268         retval = rk32_edp_read_byte_from_dpcd(edp,
 269                         DPCD_MAX_LANE_CNT, &data);
 270         if (retval < 0)
 271                 return retval;
 272
 273         return DPCD_ENHANCED_FRAME_CAP(data);
 274 }
 275
 276 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 277 {
 278         /*rk32_edp_write_byte_to_dpcd(edp,
 279                         DPCD_ADDR_USER_DEFINED1, 0);
 280         rk32_edp_write_byte_to_dpcd(edp,
 281                         DPCD_ADDR_USER_DEFINED2, 0x83);
 282         rk32_edp_write_byte_to_dpcd(edp,
 283                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 284 }
 285
 286 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 287 {
 288         u8 data;
 289         int retval;
 290
 291         retval = rk32_edp_is_enhanced_mode_available(edp);
 292         if (retval < 0)
 293                 return retval;
 294
 295         data = (u8)retval;
 296         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 297         if (retval < 0)
 298                 return retval;
 299
 300         rk32_edp_enable_enhanced_mode(edp, data);
 301
 302         return 0;
 303 }
 304
 305 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 306 {
 307         int retval;
 308
 309         rk32_edp_set_training_pattern(edp, DP_NONE);
 310
 311         retval = rk32_edp_write_byte_to_dpcd(edp,
 312                         DPCD_TRAINING_PATTERN_SET,
 313                         DPCD_TRAINING_PATTERN_DISABLED);
 314         if (retval < 0)
 315                 return retval;
 316
 317         return 0;
 318 }
 319
 320 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 321                                         int pre_emphasis, int lane)
 322 {
 323         switch (lane) {
 324         case 0:
 325                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 326                 break;
 327         case 1:
 328                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 329                 break;
 330
 331         case 2:
 332                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 333                 break;
 334
 335         case 3:
 336                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 337                 break;
 338         }
 339 }
 340
 341 static int rk32_edp_link_start(struct rk32_edp *edp)
 342 {
 343         u8 buf[4];
 344         int lane;
 345         int lane_count;
 346         int retval;
 347
 348         lane_count = edp->link_train.lane_count;
 349
 350         edp->link_train.lt_state = LT_CLK_RECOVERY;
 351         edp->link_train.eq_loop = 0;
 352
 353         for (lane = 0; lane < lane_count; lane++)
 354                 edp->link_train.cr_loop[lane] = 0;
 355
 356         /* Set sink to D0 (Sink Not Ready) mode. */
 357         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 358                                 DPCD_SET_POWER_STATE_D0);
 359         if (retval < 0) {
 360                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 361                 return retval;
 362         }
 363
 364         /* Set link rate and count as you want to establish*/
 365         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 366         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 367
 368         /* Setup RX configuration */
 369         buf[0] = edp->link_train.link_rate;
 370         buf[1] = edp->link_train.lane_count;
 371         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 372                                         2, buf);
 373         if (retval < 0) {
 374                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 375                 return retval;
 376         }
 377
 378         /* Set TX pre-emphasis to level1 */
 379         for (lane = 0; lane < lane_count; lane++)
 380                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 381                         PRE_EMPHASIS_LEVEL_1, lane);
 382
 383         /* Set training pattern 1 */
 384         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 385
 386         /* Set RX training pattern */
 387         retval = rk32_edp_write_byte_to_dpcd(edp,
 388                         DPCD_TRAINING_PATTERN_SET,
 389                         DPCD_SCRAMBLING_DISABLED |
 390                         DPCD_TRAINING_PATTERN_1);
 391         if (retval < 0) {
 392                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 393                 return retval;
 394         }
 395
 396         for (lane = 0; lane < lane_count; lane++)
 397                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 398                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 399         retval = rk32_edp_write_bytes_to_dpcd(edp,
 400                         DPCD_TRAINING_LANE0_SET,
 401                         lane_count, buf);
 402         if (retval < 0) {
 403                 dev_err(edp->dev, "failed to set training lane!\n");
 404                 return retval;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 411 {
 412         int shift = (lane & 1) * 4;
 413         u8 link_value = link_status[lane>>1];
 414
 415         return (link_value >> shift) & 0xf;
 416 }
 417
 418 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 419 {
 420         int lane;
 421         u8 lane_status;
 422
 423         for (lane = 0; lane < lane_count; lane++) {
 424                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 425                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 426                         return -EINVAL;
 427         }
 428         return 0;
 429 }
 430
 431 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 432 {
 433         int lane;
 434         u8 lane_align;
 435         u8 lane_status;
 436
 437         lane_align = link_align[2];
 438         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 439                 return -EINVAL;
 440
 441         for (lane = 0; lane < lane_count; lane++) {
 442                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 443                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 444                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 445                         return -EINVAL;
 446         }
 447
 448         return 0;
 449 }
 450
 451 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 452                                                         int lane)
 453 {
 454         int shift = (lane & 1) * 4;
 455         u8 link_value = adjust_request[lane>>1];
 456
 457         return (link_value >> shift) & 0x3;
 458 }
 459
 460 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 461                                         u8 adjust_request[2],
 462                                         int lane)
 463 {
 464         int shift = (lane & 1) * 4;
 465         u8 link_value = adjust_request[lane>>1];
 466
 467         return ((link_value >> shift) & 0xc) >> 2;
 468 }
 469
 470 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 471                                         u8 training_lane_set, int lane)
 472 {
 473         switch (lane) {
 474         case 0:
 475                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 476                 break;
 477         case 1:
 478                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 479                 break;
 480
 481         case 2:
 482                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 483                 break;
 484
 485         case 3:
 486                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 487                 break;
 488         }
 489 }
 490
 491 static unsigned int rk32_edp_get_lane_link_training(
 492                                 struct rk32_edp *edp,
 493                                 int lane)
 494 {
 495         u32 reg;
 496
 497         switch (lane) {
 498         case 0:
 499                 reg = rk32_edp_get_lane0_link_training(edp);
 500                 break;
 501         case 1:
 502                 reg = rk32_edp_get_lane1_link_training(edp);
 503                 break;
 504         case 2:
 505                 reg = rk32_edp_get_lane2_link_training(edp);
 506                 break;
 507         case 3:
 508                 reg = rk32_edp_get_lane3_link_training(edp);
 509                 break;
 510         }
 511
 512         return reg;
 513 }
 514
 515 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 516 {
 517         rk32_edp_training_pattern_dis(edp);
 518
 519         edp->link_train.lt_state = FAILED;
 520 }
 521
 522 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 523 {
 524         u8 link_status[2];
 525         int lane;
 526         int lane_count;
 527
 528         u8 adjust_request[2];
 529         u8 voltage_swing;
 530         u8 pre_emphasis;
 531         u8 training_lane;
 532         int retval;
 533
 534         udelay(100);
 535
 536         lane_count = edp->link_train.lane_count;
 537
 538         retval = rk32_edp_read_bytes_from_dpcd(edp,
 539                         DPCD_LANE0_1_STATUS,
 540                         2, link_status);
 541         if (retval < 0) {
 542                 dev_err(edp->dev, "failed to read lane status!\n");
 543                 return retval;
 544         }
 545
 546         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 547                 /* set training pattern 2 for EQ */
 548                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 549
 550                 for (lane = 0; lane < lane_count; lane++) {
 551                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 552                                         DPCD_ADJUST_REQUEST_LANE0_1,
 553                                         2, adjust_request);
 554                         if (retval < 0) {
 555                                 dev_err(edp->dev, "failed to read adjust request!\n");
 556                                 return retval;
 557                         }
 558
 559                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 560                                                         adjust_request, lane);
 561                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 562                                                         adjust_request, lane);
 563                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 564                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 565
 566                         if (voltage_swing == VOLTAGE_LEVEL_3)
 567                                 training_lane |= DPCD_MAX_SWING_REACHED;
 568                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 569                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 570
 571                         edp->link_train.training_lane[lane] = training_lane;
 572
 573                         rk32_edp_set_lane_link_training(edp,
 574                                 edp->link_train.training_lane[lane],
 575                                 lane);
 576                 }
 577
 578                 retval = rk32_edp_write_byte_to_dpcd(edp,
 579                                 DPCD_TRAINING_PATTERN_SET,
 580                                 DPCD_SCRAMBLING_DISABLED |
 581                                 DPCD_TRAINING_PATTERN_2);
 582                 if (retval < 0) {
 583                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 584                         return retval;
 585                 }
 586
 587                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 588                                 DPCD_TRAINING_LANE0_SET,
 589                                 lane_count,
 590                                 edp->link_train.training_lane);
 591                 if (retval < 0) {
 592                         dev_err(edp->dev, "failed to set training lane!\n");
 593                         return retval;
 594                 }
 595
 596                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 597                 edp->link_train.lt_state = LT_EQ_TRAINING;
 598         } else {
 599                 for (lane = 0; lane < lane_count; lane++) {
 600                         training_lane = rk32_edp_get_lane_link_training(
 601                                                         edp, lane);
 602                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 603                                         DPCD_ADJUST_REQUEST_LANE0_1,
 604                                         2, adjust_request);
 605                         if (retval < 0) {
 606                                 dev_err(edp->dev, "failed to read adjust request!\n");
 607                                 return retval;
 608                         }
 609
 610                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 611                                                         adjust_request, lane);
 612                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 613                                                         adjust_request, lane);
 614
 615                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 616                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 617                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 618                                 goto reduce_link_rate;
 619                         }
 620
 621                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 622                                         voltage_swing) &&
 623                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 624                                         pre_emphasis)) {
 625                                 edp->link_train.cr_loop[lane]++;
 626                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 627                                         dev_err(edp->dev, "CR Max loop\n");
 628                                         goto reduce_link_rate;
 629                                 }
 630                         }
 631
 632                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 633                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 634
 635                         if (voltage_swing == VOLTAGE_LEVEL_3)
 636                                 training_lane |= DPCD_MAX_SWING_REACHED;
 637                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 638                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 639
 640                         edp->link_train.training_lane[lane] = training_lane;
 641
 642                         rk32_edp_set_lane_link_training(edp,
 643                                 edp->link_train.training_lane[lane], lane);
 644                 }
 645
 646                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 647                                 DPCD_TRAINING_LANE0_SET,
 648                                 lane_count,
 649                                 edp->link_train.training_lane);
 650                 if (retval < 0) {
 651                         dev_err(edp->dev, "failed to set training lane!\n");
 652                         return retval;
 653                 }
 654         }
 655
 656         return 0;
 657
 658 reduce_link_rate:
 659         rk32_edp_reduce_link_rate(edp);
 660         return -EIO;
 661 }
 662
 663 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 664 {
 665         u8 link_status[2];
 666         u8 link_align[3];
 667         int lane;
 668         int lane_count;
 669         u32 reg;
 670
 671         u8 adjust_request[2];
 672         u8 voltage_swing;
 673         u8 pre_emphasis;
 674         u8 training_lane;
 675         int retval;
 676
 677         udelay(400);
 678
 679         lane_count = edp->link_train.lane_count;
 680
 681         retval = rk32_edp_read_bytes_from_dpcd(edp,
 682                         DPCD_LANE0_1_STATUS,
 683                         2, link_status);
 684         if (retval < 0) {
 685                 dev_err(edp->dev, "failed to read lane status!\n");
 686                 return retval;
 687         }
 688
 689         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 690                 link_align[0] = link_status[0];
 691                 link_align[1] = link_status[1];
 692
 693                 retval = rk32_edp_read_byte_from_dpcd(edp,
 694                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 695                                 &link_align[2]);
 696                 if (retval < 0) {
 697                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 698                         return retval;
 699                 }
 700
 701                 for (lane = 0; lane < lane_count; lane++) {
 702                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 703                                         DPCD_ADJUST_REQUEST_LANE0_1,
 704                                         2, adjust_request);
 705                         if (retval < 0) {
 706                                 dev_err(edp->dev, "failed to read adjust request!\n");
 707                                 return retval;
 708                         }
 709
 710                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 711                                                         adjust_request, lane);
 712                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 713                                                         adjust_request, lane);
 714                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 715                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 716
 717                         if (voltage_swing == VOLTAGE_LEVEL_3)
 718                                 training_lane |= DPCD_MAX_SWING_REACHED;
 719                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 720                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 721
 722                         edp->link_train.training_lane[lane] = training_lane;
 723                 }
 724
 725                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 726                         /* traing pattern Set to Normal */
 727                         retval = rk32_edp_training_pattern_dis(edp);
 728                         if (retval < 0) {
 729                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 730                                 return retval;
 731                         }
 732
 733                         dev_info(edp->dev, "Link Training success!\n");
 734
 735                         rk32_edp_get_link_bandwidth(edp, &reg);
 736                         edp->link_train.link_rate = reg;
 737                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 738                                 edp->link_train.link_rate);
 739
 740                         rk32_edp_get_lane_count(edp, &reg);
 741                         edp->link_train.lane_count = reg;
 742                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 743                                 edp->link_train.lane_count);
 744
 745                         edp->link_train.lt_state = FINISHED;
 746                 } else {
 747                         /* not all locked */
 748                         edp->link_train.eq_loop++;
 749
 750                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 751                                 dev_err(edp->dev, "EQ Max loop\n");
 752                                 goto reduce_link_rate;
 753                         }
 754
 755                         for (lane = 0; lane < lane_count; lane++)
 756                                 rk32_edp_set_lane_link_training(edp,
 757                                         edp->link_train.training_lane[lane],
 758                                         lane);
 759
 760                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 761                                         DPCD_TRAINING_LANE0_SET,
 762                                         lane_count,
 763                                         edp->link_train.training_lane);
 764                         if (retval < 0) {
 765                                 dev_err(edp->dev, "failed to set training lane!\n");
 766                                 return retval;
 767                         }
 768                 }
 769         } else {
 770                 goto reduce_link_rate;
 771         }
 772
 773         return 0;
 774
 775 reduce_link_rate:
 776         rk32_edp_reduce_link_rate(edp);
 777         return -EIO;
 778 }
 779
 780 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 781                                         u8 *bandwidth)
 782 {
 783         u8 data;
 784         int retval;
 785
 786         /*
 787          * For DP rev.1.1, Maximum link rate of Main Link lanes
 788          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 789          */
 790         retval = rk32_edp_read_byte_from_dpcd(edp,
 791                         DPCD_MAX_LINK_RATE, &data);
 792         if (retval < 0)
 793                 return retval;
 794
 795         *bandwidth = data;
 796         return 0;
 797 }
 798
 799 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 800                                         u8 *lane_count)
 801 {
 802         u8 data;
 803         int retval;
 804
 805         /*
 806          * For DP rev.1.1, Maximum number of Main Link lanes
 807          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 808          */
 809         retval = rk32_edp_read_byte_from_dpcd(edp,
 810                         DPCD_MAX_LANE_CNT, &data);
 811         if (retval < 0)
 812                 return retval;
 813
 814         *lane_count = DPCD_MAX_LANE_COUNT(data);
 815         return 0;
 816 }
 817
 818 static int rk32_edp_init_training(struct rk32_edp *edp,
 819                         enum link_lane_count_type max_lane,
 820                         u32 max_rate)
 821 {
 822         int retval;
 823
 824         /*
 825          * MACRO_RST must be applied after the PLL_LOCK to avoid
 826          * the DP inter pair skew issue for at least 10 us
 827          */
 828         rk32_edp_reset_macro(edp);
 829
 830
 831         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 832         if (retval < 0)
 833                 return retval;
 834
 835         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 836         if (retval < 0)
 837                 return retval;
 838         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 839                         edp->link_train.link_rate * 27/100,
 840                         edp->link_train.link_rate*27%100,
 841                         edp->link_train.lane_count);
 842
 843         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 844            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 845                 dev_err(edp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 846                         edp->link_train.link_rate);
 847                 edp->link_train.link_rate = LINK_RATE_1_62GBPS;
 848         }
 849
 850         if (edp->link_train.lane_count == 0) {
 851                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !\n",
 852                         edp->link_train.lane_count);
 853                 edp->link_train.lane_count = (u8)LANE_CNT1;
 854         }
 855
 856
 857         if (edp->link_train.lane_count > max_lane)
 858                 edp->link_train.lane_count = max_lane;
 859         if (edp->link_train.link_rate > max_rate)
 860                 edp->link_train.link_rate = max_rate;
 861
 862
 863         rk32_edp_analog_power_ctr(edp, 1);
 864
 865         return 0;
 866 }
 867
 868 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 869 {
 870         int retval = 0;
 871         int training_finished = 0;
 872
 873         edp->link_train.lt_state = LT_START;
 874
 875         /* Process here */
 876         while (!training_finished) {
 877                 switch (edp->link_train.lt_state) {
 878                 case LT_START:
 879                         retval = rk32_edp_link_start(edp);
 880                         if (retval)
 881                                 dev_err(edp->dev, "LT Start failed\n");
 882                         break;
 883                 case LT_CLK_RECOVERY:
 884                         retval = rk32_edp_process_clock_recovery(edp);
 885                         if (retval)
 886                                 dev_err(edp->dev, "LT CR failed\n");
 887                         break;
 888                 case LT_EQ_TRAINING:
 889                         retval = rk32_edp_process_equalizer_training(edp);
 890                         if (retval)
 891                                 dev_err(edp->dev, "LT EQ failed\n");
 892                         break;
 893                 case FINISHED:
 894                         training_finished = 1;
 895                         break;
 896                 case FAILED:
 897                         return -EREMOTEIO;
 898                 }
 899         }
 900
 901         return retval;
 902 }
 903
 904
 905 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 906 {
 907         u32 cnt = 50;
 908         u32 val;
 909         /* Set link rate and count as you want to establish*/
 910         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 911         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 912         rk32_edp_hw_link_training_en(edp);
 913         mdelay(1);
 914         val = rk32_edp_wait_hw_lt_done(edp);
 915         while (val) {
 916                 if (cnt-- <= 0) {
 917                         dev_err(edp->dev, "hw lt timeout");
 918                         return -ETIMEDOUT;
 919                 }
 920                 mdelay(1);
 921                 val = rk32_edp_wait_hw_lt_done(edp);
 922         }
 923
 924         val = rk32_edp_get_hw_lt_status(edp);
 925         if (val)
 926                 dev_err(edp->dev, "hw lt err:%d\n", val);
 927         return val;
 928
 929 }
 930 static int rk32_edp_set_link_train(struct rk32_edp *edp,
 931                                 u32 count,
 932                                 u32 bwtype)
 933 {
 934         int retval;
 935
 936         retval = rk32_edp_init_training(edp, count, bwtype);
 937         if (retval < 0)
 938                 dev_err(edp->dev, "DP LT init failed!\n");
 939 #if 0
 940         retval = rk32_edp_sw_link_training(edp);
 941 #else
 942         retval = rk32_edp_hw_link_training(edp);
 943 #endif
 944
 945         return retval;
 946 }
 947
 948 static int rk32_edp_config_video(struct rk32_edp *edp,
 949                         struct video_info *video_info)
 950 {
 951         int retval = 0;
 952         int timeout_loop = 0;
 953         int done_count = 0;
 954
 955         rk32_edp_config_video_slave_mode(edp, video_info);
 956
 957         rk32_edp_set_video_color_format(edp, video_info->color_depth,
 958                         video_info->color_space,
 959                         video_info->dynamic_range,
 960                         video_info->ycbcr_coeff);
 961
 962         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
 963                 dev_err(edp->dev, "PLL is not locked yet.\n");
 964                 return -EINVAL;
 965         }
 966
 967         for (;;) {
 968                 timeout_loop++;
 969                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
 970                         break;
 971                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 972                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
 973                         return -ETIMEDOUT;
 974                 }
 975
 976                 usleep_range(1, 1);
 977         }
 978
 979         /* Set to use the register calculated M/N video */
 980         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
 981
 982         /* For video bist, Video timing must be generated by register */
 983         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
 984
 985         /* Disable video mute */
 986         rk32_edp_enable_video_mute(edp, 0);
 987
 988         /* Configure video slave mode */
 989         rk32_edp_enable_video_master(edp, 0);
 990
 991         /* Enable video */
 992         rk32_edp_start_video(edp);
 993
 994         timeout_loop = 0;
 995
 996         for (;;) {
 997                 timeout_loop++;
 998                 if (rk32_edp_is_video_stream_on(edp) == 0) {
 999                         done_count++;
1000                         if (done_count > 10)
1001                                 break;
1002                 } else if (done_count) {
1003                         done_count = 0;
1004                 }
1005                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1006                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1007                         return -ETIMEDOUT;
1008                 }
1009
1010                 usleep_range(1000, 1000);
1011         }
1012
1013         if (retval != 0)
1014                 dev_err(edp->dev, "Video stream is not detected!\n");
1015
1016         return retval;
1017 }
1018
1019 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1020 {
1021         u8 data;
1022         int retval;
1023
1024         if (enable) {
1025                 rk32_edp_enable_scrambling(edp);
1026
1027                 retval = rk32_edp_read_byte_from_dpcd(edp,
1028                                 DPCD_TRAINING_PATTERN_SET,
1029                                 &data);
1030                 if (retval < 0)
1031                         return retval;
1032
1033                 retval = rk32_edp_write_byte_to_dpcd(edp,
1034                                 DPCD_TRAINING_PATTERN_SET,
1035                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1036                 if (retval < 0)
1037                         return retval;
1038         } else {
1039                 rk32_edp_disable_scrambling(edp);
1040
1041                 retval = rk32_edp_read_byte_from_dpcd(edp,
1042                                 DPCD_TRAINING_PATTERN_SET,
1043                                 &data);
1044                 if (retval < 0)
1045                         return retval;
1046
1047                 retval = rk32_edp_write_byte_to_dpcd(edp,
1048                                 DPCD_TRAINING_PATTERN_SET,
1049                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1050                 if (retval < 0)
1051                         return retval;
1052         }
1053
1054         return 0;
1055 }
1056
1057 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1058 {
1059         struct rk32_edp *edp = arg;
1060
1061         dev_info(edp->dev, "rk32_edp_isr\n");
1062         return IRQ_HANDLED;
1063 }
1064
1065 static int rk32_edp_enable(void)
1066 {
1067         int ret = 0;
1068         int retry = 0;
1069         struct rk32_edp *edp = rk32_edp;
1070         if (edp->enabled)
1071                 goto out;
1072
1073         edp->enabled = 1;
1074         clk_enable(edp->pclk);
1075         clk_enable(edp->clk_edp);
1076         clk_enable(edp->clk_24m);
1077 edp_phy_init:
1078
1079
1080         rk32_edp_init_edp(edp);
1081
1082
1083         ret = rk32_edp_handle_edid(edp);
1084         if (ret) {
1085                 dev_err(edp->dev, "unable to handle edid\n");
1086                 goto out;
1087         }
1088
1089
1090         ret = rk32_edp_enable_scramble(edp, 0);
1091         if (ret) {
1092                 dev_err(edp->dev, "unable to set scramble\n");
1093                 goto out;
1094         }
1095
1096         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1097         if (ret) {
1098                 dev_err(edp->dev, "unable to set enhanced mode\n");
1099                 goto out;
1100         }
1101         rk32_edp_enable_enhanced_mode(edp, 0);
1102
1103        /* Link Training */
1104         ret = rk32_edp_set_link_train(edp, LANE_CNT4, LINK_RATE_2_70GBPS);
1105         if (ret) {
1106                 dev_err(edp->dev, "link train failed\n");
1107                 goto out;
1108         }
1109
1110         rk32_edp_set_lane_count(edp, edp->video_info.lane_count);
1111         rk32_edp_set_link_bandwidth(edp, edp->video_info.link_rate);
1112
1113 #ifdef EDP_BIST_MODE
1114         rk32_edp_bist_cfg(edp);
1115 #else
1116         rk32_edp_init_video(edp);
1117         ret = rk32_edp_config_video(edp, &edp->video_info);
1118         if (ret) {
1119                 dev_err(edp->dev, "unable to config video\n");
1120                 goto out;
1121         }
1122 #endif
1123
1124         return 0;
1125
1126 out:
1127
1128         if (retry < 3) {
1129                 retry++;
1130                 goto edp_phy_init;
1131         }
1132
1133         dev_err(edp->dev, "DP LT exceeds max retry count");
1134
1135         return ret;
1136 }
1137
1138 static int  rk32_edp_disable(void )
1139 {
1140         struct rk32_edp *edp = rk32_edp;
1141
1142         if (!edp->enabled)
1143                 return 0;
1144
1145         edp->enabled = 0;
1146
1147         rk32_edp_reset(edp);
1148         rk32_edp_analog_power_ctr(edp, 0);
1149
1150         clk_disable(edp->clk_24m);
1151         clk_disable(edp->clk_edp);
1152         clk_disable(edp->pclk);
1153
1154         return 0;
1155 }
1156
1157
1158 static struct rk_fb_trsm_ops trsm_edp_ops = {
1159         .enable = rk32_edp_enable,
1160         .disable = rk32_edp_disable,
1161 };
1162 static int rk32_edp_probe(struct platform_device *pdev)
1163 {
1164         struct rk32_edp *edp;
1165         struct resource *res;
1166         struct device_node *np = pdev->dev.of_node;
1167         int ret;
1168
1169         if (!np) {
1170                 dev_err(&pdev->dev, "Missing device tree node.\n");
1171                 return -EINVAL;
1172         }
1173
1174         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1175         if (!edp) {
1176                 dev_err(&pdev->dev, "no memory for state\n");
1177                 return -ENOMEM;
1178         }
1179         edp->dev = &pdev->dev;
1180         edp->video_info.h_sync_polarity = 0;
1181         edp->video_info.v_sync_polarity = 0;
1182         edp->video_info.interlaced      = 0;
1183         edp->video_info.color_space     = CS_RGB;
1184         edp->video_info.dynamic_range   = VESA;
1185         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1186         edp->video_info.color_depth     = COLOR_8;
1187
1188         edp->video_info.link_rate       = LINK_RATE_2_70GBPS;
1189         edp->video_info.lane_count      = LANE_CNT4;
1190         rk_fb_get_prmry_screen(&edp->screen);
1191         if (edp->screen.type != SCREEN_EDP) {
1192                 dev_err(&pdev->dev, "screen is not edp!\n");
1193                 return -EINVAL;
1194         }
1195         platform_set_drvdata(pdev, edp);
1196         dev_set_name(edp->dev, "rk32-edp");
1197
1198         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1199         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1200         if (IS_ERR(edp->regs)) {
1201                 dev_err(&pdev->dev, "ioremap reg failed\n");
1202                 return PTR_ERR(edp->regs);
1203         }
1204
1205         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1206         if (IS_ERR(edp->clk_edp)) {
1207                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1208                 return PTR_ERR(edp->clk_edp);
1209         }
1210
1211         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1212         if (IS_ERR(edp->clk_24m)) {
1213                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1214                 return PTR_ERR(edp->clk_24m);
1215         }
1216
1217         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1218         if (IS_ERR(edp->pclk)) {
1219                 dev_err(&pdev->dev, "cannot get pclk\n");
1220                 return PTR_ERR(edp->pclk);
1221         }
1222
1223         edp->irq = platform_get_irq(pdev, 0);
1224         if (edp->irq < 0) {
1225                 dev_err(&pdev->dev, "cannot find IRQ\n");
1226                 return edp->irq;
1227         }
1228         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1229                         dev_name(&pdev->dev), edp);
1230         if (ret) {
1231                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1232                 return ret;
1233         }
1234         rk32_edp = edp;
1235         clk_prepare(edp->pclk);
1236         clk_prepare(edp->clk_edp);
1237         clk_prepare(edp->clk_24m);
1238         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1239         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1240
1241         return 0;
1242 }
1243
1244 static void rk32_edp_shutdown(struct platform_device *pdev)
1245 {
1246
1247 }
1248
1249 #if defined(CONFIG_OF)
1250 static const struct of_device_id rk32_edp_dt_ids[] = {
1251         {.compatible = "rockchip, rk32-edp",},
1252         {}
1253 };
1254
1255 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1256 #endif
1257
1258 static struct platform_driver rk32_edp_driver = {
1259         .probe = rk32_edp_probe,
1260         .driver = {
1261                    .name = "rk32-edp",
1262                    .owner = THIS_MODULE,
1263 #if defined(CONFIG_OF)
1264                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1265 #endif
1266         },
1267         .shutdown = rk32_edp_shutdown,
1268 };
1269
1270 static int __init rk32_edp_module_init(void)
1271 {
1272         return platform_driver_register(&rk32_edp_driver);
1273 }
1274
1275 static void __exit rk32_edp_module_exit(void)
1276 {
1277
1278 }
1279
1280 subsys_initcall_sync(rk32_edp_module_init);
1281 module_exit(rk32_edp_module_exit);