2 * DisplayPort driver for rk32xx
4 * Copyright (C) ROCKCHIP, Inc.
5 *Author:yxj<yxj@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/errno.h>
19 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/interrupt.h>
23 #include <linux/clk.h>
24 #include <linux/platform_device.h>
25 #include <linux/uaccess.h>
26 #include <linux/rockchip/iomap.h>
27 #include <linux/rockchip/grf.h>
30 #if defined(CONFIG_OF)
34 #if defined(CONFIG_DEBUG_FS)
36 #include <linux/debugfs.h>
37 #include <linux/seq_file.h>
40 //#define EDP_BIST_MODE
42 static struct rk32_edp *rk32_edp;
44 static int rk32_edp_clk_enable(struct rk32_edp *edp)
48 clk_enable(edp->pclk);
49 clk_enable(edp->clk_edp);
50 clk_enable(edp->clk_24m);
57 static int rk32_edp_clk_disable(struct rk32_edp *edp)
60 clk_disable(edp->pclk);
61 clk_disable(edp->clk_edp);
62 clk_disable(edp->clk_24m);
70 static int rk32_edp_pre_init(void)
73 val = GRF_EDP_REF_CLK_SEL_INTER |
74 (GRF_EDP_REF_CLK_SEL_INTER << 16);
75 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
78 writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
81 writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
85 writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
91 static int rk32_edp_init_edp(struct rk32_edp *edp)
93 struct rk_screen *screen = &edp->screen;
97 if (screen->lcdc_id == 1) /*select lcdc*/
98 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
100 val = EDP_SEL_VOP_LIT << 16;
101 writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
105 rk32_edp_init_refclk(edp);
106 rk32_edp_init_interrupt(edp);
108 rk32_edp_enable_sw_function(edp);
110 rk32_edp_init_analog_func(edp);
112 rk32_edp_init_hpd(edp);
113 rk32_edp_init_aux(edp);
118 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
120 int timeout_loop = 0;
122 rk32_edp_init_hpd(edp);
126 while (rk32_edp_get_plug_in_status(edp) != 0) {
128 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
129 dev_err(edp->dev, "failed to get hpd plug status\n");
138 static int rk32_edp_read_edid(struct rk32_edp *edp)
140 unsigned char edid[EDID_LENGTH * 2];
141 unsigned int extend_block = 0;
143 unsigned char test_vector;
147 * EDID device address is 0x50.
148 * However, if necessary, you must have set upper address
149 * into E-EDID in I2C device, 0x30.
152 /* Read Extension Flag, Number of 128-byte EDID extension blocks */
153 retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
156 dev_err(edp->dev, "EDID extension flag failed!\n");
160 if (extend_block > 0) {
161 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
164 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
165 EDID_LENGTH, &edid[EDID_HEADER]);
167 dev_err(edp->dev, "EDID Read failed!\n");
170 sum = edp_calc_edid_check_sum(edid);
172 dev_warn(edp->dev, "EDID bad checksum!\n");
176 /* Read additional EDID data */
177 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
178 EDID_LENGTH, &edid[EDID_LENGTH]);
180 dev_err(edp->dev, "EDID Read failed!\n");
183 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
185 dev_warn(edp->dev, "EDID bad checksum!\n");
189 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
192 dev_err(edp->dev, "DPCD EDID Read failed!\n");
196 if (test_vector & DPCD_TEST_EDID_READ) {
197 retval = rk32_edp_write_byte_to_dpcd(edp,
198 DPCD_TEST_EDID_CHECKSUM,
199 edid[EDID_LENGTH + EDID_CHECKSUM]);
201 dev_err(edp->dev, "DPCD EDID Write failed!\n");
204 retval = rk32_edp_write_byte_to_dpcd(edp,
206 DPCD_TEST_EDID_CHECKSUM_WRITE);
208 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
213 dev_info(edp->dev, "EDID data does not include any extensions.\n");
216 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
217 EDID_LENGTH, &edid[EDID_HEADER]);
219 dev_err(edp->dev, "EDID Read failed!\n");
222 sum = edp_calc_edid_check_sum(edid);
224 dev_warn(edp->dev, "EDID bad checksum!\n");
228 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
231 dev_err(edp->dev, "DPCD EDID Read failed!\n");
235 if (test_vector & DPCD_TEST_EDID_READ) {
236 retval = rk32_edp_write_byte_to_dpcd(edp,
237 DPCD_TEST_EDID_CHECKSUM,
238 edid[EDID_CHECKSUM]);
240 dev_err(edp->dev, "DPCD EDID Write failed!\n");
243 retval = rk32_edp_write_byte_to_dpcd(edp,
245 DPCD_TEST_EDID_CHECKSUM_WRITE);
247 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
252 fb_edid_to_monspecs(edid, &edp->specs);
253 dev_err(edp->dev, "EDID Read success!\n");
257 static int rk32_edp_handle_edid(struct rk32_edp *edp)
263 /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
264 retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
268 for (i=0 ;i < 12; i++)
269 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
271 for (i = 0; i < 3; i++) {
272 retval = rk32_edp_read_edid(edp);
280 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
286 retval = rk32_edp_read_byte_from_dpcd(edp,
287 DPCD_LANE_CNT_SET, &data);
292 retval = rk32_edp_write_byte_to_dpcd(edp,
294 DPCD_ENHANCED_FRAME_EN |
295 DPCD_LANE_COUNT_SET(data));
297 /*retval = rk32_edp_write_byte_to_dpcd(edp,
298 DPCD_ADDR_CONFIGURATION_SET, 0);*/
300 retval = rk32_edp_write_byte_to_dpcd(edp,
302 DPCD_LANE_COUNT_SET(data));
308 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
310 /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
311 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
314 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
315 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
317 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
321 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
326 retval = rk32_edp_read_byte_from_dpcd(edp,
327 DPCD_MAX_LANE_CNT, &data);
331 return DPCD_ENHANCED_FRAME_CAP(data);
334 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
336 /*rk32_edp_write_byte_to_dpcd(edp,
337 DPCD_ADDR_USER_DEFINED1, 0);
338 rk32_edp_write_byte_to_dpcd(edp,
339 DPCD_ADDR_USER_DEFINED2, 0x83);
340 rk32_edp_write_byte_to_dpcd(edp,
341 DPCD_ADDR_USER_DEFINED3, 0x27);*/
344 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
349 retval = rk32_edp_is_enhanced_mode_available(edp);
354 retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
358 rk32_edp_enable_enhanced_mode(edp, data);
363 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
367 rk32_edp_set_training_pattern(edp, DP_NONE);
369 retval = rk32_edp_write_byte_to_dpcd(edp,
370 DPCD_TRAINING_PATTERN_SET,
371 DPCD_TRAINING_PATTERN_DISABLED);
378 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
379 int pre_emphasis, int lane)
383 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
386 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
390 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
394 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
399 static int rk32_edp_link_start(struct rk32_edp *edp)
406 lane_count = edp->link_train.lane_count;
408 edp->link_train.lt_state = LT_CLK_RECOVERY;
409 edp->link_train.eq_loop = 0;
411 for (lane = 0; lane < lane_count; lane++)
412 edp->link_train.cr_loop[lane] = 0;
414 /* Set sink to D0 (Sink Not Ready) mode. */
415 retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
416 DPCD_SET_POWER_STATE_D0);
418 dev_err(edp->dev, "failed to set sink device to D0!\n");
422 /* Set link rate and count as you want to establish*/
423 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
424 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
426 /* Setup RX configuration */
427 buf[0] = edp->link_train.link_rate;
428 buf[1] = edp->link_train.lane_count;
429 retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
432 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
436 /* Set TX pre-emphasis to level1 */
437 for (lane = 0; lane < lane_count; lane++)
438 rk32_edp_set_lane_lane_pre_emphasis(edp,
439 PRE_EMPHASIS_LEVEL_1, lane);
441 /* Set training pattern 1 */
442 rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
444 /* Set RX training pattern */
445 retval = rk32_edp_write_byte_to_dpcd(edp,
446 DPCD_TRAINING_PATTERN_SET,
447 DPCD_SCRAMBLING_DISABLED |
448 DPCD_TRAINING_PATTERN_1);
450 dev_err(edp->dev, "failed to set training pattern 1!\n");
454 for (lane = 0; lane < lane_count; lane++)
455 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
456 DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
457 retval = rk32_edp_write_bytes_to_dpcd(edp,
458 DPCD_TRAINING_LANE0_SET,
461 dev_err(edp->dev, "failed to set training lane!\n");
468 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
470 int shift = (lane & 1) * 4;
471 u8 link_value = link_status[lane>>1];
473 return (link_value >> shift) & 0xf;
476 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
481 for (lane = 0; lane < lane_count; lane++) {
482 lane_status = rk32_edp_get_lane_status(link_status, lane);
483 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
489 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
495 lane_align = link_align[2];
496 if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
499 for (lane = 0; lane < lane_count; lane++) {
500 lane_status = rk32_edp_get_lane_status(link_align, lane);
501 lane_status &= DPCD_CHANNEL_EQ_BITS;
502 if (lane_status != DPCD_CHANNEL_EQ_BITS)
509 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
512 int shift = (lane & 1) * 4;
513 u8 link_value = adjust_request[lane>>1];
515 return (link_value >> shift) & 0x3;
518 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
519 u8 adjust_request[2],
522 int shift = (lane & 1) * 4;
523 u8 link_value = adjust_request[lane>>1];
525 return ((link_value >> shift) & 0xc) >> 2;
528 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
529 u8 training_lane_set, int lane)
533 rk32_edp_set_lane0_link_training(edp, training_lane_set);
536 rk32_edp_set_lane1_link_training(edp, training_lane_set);
540 rk32_edp_set_lane2_link_training(edp, training_lane_set);
544 rk32_edp_set_lane3_link_training(edp, training_lane_set);
549 static unsigned int rk32_edp_get_lane_link_training(
550 struct rk32_edp *edp,
557 reg = rk32_edp_get_lane0_link_training(edp);
560 reg = rk32_edp_get_lane1_link_training(edp);
563 reg = rk32_edp_get_lane2_link_training(edp);
566 reg = rk32_edp_get_lane3_link_training(edp);
573 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
575 rk32_edp_training_pattern_dis(edp);
577 edp->link_train.lt_state = FAILED;
580 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
586 u8 adjust_request[2];
594 lane_count = edp->link_train.lane_count;
596 retval = rk32_edp_read_bytes_from_dpcd(edp,
600 dev_err(edp->dev, "failed to read lane status!\n");
604 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
605 /* set training pattern 2 for EQ */
606 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
608 for (lane = 0; lane < lane_count; lane++) {
609 retval = rk32_edp_read_bytes_from_dpcd(edp,
610 DPCD_ADJUST_REQUEST_LANE0_1,
613 dev_err(edp->dev, "failed to read adjust request!\n");
617 voltage_swing = rk32_edp_get_adjust_request_voltage(
618 adjust_request, lane);
619 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
620 adjust_request, lane);
621 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
622 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
624 if (voltage_swing == VOLTAGE_LEVEL_3)
625 training_lane |= DPCD_MAX_SWING_REACHED;
626 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
627 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
629 edp->link_train.training_lane[lane] = training_lane;
631 rk32_edp_set_lane_link_training(edp,
632 edp->link_train.training_lane[lane],
636 retval = rk32_edp_write_byte_to_dpcd(edp,
637 DPCD_TRAINING_PATTERN_SET,
638 DPCD_SCRAMBLING_DISABLED |
639 DPCD_TRAINING_PATTERN_2);
641 dev_err(edp->dev, "failed to set training pattern 2!\n");
645 retval = rk32_edp_write_bytes_to_dpcd(edp,
646 DPCD_TRAINING_LANE0_SET,
648 edp->link_train.training_lane);
650 dev_err(edp->dev, "failed to set training lane!\n");
654 dev_info(edp->dev, "Link Training Clock Recovery success\n");
655 edp->link_train.lt_state = LT_EQ_TRAINING;
657 for (lane = 0; lane < lane_count; lane++) {
658 training_lane = rk32_edp_get_lane_link_training(
660 retval = rk32_edp_read_bytes_from_dpcd(edp,
661 DPCD_ADJUST_REQUEST_LANE0_1,
664 dev_err(edp->dev, "failed to read adjust request!\n");
668 voltage_swing = rk32_edp_get_adjust_request_voltage(
669 adjust_request, lane);
670 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
671 adjust_request, lane);
673 if (voltage_swing == VOLTAGE_LEVEL_3 ||
674 pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
675 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
676 goto reduce_link_rate;
679 if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
681 (DPCD_PRE_EMPHASIS_GET(training_lane) ==
683 edp->link_train.cr_loop[lane]++;
684 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
685 dev_err(edp->dev, "CR Max loop\n");
686 goto reduce_link_rate;
690 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
691 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
693 if (voltage_swing == VOLTAGE_LEVEL_3)
694 training_lane |= DPCD_MAX_SWING_REACHED;
695 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
696 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
698 edp->link_train.training_lane[lane] = training_lane;
700 rk32_edp_set_lane_link_training(edp,
701 edp->link_train.training_lane[lane], lane);
704 retval = rk32_edp_write_bytes_to_dpcd(edp,
705 DPCD_TRAINING_LANE0_SET,
707 edp->link_train.training_lane);
709 dev_err(edp->dev, "failed to set training lane!\n");
717 rk32_edp_reduce_link_rate(edp);
721 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
729 u8 adjust_request[2];
737 lane_count = edp->link_train.lane_count;
739 retval = rk32_edp_read_bytes_from_dpcd(edp,
743 dev_err(edp->dev, "failed to read lane status!\n");
747 if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
748 link_align[0] = link_status[0];
749 link_align[1] = link_status[1];
751 retval = rk32_edp_read_byte_from_dpcd(edp,
752 DPCD_LANE_ALIGN_STATUS_UPDATED,
755 dev_err(edp->dev, "failed to read lane aligne status!\n");
759 for (lane = 0; lane < lane_count; lane++) {
760 retval = rk32_edp_read_bytes_from_dpcd(edp,
761 DPCD_ADJUST_REQUEST_LANE0_1,
764 dev_err(edp->dev, "failed to read adjust request!\n");
768 voltage_swing = rk32_edp_get_adjust_request_voltage(
769 adjust_request, lane);
770 pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
771 adjust_request, lane);
772 training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
773 DPCD_PRE_EMPHASIS_SET(pre_emphasis);
775 if (voltage_swing == VOLTAGE_LEVEL_3)
776 training_lane |= DPCD_MAX_SWING_REACHED;
777 if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
778 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
780 edp->link_train.training_lane[lane] = training_lane;
783 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
784 /* traing pattern Set to Normal */
785 retval = rk32_edp_training_pattern_dis(edp);
787 dev_err(edp->dev, "failed to disable training pattern!\n");
791 dev_info(edp->dev, "Link Training success!\n");
793 rk32_edp_get_link_bandwidth(edp, ®);
794 edp->link_train.link_rate = reg;
795 dev_dbg(edp->dev, "final bandwidth = %.2x\n",
796 edp->link_train.link_rate);
798 rk32_edp_get_lane_count(edp, ®);
799 edp->link_train.lane_count = reg;
800 dev_dbg(edp->dev, "final lane count = %.2x\n",
801 edp->link_train.lane_count);
803 edp->link_train.lt_state = FINISHED;
806 edp->link_train.eq_loop++;
808 if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
809 dev_err(edp->dev, "EQ Max loop\n");
810 goto reduce_link_rate;
813 for (lane = 0; lane < lane_count; lane++)
814 rk32_edp_set_lane_link_training(edp,
815 edp->link_train.training_lane[lane],
818 retval = rk32_edp_write_bytes_to_dpcd(edp,
819 DPCD_TRAINING_LANE0_SET,
821 edp->link_train.training_lane);
823 dev_err(edp->dev, "failed to set training lane!\n");
828 goto reduce_link_rate;
834 rk32_edp_reduce_link_rate(edp);
838 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
845 * For DP rev.1.1, Maximum link rate of Main Link lanes
846 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
848 retval = rk32_edp_read_byte_from_dpcd(edp,
849 DPCD_MAX_LINK_RATE, &data);
858 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
865 * For DP rev.1.1, Maximum number of Main Link lanes
866 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
868 retval = rk32_edp_read_byte_from_dpcd(edp,
869 DPCD_MAX_LANE_CNT, &data);
873 *lane_count = DPCD_MAX_LANE_COUNT(data);
877 static int rk32_edp_init_training(struct rk32_edp *edp)
882 * MACRO_RST must be applied after the PLL_LOCK to avoid
883 * the DP inter pair skew issue for at least 10 us
885 rk32_edp_reset_macro(edp);
888 retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
889 retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
890 dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
891 edp->link_train.link_rate * 27/100,
892 edp->link_train.link_rate*27%100,
893 edp->link_train.lane_count);
895 if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
896 (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
897 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
898 "use default link rate:%d.%dGps\n",
899 edp->link_train.link_rate,
900 edp->video_info.link_rate*27/100,
901 edp->video_info.link_rate*27%100);
902 edp->link_train.link_rate = edp->video_info.link_rate;
905 if (edp->link_train.lane_count == 0) {
906 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
907 "use default lanes:%d\n",
908 edp->link_train.lane_count,
909 edp->video_info.lane_count);
910 edp->link_train.lane_count = edp->video_info.lane_count;
913 rk32_edp_analog_power_ctr(edp, 1);
919 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
922 int training_finished = 0;
924 edp->link_train.lt_state = LT_START;
927 while (!training_finished) {
928 switch (edp->link_train.lt_state) {
930 retval = rk32_edp_link_start(edp);
932 dev_err(edp->dev, "LT Start failed\n");
934 case LT_CLK_RECOVERY:
935 retval = rk32_edp_process_clock_recovery(edp);
937 dev_err(edp->dev, "LT CR failed\n");
940 retval = rk32_edp_process_equalizer_training(edp);
942 dev_err(edp->dev, "LT EQ failed\n");
945 training_finished = 1;
956 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
960 /* Set link rate and count as you want to establish*/
961 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
962 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
963 rk32_edp_hw_link_training_en(edp);
964 val = rk32_edp_wait_hw_lt_done(edp);
967 dev_err(edp->dev, "hw lt timeout");
971 val = rk32_edp_wait_hw_lt_done(edp);
974 val = rk32_edp_get_hw_lt_status(edp);
976 dev_err(edp->dev, "hw lt err:%d\n", val);
980 static int rk32_edp_set_link_train(struct rk32_edp *edp)
984 retval = rk32_edp_init_training(edp);
986 dev_err(edp->dev, "DP LT init failed!\n");
988 retval = rk32_edp_sw_link_training(edp);
990 retval = rk32_edp_hw_link_training(edp);
996 static int rk32_edp_config_video(struct rk32_edp *edp,
997 struct video_info *video_info)
1000 int timeout_loop = 0;
1003 rk32_edp_config_video_slave_mode(edp, video_info);
1005 rk32_edp_set_video_color_format(edp, video_info->color_depth,
1006 video_info->color_space,
1007 video_info->dynamic_range,
1008 video_info->ycbcr_coeff);
1010 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1011 dev_err(edp->dev, "PLL is not locked yet.\n");
1017 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1019 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1020 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1027 /* Set to use the register calculated M/N video */
1028 rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1030 /* For video bist, Video timing must be generated by register */
1031 #ifndef EDP_BIST_MODE
1032 rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1034 /* Disable video mute */
1035 rk32_edp_enable_video_mute(edp, 0);
1037 /* Configure video slave mode */
1038 rk32_edp_enable_video_master(edp, 0);
1041 rk32_edp_start_video(edp);
1047 if (rk32_edp_is_video_stream_on(edp) == 0) {
1049 if (done_count > 10)
1051 } else if (done_count) {
1054 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1055 dev_err(edp->dev, "Timeout of video streamclk ok\n");
1059 usleep_range(1000, 1000);
1063 dev_err(edp->dev, "Video stream is not detected!\n");
1068 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1074 rk32_edp_enable_scrambling(edp);
1076 retval = rk32_edp_read_byte_from_dpcd(edp,
1077 DPCD_TRAINING_PATTERN_SET,
1082 retval = rk32_edp_write_byte_to_dpcd(edp,
1083 DPCD_TRAINING_PATTERN_SET,
1084 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1088 rk32_edp_disable_scrambling(edp);
1090 retval = rk32_edp_read_byte_from_dpcd(edp,
1091 DPCD_TRAINING_PATTERN_SET,
1096 retval = rk32_edp_write_byte_to_dpcd(edp,
1097 DPCD_TRAINING_PATTERN_SET,
1098 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1106 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1108 struct rk32_edp *edp = arg;
1109 enum dp_irq_type irq_type;
1111 irq_type = rk32_edp_get_irq_type(edp);
1113 case DP_IRQ_TYPE_HP_CABLE_IN:
1114 dev_info(edp->dev, "Received irq - cable in\n");
1115 rk32_edp_clear_hotplug_interrupts(edp);
1117 case DP_IRQ_TYPE_HP_CABLE_OUT:
1118 dev_info(edp->dev, "Received irq - cable out\n");
1119 rk32_edp_clear_hotplug_interrupts(edp);
1121 case DP_IRQ_TYPE_HP_CHANGE:
1123 * We get these change notifications once in a while, but there
1124 * is nothing we can do with them. Just ignore it for now and
1125 * only handle cable changes.
1127 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1128 rk32_edp_clear_hotplug_interrupts(edp);
1131 dev_err(edp->dev, "Received irq - unknown type!\n");
1137 static int rk32_edp_enable(void)
1140 struct rk32_edp *edp = rk32_edp;
1143 rk32_edp_clk_enable(edp);
1144 rk32_edp_pre_init();
1145 rk32_edp_init_edp(edp);
1146 enable_irq(edp->irq);
1147 /*ret = rk32_edp_handle_edid(edp);
1149 dev_err(edp->dev, "unable to handle edid\n");
1154 ret = rk32_edp_enable_scramble(edp, 0);
1156 dev_err(edp->dev, "unable to set scramble\n");
1160 ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1162 dev_err(edp->dev, "unable to set enhanced mode\n");
1165 rk32_edp_enable_enhanced_mode(edp, 1);*/
1167 ret = rk32_edp_set_link_train(edp);
1169 dev_err(edp->dev, "link train failed!\n");
1171 dev_info(edp->dev, "link training success.\n");
1173 rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1174 rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1175 rk32_edp_init_video(edp);
1177 #ifdef EDP_BIST_MODE
1178 rk32_edp_bist_cfg(edp);
1180 ret = rk32_edp_config_video(edp, &edp->video_info);
1182 dev_err(edp->dev, "unable to config video\n");
1190 static int rk32_edp_disable(void )
1192 struct rk32_edp *edp = rk32_edp;
1194 disable_irq(edp->irq);
1195 rk32_edp_reset(edp);
1196 rk32_edp_analog_power_ctr(edp, 0);
1197 rk32_edp_clk_disable(edp);
1203 static struct rk_fb_trsm_ops trsm_edp_ops = {
1204 .enable = rk32_edp_enable,
1205 .disable = rk32_edp_disable,
1209 #if defined(CONFIG_DEBUG_FS)
1211 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1214 unsigned char buf[12];
1215 struct rk32_edp *edp = s->private;
1217 dev_err(edp->dev, "no edp device!\n");
1222 rk32_edp_read_bytes_from_dpcd(edp,
1223 DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1224 for (i=0;i< 12;i++) {
1225 seq_printf(s,"0x%02x>>0x%02x\n",0x210 + i, buf[i]);
1230 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1232 struct rk32_edp *edp = s->private;
1234 dev_err(edp->dev, "no edp device!\n");
1237 rk32_edp_read_edid(edp);
1238 seq_printf(s,"edid");
1242 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1245 struct rk32_edp *edp = s->private;
1247 dev_err(edp->dev, "no edp device!\n");
1251 for (i = 0; i < 0x284; i++) {
1253 seq_printf(s, "\n%08x: ", i*4);
1254 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1260 #define EDP_DEBUG_ENTRY(name) \
1261 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1263 return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1266 static const struct file_operations edp_##name##_debugfs_fops = { \
1267 .owner = THIS_MODULE, \
1268 .open = edp_##name##_debugfs_open, \
1270 .llseek = seq_lseek, \
1271 .release = single_release, \
1274 EDP_DEBUG_ENTRY(dpcd);
1275 EDP_DEBUG_ENTRY(edid);
1276 EDP_DEBUG_ENTRY(reg);
1280 static int rk32_edp_probe(struct platform_device *pdev)
1282 struct rk32_edp *edp;
1283 struct resource *res;
1284 struct device_node *np = pdev->dev.of_node;
1288 dev_err(&pdev->dev, "Missing device tree node.\n");
1292 edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1294 dev_err(&pdev->dev, "no memory for state\n");
1297 edp->dev = &pdev->dev;
1298 edp->video_info.h_sync_polarity = 0;
1299 edp->video_info.v_sync_polarity = 0;
1300 edp->video_info.interlaced = 0;
1301 edp->video_info.color_space = CS_RGB;
1302 edp->video_info.dynamic_range = VESA;
1303 edp->video_info.ycbcr_coeff = COLOR_YCBCR601;
1304 edp->video_info.color_depth = COLOR_8;
1306 edp->video_info.link_rate = LINK_RATE_1_62GBPS;
1307 edp->video_info.lane_count = LANE_CNT4;
1308 rk_fb_get_prmry_screen(&edp->screen);
1309 if (edp->screen.type != SCREEN_EDP) {
1310 dev_err(&pdev->dev, "screen is not edp!\n");
1313 platform_set_drvdata(pdev, edp);
1314 dev_set_name(edp->dev, "rk32-edp");
1316 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1317 edp->regs = devm_ioremap_resource(&pdev->dev, res);
1318 if (IS_ERR(edp->regs)) {
1319 dev_err(&pdev->dev, "ioremap reg failed\n");
1320 return PTR_ERR(edp->regs);
1323 edp->pd = devm_clk_get(&pdev->dev,"pd_edp");
1324 if (IS_ERR(edp->pd)) {
1325 dev_err(&pdev->dev, "cannot get pd\n");
1327 edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1328 if (IS_ERR(edp->clk_edp)) {
1329 dev_err(&pdev->dev, "cannot get clk_edp\n");
1330 return PTR_ERR(edp->clk_edp);
1333 edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1334 if (IS_ERR(edp->clk_24m)) {
1335 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1336 return PTR_ERR(edp->clk_24m);
1339 edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1340 if (IS_ERR(edp->pclk)) {
1341 dev_err(&pdev->dev, "cannot get pclk\n");
1342 return PTR_ERR(edp->pclk);
1344 clk_prepare(edp->pd);
1345 clk_prepare(edp->pclk);
1346 clk_prepare(edp->clk_edp);
1347 clk_prepare(edp->clk_24m);
1348 rk32_edp_clk_enable(edp);
1349 if (!support_uboot_display())
1350 rk32_edp_pre_init();
1351 edp->irq = platform_get_irq(pdev, 0);
1353 dev_err(&pdev->dev, "cannot find IRQ\n");
1356 ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1357 dev_name(&pdev->dev), edp);
1359 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1362 disable_irq_nosync(edp->irq);
1363 if (!support_uboot_display())
1364 rk32_edp_clk_disable(edp);
1366 rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1367 #if defined(CONFIG_DEBUG_FS)
1368 edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1369 if (IS_ERR(edp->debugfs_dir)) {
1370 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1372 debugfs_create_file("dpcd", S_IRUSR,edp->debugfs_dir,
1373 edp, &edp_dpcd_debugfs_fops);
1374 debugfs_create_file("edid", S_IRUSR,edp->debugfs_dir,
1375 edp, &edp_edid_debugfs_fops);
1376 debugfs_create_file("reg", S_IRUSR,edp->debugfs_dir,
1377 edp, &edp_reg_debugfs_fops);
1381 dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1386 static void rk32_edp_shutdown(struct platform_device *pdev)
1391 #if defined(CONFIG_OF)
1392 static const struct of_device_id rk32_edp_dt_ids[] = {
1393 {.compatible = "rockchip,rk32-edp",},
1397 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1400 static struct platform_driver rk32_edp_driver = {
1401 .probe = rk32_edp_probe,
1404 .owner = THIS_MODULE,
1405 #if defined(CONFIG_OF)
1406 .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1409 .shutdown = rk32_edp_shutdown,
1412 static int __init rk32_edp_module_init(void)
1414 return platform_driver_register(&rk32_edp_driver);
1417 static void __exit rk32_edp_module_exit(void)
1422 fs_initcall(rk32_edp_module_init);
1423 module_exit(rk32_edp_module_exit);