drivers/video/rockchip/transmitter/rk32_dp.c

   1 /*
   2  * DisplayPort driver for rk32xx
   3  *
   4  * Copyright (C) ROCKCHIP, Inc.
   5  *Author:yxj<yxj@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/string.h>
  20 #include <linux/slab.h>
  21 #include <linux/delay.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/clk.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/uaccess.h>
  26 #include <linux/rockchip/iomap.h>
  27 #include <linux/rockchip/grf.h>
  28 #include "rk32_dp.h"
  29
  30 #if defined(CONFIG_OF)
  31 #include <linux/of.h>
  32 #endif
  33
  34 #if defined(CONFIG_DEBUG_FS)
  35 #include <linux/fs.h>
  36 #include <linux/debugfs.h>
  37 #include <linux/seq_file.h>
  38 #endif
  39
  40 //#define EDP_BIST_MODE
  41
  42 static struct rk32_edp *rk32_edp;
  43
  44 static int rk32_edp_clk_enable(struct rk32_edp *edp)
  45 {
  46         if (!edp->clk_on) {
  47                 clk_enable(edp->pd);
  48                 clk_enable(edp->pclk);
  49                 clk_enable(edp->clk_edp);
  50                 clk_enable(edp->clk_24m);
  51                 edp->clk_on = true;
  52         }
  53
  54         return 0;
  55 }
  56
  57 static int rk32_edp_clk_disable(struct rk32_edp *edp)
  58 {
  59         if (edp->clk_on) {
  60                 clk_disable(edp->pclk);
  61                 clk_disable(edp->clk_edp);
  62                 clk_disable(edp->clk_24m);
  63                 clk_disable(edp->pd);
  64                 edp->clk_on = false;
  65         }
  66
  67         return 0;
  68 }
  69
  70 static int rk32_edp_pre_init(void)
  71 {
  72         u32 val;
  73         val = GRF_EDP_REF_CLK_SEL_INTER |
  74                 (GRF_EDP_REF_CLK_SEL_INTER << 16);
  75         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON12);
  76
  77         val = 0x80008000;
  78         writel_relaxed(val, RK_CRU_VIRT + 0x0d0); /*select 24m*/
  79         dsb();
  80         val = 0x80008000;
  81         writel_relaxed(val, RK_CRU_VIRT + 0x01d0); /*reset edp*/
  82         dsb();
  83         udelay(1);
  84         val = 0x80000000;
  85         writel_relaxed(val, RK_CRU_VIRT + 0x01d0);
  86         dsb();
  87         udelay(1);
  88         return 0;
  89 }
  90
  91 static int rk32_edp_init_edp(struct rk32_edp *edp)
  92 {
  93         struct rk_screen *screen = &edp->screen;
  94         u32 val = 0;
  95
  96         screen->lcdc_id = 1;
  97         if (screen->lcdc_id == 1)  /*select lcdc*/
  98                 val = EDP_SEL_VOP_LIT | (EDP_SEL_VOP_LIT << 16);
  99         else
 100                 val = EDP_SEL_VOP_LIT << 16;
 101         writel_relaxed(val, RK_GRF_VIRT + RK3288_GRF_SOC_CON6);
 102
 103
 104         rk32_edp_reset(edp);
 105         rk32_edp_init_refclk(edp);
 106         rk32_edp_init_interrupt(edp);
 107
 108         rk32_edp_enable_sw_function(edp);
 109
 110         rk32_edp_init_analog_func(edp);
 111
 112         rk32_edp_init_hpd(edp);
 113         rk32_edp_init_aux(edp);
 114
 115         return 0;
 116 }
 117
 118 static int rk32_edp_detect_hpd(struct rk32_edp *edp)
 119 {
 120         int timeout_loop = 0;
 121
 122         rk32_edp_init_hpd(edp);
 123
 124         udelay(200);
 125
 126         while (rk32_edp_get_plug_in_status(edp) != 0) {
 127                 timeout_loop++;
 128                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 129                         dev_err(edp->dev, "failed to get hpd plug status\n");
 130                         return -ETIMEDOUT;
 131                 }
 132                 udelay(10);
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk32_edp_read_edid(struct rk32_edp *edp)
 139 {
 140         unsigned char edid[EDID_LENGTH * 2];
 141         unsigned int extend_block = 0;
 142         unsigned char sum;
 143         unsigned char test_vector;
 144         int retval;
 145
 146         /*
 147          * EDID device address is 0x50.
 148          * However, if necessary, you must have set upper address
 149          * into E-EDID in I2C device, 0x30.
 150          */
 151
 152         /* Read Extension Flag, Number of 128-byte EDID extension blocks */
 153         retval = rk32_edp_read_byte_from_i2c(edp, EDID_ADDR, EDID_EXTENSION_FLAG,
 154                                                 &extend_block);
 155         if (retval < 0) {
 156                 dev_err(edp->dev, "EDID extension flag failed!\n");
 157                 return -EIO;
 158         }
 159
 160         if (extend_block > 0) {
 161                 dev_dbg(edp->dev, "EDID data includes a single extension!\n");
 162
 163                 /* Read EDID data */
 164                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 165                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 166                 if (retval != 0) {
 167                         dev_err(edp->dev, "EDID Read failed!\n");
 168                         return -EIO;
 169                 }
 170                 sum = edp_calc_edid_check_sum(edid);
 171                 if (sum != 0) {
 172                         dev_warn(edp->dev, "EDID bad checksum!\n");
 173                         return 0;
 174                 }
 175
 176                 /* Read additional EDID data */
 177                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_LENGTH,
 178                                                 EDID_LENGTH, &edid[EDID_LENGTH]);
 179                 if (retval != 0) {
 180                         dev_err(edp->dev, "EDID Read failed!\n");
 181                         return -EIO;
 182                 }
 183                 sum = edp_calc_edid_check_sum(&edid[EDID_LENGTH]);
 184                 if (sum != 0) {
 185                         dev_warn(edp->dev, "EDID bad checksum!\n");
 186                         return 0;
 187                 }
 188
 189                 retval = rk32_edp_read_byte_from_dpcd(edp, DPCD_TEST_REQUEST,
 190                                         &test_vector);
 191                 if (retval < 0) {
 192                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 193                         return retval;
 194                 }
 195
 196                 if (test_vector & DPCD_TEST_EDID_READ) {
 197                         retval = rk32_edp_write_byte_to_dpcd(edp,
 198                                         DPCD_TEST_EDID_CHECKSUM,
 199                                         edid[EDID_LENGTH + EDID_CHECKSUM]);
 200                         if (retval < 0) {
 201                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 202                                 return retval;
 203                         }
 204                         retval = rk32_edp_write_byte_to_dpcd(edp,
 205                                         DPCD_TEST_RESPONSE,
 206                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 207                         if (retval < 0) {
 208                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 209                                 return retval;
 210                         }
 211                 }
 212         } else {
 213                 dev_info(edp->dev, "EDID data does not include any extensions.\n");
 214
 215                 /* Read EDID data */
 216                 retval = rk32_edp_read_bytes_from_i2c(edp, EDID_ADDR, EDID_HEADER,
 217                                                 EDID_LENGTH, &edid[EDID_HEADER]);
 218                 if (retval != 0) {
 219                         dev_err(edp->dev, "EDID Read failed!\n");
 220                         return -EIO;
 221                 }
 222                 sum = edp_calc_edid_check_sum(edid);
 223                 if (sum != 0) {
 224                         dev_warn(edp->dev, "EDID bad checksum!\n");
 225                         return 0;
 226                 }
 227
 228                 retval = rk32_edp_read_byte_from_dpcd(edp,DPCD_TEST_REQUEST,
 229                                                 &test_vector);
 230                 if (retval < 0) {
 231                         dev_err(edp->dev, "DPCD EDID Read failed!\n");
 232                         return retval;
 233                 }
 234
 235                 if (test_vector & DPCD_TEST_EDID_READ) {
 236                         retval = rk32_edp_write_byte_to_dpcd(edp,
 237                                         DPCD_TEST_EDID_CHECKSUM,
 238                                         edid[EDID_CHECKSUM]);
 239                         if (retval < 0) {
 240                                 dev_err(edp->dev, "DPCD EDID Write failed!\n");
 241                                 return retval;
 242                         }
 243                         retval = rk32_edp_write_byte_to_dpcd(edp,
 244                                         DPCD_TEST_RESPONSE,
 245                                         DPCD_TEST_EDID_CHECKSUM_WRITE);
 246                         if (retval < 0) {
 247                                 dev_err(edp->dev, "DPCD EDID checksum failed!\n");
 248                                 return retval;
 249                         }
 250                 }
 251         }
 252         fb_edid_to_monspecs(edid, &edp->specs);
 253         dev_err(edp->dev, "EDID Read success!\n");
 254         return 0;
 255 }
 256
 257 static int rk32_edp_handle_edid(struct rk32_edp *edp)
 258 {
 259         u8 buf[12];
 260         int i;
 261         int retval;
 262
 263         /* Read DPCD DPCD_ADDR_DPCD_REV~RECEIVE_PORT1_CAP_1 */
 264         retval = rk32_edp_read_bytes_from_dpcd(edp, DPCD_REV, 12, buf);
 265         if (retval < 0)
 266                 return retval;
 267
 268         for (i=0 ;i < 12; i++)
 269                 dev_info(edp->dev, "%d:>>0x%02x\n", i, buf[i]);
 270         /* Read EDID */
 271         for (i = 0; i < 3; i++) {
 272                 retval = rk32_edp_read_edid(edp);
 273                 if (retval == 0)
 274                         break;
 275         }
 276
 277         return retval;
 278 }
 279
 280 static int rk32_edp_enable_rx_to_enhanced_mode(struct rk32_edp *edp,
 281                                                 bool enable)
 282 {
 283         u8 data;
 284         int retval;
 285
 286         retval = rk32_edp_read_byte_from_dpcd(edp,
 287                         DPCD_LANE_CNT_SET, &data);
 288         if (retval < 0)
 289                 return retval;
 290
 291         if (enable) {
 292                 retval = rk32_edp_write_byte_to_dpcd(edp,
 293                                 DPCD_LANE_CNT_SET,
 294                                 DPCD_ENHANCED_FRAME_EN |
 295                                 DPCD_LANE_COUNT_SET(data));
 296         } else {
 297                 /*retval = rk32_edp_write_byte_to_dpcd(edp,
 298                                 DPCD_ADDR_CONFIGURATION_SET, 0);*/
 299
 300                 retval = rk32_edp_write_byte_to_dpcd(edp,
 301                                 DPCD_LANE_CNT_SET,
 302                                 DPCD_LANE_COUNT_SET(data));
 303         }
 304
 305         return retval;
 306 }
 307
 308 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable)
 309 {
 310         /*rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED1,0);
 311         rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED2,0x90);
 312
 313         if (enable) {
 314                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x84);
 315                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x00);
 316         } else {
 317                 rk32_edp_write_byte_to_dpcd(edp, DPCD_ADDR_USER_DEFINED3,0x80);
 318         }*/
 319 }
 320
 321 static int rk32_edp_is_enhanced_mode_available(struct rk32_edp *edp)
 322 {
 323         u8 data;
 324         int retval;
 325
 326         retval = rk32_edp_read_byte_from_dpcd(edp,
 327                         DPCD_MAX_LANE_CNT, &data);
 328         if (retval < 0)
 329                 return retval;
 330
 331         return DPCD_ENHANCED_FRAME_CAP(data);
 332 }
 333
 334 static void rk32_edp_disable_rx_zmux(struct rk32_edp *edp)
 335 {
 336         /*rk32_edp_write_byte_to_dpcd(edp,
 337                         DPCD_ADDR_USER_DEFINED1, 0);
 338         rk32_edp_write_byte_to_dpcd(edp,
 339                         DPCD_ADDR_USER_DEFINED2, 0x83);
 340         rk32_edp_write_byte_to_dpcd(edp,
 341                         DPCD_ADDR_USER_DEFINED3, 0x27);*/
 342 }
 343
 344 static int rk32_edp_set_enhanced_mode(struct rk32_edp *edp)
 345 {
 346         u8 data;
 347         int retval;
 348
 349         retval = rk32_edp_is_enhanced_mode_available(edp);
 350         if (retval < 0)
 351                 return retval;
 352
 353         data = (u8)retval;
 354         retval = rk32_edp_enable_rx_to_enhanced_mode(edp, data);
 355         if (retval < 0)
 356                 return retval;
 357
 358         rk32_edp_enable_enhanced_mode(edp, data);
 359
 360         return 0;
 361 }
 362
 363 static int rk32_edp_training_pattern_dis(struct rk32_edp *edp)
 364 {
 365         int retval;
 366
 367         rk32_edp_set_training_pattern(edp, DP_NONE);
 368
 369         retval = rk32_edp_write_byte_to_dpcd(edp,
 370                         DPCD_TRAINING_PATTERN_SET,
 371                         DPCD_TRAINING_PATTERN_DISABLED);
 372         if (retval < 0)
 373                 return retval;
 374
 375         return 0;
 376 }
 377
 378 static void rk32_edp_set_lane_lane_pre_emphasis(struct rk32_edp *edp,
 379                                         int pre_emphasis, int lane)
 380 {
 381         switch (lane) {
 382         case 0:
 383                 rk32_edp_set_lane0_pre_emphasis(edp, pre_emphasis);
 384                 break;
 385         case 1:
 386                 rk32_edp_set_lane1_pre_emphasis(edp, pre_emphasis);
 387                 break;
 388
 389         case 2:
 390                 rk32_edp_set_lane2_pre_emphasis(edp, pre_emphasis);
 391                 break;
 392
 393         case 3:
 394                 rk32_edp_set_lane3_pre_emphasis(edp, pre_emphasis);
 395                 break;
 396         }
 397 }
 398
 399 static int rk32_edp_link_start(struct rk32_edp *edp)
 400 {
 401         u8 buf[4];
 402         int lane;
 403         int lane_count;
 404         int retval;
 405
 406         lane_count = edp->link_train.lane_count;
 407
 408         edp->link_train.lt_state = LT_CLK_RECOVERY;
 409         edp->link_train.eq_loop = 0;
 410
 411         for (lane = 0; lane < lane_count; lane++)
 412                 edp->link_train.cr_loop[lane] = 0;
 413
 414         /* Set sink to D0 (Sink Not Ready) mode. */
 415         retval = rk32_edp_write_byte_to_dpcd(edp, DPCD_SINK_POWER_STATE,
 416                                 DPCD_SET_POWER_STATE_D0);
 417         if (retval < 0) {
 418                 dev_err(edp->dev, "failed to set sink device to D0!\n");
 419                 return retval;
 420         }
 421
 422         /* Set link rate and count as you want to establish*/
 423         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 424         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 425
 426         /* Setup RX configuration */
 427         buf[0] = edp->link_train.link_rate;
 428         buf[1] = edp->link_train.lane_count;
 429         retval = rk32_edp_write_bytes_to_dpcd(edp, DPCD_LINK_BW_SET,
 430                                         2, buf);
 431         if (retval < 0) {
 432                 dev_err(edp->dev, "failed to set bandwidth and lane count!\n");
 433                 return retval;
 434         }
 435
 436         /* Set TX pre-emphasis to level1 */
 437         for (lane = 0; lane < lane_count; lane++)
 438                 rk32_edp_set_lane_lane_pre_emphasis(edp,
 439                         PRE_EMPHASIS_LEVEL_1, lane);
 440
 441         /* Set training pattern 1 */
 442         rk32_edp_set_training_pattern(edp, TRAINING_PTN1);
 443
 444         /* Set RX training pattern */
 445         retval = rk32_edp_write_byte_to_dpcd(edp,
 446                         DPCD_TRAINING_PATTERN_SET,
 447                         DPCD_SCRAMBLING_DISABLED |
 448                         DPCD_TRAINING_PATTERN_1);
 449         if (retval < 0) {
 450                 dev_err(edp->dev, "failed to set training pattern 1!\n");
 451                 return retval;
 452         }
 453
 454         for (lane = 0; lane < lane_count; lane++)
 455                 buf[lane] = DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 |
 456                             DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0;
 457         retval = rk32_edp_write_bytes_to_dpcd(edp,
 458                         DPCD_TRAINING_LANE0_SET,
 459                         lane_count, buf);
 460         if (retval < 0) {
 461                 dev_err(edp->dev, "failed to set training lane!\n");
 462                 return retval;
 463         }
 464
 465         return 0;
 466 }
 467
 468 static unsigned char rk32_edp_get_lane_status(u8 link_status[2], int lane)
 469 {
 470         int shift = (lane & 1) * 4;
 471         u8 link_value = link_status[lane>>1];
 472
 473         return (link_value >> shift) & 0xf;
 474 }
 475
 476 static int rk32_edp_clock_recovery_ok(u8 link_status[2], int lane_count)
 477 {
 478         int lane;
 479         u8 lane_status;
 480
 481         for (lane = 0; lane < lane_count; lane++) {
 482                 lane_status = rk32_edp_get_lane_status(link_status, lane);
 483                 if ((lane_status & DPCD_LANE_CR_DONE) == 0)
 484                         return -EINVAL;
 485         }
 486         return 0;
 487 }
 488
 489 static int rk32_edp_channel_eq_ok(u8 link_align[3], int lane_count)
 490 {
 491         int lane;
 492         u8 lane_align;
 493         u8 lane_status;
 494
 495         lane_align = link_align[2];
 496         if ((lane_align & DPCD_INTERLANE_ALIGN_DONE) == 0)
 497                 return -EINVAL;
 498
 499         for (lane = 0; lane < lane_count; lane++) {
 500                 lane_status = rk32_edp_get_lane_status(link_align, lane);
 501                 lane_status &= DPCD_CHANNEL_EQ_BITS;
 502                 if (lane_status != DPCD_CHANNEL_EQ_BITS)
 503                         return -EINVAL;
 504         }
 505
 506         return 0;
 507 }
 508
 509 static unsigned char rk32_edp_get_adjust_request_voltage(u8 adjust_request[2],
 510                                                         int lane)
 511 {
 512         int shift = (lane & 1) * 4;
 513         u8 link_value = adjust_request[lane>>1];
 514
 515         return (link_value >> shift) & 0x3;
 516 }
 517
 518 static unsigned char rk32_edp_get_adjust_request_pre_emphasis(
 519                                         u8 adjust_request[2],
 520                                         int lane)
 521 {
 522         int shift = (lane & 1) * 4;
 523         u8 link_value = adjust_request[lane>>1];
 524
 525         return ((link_value >> shift) & 0xc) >> 2;
 526 }
 527
 528 static void rk32_edp_set_lane_link_training(struct rk32_edp *edp,
 529                                         u8 training_lane_set, int lane)
 530 {
 531         switch (lane) {
 532         case 0:
 533                 rk32_edp_set_lane0_link_training(edp, training_lane_set);
 534                 break;
 535         case 1:
 536                 rk32_edp_set_lane1_link_training(edp, training_lane_set);
 537                 break;
 538
 539         case 2:
 540                 rk32_edp_set_lane2_link_training(edp, training_lane_set);
 541                 break;
 542
 543         case 3:
 544                 rk32_edp_set_lane3_link_training(edp, training_lane_set);
 545                 break;
 546         }
 547 }
 548
 549 static unsigned int rk32_edp_get_lane_link_training(
 550                                 struct rk32_edp *edp,
 551                                 int lane)
 552 {
 553         u32 reg;
 554
 555         switch (lane) {
 556         case 0:
 557                 reg = rk32_edp_get_lane0_link_training(edp);
 558                 break;
 559         case 1:
 560                 reg = rk32_edp_get_lane1_link_training(edp);
 561                 break;
 562         case 2:
 563                 reg = rk32_edp_get_lane2_link_training(edp);
 564                 break;
 565         case 3:
 566                 reg = rk32_edp_get_lane3_link_training(edp);
 567                 break;
 568         }
 569
 570         return reg;
 571 }
 572
 573 static void rk32_edp_reduce_link_rate(struct rk32_edp *edp)
 574 {
 575         rk32_edp_training_pattern_dis(edp);
 576
 577         edp->link_train.lt_state = FAILED;
 578 }
 579
 580 static int rk32_edp_process_clock_recovery(struct rk32_edp *edp)
 581 {
 582         u8 link_status[2];
 583         int lane;
 584         int lane_count;
 585
 586         u8 adjust_request[2];
 587         u8 voltage_swing;
 588         u8 pre_emphasis;
 589         u8 training_lane;
 590         int retval;
 591
 592         udelay(100);
 593
 594         lane_count = edp->link_train.lane_count;
 595
 596         retval = rk32_edp_read_bytes_from_dpcd(edp,
 597                         DPCD_LANE0_1_STATUS,
 598                         2, link_status);
 599         if (retval < 0) {
 600                 dev_err(edp->dev, "failed to read lane status!\n");
 601                 return retval;
 602         }
 603
 604         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 605                 /* set training pattern 2 for EQ */
 606                 rk32_edp_set_training_pattern(edp, TRAINING_PTN2);
 607
 608                 for (lane = 0; lane < lane_count; lane++) {
 609                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 610                                         DPCD_ADJUST_REQUEST_LANE0_1,
 611                                         2, adjust_request);
 612                         if (retval < 0) {
 613                                 dev_err(edp->dev, "failed to read adjust request!\n");
 614                                 return retval;
 615                         }
 616
 617                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 618                                                         adjust_request, lane);
 619                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 620                                                         adjust_request, lane);
 621                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 622                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 623
 624                         if (voltage_swing == VOLTAGE_LEVEL_3)
 625                                 training_lane |= DPCD_MAX_SWING_REACHED;
 626                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 627                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 628
 629                         edp->link_train.training_lane[lane] = training_lane;
 630
 631                         rk32_edp_set_lane_link_training(edp,
 632                                 edp->link_train.training_lane[lane],
 633                                 lane);
 634                 }
 635
 636                 retval = rk32_edp_write_byte_to_dpcd(edp,
 637                                 DPCD_TRAINING_PATTERN_SET,
 638                                 DPCD_SCRAMBLING_DISABLED |
 639                                 DPCD_TRAINING_PATTERN_2);
 640                 if (retval < 0) {
 641                         dev_err(edp->dev, "failed to set training pattern 2!\n");
 642                         return retval;
 643                 }
 644
 645                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 646                                 DPCD_TRAINING_LANE0_SET,
 647                                 lane_count,
 648                                 edp->link_train.training_lane);
 649                 if (retval < 0) {
 650                         dev_err(edp->dev, "failed to set training lane!\n");
 651                         return retval;
 652                 }
 653
 654                 dev_info(edp->dev, "Link Training Clock Recovery success\n");
 655                 edp->link_train.lt_state = LT_EQ_TRAINING;
 656         } else {
 657                 for (lane = 0; lane < lane_count; lane++) {
 658                         training_lane = rk32_edp_get_lane_link_training(
 659                                                         edp, lane);
 660                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 661                                         DPCD_ADJUST_REQUEST_LANE0_1,
 662                                         2, adjust_request);
 663                         if (retval < 0) {
 664                                 dev_err(edp->dev, "failed to read adjust request!\n");
 665                                 return retval;
 666                         }
 667
 668                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 669                                                         adjust_request, lane);
 670                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 671                                                         adjust_request, lane);
 672
 673                         if (voltage_swing == VOLTAGE_LEVEL_3 ||
 674                             pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
 675                                 dev_err(edp->dev, "voltage or pre emphasis reached max level\n");
 676                                 goto reduce_link_rate;
 677                         }
 678
 679                         if ((DPCD_VOLTAGE_SWING_GET(training_lane) ==
 680                                         voltage_swing) &&
 681                            (DPCD_PRE_EMPHASIS_GET(training_lane) ==
 682                                         pre_emphasis)) {
 683                                 edp->link_train.cr_loop[lane]++;
 684                                 if (edp->link_train.cr_loop[lane] == MAX_CR_LOOP) {
 685                                         dev_err(edp->dev, "CR Max loop\n");
 686                                         goto reduce_link_rate;
 687                                 }
 688                         }
 689
 690                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 691                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 692
 693                         if (voltage_swing == VOLTAGE_LEVEL_3)
 694                                 training_lane |= DPCD_MAX_SWING_REACHED;
 695                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 696                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 697
 698                         edp->link_train.training_lane[lane] = training_lane;
 699
 700                         rk32_edp_set_lane_link_training(edp,
 701                                 edp->link_train.training_lane[lane], lane);
 702                 }
 703
 704                 retval = rk32_edp_write_bytes_to_dpcd(edp,
 705                                 DPCD_TRAINING_LANE0_SET,
 706                                 lane_count,
 707                                 edp->link_train.training_lane);
 708                 if (retval < 0) {
 709                         dev_err(edp->dev, "failed to set training lane!\n");
 710                         return retval;
 711                 }
 712         }
 713
 714         return 0;
 715
 716 reduce_link_rate:
 717         rk32_edp_reduce_link_rate(edp);
 718         return -EIO;
 719 }
 720
 721 static int rk32_edp_process_equalizer_training(struct rk32_edp *edp)
 722 {
 723         u8 link_status[2];
 724         u8 link_align[3];
 725         int lane;
 726         int lane_count;
 727         u32 reg;
 728
 729         u8 adjust_request[2];
 730         u8 voltage_swing;
 731         u8 pre_emphasis;
 732         u8 training_lane;
 733         int retval;
 734
 735         udelay(400);
 736
 737         lane_count = edp->link_train.lane_count;
 738
 739         retval = rk32_edp_read_bytes_from_dpcd(edp,
 740                         DPCD_LANE0_1_STATUS,
 741                         2, link_status);
 742         if (retval < 0) {
 743                 dev_err(edp->dev, "failed to read lane status!\n");
 744                 return retval;
 745         }
 746
 747         if (rk32_edp_clock_recovery_ok(link_status, lane_count) == 0) {
 748                 link_align[0] = link_status[0];
 749                 link_align[1] = link_status[1];
 750
 751                 retval = rk32_edp_read_byte_from_dpcd(edp,
 752                                 DPCD_LANE_ALIGN_STATUS_UPDATED,
 753                                 &link_align[2]);
 754                 if (retval < 0) {
 755                         dev_err(edp->dev, "failed to read lane aligne status!\n");
 756                         return retval;
 757                 }
 758
 759                 for (lane = 0; lane < lane_count; lane++) {
 760                         retval = rk32_edp_read_bytes_from_dpcd(edp,
 761                                         DPCD_ADJUST_REQUEST_LANE0_1,
 762                                         2, adjust_request);
 763                         if (retval < 0) {
 764                                 dev_err(edp->dev, "failed to read adjust request!\n");
 765                                 return retval;
 766                         }
 767
 768                         voltage_swing = rk32_edp_get_adjust_request_voltage(
 769                                                         adjust_request, lane);
 770                         pre_emphasis = rk32_edp_get_adjust_request_pre_emphasis(
 771                                                         adjust_request, lane);
 772                         training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
 773                                         DPCD_PRE_EMPHASIS_SET(pre_emphasis);
 774
 775                         if (voltage_swing == VOLTAGE_LEVEL_3)
 776                                 training_lane |= DPCD_MAX_SWING_REACHED;
 777                         if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
 778                                 training_lane |= DPCD_MAX_PRE_EMPHASIS_REACHED;
 779
 780                         edp->link_train.training_lane[lane] = training_lane;
 781                 }
 782
 783                 if (rk32_edp_channel_eq_ok(link_align, lane_count) == 0) {
 784                         /* traing pattern Set to Normal */
 785                         retval = rk32_edp_training_pattern_dis(edp);
 786                         if (retval < 0) {
 787                                 dev_err(edp->dev, "failed to disable training pattern!\n");
 788                                 return retval;
 789                         }
 790
 791                         dev_info(edp->dev, "Link Training success!\n");
 792
 793                         rk32_edp_get_link_bandwidth(edp, &reg);
 794                         edp->link_train.link_rate = reg;
 795                         dev_dbg(edp->dev, "final bandwidth = %.2x\n",
 796                                 edp->link_train.link_rate);
 797
 798                         rk32_edp_get_lane_count(edp, &reg);
 799                         edp->link_train.lane_count = reg;
 800                         dev_dbg(edp->dev, "final lane count = %.2x\n",
 801                                 edp->link_train.lane_count);
 802
 803                         edp->link_train.lt_state = FINISHED;
 804                 } else {
 805                         /* not all locked */
 806                         edp->link_train.eq_loop++;
 807
 808                         if (edp->link_train.eq_loop > MAX_EQ_LOOP) {
 809                                 dev_err(edp->dev, "EQ Max loop\n");
 810                                 goto reduce_link_rate;
 811                         }
 812
 813                         for (lane = 0; lane < lane_count; lane++)
 814                                 rk32_edp_set_lane_link_training(edp,
 815                                         edp->link_train.training_lane[lane],
 816                                         lane);
 817
 818                         retval = rk32_edp_write_bytes_to_dpcd(edp,
 819                                         DPCD_TRAINING_LANE0_SET,
 820                                         lane_count,
 821                                         edp->link_train.training_lane);
 822                         if (retval < 0) {
 823                                 dev_err(edp->dev, "failed to set training lane!\n");
 824                                 return retval;
 825                         }
 826                 }
 827         } else {
 828                 goto reduce_link_rate;
 829         }
 830
 831         return 0;
 832
 833 reduce_link_rate:
 834         rk32_edp_reduce_link_rate(edp);
 835         return -EIO;
 836 }
 837
 838 static int rk32_edp_get_max_rx_bandwidth(struct rk32_edp *edp,
 839                                         u8 *bandwidth)
 840 {
 841         u8 data;
 842         int retval = 0;
 843
 844         /*
 845          * For DP rev.1.1, Maximum link rate of Main Link lanes
 846          * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
 847          */
 848         retval = rk32_edp_read_byte_from_dpcd(edp,
 849                         DPCD_MAX_LINK_RATE, &data);
 850         if (retval < 0)
 851                 *bandwidth = 0;
 852         else
 853                 *bandwidth = data;
 854         return retval;
 855
 856 }
 857
 858 static int rk32_edp_get_max_rx_lane_count(struct rk32_edp *edp,
 859                                         u8 *lane_count)
 860 {
 861         u8 data;
 862         int retval;
 863
 864         /*
 865          * For DP rev.1.1, Maximum number of Main Link lanes
 866          * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
 867          */
 868         retval = rk32_edp_read_byte_from_dpcd(edp,
 869                         DPCD_MAX_LANE_CNT, &data);
 870         if (retval < 0)
 871                 *lane_count = 0;
 872         else
 873                 *lane_count = DPCD_MAX_LANE_COUNT(data);
 874         return retval;
 875 }
 876
 877 static int rk32_edp_init_training(struct rk32_edp *edp)
 878 {
 879         int retval;
 880
 881         /*
 882          * MACRO_RST must be applied after the PLL_LOCK to avoid
 883          * the DP inter pair skew issue for at least 10 us
 884          */
 885         rk32_edp_reset_macro(edp);
 886
 887
 888         retval = rk32_edp_get_max_rx_bandwidth(edp, &edp->link_train.link_rate);
 889         retval = rk32_edp_get_max_rx_lane_count(edp, &edp->link_train.lane_count);
 890         dev_info(edp->dev, "max link rate:%d.%dGps max number of lanes:%d\n",
 891                         edp->link_train.link_rate * 27/100,
 892                         edp->link_train.link_rate*27%100,
 893                         edp->link_train.lane_count);
 894
 895         if ((edp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
 896            (edp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 897                 dev_warn(edp->dev, "Rx Max Link Rate is abnormal :%x !"
 898                         "use default link rate:%d.%dGps\n",
 899                         edp->link_train.link_rate,
 900                         edp->video_info.link_rate*27/100,
 901                         edp->video_info.link_rate*27%100);
 902                 edp->link_train.link_rate = edp->video_info.link_rate;
 903         }
 904
 905         if (edp->link_train.lane_count == 0) {
 906                 dev_err(edp->dev, "Rx Max Lane count is abnormal :%x !"
 907                         "use default lanes:%d\n",
 908                         edp->link_train.lane_count,
 909                         edp->video_info.lane_count);
 910                 edp->link_train.lane_count = edp->video_info.lane_count;
 911         }
 912
 913         rk32_edp_analog_power_ctr(edp, 1);
 914
 915
 916         return 0;
 917 }
 918
 919 static int rk32_edp_sw_link_training(struct rk32_edp *edp)
 920 {
 921         int retval = 0;
 922         int training_finished = 0;
 923
 924         edp->link_train.lt_state = LT_START;
 925
 926         /* Process here */
 927         while (!training_finished) {
 928                 switch (edp->link_train.lt_state) {
 929                 case LT_START:
 930                         retval = rk32_edp_link_start(edp);
 931                         if (retval)
 932                                 dev_err(edp->dev, "LT Start failed\n");
 933                         break;
 934                 case LT_CLK_RECOVERY:
 935                         retval = rk32_edp_process_clock_recovery(edp);
 936                         if (retval)
 937                                 dev_err(edp->dev, "LT CR failed\n");
 938                         break;
 939                 case LT_EQ_TRAINING:
 940                         retval = rk32_edp_process_equalizer_training(edp);
 941                         if (retval)
 942                                 dev_err(edp->dev, "LT EQ failed\n");
 943                         break;
 944                 case FINISHED:
 945                         training_finished = 1;
 946                         break;
 947                 case FAILED:
 948                         return -EREMOTEIO;
 949                 }
 950         }
 951
 952         return retval;
 953 }
 954
 955
 956 static int rk32_edp_hw_link_training(struct rk32_edp *edp)
 957 {
 958         u32 cnt = 50;
 959         u32 val;
 960         /* Set link rate and count as you want to establish*/
 961         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
 962         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
 963         rk32_edp_hw_link_training_en(edp);
 964         val = rk32_edp_wait_hw_lt_done(edp);
 965         while (val) {
 966                 if (cnt-- <= 0) {
 967                         dev_err(edp->dev, "hw lt timeout");
 968                         return -ETIMEDOUT;
 969                 }
 970                 mdelay(1);
 971                 val = rk32_edp_wait_hw_lt_done(edp);
 972         }
 973
 974         val = rk32_edp_get_hw_lt_status(edp);
 975         if (val)
 976                 dev_err(edp->dev, "hw lt err:%d\n", val);
 977         return val;
 978
 979 }
 980 static int rk32_edp_set_link_train(struct rk32_edp *edp)
 981 {
 982         int retval;
 983
 984         retval = rk32_edp_init_training(edp);
 985         if (retval < 0)
 986                 dev_err(edp->dev, "DP LT init failed!\n");
 987 #if 0
 988         retval = rk32_edp_sw_link_training(edp);
 989 #else
 990         retval = rk32_edp_hw_link_training(edp);
 991 #endif
 992
 993         return retval;
 994 }
 995
 996 static int rk32_edp_config_video(struct rk32_edp *edp,
 997                         struct video_info *video_info)
 998 {
 999         int retval = 0;
1000         int timeout_loop = 0;
1001         int done_count = 0;
1002
1003         rk32_edp_config_video_slave_mode(edp, video_info);
1004
1005         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1006                         video_info->color_space,
1007                         video_info->dynamic_range,
1008                         video_info->ycbcr_coeff);
1009
1010         if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_UNLOCKED) {
1011                 dev_err(edp->dev, "PLL is not locked yet.\n");
1012                 return -EINVAL;
1013         }
1014
1015         for (;;) {
1016                 timeout_loop++;
1017                 if (rk32_edp_is_slave_video_stream_clock_on(edp) == 0)
1018                         break;
1019                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1020                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1021                         return -ETIMEDOUT;
1022                 }
1023
1024                 usleep_range(1, 1);
1025         }
1026
1027         /* Set to use the register calculated M/N video */
1028         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1029
1030         /* For video bist, Video timing must be generated by register */
1031 #ifndef EDP_BIST_MODE
1032         rk32_edp_set_video_timing_mode(edp, VIDEO_TIMING_FROM_CAPTURE);
1033 #endif
1034         /* Disable video mute */
1035         rk32_edp_enable_video_mute(edp, 0);
1036
1037         /* Configure video slave mode */
1038         rk32_edp_enable_video_master(edp, 0);
1039
1040         /* Enable video */
1041         rk32_edp_start_video(edp);
1042
1043         timeout_loop = 0;
1044
1045         for (;;) {
1046                 timeout_loop++;
1047                 if (rk32_edp_is_video_stream_on(edp) == 0) {
1048                         done_count++;
1049                         if (done_count > 10)
1050                                 break;
1051                 } else if (done_count) {
1052                         done_count = 0;
1053                 }
1054                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
1055                         dev_err(edp->dev, "Timeout of video streamclk ok\n");
1056                         return -ETIMEDOUT;
1057                 }
1058
1059                 usleep_range(1000, 1000);
1060         }
1061
1062         if (retval != 0)
1063                 dev_err(edp->dev, "Video stream is not detected!\n");
1064
1065         return retval;
1066 }
1067
1068 static int rk32_edp_enable_scramble(struct rk32_edp *edp, bool enable)
1069 {
1070         u8 data;
1071         int retval;
1072
1073         if (enable) {
1074                 rk32_edp_enable_scrambling(edp);
1075
1076                 retval = rk32_edp_read_byte_from_dpcd(edp,
1077                                 DPCD_TRAINING_PATTERN_SET,
1078                                 &data);
1079                 if (retval < 0)
1080                         return retval;
1081
1082                 retval = rk32_edp_write_byte_to_dpcd(edp,
1083                                 DPCD_TRAINING_PATTERN_SET,
1084                                 (u8)(data & ~DPCD_SCRAMBLING_DISABLED));
1085                 if (retval < 0)
1086                         return retval;
1087         } else {
1088                 rk32_edp_disable_scrambling(edp);
1089
1090                 retval = rk32_edp_read_byte_from_dpcd(edp,
1091                                 DPCD_TRAINING_PATTERN_SET,
1092                                 &data);
1093                 if (retval < 0)
1094                         return retval;
1095
1096                 retval = rk32_edp_write_byte_to_dpcd(edp,
1097                                 DPCD_TRAINING_PATTERN_SET,
1098                                 (u8)(data | DPCD_SCRAMBLING_DISABLED));
1099                 if (retval < 0)
1100                         return retval;
1101         }
1102
1103         return 0;
1104 }
1105
1106 static irqreturn_t rk32_edp_isr(int irq, void *arg)
1107 {
1108         struct rk32_edp *edp = arg;
1109         enum dp_irq_type irq_type;
1110
1111         irq_type = rk32_edp_get_irq_type(edp);
1112         switch (irq_type) {
1113         case DP_IRQ_TYPE_HP_CABLE_IN:
1114                 dev_info(edp->dev, "Received irq - cable in\n");
1115                 rk32_edp_clear_hotplug_interrupts(edp);
1116                 break;
1117         case DP_IRQ_TYPE_HP_CABLE_OUT:
1118                 dev_info(edp->dev, "Received irq - cable out\n");
1119                 rk32_edp_clear_hotplug_interrupts(edp);
1120                 break;
1121         case DP_IRQ_TYPE_HP_CHANGE:
1122                 /*
1123                  * We get these change notifications once in a while, but there
1124                  * is nothing we can do with them. Just ignore it for now and
1125                  * only handle cable changes.
1126                  */
1127                 dev_info(edp->dev, "Received irq - hotplug change; ignoring.\n");
1128                 rk32_edp_clear_hotplug_interrupts(edp);
1129                 break;
1130         default:
1131                 dev_err(edp->dev, "Received irq - unknown type!\n");
1132                 break;
1133         }
1134         return IRQ_HANDLED;
1135 }
1136
1137 static int rk32_edp_enable(void)
1138 {
1139         int ret = 0;
1140         struct rk32_edp *edp = rk32_edp;
1141
1142
1143         rk32_edp_clk_enable(edp);
1144         rk32_edp_pre_init();
1145         rk32_edp_init_edp(edp);
1146         enable_irq(edp->irq);
1147         /*ret = rk32_edp_handle_edid(edp);
1148         if (ret) {
1149                 dev_err(edp->dev, "unable to handle edid\n");
1150                 //goto out;
1151         }
1152
1153
1154         ret = rk32_edp_enable_scramble(edp, 0);
1155         if (ret) {
1156                 dev_err(edp->dev, "unable to set scramble\n");
1157                 //goto out;
1158         }
1159
1160         ret = rk32_edp_enable_rx_to_enhanced_mode(edp, 0);
1161         if (ret) {
1162                 dev_err(edp->dev, "unable to set enhanced mode\n");
1163                 //goto out;
1164         }
1165         rk32_edp_enable_enhanced_mode(edp, 1);*/
1166
1167         ret = rk32_edp_set_link_train(edp);
1168         if (ret)
1169                 dev_err(edp->dev, "link train failed!\n");
1170         else
1171                 dev_info(edp->dev, "link training success.\n");
1172
1173         rk32_edp_set_lane_count(edp, edp->link_train.lane_count);
1174         rk32_edp_set_link_bandwidth(edp, edp->link_train.link_rate);
1175         rk32_edp_init_video(edp);
1176
1177 #ifdef EDP_BIST_MODE
1178         rk32_edp_bist_cfg(edp);
1179 #endif
1180         ret = rk32_edp_config_video(edp, &edp->video_info);
1181         if (ret)
1182                 dev_err(edp->dev, "unable to config video\n");
1183
1184         return ret;
1185
1186
1187
1188 }
1189
1190 static int  rk32_edp_disable(void )
1191 {
1192         struct rk32_edp *edp = rk32_edp;
1193
1194         disable_irq(edp->irq);
1195         rk32_edp_reset(edp);
1196         rk32_edp_analog_power_ctr(edp, 0);
1197         rk32_edp_clk_disable(edp);
1198
1199         return 0;
1200 }
1201
1202
1203 static struct rk_fb_trsm_ops trsm_edp_ops = {
1204         .enable = rk32_edp_enable,
1205         .disable = rk32_edp_disable,
1206 };
1207
1208
1209 #if defined(CONFIG_DEBUG_FS)
1210
1211 static int edp_dpcd_debugfs_show(struct seq_file *s, void *v)
1212 {
1213         int i = 0;
1214         unsigned char buf[12];
1215         struct rk32_edp *edp = s->private;
1216         if (!edp) {
1217                 dev_err(edp->dev, "no edp device!\n");
1218                 return -ENODEV;
1219         }
1220
1221
1222         rk32_edp_read_bytes_from_dpcd(edp,
1223                         DPCD_SYMBOL_ERR_CONUT_LANE0, 12, buf);
1224         for (i=0;i< 12;i++) {
1225                 seq_printf(s,"0x%02x>>0x%02x\n",0x210 + i, buf[i]);
1226         }
1227         return 0;
1228 }
1229
1230 static int edp_edid_debugfs_show(struct seq_file *s, void *v)
1231 {
1232         int i = 0;
1233         unsigned char buf[12];
1234         struct rk32_edp *edp = s->private;
1235         if (!edp) {
1236                 dev_err(edp->dev, "no edp device!\n");
1237                 return -ENODEV;
1238         }
1239         seq_printf(s,"edid");
1240         return 0;
1241 }
1242
1243 static int edp_reg_debugfs_show(struct seq_file *s, void *v)
1244 {
1245         int i = 0;
1246         struct rk32_edp *edp = s->private;
1247         if (!edp) {
1248                 dev_err(edp->dev, "no edp device!\n");
1249                 return -ENODEV;
1250         }
1251
1252         for (i = 0; i < 0x284; i++) {
1253                 if (!(i%4))
1254                         seq_printf(s, "\n%08x:  ", i*4);
1255                 seq_printf(s, "%08x ", readl(edp->regs + i*4));
1256         }
1257         return 0;
1258 }
1259
1260
1261 #define EDP_DEBUG_ENTRY(name) \
1262 static int edp_##name##_debugfs_open(struct inode *inode, struct file *file) \
1263 { \
1264         return single_open(file, edp_##name##_debugfs_show, inode->i_private); \
1265 } \
1266 \
1267 static const struct file_operations edp_##name##_debugfs_fops = { \
1268         .owner = THIS_MODULE, \
1269         .open = edp_##name##_debugfs_open, \
1270         .read = seq_read, \
1271         .llseek = seq_lseek, \
1272         .release = single_release, \
1273 }
1274
1275 EDP_DEBUG_ENTRY(dpcd);
1276 EDP_DEBUG_ENTRY(edid);
1277 EDP_DEBUG_ENTRY(reg);
1278
1279 #endif
1280
1281 static int rk32_edp_probe(struct platform_device *pdev)
1282 {
1283         struct rk32_edp *edp;
1284         struct resource *res;
1285         struct device_node *np = pdev->dev.of_node;
1286         int ret;
1287
1288         if (!np) {
1289                 dev_err(&pdev->dev, "Missing device tree node.\n");
1290                 return -EINVAL;
1291         }
1292
1293         edp = devm_kzalloc(&pdev->dev, sizeof(struct rk32_edp), GFP_KERNEL);
1294         if (!edp) {
1295                 dev_err(&pdev->dev, "no memory for state\n");
1296                 return -ENOMEM;
1297         }
1298         edp->dev = &pdev->dev;
1299         edp->video_info.h_sync_polarity = 0;
1300         edp->video_info.v_sync_polarity = 0;
1301         edp->video_info.interlaced      = 0;
1302         edp->video_info.color_space     = CS_RGB;
1303         edp->video_info.dynamic_range   = VESA;
1304         edp->video_info.ycbcr_coeff     = COLOR_YCBCR601;
1305         edp->video_info.color_depth     = COLOR_8;
1306
1307         edp->video_info.link_rate       = LINK_RATE_1_62GBPS;
1308         edp->video_info.lane_count      = LANE_CNT4;
1309         rk_fb_get_prmry_screen(&edp->screen);
1310         if (edp->screen.type != SCREEN_EDP) {
1311                 dev_err(&pdev->dev, "screen is not edp!\n");
1312                 return -EINVAL;
1313         }
1314         platform_set_drvdata(pdev, edp);
1315         dev_set_name(edp->dev, "rk32-edp");
1316
1317         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318         edp->regs = devm_ioremap_resource(&pdev->dev, res);
1319         if (IS_ERR(edp->regs)) {
1320                 dev_err(&pdev->dev, "ioremap reg failed\n");
1321                 return PTR_ERR(edp->regs);
1322         }
1323
1324         edp->pd = devm_clk_get(&pdev->dev,"pd_edp");
1325         if (IS_ERR(edp->pd)) {
1326                 dev_err(&pdev->dev, "cannot get pd\n");
1327         }
1328         edp->clk_edp = devm_clk_get(&pdev->dev,"clk_edp");
1329         if (IS_ERR(edp->clk_edp)) {
1330                 dev_err(&pdev->dev, "cannot get clk_edp\n");
1331                 return PTR_ERR(edp->clk_edp);
1332         }
1333
1334         edp->clk_24m = devm_clk_get(&pdev->dev,"clk_edp_24m");
1335         if (IS_ERR(edp->clk_24m)) {
1336                 dev_err(&pdev->dev, "cannot get clk_edp_24m\n");
1337                 return PTR_ERR(edp->clk_24m);
1338         }
1339
1340         edp->pclk = devm_clk_get(&pdev->dev,"pclk_edp");
1341         if (IS_ERR(edp->pclk)) {
1342                 dev_err(&pdev->dev, "cannot get pclk\n");
1343                 return PTR_ERR(edp->pclk);
1344         }
1345         clk_prepare(edp->pd);
1346         clk_prepare(edp->pclk);
1347         clk_prepare(edp->clk_edp);
1348         clk_prepare(edp->clk_24m);
1349         rk32_edp_clk_enable(edp);
1350         if (!support_uboot_display())
1351                 rk32_edp_pre_init();
1352         edp->irq = platform_get_irq(pdev, 0);
1353         if (edp->irq < 0) {
1354                 dev_err(&pdev->dev, "cannot find IRQ\n");
1355                 return edp->irq;
1356         }
1357         ret = devm_request_irq(&pdev->dev, edp->irq, rk32_edp_isr, 0,
1358                         dev_name(&pdev->dev), edp);
1359         if (ret) {
1360                 dev_err(&pdev->dev, "cannot claim IRQ %d\n", edp->irq);
1361                 return ret;
1362         }
1363         disable_irq_nosync(edp->irq);
1364         if (!support_uboot_display())
1365                 rk32_edp_clk_disable(edp);
1366         rk32_edp = edp;
1367         rk_fb_trsm_ops_register(&trsm_edp_ops, SCREEN_EDP);
1368 #if defined(CONFIG_DEBUG_FS)
1369         edp->debugfs_dir = debugfs_create_dir("edp", NULL);
1370         if (IS_ERR(edp->debugfs_dir)) {
1371                 dev_err(edp->dev, "failed to create debugfs dir for edp!\n");
1372         } else {
1373                 debugfs_create_file("dpcd", S_IRUSR,edp->debugfs_dir,
1374                                         edp, &edp_dpcd_debugfs_fops);
1375                 debugfs_create_file("edid", S_IRUSR,edp->debugfs_dir,
1376                                         edp, &edp_edid_debugfs_fops);
1377                 debugfs_create_file("reg", S_IRUSR,edp->debugfs_dir,
1378                                         edp, &edp_reg_debugfs_fops);
1379         }
1380
1381 #endif
1382         dev_info(&pdev->dev, "rk32 edp driver probe success\n");
1383
1384         return 0;
1385 }
1386
1387 static void rk32_edp_shutdown(struct platform_device *pdev)
1388 {
1389
1390 }
1391
1392 #if defined(CONFIG_OF)
1393 static const struct of_device_id rk32_edp_dt_ids[] = {
1394         {.compatible = "rockchip,rk32-edp",},
1395         {}
1396 };
1397
1398 MODULE_DEVICE_TABLE(of, rk32_edp_dt_ids);
1399 #endif
1400
1401 static struct platform_driver rk32_edp_driver = {
1402         .probe = rk32_edp_probe,
1403         .driver = {
1404                    .name = "rk32-edp",
1405                    .owner = THIS_MODULE,
1406 #if defined(CONFIG_OF)
1407                    .of_match_table = of_match_ptr(rk32_edp_dt_ids),
1408 #endif
1409         },
1410         .shutdown = rk32_edp_shutdown,
1411 };
1412
1413 static int __init rk32_edp_module_init(void)
1414 {
1415         return platform_driver_register(&rk32_edp_driver);
1416 }
1417
1418 static void __exit rk32_edp_module_exit(void)
1419 {
1420
1421 }
1422
1423 fs_initcall(rk32_edp_module_init);
1424 module_exit(rk32_edp_module_exit);