drivers/video/rockchip/transmitter/rk32_dp.h

   1 #ifndef __RK32_DP_H
   2 #define __RK32_DP_H
   3 #include <linux/rk_fb.h>
   4 #include "dpcd_edid.h"
   5
   6 #define DP_VERSION                              0x10
   7
   8 #define TX_SW_RST                               0x14
   9
  10 #define FUNC_EN_1                               0x18
  11 #define VID_CAP_FUNC_EN_N                       (0x1 << 6)
  12 #define VID_FIFO_FUNC_EN_N                      (0x1 << 5)
  13 #define AUD_FIFO_FUNC_EN_N                      (0x1 << 4)
  14 #define AUD_FUNC_EN_N                           (0x1 << 3)
  15 #define HDCP_FUNC_EN_N                          (0x1 << 2)
  16 #define SW_FUNC_EN_N                            (0x1 << 0)
  17
  18 #define FUNC_EN_2                               0x1C
  19 #define SSC_FUNC_EN_N                           (0x1 << 7)
  20 #define AUX_FUNC_EN_N                           (0x1 << 2)
  21 #define SERDES_FIFO_FUNC_EN_N                   (0x1 << 1)
  22 #define LS_CLK_DOMAIN_FUNC_EN_N                 (0x1 << 0)
  23
  24 #define VIDEO_CTL_1                             0x20
  25 #define VIDEO_EN                                (0x1 << 7)
  26 #define VIDEO_MUTE                              (0x1 << 6)
  27
  28 #define VIDEO_CTL_2                             0x24
  29 #define IN_D_RANGE_MASK                         (0x1 << 7)
  30 #define IN_D_RANGE_SHIFT                        (7)
  31 #define IN_D_RANGE_CEA                          (0x1 << 7)
  32 #define IN_D_RANGE_VESA                         (0x0 << 7)
  33 #define IN_BPC_MASK                             (0x7 << 4)
  34 #define IN_BPC_SHIFT                            (4)
  35 #define IN_BPC_12_BITS                          (0x3 << 4)
  36 #define IN_BPC_10_BITS                          (0x2 << 4)
  37 #define IN_BPC_8_BITS                           (0x1 << 4)
  38 #define IN_BPC_6_BITS                           (0x0 << 4)
  39 #define IN_COLOR_F_MASK                         (0x3 << 0)
  40 #define IN_COLOR_F_SHIFT                        (0)
  41 #define IN_COLOR_F_YCBCR444                     (0x2 << 0)
  42 #define IN_COLOR_F_YCBCR422                     (0x1 << 0)
  43 #define IN_COLOR_F_RGB                          (0x0 << 0)
  44
  45 #define VIDEO_CTL_3                             0x28
  46 #define IN_YC_COEFFI_MASK                       (0x1 << 7)
  47 #define IN_YC_COEFFI_SHIFT                      (7)
  48 #define IN_YC_COEFFI_ITU709                     (0x1 << 7)
  49 #define IN_YC_COEFFI_ITU601                     (0x0 << 7)
  50 #define VID_CHK_UPDATE_TYPE_MASK                (0x1 << 4)
  51 #define VID_CHK_UPDATE_TYPE_SHIFT               (4)
  52 #define VID_CHK_UPDATE_TYPE_1                   (0x1 << 4)
  53 #define VID_CHK_UPDATE_TYPE_0                   (0x0 << 4)
  54
  55 #define VIDEO_CTL_4                             0x2c
  56 #define BIST_EN                                 (0x1 << 3)
  57 #define BIST_WH_64                              (0x1 << 2)
  58 #define BIST_WH_32                              (0x0 << 2)
  59 #define BIST_TYPE_COLR_BAR                      (0x0 << 0)
  60 #define BIST_TYPE_GRAY_BAR                      (0x1 << 0)
  61 #define BIST_TYPE_MOBILE_BAR                    (0x2 << 0)
  62
  63 #define VIDEO_CTL_8                             0x3C
  64 #define VID_HRES_TH(x)                          (((x) & 0xf) << 4)
  65 #define VID_VRES_TH(x)                          (((x) & 0xf) << 0)
  66
  67 #define VIDEO_CTL_10                            0x44
  68 #define F_SEL                                   (0x1 << 4)
  69 #define INTERACE_SCAN_CFG                       (0x1 << 2)
  70 #define VSYNC_POLARITY_CFG                      (0x1 << 1)
  71 #define HSYNC_POLARITY_CFG                      (0x1 << 0)
  72
  73 #define TOTAL_LINE_CFG_L                        0x48
  74 #define TOTAL_LINE_CFG_H                        0x4c
  75 #define ATV_LINE_CFG_L                          0x50
  76 #define ATV_LINE_CFG_H                          0x54
  77 #define VF_PORCH_REG                            0x58
  78 #define VSYNC_CFG_REG                           0x5c
  79 #define VB_PORCH_REG                            0x60
  80 #define TOTAL_PIXELL_REG                        0x64
  81 #define TOTAL_PIXELH_REG                        0x68
  82 #define ATV_PIXELL_REG                          0x6c
  83 #define ATV_PIXELH_REG                          0x70
  84 #define HF_PORCHL_REG                           0x74
  85 #define HF_PORCHH_REG                           0x78
  86 #define HSYNC_CFGL_REG                          0x7c
  87 #define HSYNC_CFGH_REG                          0x80
  88 #define HB_PORCHL_REG                           0x84
  89 #define HB_PORCHH_REG                           0x88
  90
  91
  92 #define SSC_REG                                 0x104
  93 #define TX_REG_COMMON                           0x114
  94 #define DP_AUX                                  0x120
  95 #define DP_BIAS                                 0x124
  96
  97 #define PLL_REG_1                               0xfc
  98 #define REF_CLK_24M                             (0x1 << 1)
  99 #define REF_CLK_27M                             (0x0 << 1)
 100
 101 #define PLL_REG_2                               0x9e4
 102 #define PLL_REG_3                               0x9e8
 103 #define PLL_REG_4                               0x9ec
 104 #define PLL_REG_5                               0xa00
 105 #define DP_PWRDN                                0x12c
 106 #define PD_INC_BG                               (0x1 << 7)
 107 #define PD_EXP_BG                               (0x1 << 6)
 108 #define PD_AUX                                  (0x1 << 5)
 109 #define PD_PLL                                  (0x1 << 4)
 110 #define PD_CH3                                  (0x1 << 3)
 111 #define PD_CH2                                  (0x1 << 2)
 112 #define PD_CH1                                  (0x1 << 1)
 113 #define PD_CH0                                  (0x1 << 0)
 114
 115 #define DP_RESERVE2                             0x134
 116
 117 #define LANE_MAP                                0x35C
 118 #define LANE3_MAP_LOGIC_LANE_0                  (0x0 << 6)
 119 #define LANE3_MAP_LOGIC_LANE_1                  (0x1 << 6)
 120 #define LANE3_MAP_LOGIC_LANE_2                  (0x2 << 6)
 121 #define LANE3_MAP_LOGIC_LANE_3                  (0x3 << 6)
 122 #define LANE2_MAP_LOGIC_LANE_0                  (0x0 << 4)
 123 #define LANE2_MAP_LOGIC_LANE_1                  (0x1 << 4)
 124 #define LANE2_MAP_LOGIC_LANE_2                  (0x2 << 4)
 125 #define LANE2_MAP_LOGIC_LANE_3                  (0x3 << 4)
 126 #define LANE1_MAP_LOGIC_LANE_0                  (0x0 << 2)
 127 #define LANE1_MAP_LOGIC_LANE_1                  (0x1 << 2)
 128 #define LANE1_MAP_LOGIC_LANE_2                  (0x2 << 2)
 129 #define LANE1_MAP_LOGIC_LANE_3                  (0x3 << 2)
 130 #define LANE0_MAP_LOGIC_LANE_0                  (0x0 << 0)
 131 #define LANE0_MAP_LOGIC_LANE_1                  (0x1 << 0)
 132 #define LANE0_MAP_LOGIC_LANE_2                  (0x2 << 0)
 133 #define LANE0_MAP_LOGIC_LANE_3                  (0x3 << 0)
 134
 135 #define ANALOG_CTL_2                            0x374
 136 #define SEL_24M                                 (0x1 << 3)
 137
 138 /*#define ANALOG_CTL_3                          0x378
 139 #define PLL_FILTER_CTL_1                        0x37C
 140 #define TX_AMP_TUNING_CTL                       0x380*/
 141
 142 #define AUX_HW_RETRY_CTL                        0x390
 143
 144 #define INT_STA                                 0x3c0
 145
 146 #define COMMON_INT_STA_1                        0x3C4
 147 #define VSYNC_DET                               (0x1 << 7)
 148 #define PLL_LOCK_CHG                            (0x1 << 6)
 149 #define SPDIF_ERR                               (0x1 << 5)
 150 #define SPDIF_UNSTBL                            (0x1 << 4)
 151 #define VID_FORMAT_CHG                          (0x1 << 3)
 152 #define AUD_CLK_CHG                             (0x1 << 2)
 153 #define VID_CLK_CHG                             (0x1 << 1)
 154 #define SW_INT                                  (0x1 << 0)
 155
 156 #define COMMON_INT_STA_2                        0x3C8
 157 #define ENC_EN_CHG                              (0x1 << 6)
 158 #define HW_BKSV_RDY                             (0x1 << 3)
 159 #define HW_SHA_DONE                             (0x1 << 2)
 160 #define HW_AUTH_STATE_CHG                       (0x1 << 1)
 161 #define HW_AUTH_DONE                            (0x1 << 0)
 162
 163 #define COMMON_INT_STA_3                        0x3CC
 164 #define AFIFO_UNDER                             (0x1 << 7)
 165 #define AFIFO_OVER                              (0x1 << 6)
 166 #define R0_CHK_FLAG                             (0x1 << 5)
 167
 168 #define COMMON_INT_STA_4                        0x3D0
 169 #define PSR_ACTIVE                              (0x1 << 7)
 170 #define PSR_INACTIVE                            (0x1 << 6)
 171 #define SPDIF_BI_PHASE_ERR                      (0x1 << 5)
 172 #define HOTPLUG_CHG                             (0x1 << 2)
 173 #define HPD_LOST                                (0x1 << 1)
 174 #define PLUG                                    (0x1 << 0)
 175
 176 #define DP_INT_STA                              0x3DC
 177 #define INT_HPD                                 (0x1 << 6)
 178 #define HW_LT_DONE                              (0x1 << 5)
 179 #define SINK_LOST                               (0x1 << 3)
 180 #define LINK_LOST                               (0x1 << 2)
 181 #define RPLY_RECEIV                             (0x1 << 1)
 182 #define AUX_ERR                                 (0x1 << 0)
 183
 184 #define COMMON_INT_MASK_1                       0x3E0
 185 #define COMMON_INT_MASK_2                       0x3E4
 186 #define COMMON_INT_MASK_3                       0x3E8
 187 #define COMMON_INT_MASK_4                       0x3EC
 188 #define DP_INT_STA_MASK                         0x3F8
 189
 190 #define INT_CTL                                 0x3FC
 191 #define SOFT_INT_CTRL                           (0x1 << 2)
 192 #define INT_POL                                 (0x1 << 0)
 193
 194 #define SYS_CTL_1                               0x600
 195 #define DET_STA                                 (0x1 << 2)
 196 #define FORCE_DET                               (0x1 << 1)
 197 #define DET_CTRL                                (0x1 << 0)
 198
 199 #define SYS_CTL_2                               0x604
 200 #define CHA_CRI(x)                              (((x) & 0xf) << 4)
 201 #define CHA_STA                                 (0x1 << 2)
 202 #define FORCE_CHA                               (0x1 << 1)
 203 #define CHA_CTRL                                (0x1 << 0)
 204
 205 #define SYS_CTL_3                               0x608
 206 #define HPD_STATUS                              (0x1 << 6)
 207 #define F_HPD                                   (0x1 << 5)
 208 #define HPD_CTRL                                (0x1 << 4)
 209 #define HDCP_RDY                                (0x1 << 3)
 210 #define STRM_VALID                              (0x1 << 2)
 211 #define F_VALID                                 (0x1 << 1)
 212 #define VALID_CTRL                              (0x1 << 0)
 213
 214 #define SYS_CTL_4                               0x60C
 215 #define FIX_M_AUD                               (0x1 << 4)
 216 #define ENHANCED                                (0x1 << 3)
 217 #define FIX_M_VID                               (0x1 << 2)
 218 #define M_VID_UPDATE_CTRL                       (0x3 << 0)
 219
 220
 221 #define PKT_SEND_CTL                            0x640
 222 #define HDCP_CTL                                0x648
 223
 224 #define LINK_BW_SET                             0x680
 225 #define LANE_CNT_SET                            0x684
 226
 227 #define TRAINING_PTN_SET                        0x688
 228 #define SCRAMBLING_DISABLE                      (0x1 << 5)
 229 #define SCRAMBLING_ENABLE                       (0x0 << 5)
 230 #define LINK_QUAL_PATTERN_SET_MASK              (0x7 << 2)
 231 #define LINK_QUAL_PATTERN_SET_HBR2              (0x5 << 2)
 232 #define LINK_QUAL_PATTERN_SET_80BIT             (0x4 << 2)
 233 #define LINK_QUAL_PATTERN_SET_PRBS7             (0x3 << 2)
 234 #define LINK_QUAL_PATTERN_SET_D10_2             (0x1 << 2)
 235 #define LINK_QUAL_PATTERN_SET_DISABLE           (0x0 << 2)
 236 #define SW_TRAINING_PATTERN_SET_MASK            (0x3 << 0)
 237 #define SW_TRAINING_PATTERN_SET_PTN2            (0x2 << 0)
 238 #define SW_TRAINING_PATTERN_SET_PTN1            (0x1 << 0)
 239 #define SW_TRAINING_PATTERN_SET_DISABLE         (0x0 << 0)
 240
 241 #define LN0_LINK_TRAINING_CTL                   0x68C
 242 #define LN1_LINK_TRAINING_CTL                   0x690
 243 #define LN2_LINK_TRAINING_CTL                   0x694
 244 #define LN3_LINK_TRAINING_CTL                   0x698
 245
 246 #define HW_LT_CTL                               0x6a0
 247 #define HW_LT_ERR_CODE_MASK                     0x70
 248 #define HW_LT_EN                                (0x1 << 0)
 249
 250 #define DEBUG_CTL                               0x6C0
 251 #define PLL_LOCK                                (0x1 << 4)
 252 #define F_PLL_LOCK                              (0x1 << 3)
 253 #define PLL_LOCK_CTRL                           (0x1 << 2)
 254 #define POLL_EN                                 (0x1 << 1)
 255 #define PN_INV                                  (0x1 << 0)
 256
 257 #define HPD_DEGLITCH_L                          0x6C4
 258 #define HPD_DEGLITCH_H                          0x6C8
 259 #define LINK_DEBUG_CTL                          0x6E0
 260
 261 #define M_VID_0                                 0x700
 262 #define M_VID_1                                 0x704
 263 #define M_VID_2                                 0x708
 264 #define N_VID_0                                 0x70C
 265 #define N_VID_1                                 0x710
 266 #define N_VID_2                                 0x714
 267
 268 #define VIDEO_FIFO_THRD                         0x730
 269 #define AUDIO_MARGIN                            0x73C
 270
 271 #define M_VID_GEN_FILTER_TH                     0x764
 272 #define M_AUD_GEN_FILTER_TH                     0x778
 273
 274 #define AUX_CH_STA                              0x780
 275 #define AUX_BUSY                                (0x1 << 4)
 276 #define AUX_STATUS_MASK                         (0xf << 0)
 277
 278 #define AUX_CH_DEFER_CTL                        0x788
 279 #define DEFER_CTRL_EN                           (0x1 << 7)
 280 #define DEFER_COUNT(x)                          (((x) & 0x7f) << 0)
 281
 282 #define AUX_RX_COMM                             0x78C
 283 #define BUFFER_DATA_CTL                         0x790
 284 #define BUF_CLR                                 (0x1 << 7)
 285 #define BUF_HAVE_DATA                           (0x1 << 4)
 286 #define BUF_DATA_COUNT(x)                       (((x) & 0xf) << 0)
 287
 288 #define AUX_CH_CTL_1                            0x794
 289 #define AUX_LENGTH(x)                           (((x - 1) & 0xf) << 4)
 290 #define AUX_TX_COMM_MASK                        (0xf << 0)
 291 #define AUX_TX_COMM_DP_TRANSACTION              (0x1 << 3)
 292 #define AUX_TX_COMM_I2C_TRANSACTION             (0x0 << 3)
 293 #define AUX_TX_COMM_MOT                         (0x1 << 2)
 294 #define AUX_TX_COMM_WRITE                       (0x0 << 0)
 295 #define AUX_TX_COMM_READ                        (0x1 << 0)
 296
 297 #define DP_AUX_ADDR_7_0                         0x798
 298 #define DP_AUX_ADDR_15_8                        0x79C
 299 #define DP_AUX_ADDR_19_16                       0x7A0
 300
 301 #define AUX_CH_CTL_2                            0x7A4
 302 #define PD_AUX_IDLE                             (0x1 << 3)
 303 #define ADDR_ONLY                               (0x1 << 1)
 304 #define AUX_EN                                  (0x1 << 0)
 305
 306 #define BUF_DATA_0                              0x7C0
 307
 308 #define SOC_GENERAL_CTL                         0x800
 309
 310 /* TX_SW_RESET */
 311 #define RST_DP_TX                               (0x1 << 0)
 312
 313 /* ANALOG_CTL_1 */
 314 #define TX_TERMINAL_CTRL_50_OHM                 (0x1 << 4)
 315
 316
 317
 318 /* ANALOG_CTL_3 */
 319 #define DRIVE_DVDD_BIT_1_0625V                  (0x4 << 5)
 320 #define VCO_BIT_600_MICRO                       (0x5 << 0)
 321
 322 /* PLL_FILTER_CTL_1 */
 323 #define PD_RING_OSC                             (0x1 << 6)
 324 #define AUX_TERMINAL_CTRL_37_5_OHM              (0x0 << 4)
 325 #define AUX_TERMINAL_CTRL_45_OHM                (0x1 << 4)
 326 #define AUX_TERMINAL_CTRL_50_OHM                (0x2 << 4)
 327 #define AUX_TERMINAL_CTRL_65_OHM                (0x3 << 4)
 328 #define TX_CUR1_2X                              (0x1 << 2)
 329 #define TX_CUR_16_MA                            (0x3 << 0)
 330
 331 /* TX_AMP_TUNING_CTL */
 332 #define CH3_AMP_SHIFT                           (24)
 333 #define CH3_AMP_400_MV                          (0x0 << 24)
 334 #define CH2_AMP_SHIFT                           (16)
 335 #define CH2_AMP_400_MV                          (0x0 << 16)
 336 #define CH1_AMP_SHIFT                           (8)
 337 #define CH1_AMP_400_MV                          (0x0 << 8)
 338 #define CH0_AMP_SHIFT                           (0)
 339 #define CH0_AMP_400_MV                          (0x0 << 0)
 340
 341 /* AUX_HW_RETRY_CTL */
 342 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)        (((x) & 0x7) << 8)
 343 #define AUX_HW_RETRY_INTERVAL_MASK              (0x3 << 3)
 344 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS  (0x0 << 3)
 345 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS  (0x1 << 3)
 346 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
 347 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
 348 #define AUX_HW_RETRY_COUNT_SEL(x)               (((x) & 0x7) << 0)
 349
 350
 351
 352 /* LN0_LINK_TRAINING_CTL */
 353 #define PRE_EMPHASIS_SET_MASK                   (0x3 << 3)
 354 #define PRE_EMPHASIS_SET_SHIFT                  (3)
 355
 356
 357 /* PLL_CTL */
 358 #define DP_PLL_PD                               (0x1 << 7)
 359 #define DP_PLL_RESET                            (0x1 << 6)
 360 #define DP_PLL_LOOP_BIT_DEFAULT                 (0x1 << 4)
 361 #define DP_PLL_REF_BIT_1_1250V                  (0x5 << 0)
 362 #define DP_PLL_REF_BIT_1_2500V                  (0x7 << 0)
 363
 364 /* PHY_TEST */
 365 #define MACRO_RST                               (0x1 << 5)
 366 #define CH1_TEST                                (0x1 << 1)
 367 #define CH0_TEST                                (0x1 << 0)
 368
 369
 370
 371
 372
 373
 374
 375 #define DP_TIMEOUT_LOOP_CNT 100
 376 #define MAX_CR_LOOP 5
 377 #define MAX_EQ_LOOP 5
 378
 379
 380
 381 #define GRF_EDP_REF_CLK_SEL_INTER               (1 << 4)
 382 #define GRF_EDP_HDCP_EN                         (1 << 15)
 383 #define GRF_EDP_BIST_EN                         (1 << 14)
 384 #define GRF_EDP_MEM_CTL_BY_EDP                  (1 << 13)
 385 #define GRF_EDP_SECURE_EN                       (1 << 3)
 386 #define EDP_SEL_VOP_LIT                         (1 << 5)
 387
 388 enum dp_irq_type {
 389         DP_IRQ_TYPE_HP_CABLE_IN,
 390         DP_IRQ_TYPE_HP_CABLE_OUT,
 391         DP_IRQ_TYPE_HP_CHANGE,
 392         DP_IRQ_TYPE_UNKNOWN,
 393 };
 394
 395 enum color_coefficient {
 396         COLOR_YCBCR601,
 397         COLOR_YCBCR709
 398 };
 399
 400 enum dynamic_range {
 401         VESA,
 402         CEA
 403 };
 404
 405 enum pll_status {
 406         DP_PLL_UNLOCKED,
 407         DP_PLL_LOCKED
 408 };
 409
 410 enum clock_recovery_m_value_type {
 411         CALCULATED_M,
 412         REGISTER_M
 413 };
 414
 415 enum video_timing_recognition_type {
 416         VIDEO_TIMING_FROM_CAPTURE,
 417         VIDEO_TIMING_FROM_REGISTER
 418 };
 419
 420 enum pattern_set {
 421         PRBS7,
 422         D10_2,
 423         TRAINING_PTN1,
 424         TRAINING_PTN2,
 425         DP_NONE
 426 };
 427
 428 enum color_space {
 429         CS_RGB,
 430         CS_YCBCR422,
 431         CS_YCBCR444
 432 };
 433
 434 enum color_depth {
 435         COLOR_6,
 436         COLOR_8,
 437         COLOR_10,
 438         COLOR_12
 439 };
 440
 441 enum link_rate_type {
 442         LINK_RATE_1_62GBPS = 0x06,
 443         LINK_RATE_2_70GBPS = 0x0a
 444 };
 445
 446 enum link_lane_count_type {
 447         LANE_CNT1 = 1,
 448         LANE_CNT2 = 2,
 449         LANE_CNT4 = 4
 450 };
 451
 452 enum link_training_state {
 453         LT_START,
 454         LT_CLK_RECOVERY,
 455         LT_EQ_TRAINING,
 456         FINISHED,
 457         FAILED
 458 };
 459
 460 enum voltage_swing_level {
 461         VOLTAGE_LEVEL_0,
 462         VOLTAGE_LEVEL_1,
 463         VOLTAGE_LEVEL_2,
 464         VOLTAGE_LEVEL_3,
 465 };
 466
 467 enum pre_emphasis_level {
 468         PRE_EMPHASIS_LEVEL_0,
 469         PRE_EMPHASIS_LEVEL_1,
 470         PRE_EMPHASIS_LEVEL_2,
 471         PRE_EMPHASIS_LEVEL_3,
 472 };
 473
 474 enum analog_power_block {
 475         AUX_BLOCK,
 476         CH0_BLOCK,
 477         CH1_BLOCK,
 478         CH2_BLOCK,
 479         CH3_BLOCK,
 480         ANALOG_TOTAL,
 481         POWER_ALL
 482 };
 483
 484 struct video_info {
 485         char *name;
 486
 487         bool h_sync_polarity;
 488         bool v_sync_polarity;
 489         bool interlaced;
 490
 491         enum color_space color_space;
 492         enum dynamic_range dynamic_range;
 493         enum color_coefficient ycbcr_coeff;
 494         enum color_depth color_depth;
 495
 496         enum link_rate_type link_rate;
 497         enum link_lane_count_type lane_count;
 498 };
 499
 500 struct link_train {
 501         int eq_loop;
 502         int cr_loop[4];
 503
 504         u8 link_rate;
 505         u8 lane_count;
 506         u8 training_lane[4];
 507
 508         enum link_training_state lt_state;
 509 };
 510
 511
 512
 513 struct rk32_edp {
 514         struct device           *dev;
 515         void __iomem            *regs;
 516         unsigned int            irq;
 517         struct clk              *pd;
 518         struct clk              *clk_edp;  /*clk for edp controller*/
 519         struct clk              *clk_24m;  /*clk for edp phy*/
 520         struct clk              *pclk;     /*clk for phb bus*/
 521         struct link_train       link_train;
 522         struct video_info       video_info;
 523         struct rk_screen        screen;
 524         struct fb_monspecs      specs;
 525         bool                    clk_on;
 526         struct dentry *debugfs_dir;
 527 };
 528
 529
 530 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable);
 531 void rk32_edp_stop_video(struct rk32_edp *edp);
 532 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable);
 533 void rk32_edp_init_refclk(struct rk32_edp *edp);
 534 void rk32_edp_init_interrupt(struct rk32_edp *edp);
 535 void rk32_edp_reset(struct rk32_edp *edp);
 536 void rk32_edp_config_interrupt(struct rk32_edp *edp);
 537 u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp);
 538 void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable);
 539 void rk32_edp_init_analog_func(struct rk32_edp *edp);
 540 void rk32_edp_init_hpd(struct rk32_edp *edp);
 541 void rk32_edp_reset_aux(struct rk32_edp *edp);
 542 void rk32_edp_init_aux(struct rk32_edp *edp);
 543 int rk32_edp_get_plug_in_status(struct rk32_edp *edp);
 544 void rk32_edp_enable_sw_function(struct rk32_edp *edp);
 545 int rk32_edp_start_aux_transaction(struct rk32_edp *edp);
 546 int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
 547                                 unsigned int reg_addr,
 548                                 unsigned char data);
 549 int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
 550                                 unsigned int reg_addr,
 551                                 unsigned char *data);
 552 int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
 553                                 unsigned int reg_addr,
 554                                 unsigned int count,
 555                                 unsigned char data[]);
 556 int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
 557                                 unsigned int reg_addr,
 558                                 unsigned int count,
 559                                 unsigned char data[]);
 560 int rk32_edp_select_i2c_device(struct rk32_edp *edp,
 561                                 unsigned int device_addr,
 562                                 unsigned int reg_addr);
 563 int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
 564                                 unsigned int device_addr,
 565                                 unsigned int reg_addr,
 566                                 unsigned int *data);
 567 int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
 568                                 unsigned int device_addr,
 569                                 unsigned int reg_addr,
 570                                 unsigned int count,
 571                                 unsigned char edid[]);
 572 void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype);
 573 void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype);
 574 void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count);
 575 void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count);
 576 void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable);
 577 void rk32_edp_set_training_pattern(struct rk32_edp *edp,
 578                                  enum pattern_set pattern);
 579 void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level);
 580 void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level);
 581 void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level);
 582 void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level);
 583 void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
 584                                 u32 training_lane);
 585 void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
 586                                 u32 training_lane);
 587 void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
 588                                 u32 training_lane);
 589 void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
 590                                 u32 training_lane);
 591 u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp);
 592 u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp);
 593 u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp);
 594 u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp);
 595 void rk32_edp_reset_macro(struct rk32_edp *edp);
 596 int rk32_edp_init_video(struct rk32_edp *edp);
 597
 598 void rk32_edp_set_video_color_format(struct rk32_edp *edp,
 599                                 u32 color_depth,
 600                                 u32 color_space,
 601                                 u32 dynamic_range,
 602                                 u32 coeff);
 603 int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp);
 604 void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
 605                         enum clock_recovery_m_value_type type,
 606                         u32 m_value,
 607                         u32 n_value);
 608 void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type);
 609 void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable);
 610 void rk32_edp_start_video(struct rk32_edp *edp);
 611 int rk32_edp_is_video_stream_on(struct rk32_edp *edp);
 612 void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
 613                         struct video_info *video_info);
 614 void rk32_edp_enable_scrambling(struct rk32_edp *edp);
 615 void rk32_edp_disable_scrambling(struct rk32_edp *edp);
 616 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable);
 617 int rk32_edp_bist_cfg(struct rk32_edp *edp);
 618 void rk32_edp_hw_link_training_en(struct rk32_edp * edp);
 619 int rk32_edp_get_hw_lt_status(struct rk32_edp *edp);
 620 int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp);
 621 enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp);
 622 void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp);
 623
 624 #endif