drivers/video/rockchip/transmitter/rk32_dp.h

   1 #ifndef __RK32_DP_H
   2 #define __RK32_DP_H
   3
   4 #include <linux/mfd/syscon.h>
   5 #include <linux/regmap.h>
   6 #include <linux/reset.h>
   7 #include <linux/rk_fb.h>
   8
   9 #include "dpcd_edid.h"
  10
  11 #define DP_VERSION                              0x10
  12
  13 #define TX_SW_RST                               0x14
  14
  15 #define FUNC_EN_1                               0x18
  16 #define VID_CAP_FUNC_EN_N                       (0x1 << 6)
  17 #define VID_FIFO_FUNC_EN_N                      (0x1 << 5)
  18 #define AUD_FIFO_FUNC_EN_N                      (0x1 << 4)
  19 #define AUD_FUNC_EN_N                           (0x1 << 3)
  20 #define HDCP_FUNC_EN_N                          (0x1 << 2)
  21 #define SW_FUNC_EN_N                            (0x1 << 0)
  22
  23 #define FUNC_EN_2                               0x1C
  24 #define SSC_FUNC_EN_N                           (0x1 << 7)
  25 #define AUX_FUNC_EN_N                           (0x1 << 2)
  26 #define SERDES_FIFO_FUNC_EN_N                   (0x1 << 1)
  27 #define LS_CLK_DOMAIN_FUNC_EN_N                 (0x1 << 0)
  28
  29 #define VIDEO_CTL_1                             0x20
  30 #define VIDEO_EN                                (0x1 << 7)
  31 #define VIDEO_MUTE                              (0x1 << 6)
  32
  33 #define VIDEO_CTL_2                             0x24
  34 #define IN_D_RANGE_MASK                         (0x1 << 7)
  35 #define IN_D_RANGE_SHIFT                        (7)
  36 #define IN_D_RANGE_CEA                          (0x1 << 7)
  37 #define IN_D_RANGE_VESA                         (0x0 << 7)
  38 #define IN_BPC_MASK                             (0x7 << 4)
  39 #define IN_BPC_SHIFT                            (4)
  40 #define IN_BPC_12_BITS                          (0x3 << 4)
  41 #define IN_BPC_10_BITS                          (0x2 << 4)
  42 #define IN_BPC_8_BITS                           (0x1 << 4)
  43 #define IN_BPC_6_BITS                           (0x0 << 4)
  44 #define IN_COLOR_F_MASK                         (0x3 << 0)
  45 #define IN_COLOR_F_SHIFT                        (0)
  46 #define IN_COLOR_F_YCBCR444                     (0x2 << 0)
  47 #define IN_COLOR_F_YCBCR422                     (0x1 << 0)
  48 #define IN_COLOR_F_RGB                          (0x0 << 0)
  49
  50 #define VIDEO_CTL_3                             0x28
  51 #define IN_YC_COEFFI_MASK                       (0x1 << 7)
  52 #define IN_YC_COEFFI_SHIFT                      (7)
  53 #define IN_YC_COEFFI_ITU709                     (0x1 << 7)
  54 #define IN_YC_COEFFI_ITU601                     (0x0 << 7)
  55 #define VID_CHK_UPDATE_TYPE_MASK                (0x1 << 4)
  56 #define VID_CHK_UPDATE_TYPE_SHIFT               (4)
  57 #define VID_CHK_UPDATE_TYPE_1                   (0x1 << 4)
  58 #define VID_CHK_UPDATE_TYPE_0                   (0x0 << 4)
  59
  60 #define VIDEO_CTL_4                             0x2c
  61 #define BIST_EN                                 (0x1 << 3)
  62 #define BIST_WH_64                              (0x1 << 2)
  63 #define BIST_WH_32                              (0x0 << 2)
  64 #define BIST_TYPE_COLR_BAR                      (0x0 << 0)
  65 #define BIST_TYPE_GRAY_BAR                      (0x1 << 0)
  66 #define BIST_TYPE_MOBILE_BAR                    (0x2 << 0)
  67
  68 #define VIDEO_CTL_8                             0x3C
  69 #define VID_HRES_TH(x)                          (((x) & 0xf) << 4)
  70 #define VID_VRES_TH(x)                          (((x) & 0xf) << 0)
  71
  72 #define VIDEO_CTL_10                            0x44
  73 #define F_SEL                                   (0x1 << 4)
  74 #define INTERACE_SCAN_CFG                       (0x1 << 2)
  75 #define VSYNC_POLARITY_CFG                      (0x1 << 1)
  76 #define HSYNC_POLARITY_CFG                      (0x1 << 0)
  77
  78 #define TOTAL_LINE_CFG_L                        0x48
  79 #define TOTAL_LINE_CFG_H                        0x4c
  80 #define ATV_LINE_CFG_L                          0x50
  81 #define ATV_LINE_CFG_H                          0x54
  82 #define VF_PORCH_REG                            0x58
  83 #define VSYNC_CFG_REG                           0x5c
  84 #define VB_PORCH_REG                            0x60
  85 #define TOTAL_PIXELL_REG                        0x64
  86 #define TOTAL_PIXELH_REG                        0x68
  87 #define ATV_PIXELL_REG                          0x6c
  88 #define ATV_PIXELH_REG                          0x70
  89 #define HF_PORCHL_REG                           0x74
  90 #define HF_PORCHH_REG                           0x78
  91 #define HSYNC_CFGL_REG                          0x7c
  92 #define HSYNC_CFGH_REG                          0x80
  93 #define HB_PORCHL_REG                           0x84
  94 #define HB_PORCHH_REG                           0x88
  95
  96
  97 #define SSC_REG                                 0x104
  98 #define TX_REG_COMMON                           0x114
  99 #define DP_AUX                                  0x120
 100 #define DP_BIAS                                 0x124
 101
 102 #define PLL_REG_1                               0xfc
 103 #define REF_CLK_24M                             (0x1 << 1)
 104 #define REF_CLK_27M                             (0x0 << 1)
 105
 106 #define PLL_REG_2                               0x9e4
 107 #define PLL_REG_3                               0x9e8
 108 #define PLL_REG_4                               0x9ec
 109 #define PLL_REG_5                               0xa00
 110 #define DP_PWRDN                                0x12c
 111 #define PD_INC_BG                               (0x1 << 7)
 112 #define PD_EXP_BG                               (0x1 << 6)
 113 #define PD_AUX                                  (0x1 << 5)
 114 #define PD_PLL                                  (0x1 << 4)
 115 #define PD_CH3                                  (0x1 << 3)
 116 #define PD_CH2                                  (0x1 << 2)
 117 #define PD_CH1                                  (0x1 << 1)
 118 #define PD_CH0                                  (0x1 << 0)
 119
 120 #define DP_RESERVE2                             0x134
 121
 122 #define LANE_MAP                                0x35C
 123 #define LANE3_MAP_LOGIC_LANE_0                  (0x0 << 6)
 124 #define LANE3_MAP_LOGIC_LANE_1                  (0x1 << 6)
 125 #define LANE3_MAP_LOGIC_LANE_2                  (0x2 << 6)
 126 #define LANE3_MAP_LOGIC_LANE_3                  (0x3 << 6)
 127 #define LANE2_MAP_LOGIC_LANE_0                  (0x0 << 4)
 128 #define LANE2_MAP_LOGIC_LANE_1                  (0x1 << 4)
 129 #define LANE2_MAP_LOGIC_LANE_2                  (0x2 << 4)
 130 #define LANE2_MAP_LOGIC_LANE_3                  (0x3 << 4)
 131 #define LANE1_MAP_LOGIC_LANE_0                  (0x0 << 2)
 132 #define LANE1_MAP_LOGIC_LANE_1                  (0x1 << 2)
 133 #define LANE1_MAP_LOGIC_LANE_2                  (0x2 << 2)
 134 #define LANE1_MAP_LOGIC_LANE_3                  (0x3 << 2)
 135 #define LANE0_MAP_LOGIC_LANE_0                  (0x0 << 0)
 136 #define LANE0_MAP_LOGIC_LANE_1                  (0x1 << 0)
 137 #define LANE0_MAP_LOGIC_LANE_2                  (0x2 << 0)
 138 #define LANE0_MAP_LOGIC_LANE_3                  (0x3 << 0)
 139
 140 #define ANALOG_CTL_2                            0x374
 141 #define SEL_24M                                 (0x1 << 3)
 142
 143 /*#define ANALOG_CTL_3                          0x378
 144 #define PLL_FILTER_CTL_1                        0x37C
 145 #define TX_AMP_TUNING_CTL                       0x380*/
 146
 147 #define AUX_HW_RETRY_CTL                        0x390
 148
 149 #define INT_STA                                 0x3c0
 150
 151 #define COMMON_INT_STA_1                        0x3C4
 152 #define VSYNC_DET                               (0x1 << 7)
 153 #define PLL_LOCK_CHG                            (0x1 << 6)
 154 #define SPDIF_ERR                               (0x1 << 5)
 155 #define SPDIF_UNSTBL                            (0x1 << 4)
 156 #define VID_FORMAT_CHG                          (0x1 << 3)
 157 #define AUD_CLK_CHG                             (0x1 << 2)
 158 #define VID_CLK_CHG                             (0x1 << 1)
 159 #define SW_INT                                  (0x1 << 0)
 160
 161 #define COMMON_INT_STA_2                        0x3C8
 162 #define ENC_EN_CHG                              (0x1 << 6)
 163 #define HW_BKSV_RDY                             (0x1 << 3)
 164 #define HW_SHA_DONE                             (0x1 << 2)
 165 #define HW_AUTH_STATE_CHG                       (0x1 << 1)
 166 #define HW_AUTH_DONE                            (0x1 << 0)
 167
 168 #define COMMON_INT_STA_3                        0x3CC
 169 #define AFIFO_UNDER                             (0x1 << 7)
 170 #define AFIFO_OVER                              (0x1 << 6)
 171 #define R0_CHK_FLAG                             (0x1 << 5)
 172
 173 #define COMMON_INT_STA_4                        0x3D0
 174 #define PSR_ACTIVE                              (0x1 << 7)
 175 #define PSR_INACTIVE                            (0x1 << 6)
 176 #define SPDIF_BI_PHASE_ERR                      (0x1 << 5)
 177 #define HOTPLUG_CHG                             (0x1 << 2)
 178 #define HPD_LOST                                (0x1 << 1)
 179 #define PLUG                                    (0x1 << 0)
 180
 181 #define DP_INT_STA                              0x3DC
 182 #define INT_HPD                                 (0x1 << 6)
 183 #define HW_LT_DONE                              (0x1 << 5)
 184 #define SINK_LOST                               (0x1 << 3)
 185 #define LINK_LOST                               (0x1 << 2)
 186 #define RPLY_RECEIV                             (0x1 << 1)
 187 #define AUX_ERR                                 (0x1 << 0)
 188
 189 #define COMMON_INT_MASK_1                       0x3E0
 190 #define COMMON_INT_MASK_2                       0x3E4
 191 #define COMMON_INT_MASK_3                       0x3E8
 192 #define COMMON_INT_MASK_4                       0x3EC
 193 #define DP_INT_STA_MASK                         0x3F8
 194
 195 #define INT_CTL                                 0x3FC
 196 #define SOFT_INT_CTRL                           (0x1 << 2)
 197 #define INT_POL                                 (0x1 << 0)
 198
 199 #define SYS_CTL_1                               0x600
 200 #define DET_STA                                 (0x1 << 2)
 201 #define FORCE_DET                               (0x1 << 1)
 202 #define DET_CTRL                                (0x1 << 0)
 203
 204 #define SYS_CTL_2                               0x604
 205 #define CHA_CRI(x)                              (((x) & 0xf) << 4)
 206 #define CHA_STA                                 (0x1 << 2)
 207 #define FORCE_CHA                               (0x1 << 1)
 208 #define CHA_CTRL                                (0x1 << 0)
 209
 210 #define SYS_CTL_3                               0x608
 211 #define HPD_STATUS                              (0x1 << 6)
 212 #define F_HPD                                   (0x1 << 5)
 213 #define HPD_CTRL                                (0x1 << 4)
 214 #define HDCP_RDY                                (0x1 << 3)
 215 #define STRM_VALID                              (0x1 << 2)
 216 #define F_VALID                                 (0x1 << 1)
 217 #define VALID_CTRL                              (0x1 << 0)
 218
 219 #define SYS_CTL_4                               0x60C
 220 #define FIX_M_AUD                               (0x1 << 4)
 221 #define ENHANCED                                (0x1 << 3)
 222 #define FIX_M_VID                               (0x1 << 2)
 223 #define M_VID_UPDATE_CTRL                       (0x3 << 0)
 224
 225
 226 #define PKT_SEND_CTL                            0x640
 227 #define HDCP_CTL                                0x648
 228
 229 #define LINK_BW_SET                             0x680
 230 #define LANE_CNT_SET                            0x684
 231
 232 #define TRAINING_PTN_SET                        0x688
 233 #define SCRAMBLING_DISABLE                      (0x1 << 5)
 234 #define SCRAMBLING_ENABLE                       (0x0 << 5)
 235 #define LINK_QUAL_PATTERN_SET_MASK              (0x7 << 2)
 236 #define LINK_QUAL_PATTERN_SET_HBR2              (0x5 << 2)
 237 #define LINK_QUAL_PATTERN_SET_80BIT             (0x4 << 2)
 238 #define LINK_QUAL_PATTERN_SET_PRBS7             (0x3 << 2)
 239 #define LINK_QUAL_PATTERN_SET_D10_2             (0x1 << 2)
 240 #define LINK_QUAL_PATTERN_SET_DISABLE           (0x0 << 2)
 241 #define SW_TRAINING_PATTERN_SET_MASK            (0x3 << 0)
 242 #define SW_TRAINING_PATTERN_SET_PTN2            (0x2 << 0)
 243 #define SW_TRAINING_PATTERN_SET_PTN1            (0x1 << 0)
 244 #define SW_TRAINING_PATTERN_SET_DISABLE         (0x0 << 0)
 245
 246 #define LN0_LINK_TRAINING_CTL                   0x68C
 247 #define LN1_LINK_TRAINING_CTL                   0x690
 248 #define LN2_LINK_TRAINING_CTL                   0x694
 249 #define LN3_LINK_TRAINING_CTL                   0x698
 250
 251 #define HW_LT_CTL                               0x6a0
 252 #define HW_LT_ERR_CODE_MASK                     0x70
 253 #define HW_LT_EN                                (0x1 << 0)
 254
 255 #define DEBUG_CTL                               0x6C0
 256 #define PLL_LOCK                                (0x1 << 4)
 257 #define F_PLL_LOCK                              (0x1 << 3)
 258 #define PLL_LOCK_CTRL                           (0x1 << 2)
 259 #define POLL_EN                                 (0x1 << 1)
 260 #define PN_INV                                  (0x1 << 0)
 261
 262 #define HPD_DEGLITCH_L                          0x6C4
 263 #define HPD_DEGLITCH_H                          0x6C8
 264 #define LINK_DEBUG_CTL                          0x6E0
 265
 266 #define M_VID_0                                 0x700
 267 #define M_VID_1                                 0x704
 268 #define M_VID_2                                 0x708
 269 #define N_VID_0                                 0x70C
 270 #define N_VID_1                                 0x710
 271 #define N_VID_2                                 0x714
 272
 273 #define VIDEO_FIFO_THRD                         0x730
 274 #define AUDIO_MARGIN                            0x73C
 275
 276 #define M_VID_GEN_FILTER_TH                     0x764
 277 #define M_AUD_GEN_FILTER_TH                     0x778
 278
 279 #define AUX_CH_STA                              0x780
 280 #define AUX_BUSY                                (0x1 << 4)
 281 #define AUX_STATUS_MASK                         (0xf << 0)
 282
 283 #define AUX_CH_DEFER_CTL                        0x788
 284 #define DEFER_CTRL_EN                           (0x1 << 7)
 285 #define DEFER_COUNT(x)                          (((x) & 0x7f) << 0)
 286
 287 #define AUX_RX_COMM                             0x78C
 288 #define BUFFER_DATA_CTL                         0x790
 289 #define BUF_CLR                                 (0x1 << 7)
 290 #define BUF_HAVE_DATA                           (0x1 << 4)
 291 #define BUF_DATA_COUNT(x)                       (((x) & 0xf) << 0)
 292
 293 #define AUX_CH_CTL_1                            0x794
 294 #define AUX_LENGTH(x)                           (((x - 1) & 0xf) << 4)
 295 #define AUX_TX_COMM_MASK                        (0xf << 0)
 296 #define AUX_TX_COMM_DP_TRANSACTION              (0x1 << 3)
 297 #define AUX_TX_COMM_I2C_TRANSACTION             (0x0 << 3)
 298 #define AUX_TX_COMM_MOT                         (0x1 << 2)
 299 #define AUX_TX_COMM_WRITE                       (0x0 << 0)
 300 #define AUX_TX_COMM_READ                        (0x1 << 0)
 301
 302 #define DP_AUX_ADDR_7_0                         0x798
 303 #define DP_AUX_ADDR_15_8                        0x79C
 304 #define DP_AUX_ADDR_19_16                       0x7A0
 305
 306 #define AUX_CH_CTL_2                            0x7A4
 307 #define PD_AUX_IDLE                             (0x1 << 3)
 308 #define ADDR_ONLY                               (0x1 << 1)
 309 #define AUX_EN                                  (0x1 << 0)
 310
 311 #define BUF_DATA_0                              0x7C0
 312
 313 #define SOC_GENERAL_CTL                         0x800
 314
 315 /* TX_SW_RESET */
 316 #define RST_DP_TX                               (0x1 << 0)
 317
 318 /* ANALOG_CTL_1 */
 319 #define TX_TERMINAL_CTRL_50_OHM                 (0x1 << 4)
 320
 321
 322
 323 /* ANALOG_CTL_3 */
 324 #define DRIVE_DVDD_BIT_1_0625V                  (0x4 << 5)
 325 #define VCO_BIT_600_MICRO                       (0x5 << 0)
 326
 327 /* PLL_FILTER_CTL_1 */
 328 #define PD_RING_OSC                             (0x1 << 6)
 329 #define AUX_TERMINAL_CTRL_37_5_OHM              (0x0 << 4)
 330 #define AUX_TERMINAL_CTRL_45_OHM                (0x1 << 4)
 331 #define AUX_TERMINAL_CTRL_50_OHM                (0x2 << 4)
 332 #define AUX_TERMINAL_CTRL_65_OHM                (0x3 << 4)
 333 #define TX_CUR1_2X                              (0x1 << 2)
 334 #define TX_CUR_16_MA                            (0x3 << 0)
 335
 336 /* TX_AMP_TUNING_CTL */
 337 #define CH3_AMP_SHIFT                           (24)
 338 #define CH3_AMP_400_MV                          (0x0 << 24)
 339 #define CH2_AMP_SHIFT                           (16)
 340 #define CH2_AMP_400_MV                          (0x0 << 16)
 341 #define CH1_AMP_SHIFT                           (8)
 342 #define CH1_AMP_400_MV                          (0x0 << 8)
 343 #define CH0_AMP_SHIFT                           (0)
 344 #define CH0_AMP_400_MV                          (0x0 << 0)
 345
 346 /* AUX_HW_RETRY_CTL */
 347 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)        (((x) & 0x7) << 8)
 348 #define AUX_HW_RETRY_INTERVAL_MASK              (0x3 << 3)
 349 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS  (0x0 << 3)
 350 #define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS  (0x1 << 3)
 351 #define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3)
 352 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3)
 353 #define AUX_HW_RETRY_COUNT_SEL(x)               (((x) & 0x7) << 0)
 354
 355
 356
 357 /* LN0_LINK_TRAINING_CTL */
 358 #define PRE_EMPHASIS_SET_MASK                   (0x3 << 3)
 359 #define PRE_EMPHASIS_SET_SHIFT                  (3)
 360
 361
 362 /* PLL_CTL */
 363 #define DP_PLL_PD                               (0x1 << 7)
 364 #define DP_PLL_RESET                            (0x1 << 6)
 365 #define DP_PLL_LOOP_BIT_DEFAULT                 (0x1 << 4)
 366 #define DP_PLL_REF_BIT_1_1250V                  (0x5 << 0)
 367 #define DP_PLL_REF_BIT_1_2500V                  (0x7 << 0)
 368
 369 /* PHY_TEST */
 370 #define MACRO_RST                               (0x1 << 5)
 371 #define CH1_TEST                                (0x1 << 1)
 372 #define CH0_TEST                                (0x1 << 0)
 373
 374
 375
 376
 377
 378
 379
 380 #define DP_TIMEOUT_LOOP_CNT 100
 381 #define MAX_CR_LOOP 5
 382 #define MAX_EQ_LOOP 5
 383
 384
 385
 386 #define GRF_EDP_REF_CLK_SEL_INTER               (1 << 4)
 387 #define GRF_EDP_HDCP_EN                         (1 << 15)
 388 #define GRF_EDP_BIST_EN                         (1 << 14)
 389 #define GRF_EDP_MEM_CTL_BY_EDP                  (1 << 13)
 390 #define GRF_EDP_SECURE_EN                       (1 << 3)
 391 #define EDP_SEL_VOP_LIT                         (1 << 5)
 392
 393 /* PSR */
 394 #define PANEL_SELF_REFRESH_CAPABILITY_SUPPORTED_AND_VERSION 0x70
 395 #define PANEL_SELF_REFRESH_CAPABILITIES 0x71
 396 #define PSR_SUPPORT 0x1
 397 #define PSR_ENABLE 0x170
 398 #define SUORPSR_EVENT_STATUS_INDICATOR 0x2007
 399 #define SINK_DEVICE_PANEL_SELF_REFRESH_STATUS 0x2008
 400 #define LAST_RECEIVED_PSR_SDP 0x200a
 401 #define DEFINITION_WITHIN_LINKORSINK_DEVICE_POWER_CONTROL_FIELD 0x600
 402
 403 #define HB0 0x02F8
 404 #define HB1 0x02FC
 405 #define HB2 0x0300
 406 #define HB3 0x0304
 407 #define PB0 0x0308
 408 #define PB1 0x030C
 409 #define PB2 0x0310
 410 #define PB3 0x0314
 411 #define DB0 0x0254
 412 #define DB1 0x0258
 413 #define DB2 0x025C
 414 #define DB3 0x0260
 415 #define DB4 0x0264
 416 #define DB5 0x0268
 417 #define DB6 0x026c
 418 #define DB7 0x0270
 419 #define DP_PD 0x012C
 420 #define IF_TYPE 0x0244
 421 #define VSC_SHADOW_DB1 0x0320
 422 #define PSR_FRAME_UPDATA_CTRL 0x0318
 423 #define SPDIF_AUDIO_CTL_0 0x00D8
 424 /* PSR END */
 425
 426 enum dp_irq_type {
 427         DP_IRQ_TYPE_HP_CABLE_IN,
 428         DP_IRQ_TYPE_HP_CABLE_OUT,
 429         DP_IRQ_TYPE_HP_CHANGE,
 430         DP_IRQ_TYPE_UNKNOWN,
 431 };
 432
 433 enum color_coefficient {
 434         COLOR_YCBCR601,
 435         COLOR_YCBCR709
 436 };
 437
 438 enum dynamic_range {
 439         VESA,
 440         CEA
 441 };
 442
 443 enum pll_status {
 444         DP_PLL_UNLOCKED,
 445         DP_PLL_LOCKED
 446 };
 447
 448 enum clock_recovery_m_value_type {
 449         CALCULATED_M,
 450         REGISTER_M
 451 };
 452
 453 enum video_timing_recognition_type {
 454         VIDEO_TIMING_FROM_CAPTURE,
 455         VIDEO_TIMING_FROM_REGISTER
 456 };
 457
 458 enum pattern_set {
 459         PRBS7,
 460         D10_2,
 461         TRAINING_PTN1,
 462         TRAINING_PTN2,
 463         DP_NONE
 464 };
 465
 466 enum color_space {
 467         CS_RGB,
 468         CS_YCBCR422,
 469         CS_YCBCR444
 470 };
 471
 472 enum color_depth {
 473         COLOR_6,
 474         COLOR_8,
 475         COLOR_10,
 476         COLOR_12
 477 };
 478
 479 enum link_rate_type {
 480         LINK_RATE_1_62GBPS = 0x06,
 481         LINK_RATE_2_70GBPS = 0x0a
 482 };
 483
 484 enum link_lane_count_type {
 485         LANE_CNT1 = 1,
 486         LANE_CNT2 = 2,
 487         LANE_CNT4 = 4
 488 };
 489
 490 enum link_training_state {
 491         LT_START,
 492         LT_CLK_RECOVERY,
 493         LT_EQ_TRAINING,
 494         FINISHED,
 495         FAILED
 496 };
 497
 498 enum voltage_swing_level {
 499         VOLTAGE_LEVEL_0,
 500         VOLTAGE_LEVEL_1,
 501         VOLTAGE_LEVEL_2,
 502         VOLTAGE_LEVEL_3,
 503 };
 504
 505 enum pre_emphasis_level {
 506         PRE_EMPHASIS_LEVEL_0,
 507         PRE_EMPHASIS_LEVEL_1,
 508         PRE_EMPHASIS_LEVEL_2,
 509         PRE_EMPHASIS_LEVEL_3,
 510 };
 511
 512 enum analog_power_block {
 513         AUX_BLOCK,
 514         CH0_BLOCK,
 515         CH1_BLOCK,
 516         CH2_BLOCK,
 517         CH3_BLOCK,
 518         ANALOG_TOTAL,
 519         POWER_ALL
 520 };
 521
 522 struct video_info {
 523         char *name;
 524
 525         bool h_sync_polarity;
 526         bool v_sync_polarity;
 527         bool interlaced;
 528
 529         enum color_space color_space;
 530         enum dynamic_range dynamic_range;
 531         enum color_coefficient ycbcr_coeff;
 532         enum color_depth color_depth;
 533
 534         enum link_rate_type link_rate;
 535         enum link_lane_count_type lane_count;
 536 };
 537
 538 struct link_train {
 539         int eq_loop;
 540         int cr_loop[4];
 541
 542         u8 link_rate;
 543         u8 lane_count;
 544         u8 training_lane[4];
 545
 546         enum link_training_state lt_state;
 547 };
 548
 549 enum {
 550         SOC_COMMON = 0,
 551         SOC_RK3399
 552 };
 553
 554 struct rk32_edp {
 555         struct device           *dev;
 556         void __iomem            *regs;
 557         struct regmap           *grf;
 558         unsigned int            irq;
 559         struct clk              *grf_clk;
 560         struct clk              *pd;
 561         struct clk              *clk_edp;  /*clk for edp controller*/
 562         struct clk              *clk_24m;  /*clk for edp phy*/
 563         struct clk              *pclk;     /*clk for phb bus*/
 564         struct reset_control    *rst_24m;
 565         struct reset_control    *rst_apb;
 566         struct link_train       link_train;
 567         struct video_info       video_info;
 568         struct rk_screen        screen;
 569         struct fb_monspecs      specs;
 570         bool clk_on;
 571         bool edp_en;
 572         int soctype;
 573         struct dentry *debugfs_dir;
 574 };
 575
 576
 577 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable);
 578 void rk32_edp_stop_video(struct rk32_edp *edp);
 579 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable);
 580 void rk32_edp_init_refclk(struct rk32_edp *edp);
 581 void rk32_edp_init_interrupt(struct rk32_edp *edp);
 582 void rk32_edp_reset(struct rk32_edp *edp);
 583 void rk32_edp_config_interrupt(struct rk32_edp *edp);
 584 u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp);
 585 void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable);
 586 void rk32_edp_init_analog_func(struct rk32_edp *edp);
 587 void rk32_edp_init_hpd(struct rk32_edp *edp);
 588 void rk32_edp_reset_aux(struct rk32_edp *edp);
 589 void rk32_edp_init_aux(struct rk32_edp *edp);
 590 int rk32_edp_get_plug_in_status(struct rk32_edp *edp);
 591 void rk32_edp_enable_sw_function(struct rk32_edp *edp);
 592 int rk32_edp_start_aux_transaction(struct rk32_edp *edp);
 593 int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
 594                                 unsigned int reg_addr,
 595                                 unsigned char data);
 596 int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
 597                                  unsigned int reg_addr,
 598                                  unsigned char *data);
 599 int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
 600                                  unsigned int reg_addr,
 601                                  unsigned int count,
 602                                  unsigned char data[]);
 603 int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
 604                                   unsigned int reg_addr,
 605                                   unsigned int count,
 606                                   unsigned char data[]);
 607 int rk32_edp_select_i2c_device(struct rk32_edp *edp,
 608                                unsigned int device_addr,
 609                                unsigned int reg_addr);
 610 int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
 611                                 unsigned int device_addr,
 612                                 unsigned int reg_addr,
 613                                 unsigned int *data);
 614 int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
 615                                  unsigned int device_addr,
 616                                  unsigned int reg_addr,
 617                                  unsigned int count,
 618                                  unsigned char edid[]);
 619 void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype);
 620 void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype);
 621 void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count);
 622 void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count);
 623 void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable);
 624 void rk32_edp_set_training_pattern(struct rk32_edp *edp,
 625                                    enum pattern_set pattern);
 626 void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level);
 627 void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level);
 628 void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level);
 629 void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level);
 630 void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
 631                                       u32 training_lane);
 632 void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
 633                                       u32 training_lane);
 634 void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
 635                                       u32 training_lane);
 636 void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
 637                                       u32 training_lane);
 638 u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp);
 639 u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp);
 640 u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp);
 641 u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp);
 642 void rk32_edp_reset_macro(struct rk32_edp *edp);
 643 int rk32_edp_init_video(struct rk32_edp *edp);
 644
 645 void rk32_edp_set_video_color_format(struct rk32_edp *edp,
 646                                      u32 color_depth,
 647                                      u32 color_space,
 648                                      u32 dynamic_range,
 649                                      u32 coeff);
 650 int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp);
 651 void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
 652                               enum clock_recovery_m_value_type type,
 653                               u32 m_value,
 654                               u32 n_value);
 655 void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type);
 656 void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable);
 657 void rk32_edp_start_video(struct rk32_edp *edp);
 658 int rk32_edp_is_video_stream_on(struct rk32_edp *edp);
 659 void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
 660                                       struct video_info *video_info);
 661 void rk32_edp_enable_scrambling(struct rk32_edp *edp);
 662 void rk32_edp_disable_scrambling(struct rk32_edp *edp);
 663 void rk32_edp_rx_control(struct rk32_edp *edp, bool enable);
 664 int rk32_edp_bist_cfg(struct rk32_edp *edp);
 665 void rk32_edp_hw_link_training_en(struct rk32_edp *edp);
 666 int rk32_edp_get_hw_lt_status(struct rk32_edp *edp);
 667 int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp);
 668 enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp);
 669 void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp);
 670
 671 #endif