drivers/video/rockchip/transmitter/rk32_dp_reg.c

   1 /*
   2  *RockChip DP (Display port) register interface driver.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  */
   9
  10 #include <linux/device.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/rockchip/cpu.h>
  14 #include <linux/rockchip/iomap.h>
  15 #include <linux/rockchip/grf.h>
  16 #include "rk32_dp.h"
  17
  18
  19 void rk32_edp_enable_video_mute(struct rk32_edp *edp, bool enable)
  20 {
  21         u32 val;
  22
  23         if (enable) {
  24                 val = readl(edp->regs + VIDEO_CTL_1);
  25                 val |= VIDEO_MUTE;
  26                 writel(val, edp->regs + VIDEO_CTL_1);
  27         } else {
  28                 val = readl(edp->regs + VIDEO_CTL_1);
  29                 val &= ~VIDEO_MUTE;
  30                 writel(val, edp->regs + VIDEO_CTL_1);
  31         }
  32 }
  33
  34 void rk32_edp_stop_video(struct rk32_edp *edp)
  35 {
  36         u32 val;
  37
  38         val = readl(edp->regs + VIDEO_CTL_1);
  39         val &= ~VIDEO_EN;
  40         writel(val, edp->regs + VIDEO_CTL_1);
  41 }
  42
  43 void rk32_edp_lane_swap(struct rk32_edp *edp, bool enable)
  44 {
  45         u32 val;
  46
  47
  48         if (enable)
  49                 val = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
  50                         LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
  51         else
  52                 val = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
  53                         LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
  54
  55         writel(val, edp->regs + LANE_MAP);
  56 }
  57
  58 void rk32_edp_init_refclk(struct rk32_edp *edp)
  59 {
  60         u32 val;
  61         /*struct rk32_edp_platdata *pdata = edp->dev->platform_data;
  62         struct analog_param *analog_param = pdata->analog_param;
  63
  64         val = TX_TERMINAL_CTRL_50_OHM;
  65         writel(val, edp->regs + ANALOG_CTL_1);*/
  66
  67         val = SEL_24M;
  68         writel(val, edp->regs + ANALOG_CTL_2);
  69
  70         val = REF_CLK_24M;
  71         writel(val, edp->regs + PLL_REG_1);
  72
  73         val = 0x95;
  74         writel(val, edp->regs + PLL_REG_2);
  75
  76         val = 0x40;
  77         writel(val, edp->regs + PLL_REG_3);
  78
  79         val = 0x58;
  80         writel(val, edp->regs + PLL_REG_4);
  81
  82         val = 0x22;
  83         writel(val, edp->regs + PLL_REG_5);
  84
  85         val = 0x19;
  86         writel(val, edp->regs + SSC_REG);
  87         val = 0x87;
  88         writel(val, edp->regs + TX_REG_COMMON);
  89         val = 0x03;
  90         writel(val, edp->regs + DP_AUX);
  91         val = 0x46;
  92         writel(val, edp->regs + DP_BIAS);
  93         val = 0x55;
  94         writel(val, edp->regs + DP_RESERVE2);
  95
  96
  97         /*val = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
  98         writel(val, edp->regs + ANALOG_CTL_3);
  99
 100         if (!analog_param) {
 101                 val = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
 102                         TX_CUR1_2X | TX_CUR_16_MA;
 103                 writel(val, edp->regs + PLL_FILTER_CTL_1);
 104
 105                 val = CH3_AMP_400_MV | CH2_AMP_400_MV |
 106                         CH1_AMP_400_MV | CH0_AMP_400_MV;
 107                 writel(val, edp->regs + TX_AMP_TUNING_CTL);
 108         } else {
 109                 int tx_amp;
 110
 111                 val = PD_RING_OSC | TX_CUR1_2X | TX_CUR_16_MA;
 112                 switch (analog_param->aux_tx_terminal_resistor) {
 113                 case AUX_TX_37_5_OHM:
 114                         val |= AUX_TERMINAL_CTRL_37_5_OHM;
 115                         break;
 116                 case AUX_TX_45_OHM:
 117                         val |= AUX_TERMINAL_CTRL_45_OHM;
 118                         break;
 119                 case AUX_TX_50_OHM:
 120                         val |= AUX_TERMINAL_CTRL_50_OHM;
 121                         break;
 122                 case AUX_TX_65_OHM:
 123                         val |= AUX_TERMINAL_CTRL_65_OHM;
 124                         break;
 125                 }
 126                 writel(val, edp->regs + PLL_FILTER_CTL_1);
 127
 128                 tx_amp = analog_param->tx_amplitude;
 129                 if (tx_amp < 200000 || tx_amp > 500000) {
 130                         dev_warn(edp->dev,
 131                                  "TX amp out of range, defaulting to 400mV\n");
 132                         tx_amp = 400000;
 133                 }
 134
 135                 tx_amp = ((tx_amp - 400000) / 12500) & 0x1f;
 136
 137                 val = (tx_amp << CH3_AMP_SHIFT) | (tx_amp << CH2_AMP_SHIFT) |
 138                         (tx_amp << CH1_AMP_SHIFT) | (tx_amp << CH0_AMP_SHIFT);
 139                 writel(val, edp->regs + TX_AMP_TUNING_CTL);
 140         }*/
 141 }
 142
 143 void rk32_edp_init_interrupt(struct rk32_edp *edp)
 144 {
 145         /* Set interrupt pin assertion polarity as high */
 146         writel(INT_POL, edp->regs + INT_CTL);
 147
 148         /* Clear pending valisers */
 149         writel(0xff, edp->regs + COMMON_INT_STA_1);
 150         writel(0x4f, edp->regs + COMMON_INT_STA_2);
 151         writel(0xff, edp->regs + COMMON_INT_STA_3);
 152         writel(0x27, edp->regs + COMMON_INT_STA_4);
 153
 154         writel(0x7f, edp->regs + DP_INT_STA);
 155
 156         /* 0:mask,1: unmask */
 157         writel(0x00, edp->regs + COMMON_INT_MASK_1);
 158         writel(0x00, edp->regs + COMMON_INT_MASK_2);
 159         writel(0x00, edp->regs + COMMON_INT_MASK_3);
 160         writel(0x00, edp->regs + COMMON_INT_MASK_4);
 161         writel(0x00, edp->regs + DP_INT_STA_MASK);
 162 }
 163
 164 void rk32_edp_reset(struct rk32_edp *edp)
 165 {
 166         u32 val;
 167
 168         rk32_edp_stop_video(edp);
 169         rk32_edp_enable_video_mute(edp, 0);
 170
 171         val = VID_CAP_FUNC_EN_N | AUD_FIFO_FUNC_EN_N |
 172                 AUD_FUNC_EN_N | HDCP_FUNC_EN_N | SW_FUNC_EN_N;
 173         writel(val, edp->regs + FUNC_EN_1);
 174
 175         val = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 176                 SERDES_FIFO_FUNC_EN_N |
 177                 LS_CLK_DOMAIN_FUNC_EN_N;
 178         writel(val, edp->regs + FUNC_EN_2);
 179
 180         udelay(20);
 181
 182         rk32_edp_lane_swap(edp, 0);
 183
 184         writel(0x0, edp->regs + SYS_CTL_1);
 185         writel(0x40, edp->regs + SYS_CTL_2);
 186         writel(0x0, edp->regs + SYS_CTL_3);
 187         writel(0x0, edp->regs + SYS_CTL_4);
 188
 189         writel(0x0, edp->regs + PKT_SEND_CTL);
 190         writel(0x0, edp->regs + HDCP_CTL);
 191
 192         writel(0x5e, edp->regs + HPD_DEGLITCH_L);
 193         writel(0x1a, edp->regs + HPD_DEGLITCH_H);
 194
 195         writel(0x10, edp->regs + LINK_DEBUG_CTL);
 196
 197         writel(0x0, edp->regs + VIDEO_FIFO_THRD);
 198         writel(0x20, edp->regs + AUDIO_MARGIN);
 199
 200         writel(0x4, edp->regs + M_VID_GEN_FILTER_TH);
 201         writel(0x2, edp->regs + M_AUD_GEN_FILTER_TH);
 202
 203         writel(0x0, edp->regs + SOC_GENERAL_CTL);
 204
 205 }
 206
 207 void rk32_edp_config_interrupt(struct rk32_edp *edp)
 208 {
 209         u32 val;
 210
 211         /* 0: mask, 1: unmask */
 212         val = 0;
 213         writel(val, edp->regs + COMMON_INT_MASK_1);
 214
 215         writel(val, edp->regs + COMMON_INT_MASK_2);
 216
 217         writel(val, edp->regs + COMMON_INT_MASK_3);
 218
 219         writel(val, edp->regs + COMMON_INT_MASK_4);
 220
 221         writel(val, edp->regs + DP_INT_STA_MASK);
 222 }
 223
 224 u32 rk32_edp_get_pll_lock_status(struct rk32_edp *edp)
 225 {
 226         u32 val;
 227
 228         val = readl(edp->regs + DEBUG_CTL);
 229         if (val & PLL_LOCK)
 230                 return DP_PLL_LOCKED;
 231         else
 232                 return DP_PLL_UNLOCKED;
 233 }
 234
 235
 236 void rk32_edp_analog_power_ctr(struct rk32_edp *edp, bool enable)
 237 {
 238         u32 val;
 239
 240         if (enable) {
 241                 val = PD_EXP_BG | PD_AUX | PD_PLL |
 242                         PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
 243                 writel(val, edp->regs + DP_PWRDN);
 244                 udelay(10);
 245                 writel(0x0, edp->regs + DP_PWRDN);
 246         } else {
 247                 val = PD_EXP_BG | PD_AUX | PD_PLL |
 248                         PD_CH3 | PD_CH2 | PD_CH1 | PD_CH0;
 249                 writel(val, edp->regs + DP_PWRDN);
 250         }
 251 }
 252
 253
 254 void rk32_edp_init_analog_func(struct rk32_edp *edp)
 255 {
 256         u32 val;
 257         int wt = 0;
 258         rk32_edp_analog_power_ctr(edp, 1);
 259
 260         val = PLL_LOCK_CHG;
 261         writel(val, edp->regs + COMMON_INT_STA_1);
 262
 263         val = readl(edp->regs + DEBUG_CTL);
 264         val &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
 265         writel(val, edp->regs + DEBUG_CTL);
 266
 267         /* Power up PLL */
 268         while (wt < 100) {
 269                 if (rk32_edp_get_pll_lock_status(edp) == DP_PLL_LOCKED) {
 270                         dev_info(edp->dev, "edp pll locked\n");
 271                         break;
 272                 } else {
 273                         wt++;
 274                         udelay(5);
 275                 }
 276         }
 277
 278         /* Enable Serdes FIFO function and Link symbol clock domain module */
 279         val = readl(edp->regs + FUNC_EN_2);
 280         val &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 281                 | AUX_FUNC_EN_N | SSC_FUNC_EN_N);
 282         writel(val, edp->regs + FUNC_EN_2);
 283 }
 284
 285 void rk32_edp_init_hpd(struct rk32_edp *edp)
 286 {
 287         u32 val;
 288
 289         val = HOTPLUG_CHG | HPD_LOST | PLUG;
 290         writel(val, edp->regs + COMMON_INT_STA_4);
 291
 292         val = INT_HPD;
 293         writel(val, edp->regs + DP_INT_STA);
 294
 295         val = readl(edp->regs + SYS_CTL_3);
 296         val |= (F_HPD | HPD_CTRL);
 297         writel(val, edp->regs + SYS_CTL_3);
 298 }
 299
 300 void rk32_edp_reset_aux(struct rk32_edp *edp)
 301 {
 302         u32 val;
 303
 304         /* Disable AUX channel module */
 305         val = readl(edp->regs + FUNC_EN_2);
 306         val |= AUX_FUNC_EN_N;
 307         writel(val, edp->regs + FUNC_EN_2);
 308 }
 309
 310 void rk32_edp_init_aux(struct rk32_edp *edp)
 311 {
 312         u32 val;
 313
 314         /* Clear inerrupts related to AUX channel */
 315         val = RPLY_RECEIV | AUX_ERR;
 316         writel(val, edp->regs + DP_INT_STA);
 317
 318         rk32_edp_reset_aux(edp);
 319
 320         /* Disable AUX transaction H/W retry */
 321         /*val = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 322                 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 323         writel(val, edp->regs + AUX_HW_RETRY_CTL) ;*/
 324
 325         /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 326         val = DEFER_CTRL_EN | DEFER_COUNT(1);
 327         writel(val, edp->regs + AUX_CH_DEFER_CTL);
 328
 329         /* Enable AUX channel module */
 330         val = readl(edp->regs + FUNC_EN_2);
 331         val &= ~AUX_FUNC_EN_N;
 332         writel(val, edp->regs + FUNC_EN_2);
 333 }
 334
 335 int rk32_edp_get_plug_in_status(struct rk32_edp *edp)
 336 {
 337         u32 val;
 338
 339         val = readl(edp->regs + SYS_CTL_3);
 340         if (val & HPD_STATUS)
 341                 return 0;
 342
 343         return -EINVAL;
 344 }
 345
 346 void rk32_edp_enable_sw_function(struct rk32_edp *edp)
 347 {
 348         u32 val;
 349         val = readl(edp->regs + FUNC_EN_1);
 350         val &= ~SW_FUNC_EN_N;
 351         writel(val, edp->regs + FUNC_EN_1);
 352 }
 353
 354 int rk32_edp_start_aux_transaction(struct rk32_edp *edp)
 355 {
 356         int val;
 357         int retval = 0;
 358         int timeout_loop = 0;
 359         int aux_timeout = 0;
 360
 361         /* Enable AUX CH operation */
 362         val = readl(edp->regs + AUX_CH_CTL_2);
 363         val |= AUX_EN;
 364         writel(val, edp->regs + AUX_CH_CTL_2);
 365
 366         /* Is AUX CH operation enabled? */
 367         val = readl(edp->regs + AUX_CH_CTL_2);
 368         while (val & AUX_EN) {
 369                 aux_timeout++;
 370                 if ((DP_TIMEOUT_LOOP_CNT * 10) < aux_timeout) {
 371                         dev_err(edp->dev, "AUX CH enable timeout!\n");
 372                         return -ETIMEDOUT;
 373                 }
 374                 val = readl(edp->regs + AUX_CH_CTL_2);
 375                 udelay(100);
 376         }
 377
 378         /* Is AUX CH command redply received? */
 379         val = readl(edp->regs + DP_INT_STA);
 380         while (!(val & RPLY_RECEIV)) {
 381                 timeout_loop++;
 382                 if (DP_TIMEOUT_LOOP_CNT < timeout_loop) {
 383                         dev_err(edp->dev, "AUX CH command redply failed!\n");
 384                         return -ETIMEDOUT;
 385                 }
 386                 val = readl(edp->regs + DP_INT_STA);
 387                 udelay(10);
 388         }
 389
 390         /* Clear interrupt source for AUX CH command redply */
 391         writel(RPLY_RECEIV, edp->regs + DP_INT_STA);
 392
 393         /* Clear interrupt source for AUX CH access error */
 394         val = readl(edp->regs + DP_INT_STA);
 395         if (val & AUX_ERR) {
 396                 writel(AUX_ERR, edp->regs + DP_INT_STA);
 397                 return -EREMOTEIO;
 398         }
 399
 400         /* Check AUX CH error access status */
 401         val = readl(edp->regs + AUX_CH_STA);
 402         if ((val & AUX_STATUS_MASK) != 0) {
 403                 dev_err(edp->dev, "AUX CH error happens: %d\n\n",
 404                         val & AUX_STATUS_MASK);
 405                 return -EREMOTEIO;
 406         }
 407
 408         return retval;
 409 }
 410
 411 int rk32_edp_write_byte_to_dpcd(struct rk32_edp *edp,
 412                                 unsigned int val_addr,
 413                                 unsigned char data)
 414 {
 415         u32 val;
 416         int i;
 417         int retval;
 418
 419         for (i = 0; i < 3; i++) {
 420                 /* Clear AUX CH data buffer */
 421                 val = BUF_CLR;
 422                 writel(val, edp->regs + BUFFER_DATA_CTL);
 423
 424                 /* Select DPCD device address */
 425                 val = AUX_ADDR_7_0(val_addr);
 426                 writel(val, edp->regs + DP_AUX_ADDR_7_0);
 427                 val = AUX_ADDR_15_8(val_addr);
 428                 writel(val, edp->regs + DP_AUX_ADDR_15_8);
 429                 val = AUX_ADDR_19_16(val_addr);
 430                 writel(val, edp->regs + DP_AUX_ADDR_19_16);
 431
 432                 /* Write data buffer */
 433                 val = (unsigned int)data;
 434                 writel(val, edp->regs + BUF_DATA_0);
 435
 436                 /*
 437                  * Set DisplayPort transaction and write 1 byte
 438                  * If bit 3 is 1, DisplayPort transaction.
 439                  * If Bit 3 is 0, I2C transaction.
 440                  */
 441                 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 442                 writel(val, edp->regs + AUX_CH_CTL_1);
 443
 444                 /* Start AUX transaction */
 445                 retval = rk32_edp_start_aux_transaction(edp);
 446                 if (retval == 0)
 447                         break;
 448                 else
 449                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 450         }
 451
 452         return retval;
 453 }
 454
 455 int rk32_edp_read_byte_from_dpcd(struct rk32_edp *edp,
 456                                 unsigned int val_addr,
 457                                 unsigned char *data)
 458 {
 459         u32 val;
 460         int i;
 461         int retval;
 462
 463         for (i = 0; i < 10; i++) {
 464                 /* Clear AUX CH data buffer */
 465                 val = BUF_CLR;
 466                 writel(val, edp->regs + BUFFER_DATA_CTL);
 467
 468                 /* Select DPCD device address */
 469                 val = AUX_ADDR_7_0(val_addr);
 470                 writel(val, edp->regs + DP_AUX_ADDR_7_0);
 471                 val = AUX_ADDR_15_8(val_addr);
 472                 writel(val, edp->regs + DP_AUX_ADDR_15_8);
 473                 val = AUX_ADDR_19_16(val_addr);
 474                 writel(val, edp->regs + DP_AUX_ADDR_19_16);
 475
 476                 /*
 477                  * Set DisplayPort transaction and read 1 byte
 478                  * If bit 3 is 1, DisplayPort transaction.
 479                  * If Bit 3 is 0, I2C transaction.
 480                  */
 481                 val = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 482                 writel(val, edp->regs + AUX_CH_CTL_1);
 483
 484                 /* Start AUX transaction */
 485                 retval = rk32_edp_start_aux_transaction(edp);
 486                 if (retval == 0)
 487                         break;
 488                 else
 489                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 490         }
 491
 492         /* Read data buffer */
 493         val = readl(edp->regs + BUF_DATA_0);
 494         *data = (unsigned char)(val & 0xff);
 495
 496         return retval;
 497 }
 498
 499 int rk32_edp_write_bytes_to_dpcd(struct rk32_edp *edp,
 500                                 unsigned int val_addr,
 501                                 unsigned int count,
 502                                 unsigned char data[])
 503 {
 504         u32 val;
 505         unsigned int start_offset;
 506         unsigned int cur_data_count;
 507         unsigned int cur_data_idx;
 508         int i;
 509         int retval = 0;
 510
 511         /* Clear AUX CH data buffer */
 512         val = BUF_CLR;
 513         writel(val, edp->regs + BUFFER_DATA_CTL);
 514
 515         start_offset = 0;
 516         while (start_offset < count) {
 517                 /* Buffer size of AUX CH is 16 * 4bytes */
 518                 if ((count - start_offset) > 16)
 519                         cur_data_count = 16;
 520                 else
 521                         cur_data_count = count - start_offset;
 522
 523                 for (i = 0; i < 10; i++) {
 524                         /* Select DPCD device address */
 525                         val = AUX_ADDR_7_0(val_addr + start_offset);
 526                         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 527                         val = AUX_ADDR_15_8(val_addr + start_offset);
 528                         writel(val, edp->regs + DP_AUX_ADDR_15_8);
 529                         val = AUX_ADDR_19_16(val_addr + start_offset);
 530                         writel(val, edp->regs + DP_AUX_ADDR_19_16);
 531
 532                         for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 533                              cur_data_idx++) {
 534                                 val = data[start_offset + cur_data_idx];
 535                                 writel(val, edp->regs + BUF_DATA_0
 536                                                           + 4 * cur_data_idx);
 537                         }
 538
 539                         /*
 540                          * Set DisplayPort transaction and write
 541                          * If bit 3 is 1, DisplayPort transaction.
 542                          * If Bit 3 is 0, I2C transaction.
 543                          */
 544                         val = AUX_LENGTH(cur_data_count) |
 545                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
 546                         writel(val, edp->regs + AUX_CH_CTL_1);
 547
 548                         /* Start AUX transaction */
 549                         retval = rk32_edp_start_aux_transaction(edp);
 550                         if (retval == 0)
 551                                 break;
 552                         else
 553                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 554                 }
 555
 556                 start_offset += cur_data_count;
 557         }
 558
 559         return retval;
 560 }
 561
 562 int rk32_edp_read_bytes_from_dpcd(struct rk32_edp *edp,
 563                                 unsigned int val_addr,
 564                                 unsigned int count,
 565                                 unsigned char data[])
 566 {
 567         u32 val;
 568         unsigned int start_offset;
 569         unsigned int cur_data_count;
 570         unsigned int cur_data_idx;
 571         int i;
 572         int retval = 0;
 573
 574         /* Clear AUX CH data buffer */
 575         val = BUF_CLR;
 576         writel(val, edp->regs + BUFFER_DATA_CTL);
 577
 578         start_offset = 0;
 579         while (start_offset < count) {
 580                 /* Buffer size of AUX CH is 16 * 4bytes */
 581                 if ((count - start_offset) > 16)
 582                         cur_data_count = 16;
 583                 else
 584                         cur_data_count = count - start_offset;
 585
 586                 /* AUX CH Request Transaction process */
 587                 for (i = 0; i < 10; i++) {
 588                         /* Select DPCD device address */
 589                         val = AUX_ADDR_7_0(val_addr + start_offset);
 590                         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 591                         val = AUX_ADDR_15_8(val_addr + start_offset);
 592                         writel(val, edp->regs + DP_AUX_ADDR_15_8);
 593                         val = AUX_ADDR_19_16(val_addr + start_offset);
 594                         writel(val, edp->regs + DP_AUX_ADDR_19_16);
 595
 596                         /*
 597                          * Set DisplayPort transaction and read
 598                          * If bit 3 is 1, DisplayPort transaction.
 599                          * If Bit 3 is 0, I2C transaction.
 600                          */
 601                         val = AUX_LENGTH(cur_data_count) |
 602                                 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
 603                         writel(val, edp->regs + AUX_CH_CTL_1);
 604
 605                         /* Start AUX transaction */
 606                         retval = rk32_edp_start_aux_transaction(edp);
 607                         if (retval == 0)
 608                                 break;
 609                         else
 610                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 611                 }
 612
 613                 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 614                     cur_data_idx++) {
 615                         val = readl(edp->regs + BUF_DATA_0
 616                                                  + 4 * cur_data_idx);
 617                         data[start_offset + cur_data_idx] =
 618                                 (unsigned char)val;
 619                 }
 620
 621                 start_offset += cur_data_count;
 622         }
 623
 624         return retval;
 625 }
 626
 627 int rk32_edp_select_i2c_device(struct rk32_edp *edp,
 628                                 unsigned int device_addr,
 629                                 unsigned int val_addr)
 630 {
 631         u32 val;
 632         int retval;
 633
 634         /* Set EDID device address */
 635         val = device_addr;
 636         writel(val, edp->regs + DP_AUX_ADDR_7_0);
 637         writel(0x0, edp->regs + DP_AUX_ADDR_15_8);
 638         writel(0x0, edp->regs + DP_AUX_ADDR_19_16);
 639
 640         /* Set offset from base address of EDID device */
 641         writel(val_addr, edp->regs + BUF_DATA_0);
 642
 643         /*
 644          * Set I2C transaction and write address
 645          * If bit 3 is 1, DisplayPort transaction.
 646          * If Bit 3 is 0, I2C transaction.
 647          */
 648         val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 649                 AUX_TX_COMM_WRITE;
 650         writel(val, edp->regs + AUX_CH_CTL_1);
 651
 652         /* Start AUX transaction */
 653         retval = rk32_edp_start_aux_transaction(edp);
 654         if (retval != 0)
 655                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 656
 657         return retval;
 658 }
 659
 660 int rk32_edp_read_byte_from_i2c(struct rk32_edp *edp,
 661                                 unsigned int device_addr,
 662                                 unsigned int val_addr,
 663                                 unsigned int *data)
 664 {
 665         u32 val;
 666         int i;
 667         int retval;
 668
 669         for (i = 0; i < 10; i++) {
 670                 /* Clear AUX CH data buffer */
 671                 val = BUF_CLR;
 672                 writel(val, edp->regs + BUFFER_DATA_CTL);
 673
 674                 /* Select EDID device */
 675                 retval = rk32_edp_select_i2c_device(edp, device_addr, val_addr);
 676                 if (retval != 0) {
 677                         dev_err(edp->dev, "Select EDID device fail!\n");
 678                         continue;
 679                 }
 680
 681                 /*
 682                  * Set I2C transaction and read data
 683                  * If bit 3 is 1, DisplayPort transaction.
 684                  * If Bit 3 is 0, I2C transaction.
 685                  */
 686                 val = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_READ;
 687                 writel(val, edp->regs + AUX_CH_CTL_1);
 688
 689                 /* Start AUX transaction */
 690                 retval = rk32_edp_start_aux_transaction(edp);
 691                 if (retval == 0)
 692                         break;
 693                 else
 694                         dev_dbg(edp->dev, "Aux Transaction fail!\n");
 695         }
 696
 697         /* Read data */
 698         if (retval == 0)
 699                 *data = readl(edp->regs + BUF_DATA_0);
 700
 701         return retval;
 702 }
 703
 704 int rk32_edp_read_bytes_from_i2c(struct rk32_edp *edp,
 705                                 unsigned int device_addr,
 706                                 unsigned int val_addr,
 707                                 unsigned int count,
 708                                 unsigned char edid[])
 709 {
 710         u32 val;
 711         unsigned int i, j;
 712         unsigned int cur_data_idx;
 713         unsigned int defer = 0;
 714         int retval = 0;
 715
 716         for (i = 0; i < count; i += 16) {
 717                 for (j = 0; j < 100; j++) {
 718                         /* Clear AUX CH data buffer */
 719                         val = BUF_CLR;
 720                         writel(val, edp->regs + BUFFER_DATA_CTL);
 721
 722                         /* Set normal AUX CH command */
 723                         val = readl(edp->regs + AUX_CH_CTL_2);
 724                         val &= ~ADDR_ONLY;
 725                         writel(val, edp->regs + AUX_CH_CTL_2);
 726
 727                         /*
 728                          * If Rx sends defer, Tx sends only reads
 729                          * request without sending addres
 730                          */
 731                         if (!defer)
 732                                 retval = rk32_edp_select_i2c_device(edp,
 733                                                 device_addr, val_addr + i);
 734                         else
 735                                 defer = 0;
 736
 737                         /*
 738                          * Set I2C transaction and write data
 739                          * If bit 3 is 1, DisplayPort transaction.
 740                          * If Bit 3 is 0, I2C transaction.
 741                          */
 742                         val = AUX_LENGTH(16) | AUX_TX_COMM_I2C_TRANSACTION |
 743                                 AUX_TX_COMM_READ;
 744                         writel(val, edp->regs + AUX_CH_CTL_1);
 745
 746                         /* Start AUX transaction */
 747                         retval = rk32_edp_start_aux_transaction(edp);
 748                         if (retval == 0)
 749                                 break;
 750                         else
 751                                 dev_dbg(edp->dev, "Aux Transaction fail!\n");
 752
 753                         /* Check if Rx sends defer */
 754                         val = readl(edp->regs + AUX_RX_COMM);
 755                         if (val == AUX_RX_COMM_AUX_DEFER ||
 756                                 val == AUX_RX_COMM_I2C_DEFER) {
 757                                 dev_err(edp->dev, "Defer: %d\n\n", val);
 758                                 defer = 1;
 759                         }
 760                 }
 761
 762                 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
 763                         val = readl(edp->regs + BUF_DATA_0 + 4 * cur_data_idx);
 764                         edid[i + cur_data_idx] = (unsigned char)val;
 765                 }
 766         }
 767
 768         return retval;
 769 }
 770
 771 void rk32_edp_set_link_bandwidth(struct rk32_edp *edp, u32 bwtype)
 772 {
 773         u32 val;
 774
 775         val = bwtype;
 776         if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
 777                 writel(val, edp->regs + LINK_BW_SET);
 778 }
 779
 780 void rk32_edp_get_link_bandwidth(struct rk32_edp *edp, u32 *bwtype)
 781 {
 782         u32 val;
 783
 784         val = readl(edp->regs + LINK_BW_SET);
 785         *bwtype = val;
 786 }
 787
 788 void rk32_edp_hw_link_training_en(struct rk32_edp *edp)
 789 {
 790         u32 val;
 791         val = HW_LT_EN;
 792         writel(val, edp->regs + HW_LT_CTL);
 793 }
 794
 795 int rk32_edp_wait_hw_lt_done(struct rk32_edp *edp)
 796 {
 797         u32 val;
 798 #if 0
 799         val = readl(edp->regs + HW_LT_CTL);
 800         return val&0x01;
 801 #else
 802         val = readl(edp->regs + DP_INT_STA);
 803         if (val&HW_LT_DONE) {
 804                 writel(val, edp->regs + DP_INT_STA);
 805                 return 0;
 806         } else {
 807                 return 1;
 808         }
 809 #endif
 810 }
 811
 812 int rk32_edp_get_hw_lt_status(struct rk32_edp *edp)
 813 {
 814         u32 val;
 815         val = readl(edp->regs + HW_LT_CTL);
 816         return (val & HW_LT_ERR_CODE_MASK) >> 4;
 817 }
 818 void rk32_edp_set_lane_count(struct rk32_edp *edp, u32 count)
 819 {
 820         u32 val;
 821
 822         val = count;
 823         writel(val, edp->regs + LANE_CNT_SET);
 824 }
 825
 826 void rk32_edp_get_lane_count(struct rk32_edp *edp, u32 *count)
 827 {
 828         u32 val;
 829
 830         val = readl(edp->regs + LANE_CNT_SET);
 831         *count = val;
 832 }
 833
 834 void rk32_edp_enable_enhanced_mode(struct rk32_edp *edp, bool enable)
 835 {
 836         u32 val;
 837
 838         if (enable) {
 839                 val = readl(edp->regs + SYS_CTL_4);
 840                 val |= ENHANCED;
 841                 writel(val, edp->regs + SYS_CTL_4);
 842         } else {
 843                 val = readl(edp->regs + SYS_CTL_4);
 844                 val &= ~ENHANCED;
 845                 writel(val, edp->regs + SYS_CTL_4);
 846         }
 847 }
 848
 849 void rk32_edp_set_training_pattern(struct rk32_edp *edp,
 850                                  enum pattern_set pattern)
 851 {
 852         u32 val;
 853
 854         switch (pattern) {
 855         case PRBS7:
 856                 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
 857                 writel(val, edp->regs + TRAINING_PTN_SET);
 858                 break;
 859         case D10_2:
 860                 val = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
 861                 writel(val, edp->regs + TRAINING_PTN_SET);
 862                 break;
 863         case TRAINING_PTN1:
 864                 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
 865                 writel(val, edp->regs + TRAINING_PTN_SET);
 866                 break;
 867         case TRAINING_PTN2:
 868                 val = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
 869                 writel(val, edp->regs + TRAINING_PTN_SET);
 870                 break;
 871         case DP_NONE:
 872                 val = SCRAMBLING_ENABLE |
 873                         LINK_QUAL_PATTERN_SET_DISABLE |
 874                         SW_TRAINING_PATTERN_SET_DISABLE;
 875                 writel(val, edp->regs + TRAINING_PTN_SET);
 876                 break;
 877         default:
 878                 break;
 879         }
 880 }
 881
 882 void rk32_edp_set_lane0_pre_emphasis(struct rk32_edp *edp, u32 level)
 883 {
 884         u32 val;
 885
 886         val = level << PRE_EMPHASIS_SET_SHIFT;
 887         writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
 888 }
 889
 890 void rk32_edp_set_lane1_pre_emphasis(struct rk32_edp *edp, u32 level)
 891 {
 892         u32 val;
 893
 894         val = level << PRE_EMPHASIS_SET_SHIFT;
 895         writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
 896 }
 897
 898 void rk32_edp_set_lane2_pre_emphasis(struct rk32_edp *edp, u32 level)
 899 {
 900         u32 val;
 901
 902         val = level << PRE_EMPHASIS_SET_SHIFT;
 903         writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
 904 }
 905
 906 void rk32_edp_set_lane3_pre_emphasis(struct rk32_edp *edp, u32 level)
 907 {
 908         u32 val;
 909
 910         val = level << PRE_EMPHASIS_SET_SHIFT;
 911         writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
 912 }
 913
 914 void rk32_edp_set_lane0_link_training(struct rk32_edp *edp,
 915                                         u32 training_lane)
 916 {
 917         u32 val;
 918
 919         val = training_lane;
 920         writel(val, edp->regs + LN0_LINK_TRAINING_CTL);
 921 }
 922
 923 void rk32_edp_set_lane1_link_training(struct rk32_edp *edp,
 924                                         u32 training_lane)
 925 {
 926         u32 val;
 927
 928         val = training_lane;
 929         writel(val, edp->regs + LN1_LINK_TRAINING_CTL);
 930 }
 931
 932 void rk32_edp_set_lane2_link_training(struct rk32_edp *edp,
 933                                         u32 training_lane)
 934 {
 935         u32 val;
 936
 937         val = training_lane;
 938         writel(val, edp->regs + LN2_LINK_TRAINING_CTL);
 939 }
 940
 941 void rk32_edp_set_lane3_link_training(struct rk32_edp *edp,
 942                                         u32 training_lane)
 943 {
 944         u32 val;
 945
 946         val = training_lane;
 947         writel(val, edp->regs + LN3_LINK_TRAINING_CTL);
 948 }
 949
 950 u32 rk32_edp_get_lane0_link_training(struct rk32_edp *edp)
 951 {
 952         u32 val;
 953
 954         val = readl(edp->regs + LN0_LINK_TRAINING_CTL);
 955         return val;
 956 }
 957
 958 u32 rk32_edp_get_lane1_link_training(struct rk32_edp *edp)
 959 {
 960         u32 val;
 961
 962         val = readl(edp->regs + LN1_LINK_TRAINING_CTL);
 963         return val;
 964 }
 965
 966 u32 rk32_edp_get_lane2_link_training(struct rk32_edp *edp)
 967 {
 968         u32 val;
 969
 970         val = readl(edp->regs + LN2_LINK_TRAINING_CTL);
 971         return val;
 972 }
 973
 974 u32 rk32_edp_get_lane3_link_training(struct rk32_edp *edp)
 975 {
 976         u32 val;
 977
 978         val = readl(edp->regs + LN3_LINK_TRAINING_CTL);
 979         return val;
 980 }
 981
 982 void rk32_edp_reset_macro(struct rk32_edp *edp)
 983 {
 984         /*u32 val;
 985
 986         val = readl(edp->regs + PHY_TEST);
 987         val |= MACRO_RST;
 988         writel(val, edp->regs + PHY_TEST);
 989
 990
 991         udelay(10);
 992
 993         val &= ~MACRO_RST;
 994         writel(val, edp->regs + PHY_TEST);*/
 995 }
 996
 997 int rk32_edp_init_video(struct rk32_edp *edp)
 998 {
 999         u32 val;
1000
1001         val = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1002         writel(val, edp->regs + COMMON_INT_STA_1);
1003
1004         val = 0x0;
1005         writel(val, edp->regs + SYS_CTL_1);
1006
1007         val = CHA_CRI(4) | CHA_CTRL;
1008         writel(val, edp->regs + SYS_CTL_2);
1009
1010         /*val = 0x0;
1011         writel(val, edp->regs + SYS_CTL_3);*/
1012
1013         val = VID_HRES_TH(2) | VID_VRES_TH(0);
1014         writel(val, edp->regs + VIDEO_CTL_8);
1015
1016         return 0;
1017 }
1018
1019 void rk32_edp_set_video_color_format(struct rk32_edp *edp,
1020                         u32 color_dedpth,
1021                         u32 color_space,
1022                         u32 dynamic_range,
1023                         u32 coeff)
1024 {
1025         u32 val;
1026
1027         /* Configure the input color dedpth, color space, dynamic range */
1028         val = (dynamic_range << IN_D_RANGE_SHIFT) |
1029                 (color_dedpth << IN_BPC_SHIFT) |
1030                 (color_space << IN_COLOR_F_SHIFT);
1031         writel(val, edp->regs + VIDEO_CTL_2);
1032
1033         /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1034         val = readl(edp->regs + VIDEO_CTL_3);
1035         val &= ~IN_YC_COEFFI_MASK;
1036         if (coeff)
1037                 val |= IN_YC_COEFFI_ITU709;
1038         else
1039                 val |= IN_YC_COEFFI_ITU601;
1040         writel(val, edp->regs + VIDEO_CTL_3);
1041 }
1042
1043 int rk32_edp_is_slave_video_stream_clock_on(struct rk32_edp *edp)
1044 {
1045         u32 val;
1046
1047         val = readl(edp->regs + SYS_CTL_1);
1048         writel(val, edp->regs + SYS_CTL_1);
1049
1050         val = readl(edp->regs + SYS_CTL_1);
1051
1052         if (!(val & DET_STA)) {
1053                 dev_dbg(edp->dev, "Input stream clock not detected.\n");
1054                 return -EINVAL;
1055         }
1056
1057         val = readl(edp->regs + SYS_CTL_2);
1058         writel(val, edp->regs + SYS_CTL_2);
1059
1060         val = readl(edp->regs + SYS_CTL_2);
1061         if (val & CHA_STA) {
1062                 dev_dbg(edp->dev, "Input stream clk is changing\n");
1063                 return -EINVAL;
1064         }
1065
1066         return 0;
1067 }
1068
1069
1070 void rk32_edp_set_video_cr_mn(struct rk32_edp *edp,
1071                 enum clock_recovery_m_value_type type,
1072                 u32 m_value,
1073                 u32 n_value)
1074 {
1075         u32 val;
1076
1077         if (type == REGISTER_M) {
1078                 val = readl(edp->regs + SYS_CTL_4);
1079                 val |= FIX_M_VID;
1080                 writel(val, edp->regs + SYS_CTL_4);
1081                 val = m_value & 0xff;
1082                 writel(val, edp->regs + M_VID_0);
1083                 val = (m_value >> 8) & 0xff;
1084                 writel(val, edp->regs + M_VID_1);
1085                 val = (m_value >> 16) & 0xff;
1086                 writel(val, edp->regs + M_VID_2);
1087
1088                 val = n_value & 0xff;
1089                 writel(val, edp->regs + N_VID_0);
1090                 val = (n_value >> 8) & 0xff;
1091                 writel(val, edp->regs + N_VID_1);
1092                 val = (n_value >> 16) & 0xff;
1093                 writel(val, edp->regs + N_VID_2);
1094         } else  {
1095                 val = readl(edp->regs + SYS_CTL_4);
1096                 val &= ~FIX_M_VID;
1097                 writel(val, edp->regs + SYS_CTL_4);
1098
1099                 writel(0x00, edp->regs + N_VID_0);
1100                 writel(0x80, edp->regs + N_VID_1);
1101                 writel(0x00, edp->regs + N_VID_2);
1102         }
1103 }
1104
1105 void rk32_edp_set_video_timing_mode(struct rk32_edp *edp, u32 type)
1106 {
1107         u32 val;
1108
1109         if (type == VIDEO_TIMING_FROM_CAPTURE) {
1110                 val = readl(edp->regs + VIDEO_CTL_10);
1111                 val &= ~F_SEL;
1112                 writel(val, edp->regs + VIDEO_CTL_10);
1113         } else {
1114                 val = readl(edp->regs + VIDEO_CTL_10);
1115                 val |= F_SEL;
1116                 writel(val, edp->regs + VIDEO_CTL_10);
1117         }
1118 }
1119
1120 int rk32_edp_bist_cfg(struct rk32_edp *edp)
1121 {
1122         struct video_info *video_info = &edp->video_info;
1123         struct rk_screen *screen = &edp->screen;
1124         u16 x_total, y_total, x_act;
1125         u32 val;
1126         x_total = screen->mode.left_margin + screen->mode.right_margin +
1127                         screen->mode.xres + screen->mode.hsync_len;
1128         y_total = screen->mode.upper_margin + screen->mode.lower_margin +
1129                         screen->mode.yres + screen->mode.vsync_len;
1130         x_act = screen->mode.xres;
1131
1132         rk32_edp_set_video_cr_mn(edp, CALCULATED_M, 0, 0);
1133         rk32_edp_set_video_color_format(edp, video_info->color_depth,
1134                                         video_info->color_space,
1135                                         video_info->dynamic_range,
1136                                         video_info->ycbcr_coeff);
1137
1138         val = y_total & 0xff;
1139         writel(val, edp->regs + TOTAL_LINE_CFG_L);
1140         val = (y_total >> 8);
1141         writel(val, edp->regs + TOTAL_LINE_CFG_H);
1142         val = (screen->mode.yres & 0xff);
1143         writel(val, edp->regs + ATV_LINE_CFG_L);
1144         val = (screen->mode.yres >> 8);
1145         writel(val, edp->regs + ATV_LINE_CFG_H);
1146         val = screen->mode.lower_margin;
1147         writel(val, edp->regs + VF_PORCH_REG);
1148         val = screen->mode.vsync_len;
1149         writel(val, edp->regs + VSYNC_CFG_REG);
1150         val = screen->mode.upper_margin;
1151         writel(val, edp->regs + VB_PORCH_REG);
1152         val = x_total & 0xff;
1153         writel(val, edp->regs + TOTAL_PIXELL_REG);
1154         val = x_total >> 8;
1155         writel(val, edp->regs + TOTAL_PIXELH_REG);
1156         val = (x_act & 0xff);
1157         writel(val, edp->regs + ATV_PIXELL_REG);
1158         val = (x_act >> 8);
1159         writel(val, edp->regs + ATV_PIXELH_REG);
1160         val = screen->mode.right_margin & 0xff;
1161         writel(val, edp->regs + HF_PORCHL_REG);
1162         val = screen->mode.right_margin >> 8;
1163         writel(val, edp->regs + HF_PORCHH_REG);
1164         val = screen->mode.hsync_len & 0xff;
1165         writel(val, edp->regs + HSYNC_CFGL_REG);
1166         val = screen->mode.hsync_len >> 8;
1167         writel(val, edp->regs + HSYNC_CFGH_REG);
1168         val = screen->mode.left_margin & 0xff;
1169         writel(val, edp->regs + HB_PORCHL_REG);
1170         val = screen->mode.left_margin  >> 8;
1171         writel(val, edp->regs + HB_PORCHH_REG);
1172
1173         val = BIST_EN | BIST_WH_64 | BIST_TYPE_COLR_BAR;
1174         writel(val, edp->regs + VIDEO_CTL_4);
1175
1176         val = readl(edp->regs + VIDEO_CTL_10);
1177         val &= ~F_SEL;
1178         writel(val, edp->regs + VIDEO_CTL_10);
1179         return 0;
1180
1181 }
1182
1183 void rk32_edp_enable_video_master(struct rk32_edp *edp, bool enable)
1184 {
1185         /*u32 val;
1186
1187         if (enable) {
1188                 val = readl(edp->regs + SOC_GENERAL_CTL);
1189                 val &= ~VIDEO_MODE_MASK;
1190                 val |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1191                 writel(val, edp->regs + SOC_GENERAL_CTL);
1192         } else {
1193                 val = readl(edp->regs + SOC_GENERAL_CTL);
1194                 val &= ~VIDEO_MODE_MASK;
1195                 val |= VIDEO_MODE_SLAVE_MODE;
1196                 writel(val, edp->regs + SOC_GENERAL_CTL);
1197         }*/
1198 }
1199
1200 void rk32_edp_start_video(struct rk32_edp *edp)
1201 {
1202         u32 val;
1203
1204         val = readl(edp->regs + VIDEO_CTL_1);
1205         val |= VIDEO_EN;
1206         writel(val, edp->regs + VIDEO_CTL_1);
1207 }
1208
1209 int rk32_edp_is_video_stream_on(struct rk32_edp *edp)
1210 {
1211         u32 val;
1212
1213         val = readl(edp->regs + SYS_CTL_3);
1214         writel(val, edp->regs + SYS_CTL_3);
1215
1216         val = readl(edp->regs + SYS_CTL_3);
1217         if (!(val & STRM_VALID)) {
1218                 dev_dbg(edp->dev, "Input video stream is not detected.\n");
1219                 return -EINVAL;
1220         }
1221
1222         return 0;
1223 }
1224
1225 void rk32_edp_config_video_slave_mode(struct rk32_edp *edp,
1226                         struct video_info *video_info)
1227 {
1228         u32 val;
1229
1230         val = readl(edp->regs + FUNC_EN_1);
1231         val &= ~(VID_FIFO_FUNC_EN_N | VID_CAP_FUNC_EN_N);
1232         writel(val, edp->regs + FUNC_EN_1);
1233
1234         val = readl(edp->regs + VIDEO_CTL_10);
1235         val &= ~INTERACE_SCAN_CFG;
1236         val |= (video_info->interlaced << 2);
1237         writel(val, edp->regs + VIDEO_CTL_10);
1238
1239         val = readl(edp->regs + VIDEO_CTL_10);
1240         val &= ~VSYNC_POLARITY_CFG;
1241         val |= (video_info->v_sync_polarity << 1);
1242         writel(val, edp->regs + VIDEO_CTL_10);
1243
1244         val = readl(edp->regs + VIDEO_CTL_10);
1245         val &= ~HSYNC_POLARITY_CFG;
1246         val |= (video_info->h_sync_polarity << 0);
1247         writel(val, edp->regs + VIDEO_CTL_10);
1248
1249         /*val = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1250         writel(val, edp->regs + SOC_GENERAL_CTL);*/
1251 }
1252
1253 void rk32_edp_enable_scrambling(struct rk32_edp *edp)
1254 {
1255         u32 val;
1256
1257         val = readl(edp->regs + TRAINING_PTN_SET);
1258         val &= ~SCRAMBLING_DISABLE;
1259         writel(val, edp->regs + TRAINING_PTN_SET);
1260 }
1261
1262 void rk32_edp_disable_scrambling(struct rk32_edp *edp)
1263 {
1264         u32 val;
1265
1266         val = readl(edp->regs + TRAINING_PTN_SET);
1267         val |= SCRAMBLING_DISABLE;
1268         writel(val, edp->regs + TRAINING_PTN_SET);
1269 }
1270
1271 enum dp_irq_type rk32_edp_get_irq_type(struct rk32_edp *edp)
1272 {
1273         u32 val;
1274
1275         /* Parse hotplug interrupt status register */
1276         val = readl(edp->regs + COMMON_INT_STA_4);
1277         if (val & PLUG)
1278                 return DP_IRQ_TYPE_HP_CABLE_IN;
1279
1280         if (val & HPD_LOST)
1281                 return DP_IRQ_TYPE_HP_CABLE_OUT;
1282
1283         if (val & HOTPLUG_CHG)
1284                 return DP_IRQ_TYPE_HP_CHANGE;
1285
1286         return DP_IRQ_TYPE_UNKNOWN;
1287 }
1288
1289 void rk32_edp_clear_hotplug_interrupts(struct rk32_edp *edp)
1290 {
1291         u32 val;
1292
1293         val = HOTPLUG_CHG | HPD_LOST | PLUG;
1294         writel(val, edp->regs + COMMON_INT_STA_4);
1295
1296         val = INT_HPD;
1297         writel(val, edp->regs + DP_INT_STA);
1298 }