2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: Herman Chen herman.chen@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_INFO_H
18 #define __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_INFO_H
21 * Hardware id is for hardware detection
22 * Driver will read the hardware ID register first, then try to find a mactch
23 * hardware from the enum ID below.
26 VPU_DEC_ID_9190 = 0x6731,
35 * Different hardware has different feature. So we catalogue these features
38 * 1. register io feature determined by hardware type
39 * including register offset, register file size, etc
41 * 2. runtime register config feature determined by task type
42 * including irq / enable / length register, bit mask, etc
44 * 3. file handle translate feature determined by vcodec format type
45 * register translation map table
47 * These three type features composite a complete codec information structure
66 FMT_JPEGD = FMT_DEC_BASE,
86 FMT_PP_BASE = FMT_DEC_BUTT,
90 FMT_ENC_BASE = FMT_PP_BUTT,
91 FMT_JPEGE = FMT_ENC_BASE,
98 FMT_TYPE_BUTT = FMT_ENC_BUTT,
102 * struct for hardware task operation
105 enum VPU_HW_ID hw_id;
115 * register range for enc/dec/pp/dec_pp
116 * base/end of dec/pp/dec_pp specify the register range to config
126 struct vpu_task_info {
128 struct timeval start;
132 * task enable register
133 * use for enable hardware task process
138 /* register of task auto gating, alway valid */
141 /* register of task irq, alway valid */
145 * stream length register
146 * only valid for decoder task
147 * -1 for invalid (encoder)
153 * special offset scale, offset multiply by 16
155 * valid on vpu & vpu2
162 * special register for scaling list address process
170 * decoder pipeline mode register
172 * valid on vpu & vpu2
177 /* task enable bit mask for enable register */
180 /* task auto gating mask for enable register */
183 /* task pipeline mode mask for pipe register */
186 /* task inturrpt bit mask for irq register */
189 /* task ready bit mask for irq register */
192 /* task error bit mask for irq register */
195 enum FORMAT_TYPE (*get_fmt)(u32 *regs);
198 struct vpu_trans_info {
200 const char * const table;
204 enum VPU_HW_ID hw_id;
205 struct vpu_hw_info *hw_info;
206 struct vpu_task_info *task_info;
207 const struct vpu_trans_info *trans_info;
210 #define DEF_FMT_TRANS_TBL(fmt, args...) \
211 static const char trans_tbl_##fmt[] = { \
215 #define SETUP_FMT_TBL(id, fmt) \
217 .count = sizeof(trans_tbl_##fmt), \
218 .table = trans_tbl_##fmt, \
221 #define EMPTY_FMT_TBL(id) \