2 * Copyright (C) 2015 Fuzhou Rockchip Electronics Co., Ltd
3 * author: chenhengming chm@rock-chips.com
4 * Alpha Lin, alpha.lin@rock-chips.com
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #ifndef __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_RKV_H
18 #define __ARCH_ARM_MACH_ROCKCHIP_VCODEC_HW_RKV_H
20 #include "vcodec_hw_info.h"
22 /* hardware information */
23 #define REG_NUM_HEVC_DEC (68)
24 #define REG_NUM_RKV_DEC (78)
26 /* enable and gating register */
27 #define RKV_REG_EN_DEC 1
28 #define RKV_REG_DEC_GATING_BIT BIT(1)
30 /* interrupt and error status register */
31 #define HEVC_INTERRUPT_REGISTER 1
32 #define HEVC_INTERRUPT_BIT BIT(8)
33 #define HEVC_DEC_INT_RAW_BIT BIT(9)
34 #define HEVC_READY_BIT BIT(12)
35 #define HEVC_DEC_BUS_ERROR_BIT BIT(13)
36 #define HEVC_DEC_STR_ERROR_BIT BIT(14)
37 #define HEVC_DEC_TIMEOUT_BIT BIT(15)
38 #define HEVC_DEC_BUFFER_EMPTY_BIT BIT(16)
39 #define HEVC_DEC_COLMV_ERROR_BIT BIT(17)
40 #define HEVC_DEC_ERR_MASK (HEVC_DEC_BUS_ERROR_BIT \
41 |HEVC_DEC_STR_ERROR_BIT \
42 |HEVC_DEC_TIMEOUT_BIT \
43 |HEVC_DEC_BUFFER_EMPTY_BIT \
44 |HEVC_DEC_COLMV_ERROR_BIT)
46 #define RKV_DEC_INTERRUPT_REGISTER 1
47 #define RKV_DEC_INTERRUPT_BIT BIT(8)
48 #define RKV_DEC_INT_RAW_BIT BIT(9)
49 #define RKV_DEC_READY_BIT BIT(12)
50 #define RKV_DEC_BUS_ERROR_BIT BIT(13)
51 #define RKV_DEC_STR_ERROR_BIT BIT(14)
52 #define RKV_DEC_TIMEOUT_BIT BIT(15)
53 #define RKV_DEC_BUFFER_EMPTY_BIT BIT(16)
54 #define RKV_DEC_COLMV_ERROR_BIT BIT(17)
55 #define RKV_DEC_ERR_MASK (RKV_DEC_BUS_ERROR_BIT \
56 |RKV_DEC_STR_ERROR_BIT \
57 |RKV_DEC_TIMEOUT_BIT \
58 |RKV_DEC_BUFFER_EMPTY_BIT \
59 |RKV_DEC_COLMV_ERROR_BIT)
61 static const enum FORMAT_TYPE rkv_dec_fmt_tbl[] = {
68 static enum FORMAT_TYPE rkv_dec_get_fmt(u32 *regs)
70 u32 fmt_id = (regs[2] >> 20) & 0x3;
71 enum FORMAT_TYPE type = rkv_dec_fmt_tbl[fmt_id];
75 static struct vpu_task_info task_rkv[TASK_TYPE_BUTT] = {
94 .reg_en = RKV_REG_EN_DEC,
95 .reg_irq = RKV_DEC_INTERRUPT_REGISTER,
101 .gating_mask = RKV_REG_DEC_GATING_BIT,
102 .irq_mask = HEVC_INTERRUPT_BIT,
104 .ready_mask = HEVC_READY_BIT,
105 .error_mask = HEVC_DEC_ERR_MASK,
106 .get_fmt = rkv_dec_get_fmt,
141 static struct vpu_hw_info hw_rkhevc = {
149 .dec_reg_num = REG_NUM_HEVC_DEC,
150 .dec_io_size = REG_NUM_HEVC_DEC * 4,
152 /* NOTE: can not write to register 0 */
156 .end_dec = REG_NUM_HEVC_DEC,
161 static struct vpu_hw_info hw_rkvdec = {
169 .dec_reg_num = REG_NUM_RKV_DEC,
170 .dec_io_size = REG_NUM_RKV_DEC * 4,
172 /* NOTE: can not write to register 0 */
176 .end_dec = REG_NUM_RKV_DEC,
182 * file handle translate information
184 DEF_FMT_TRANS_TBL(rkv_h264d,
185 4, 6, 7, 10, 11, 12, 13, 14,
186 15, 16, 17, 18, 19, 20, 21, 22,
187 23, 24, 41, 42, 43, 48, 75
190 DEF_FMT_TRANS_TBL(rkv_h265d,
191 4, 6, 7, 10, 11, 12, 13, 14,
192 15, 16, 17, 18, 19, 20, 21, 22,
196 DEF_FMT_TRANS_TBL(rkv_vp9d,
197 4, 6, 7, 11, 12, 13, 14, 15,
201 const struct vpu_trans_info trans_rkv[FMT_TYPE_BUTT] = {
202 EMPTY_FMT_TBL(FMT_JPEGD),
203 EMPTY_FMT_TBL(FMT_H263D),
204 SETUP_FMT_TBL(FMT_H264D , rkv_h264d),
205 SETUP_FMT_TBL(FMT_H265D , rkv_h265d),
207 EMPTY_FMT_TBL(FMT_MPEG1D),
208 EMPTY_FMT_TBL(FMT_MPEG2D),
209 EMPTY_FMT_TBL(FMT_MPEG4D),
211 EMPTY_FMT_TBL(FMT_VP6D),
212 EMPTY_FMT_TBL(FMT_VP7D),
213 EMPTY_FMT_TBL(FMT_VP8D),
214 SETUP_FMT_TBL(FMT_VP9D , rkv_vp9d),
216 EMPTY_FMT_TBL(FMT_PP),
218 EMPTY_FMT_TBL(FMT_VC1D),
219 EMPTY_FMT_TBL(FMT_AVSD),
221 EMPTY_FMT_TBL(FMT_JPEGE),
222 EMPTY_FMT_TBL(FMT_H264E),
223 EMPTY_FMT_TBL(FMT_VP8E),