1 /* linux/drivers/video/s3c-fb.c
3 * Copyright 2008 Openmoko Inc.
4 * Copyright 2008-2010 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
8 * Samsung SoC Framebuffer driver
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software FoundatIon.
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/platform_device.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/slab.h>
20 #include <linux/init.h>
21 #include <linux/clk.h>
24 #include <linux/uaccess.h>
25 #include <linux/interrupt.h>
26 #include <linux/pm_runtime.h>
29 #include <plat/regs-fb-v4.h>
32 /* This driver will export a number of framebuffer interfaces depending
33 * on the configuration passed in via the platform data. Each fb instance
34 * maps to a hardware window. Currently there is no support for runtime
35 * setting of the alpha-blending functions that each window has, so only
36 * window 0 is actually useful.
38 * Window 0 is treated specially, it is used for the basis of the LCD
39 * output timings and as the control for the output power-down state.
42 /* note, the previous use of <mach/regs-fb.h> to get platform specific data
43 * has been replaced by using the platform device name to pick the correct
44 * configuration data for the system.
47 #ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
49 #define writel(v, r) do { \
50 printk(KERN_DEBUG "%s: %08x => %p\n", __func__, (unsigned int)v, r); \
51 __raw_writel(v, r); } while (0)
52 #endif /* FB_S3C_DEBUG_REGWRITE */
55 #define S3C_FB_VSYNC_IRQ_EN 0
57 #define VSYNC_TIMEOUT_MSEC 50
61 #define VALID_BPP(x) (1 << ((x) - 1))
63 #define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
64 #define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
65 #define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
66 #define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
67 #define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
70 * struct s3c_fb_variant - fb variant information
71 * @is_2443: Set if S3C2443/S3C2416 style hardware.
72 * @nr_windows: The number of windows.
73 * @vidtcon: The base for the VIDTCONx registers
74 * @wincon: The base for the WINxCON registers.
75 * @winmap: The base for the WINxMAP registers.
76 * @keycon: The abse for the WxKEYCON registers.
77 * @buf_start: Offset of buffer start registers.
78 * @buf_size: Offset of buffer size registers.
79 * @buf_end: Offset of buffer end registers.
80 * @osd: The base for the OSD registers.
81 * @palette: Address of palette memory, or 0 if none.
82 * @has_prtcon: Set if has PRTCON register.
83 * @has_shadowcon: Set if has SHADOWCON register.
84 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
86 struct s3c_fb_variant {
87 unsigned int is_2443:1;
88 unsigned short nr_windows;
89 unsigned short vidtcon;
90 unsigned short wincon;
91 unsigned short winmap;
92 unsigned short keycon;
93 unsigned short buf_start;
94 unsigned short buf_end;
95 unsigned short buf_size;
97 unsigned short osd_stride;
98 unsigned short palette[S3C_FB_MAX_WIN];
100 unsigned int has_prtcon:1;
101 unsigned int has_shadowcon:1;
102 unsigned int has_clksel:1;
106 * struct s3c_fb_win_variant
107 * @has_osd_c: Set if has OSD C register.
108 * @has_osd_d: Set if has OSD D register.
109 * @has_osd_alpha: Set if can change alpha transparency for a window.
110 * @palette_sz: Size of palette in entries.
111 * @palette_16bpp: Set if palette is 16bits wide.
112 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
113 * register is located at the given offset from OSD_BASE.
114 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
116 * valid_bpp bit x is set if (x+1)BPP is supported.
118 struct s3c_fb_win_variant {
119 unsigned int has_osd_c:1;
120 unsigned int has_osd_d:1;
121 unsigned int has_osd_alpha:1;
122 unsigned int palette_16bpp:1;
123 unsigned short osd_size_off;
124 unsigned short palette_sz;
129 * struct s3c_fb_driverdata - per-device type driver data for init time.
130 * @variant: The variant information for this driver.
131 * @win: The window information for each window.
133 struct s3c_fb_driverdata {
134 struct s3c_fb_variant variant;
135 struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
139 * struct s3c_fb_palette - palette information
141 * @g: Green bitfield.
143 * @a: Alpha bitfield.
145 struct s3c_fb_palette {
146 struct fb_bitfield r;
147 struct fb_bitfield g;
148 struct fb_bitfield b;
149 struct fb_bitfield a;
153 * struct s3c_fb_win - per window private data for each framebuffer.
154 * @windata: The platform data supplied for the window configuration.
155 * @parent: The hardware that this window is part of.
156 * @fbinfo: Pointer pack to the framebuffer info for this window.
157 * @varint: The variant information for this window.
158 * @palette_buffer: Buffer/cache to hold palette entries.
159 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
160 * @index: The window number of this window.
161 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
164 struct s3c_fb_pd_win *windata;
165 struct s3c_fb *parent;
166 struct fb_info *fbinfo;
167 struct s3c_fb_palette palette;
168 struct s3c_fb_win_variant variant;
171 u32 pseudo_palette[16];
176 * struct s3c_fb_vsync - vsync information
177 * @wait: a queue for processes waiting for vsync
178 * @count: vsync interrupt count
180 struct s3c_fb_vsync {
181 wait_queue_head_t wait;
186 * struct s3c_fb - overall hardware state of the hardware
187 * @slock: The spinlock protection for this data sturcture.
188 * @dev: The device that we bound to, for printing, etc.
189 * @regs_res: The resource we claimed for the IO registers.
190 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
191 * @lcd_clk: The clk (sclk) feeding pixclk.
192 * @regs: The mapped hardware registers.
193 * @variant: Variant information for this hardware.
194 * @enabled: A bitmask of enabled hardware windows.
195 * @output_on: Flag if the physical output is enabled.
196 * @pdata: The platform configuration data passed with the device.
197 * @windows: The hardware windows that have been claimed.
198 * @irq_no: IRQ line number
199 * @irq_flags: irq flags
200 * @vsync_info: VSYNC-related information (count, queues...)
205 struct resource *regs_res;
209 struct s3c_fb_variant variant;
211 unsigned char enabled;
214 struct s3c_fb_platdata *pdata;
215 struct s3c_fb_win *windows[S3C_FB_MAX_WIN];
218 unsigned long irq_flags;
219 struct s3c_fb_vsync vsync_info;
223 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
224 * @win: The device window.
225 * @bpp: The bit depth.
227 static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
229 return win->variant.valid_bpp & VALID_BPP(bpp);
233 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
234 * @var: The screen information to verify.
235 * @info: The framebuffer device.
237 * Framebuffer layer call to verify the given information and allow us to
238 * update various information depending on the hardware capabilities.
240 static int s3c_fb_check_var(struct fb_var_screeninfo *var,
241 struct fb_info *info)
243 struct s3c_fb_win *win = info->par;
244 struct s3c_fb *sfb = win->parent;
246 dev_dbg(sfb->dev, "checking parameters\n");
248 var->xres_virtual = max(var->xres_virtual, var->xres);
249 var->yres_virtual = max(var->yres_virtual, var->yres);
251 if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
252 dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
253 win->index, var->bits_per_pixel);
257 /* always ensure these are zero, for drop through cases below */
258 var->transp.offset = 0;
259 var->transp.length = 0;
261 switch (var->bits_per_pixel) {
266 if (sfb->variant.palette[win->index] != 0) {
267 /* non palletised, A:1,R:2,G:3,B:2 mode */
269 var->green.offset = 2;
270 var->blue.offset = 0;
272 var->green.length = 3;
273 var->blue.length = 2;
274 var->transp.offset = 7;
275 var->transp.length = 1;
278 var->red.length = var->bits_per_pixel;
279 var->green = var->red;
280 var->blue = var->red;
285 /* 666 with one bit alpha/transparency */
286 var->transp.offset = 18;
287 var->transp.length = 1;
289 var->bits_per_pixel = 32;
292 var->red.offset = 12;
293 var->green.offset = 6;
294 var->blue.offset = 0;
296 var->green.length = 6;
297 var->blue.length = 6;
301 /* 16 bpp, 565 format */
302 var->red.offset = 11;
303 var->green.offset = 5;
304 var->blue.offset = 0;
306 var->green.length = 6;
307 var->blue.length = 5;
313 var->transp.length = var->bits_per_pixel - 24;
314 var->transp.offset = 24;
317 /* our 24bpp is unpacked, so 32bpp */
318 var->bits_per_pixel = 32;
319 var->red.offset = 16;
321 var->green.offset = 8;
322 var->green.length = 8;
323 var->blue.offset = 0;
324 var->blue.length = 8;
328 dev_err(sfb->dev, "invalid bpp\n");
331 dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
336 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
337 * @sfb: The hardware state.
338 * @pixclock: The pixel clock wanted, in picoseconds.
340 * Given the specified pixel clock, work out the necessary divider to get
341 * close to the output frequency.
343 static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
346 unsigned long long tmp;
349 if (sfb->variant.has_clksel)
350 clk = clk_get_rate(sfb->bus_clk);
352 clk = clk_get_rate(sfb->lcd_clk);
354 tmp = (unsigned long long)clk;
357 do_div(tmp, 1000000000UL);
358 result = (unsigned int)tmp / 1000;
360 dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
361 pixclk, clk, result, clk / result);
367 * s3c_fb_align_word() - align pixel count to word boundary
368 * @bpp: The number of bits per pixel
369 * @pix: The value to be aligned.
371 * Align the given pixel count so that it will start on an 32bit word
374 static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
381 pix_per_word = (8 * 32) / bpp;
382 return ALIGN(pix, pix_per_word);
386 * vidosd_set_size() - set OSD size for a window
388 * @win: the window to set OSD size for
389 * @size: OSD size register value
391 static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
393 struct s3c_fb *sfb = win->parent;
395 /* OSD can be set up if osd_size_off != 0 for this window */
396 if (win->variant.osd_size_off)
397 writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
398 + win->variant.osd_size_off);
402 * vidosd_set_alpha() - set alpha transparency for a window
404 * @win: the window to set OSD size for
405 * @alpha: alpha register value
407 static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
409 struct s3c_fb *sfb = win->parent;
411 if (win->variant.has_osd_alpha)
412 writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
416 * shadow_protect_win() - disable updating values from shadow registers at vsync
418 * @win: window to protect registers for
419 * @protect: 1 to protect (disable updates)
421 static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
423 struct s3c_fb *sfb = win->parent;
427 if (sfb->variant.has_prtcon) {
428 writel(PRTCON_PROTECT, sfb->regs + PRTCON);
429 } else if (sfb->variant.has_shadowcon) {
430 reg = readl(sfb->regs + SHADOWCON);
431 writel(reg | SHADOWCON_WINx_PROTECT(win->index),
432 sfb->regs + SHADOWCON);
435 if (sfb->variant.has_prtcon) {
436 writel(0, sfb->regs + PRTCON);
437 } else if (sfb->variant.has_shadowcon) {
438 reg = readl(sfb->regs + SHADOWCON);
439 writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
440 sfb->regs + SHADOWCON);
446 * s3c_fb_enable() - Set the state of the main LCD output
447 * @sfb: The main framebuffer state.
448 * @enable: The state to set.
450 static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
452 u32 vidcon0 = readl(sfb->regs + VIDCON0);
454 if (enable && !sfb->output_on)
455 pm_runtime_get_sync(sfb->dev);
458 vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
460 /* see the note in the framebuffer datasheet about
461 * why you cannot take both of these bits down at the
464 if (vidcon0 & VIDCON0_ENVID) {
465 vidcon0 |= VIDCON0_ENVID;
466 vidcon0 &= ~VIDCON0_ENVID_F;
470 writel(vidcon0, sfb->regs + VIDCON0);
472 if (!enable && sfb->output_on)
473 pm_runtime_put_sync(sfb->dev);
475 sfb->output_on = enable;
479 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
480 * @info: The framebuffer to change.
482 * Framebuffer layer request to set a new mode for the specified framebuffer
484 static int s3c_fb_set_par(struct fb_info *info)
486 struct fb_var_screeninfo *var = &info->var;
487 struct s3c_fb_win *win = info->par;
488 struct s3c_fb *sfb = win->parent;
489 void __iomem *regs = sfb->regs;
490 void __iomem *buf = regs;
491 int win_no = win->index;
497 dev_dbg(sfb->dev, "setting framebuffer parameters\n");
499 pm_runtime_get_sync(sfb->dev);
501 shadow_protect_win(win, 1);
503 switch (var->bits_per_pixel) {
508 info->fix.visual = FB_VISUAL_TRUECOLOR;
511 if (win->variant.palette_sz >= 256)
512 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
514 info->fix.visual = FB_VISUAL_TRUECOLOR;
517 info->fix.visual = FB_VISUAL_MONO01;
520 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
524 info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
526 info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
527 info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
529 /* disable the window whilst we update it */
530 writel(0, regs + WINCON(win_no));
532 /* use platform specified window as the basis for the lcd timings */
534 if (win_no == sfb->pdata->default_win) {
535 clkdiv = s3c_fb_calc_pixclk(sfb, var->pixclock);
537 data = sfb->pdata->vidcon0;
538 data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
541 data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
543 data &= ~VIDCON0_CLKDIR; /* 1:1 clock */
545 /* write the timing data to the panel */
547 if (sfb->variant.is_2443)
550 writel(data, regs + VIDCON0);
552 s3c_fb_enable(sfb, 1);
554 data = VIDTCON0_VBPD(var->upper_margin - 1) |
555 VIDTCON0_VFPD(var->lower_margin - 1) |
556 VIDTCON0_VSPW(var->vsync_len - 1);
558 writel(data, regs + sfb->variant.vidtcon);
560 data = VIDTCON1_HBPD(var->left_margin - 1) |
561 VIDTCON1_HFPD(var->right_margin - 1) |
562 VIDTCON1_HSPW(var->hsync_len - 1);
565 writel(data, regs + sfb->variant.vidtcon + 4);
567 data = VIDTCON2_LINEVAL(var->yres - 1) |
568 VIDTCON2_HOZVAL(var->xres - 1);
569 writel(data, regs + sfb->variant.vidtcon + 8);
572 /* write the buffer address */
574 /* start and end registers stride is 8 */
575 buf = regs + win_no * 8;
577 writel(info->fix.smem_start, buf + sfb->variant.buf_start);
579 data = info->fix.smem_start + info->fix.line_length * var->yres;
580 writel(data, buf + sfb->variant.buf_end);
582 pagewidth = (var->xres * var->bits_per_pixel) >> 3;
583 data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
584 VIDW_BUF_SIZE_PAGEWIDTH(pagewidth);
585 writel(data, regs + sfb->variant.buf_size + (win_no * 4));
587 /* write 'OSD' registers to control position of framebuffer */
589 data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0);
590 writel(data, regs + VIDOSD_A(win_no, sfb->variant));
592 data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
594 VIDOSDxB_BOTRIGHT_Y(var->yres - 1);
596 writel(data, regs + VIDOSD_B(win_no, sfb->variant));
598 data = var->xres * var->yres;
600 alpha = VIDISD14C_ALPHA1_R(0xf) |
601 VIDISD14C_ALPHA1_G(0xf) |
602 VIDISD14C_ALPHA1_B(0xf);
604 vidosd_set_alpha(win, alpha);
605 vidosd_set_size(win, data);
607 /* Enable DMA channel for this window */
608 if (sfb->variant.has_shadowcon) {
609 data = readl(sfb->regs + SHADOWCON);
610 data |= SHADOWCON_CHx_ENABLE(win_no);
611 writel(data, sfb->regs + SHADOWCON);
614 data = WINCONx_ENWIN;
615 sfb->enabled |= (1 << win->index);
617 /* note, since we have to round up the bits-per-pixel, we end up
618 * relying on the bitfield information for r/g/b/a to work out
619 * exactly which mode of operation is intended. */
621 switch (var->bits_per_pixel) {
623 data |= WINCON0_BPPMODE_1BPP;
624 data |= WINCONx_BITSWP;
625 data |= WINCONx_BURSTLEN_4WORD;
628 data |= WINCON0_BPPMODE_2BPP;
629 data |= WINCONx_BITSWP;
630 data |= WINCONx_BURSTLEN_8WORD;
633 data |= WINCON0_BPPMODE_4BPP;
634 data |= WINCONx_BITSWP;
635 data |= WINCONx_BURSTLEN_8WORD;
638 if (var->transp.length != 0)
639 data |= WINCON1_BPPMODE_8BPP_1232;
641 data |= WINCON0_BPPMODE_8BPP_PALETTE;
642 data |= WINCONx_BURSTLEN_8WORD;
643 data |= WINCONx_BYTSWP;
646 if (var->transp.length != 0)
647 data |= WINCON1_BPPMODE_16BPP_A1555;
649 data |= WINCON0_BPPMODE_16BPP_565;
650 data |= WINCONx_HAWSWP;
651 data |= WINCONx_BURSTLEN_16WORD;
655 if (var->red.length == 6) {
656 if (var->transp.length != 0)
657 data |= WINCON1_BPPMODE_19BPP_A1666;
659 data |= WINCON1_BPPMODE_18BPP_666;
660 } else if (var->transp.length == 1)
661 data |= WINCON1_BPPMODE_25BPP_A1888
663 else if ((var->transp.length == 4) ||
664 (var->transp.length == 8))
665 data |= WINCON1_BPPMODE_28BPP_A4888
666 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
668 data |= WINCON0_BPPMODE_24BPP_888;
670 data |= WINCONx_WSWP;
671 data |= WINCONx_BURSTLEN_16WORD;
675 /* Enable the colour keying for the window below this one */
677 u32 keycon0_data = 0, keycon1_data = 0;
678 void __iomem *keycon = regs + sfb->variant.keycon;
680 keycon0_data = ~(WxKEYCON0_KEYBL_EN |
682 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
684 keycon1_data = WxKEYCON1_COLVAL(0xffffff);
686 keycon += (win_no - 1) * 8;
688 writel(keycon0_data, keycon + WKEYCON0);
689 writel(keycon1_data, keycon + WKEYCON1);
692 writel(data, regs + sfb->variant.wincon + (win_no * 4));
693 writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
695 shadow_protect_win(win, 0);
697 pm_runtime_put_sync(sfb->dev);
703 * s3c_fb_update_palette() - set or schedule a palette update.
704 * @sfb: The hardware information.
705 * @win: The window being updated.
706 * @reg: The palette index being changed.
707 * @value: The computed palette value.
709 * Change the value of a palette register, either by directly writing to
710 * the palette (this requires the palette RAM to be disconnected from the
711 * hardware whilst this is in progress) or schedule the update for later.
713 * At the moment, since we have no VSYNC interrupt support, we simply set
714 * the palette entry directly.
716 static void s3c_fb_update_palette(struct s3c_fb *sfb,
717 struct s3c_fb_win *win,
721 void __iomem *palreg;
724 palreg = sfb->regs + sfb->variant.palette[win->index];
726 dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
727 __func__, win->index, reg, palreg, value);
729 win->palette_buffer[reg] = value;
731 palcon = readl(sfb->regs + WPALCON);
732 writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
734 if (win->variant.palette_16bpp)
735 writew(value, palreg + (reg * 2));
737 writel(value, palreg + (reg * 4));
739 writel(palcon, sfb->regs + WPALCON);
742 static inline unsigned int chan_to_field(unsigned int chan,
743 struct fb_bitfield *bf)
746 chan >>= 16 - bf->length;
747 return chan << bf->offset;
751 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
752 * @regno: The palette index to change.
753 * @red: The red field for the palette data.
754 * @green: The green field for the palette data.
755 * @blue: The blue field for the palette data.
756 * @trans: The transparency (alpha) field for the palette data.
757 * @info: The framebuffer being changed.
759 static int s3c_fb_setcolreg(unsigned regno,
760 unsigned red, unsigned green, unsigned blue,
761 unsigned transp, struct fb_info *info)
763 struct s3c_fb_win *win = info->par;
764 struct s3c_fb *sfb = win->parent;
767 dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
768 __func__, win->index, regno, red, green, blue);
770 pm_runtime_get_sync(sfb->dev);
772 switch (info->fix.visual) {
773 case FB_VISUAL_TRUECOLOR:
774 /* true-colour, use pseudo-palette */
777 u32 *pal = info->pseudo_palette;
779 val = chan_to_field(red, &info->var.red);
780 val |= chan_to_field(green, &info->var.green);
781 val |= chan_to_field(blue, &info->var.blue);
787 case FB_VISUAL_PSEUDOCOLOR:
788 if (regno < win->variant.palette_sz) {
789 val = chan_to_field(red, &win->palette.r);
790 val |= chan_to_field(green, &win->palette.g);
791 val |= chan_to_field(blue, &win->palette.b);
793 s3c_fb_update_palette(sfb, win, regno, val);
799 pm_runtime_put_sync(sfb->dev);
800 return 1; /* unknown type */
803 pm_runtime_put_sync(sfb->dev);
808 * s3c_fb_blank() - blank or unblank the given window
809 * @blank_mode: The blank state from FB_BLANK_*
810 * @info: The framebuffer to blank.
812 * Framebuffer layer request to change the power state.
814 static int s3c_fb_blank(int blank_mode, struct fb_info *info)
816 struct s3c_fb_win *win = info->par;
817 struct s3c_fb *sfb = win->parent;
818 unsigned int index = win->index;
821 dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
823 pm_runtime_get_sync(sfb->dev);
825 wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
827 switch (blank_mode) {
828 case FB_BLANK_POWERDOWN:
829 wincon &= ~WINCONx_ENWIN;
830 sfb->enabled &= ~(1 << index);
831 /* fall through to FB_BLANK_NORMAL */
833 case FB_BLANK_NORMAL:
834 /* disable the DMA and display 0x0 (black) */
835 shadow_protect_win(win, 1);
836 writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
837 sfb->regs + sfb->variant.winmap + (index * 4));
838 shadow_protect_win(win, 0);
841 case FB_BLANK_UNBLANK:
842 shadow_protect_win(win, 1);
843 writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
844 shadow_protect_win(win, 0);
845 wincon |= WINCONx_ENWIN;
846 sfb->enabled |= (1 << index);
849 case FB_BLANK_VSYNC_SUSPEND:
850 case FB_BLANK_HSYNC_SUSPEND:
852 pm_runtime_put_sync(sfb->dev);
856 shadow_protect_win(win, 1);
857 writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
858 shadow_protect_win(win, 0);
860 /* Check the enabled state to see if we need to be running the
861 * main LCD interface, as if there are no active windows then
862 * it is highly likely that we also do not need to output
866 /* We could do something like the following code, but the current
867 * system of using framebuffer events means that we cannot make
868 * the distinction between just window 0 being inactive and all
869 * the windows being down.
871 * s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
874 /* we're stuck with this until we can do something about overriding
875 * the power control using the blanking event for a single fb.
877 if (index == sfb->pdata->default_win) {
878 shadow_protect_win(win, 1);
879 s3c_fb_enable(sfb, blank_mode != FB_BLANK_POWERDOWN ? 1 : 0);
880 shadow_protect_win(win, 0);
883 pm_runtime_put_sync(sfb->dev);
889 * s3c_fb_pan_display() - Pan the display.
891 * Note that the offsets can be written to the device at any time, as their
892 * values are latched at each vsync automatically. This also means that only
893 * the last call to this function will have any effect on next vsync, but
894 * there is no need to sleep waiting for it to prevent tearing.
896 * @var: The screen information to verify.
897 * @info: The framebuffer device.
899 static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
900 struct fb_info *info)
902 struct s3c_fb_win *win = info->par;
903 struct s3c_fb *sfb = win->parent;
904 void __iomem *buf = sfb->regs + win->index * 8;
905 unsigned int start_boff, end_boff;
907 pm_runtime_get_sync(sfb->dev);
909 /* Offset in bytes to the start of the displayed area */
910 start_boff = var->yoffset * info->fix.line_length;
911 /* X offset depends on the current bpp */
912 if (info->var.bits_per_pixel >= 8) {
913 start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
915 switch (info->var.bits_per_pixel) {
917 start_boff += var->xoffset >> 1;
920 start_boff += var->xoffset >> 2;
923 start_boff += var->xoffset >> 3;
926 dev_err(sfb->dev, "invalid bpp\n");
927 pm_runtime_put_sync(sfb->dev);
931 /* Offset in bytes to the end of the displayed area */
932 end_boff = start_boff + info->var.yres * info->fix.line_length;
934 /* Temporarily turn off per-vsync update from shadow registers until
935 * both start and end addresses are updated to prevent corruption */
936 shadow_protect_win(win, 1);
938 writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
939 writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
941 shadow_protect_win(win, 0);
943 pm_runtime_put_sync(sfb->dev);
948 * s3c_fb_enable_irq() - enable framebuffer interrupts
949 * @sfb: main hardware state
951 static void s3c_fb_enable_irq(struct s3c_fb *sfb)
953 void __iomem *regs = sfb->regs;
956 if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
957 /* IRQ disabled, enable it */
958 irq_ctrl_reg = readl(regs + VIDINTCON0);
960 irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
961 irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
963 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
964 irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
965 irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
966 irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
968 writel(irq_ctrl_reg, regs + VIDINTCON0);
973 * s3c_fb_disable_irq() - disable framebuffer interrupts
974 * @sfb: main hardware state
976 static void s3c_fb_disable_irq(struct s3c_fb *sfb)
978 void __iomem *regs = sfb->regs;
981 if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
982 /* IRQ enabled, disable it */
983 irq_ctrl_reg = readl(regs + VIDINTCON0);
985 irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
986 irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
988 writel(irq_ctrl_reg, regs + VIDINTCON0);
992 static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
994 struct s3c_fb *sfb = dev_id;
995 void __iomem *regs = sfb->regs;
998 spin_lock(&sfb->slock);
1000 irq_sts_reg = readl(regs + VIDINTCON1);
1002 if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
1004 /* VSYNC interrupt, accept it */
1005 writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
1007 sfb->vsync_info.count++;
1008 wake_up_interruptible(&sfb->vsync_info.wait);
1011 /* We only support waiting for VSYNC for now, so it's safe
1012 * to always disable irqs here.
1014 s3c_fb_disable_irq(sfb);
1016 spin_unlock(&sfb->slock);
1021 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
1022 * @sfb: main hardware state
1023 * @crtc: head index.
1025 static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
1027 unsigned long count;
1033 pm_runtime_get_sync(sfb->dev);
1035 count = sfb->vsync_info.count;
1036 s3c_fb_enable_irq(sfb);
1037 ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1038 count != sfb->vsync_info.count,
1039 msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1041 pm_runtime_put_sync(sfb->dev);
1049 static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1052 struct s3c_fb_win *win = info->par;
1053 struct s3c_fb *sfb = win->parent;
1058 case FBIO_WAITFORVSYNC:
1059 if (get_user(crtc, (u32 __user *)arg)) {
1064 ret = s3c_fb_wait_for_vsync(sfb, crtc);
1073 static int s3c_fb_open(struct fb_info *info, int user)
1075 struct s3c_fb_win *win = info->par;
1076 struct s3c_fb *sfb = win->parent;
1078 pm_runtime_get_sync(sfb->dev);
1083 static int s3c_fb_release(struct fb_info *info, int user)
1085 struct s3c_fb_win *win = info->par;
1086 struct s3c_fb *sfb = win->parent;
1088 pm_runtime_put_sync(sfb->dev);
1093 static struct fb_ops s3c_fb_ops = {
1094 .owner = THIS_MODULE,
1095 .fb_open = s3c_fb_open,
1096 .fb_release = s3c_fb_release,
1097 .fb_check_var = s3c_fb_check_var,
1098 .fb_set_par = s3c_fb_set_par,
1099 .fb_blank = s3c_fb_blank,
1100 .fb_setcolreg = s3c_fb_setcolreg,
1101 .fb_fillrect = cfb_fillrect,
1102 .fb_copyarea = cfb_copyarea,
1103 .fb_imageblit = cfb_imageblit,
1104 .fb_pan_display = s3c_fb_pan_display,
1105 .fb_ioctl = s3c_fb_ioctl,
1109 * s3c_fb_missing_pixclock() - calculates pixel clock
1110 * @mode: The video mode to change.
1112 * Calculate the pixel clock when none has been given through platform data.
1114 static void __devinit s3c_fb_missing_pixclock(struct fb_videomode *mode)
1116 u64 pixclk = 1000000000000ULL;
1119 div = mode->left_margin + mode->hsync_len + mode->right_margin +
1121 div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1123 div *= mode->refresh ? : 60;
1125 do_div(pixclk, div);
1127 mode->pixclock = pixclk;
1131 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1132 * @sfb: The base resources for the hardware.
1133 * @win: The window to initialise memory for.
1135 * Allocate memory for the given framebuffer.
1137 static int __devinit s3c_fb_alloc_memory(struct s3c_fb *sfb,
1138 struct s3c_fb_win *win)
1140 struct s3c_fb_pd_win *windata = win->windata;
1141 unsigned int real_size, virt_size, size;
1142 struct fb_info *fbi = win->fbinfo;
1145 dev_dbg(sfb->dev, "allocating memory for display\n");
1147 real_size = windata->win_mode.xres * windata->win_mode.yres;
1148 virt_size = windata->virtual_x * windata->virtual_y;
1150 dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1151 real_size, windata->win_mode.xres, windata->win_mode.yres,
1152 virt_size, windata->virtual_x, windata->virtual_y);
1154 size = (real_size > virt_size) ? real_size : virt_size;
1155 size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1158 fbi->fix.smem_len = size;
1159 size = PAGE_ALIGN(size);
1161 dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1163 fbi->screen_base = dma_alloc_writecombine(sfb->dev, size,
1164 &map_dma, GFP_KERNEL);
1165 if (!fbi->screen_base)
1168 dev_dbg(sfb->dev, "mapped %x to %p\n",
1169 (unsigned int)map_dma, fbi->screen_base);
1171 memset(fbi->screen_base, 0x0, size);
1172 fbi->fix.smem_start = map_dma;
1178 * s3c_fb_free_memory() - free the display memory for the given window
1179 * @sfb: The base resources for the hardware.
1180 * @win: The window to free the display memory for.
1182 * Free the display memory allocated by s3c_fb_alloc_memory().
1184 static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1186 struct fb_info *fbi = win->fbinfo;
1188 if (fbi->screen_base)
1189 dma_free_writecombine(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1190 fbi->screen_base, fbi->fix.smem_start);
1194 * s3c_fb_release_win() - release resources for a framebuffer window.
1195 * @win: The window to cleanup the resources for.
1197 * Release the resources that where claimed for the hardware window,
1198 * such as the framebuffer instance and any memory claimed for it.
1200 static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1205 if (sfb->variant.has_shadowcon) {
1206 data = readl(sfb->regs + SHADOWCON);
1207 data &= ~SHADOWCON_CHx_ENABLE(win->index);
1208 data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1209 writel(data, sfb->regs + SHADOWCON);
1211 unregister_framebuffer(win->fbinfo);
1212 if (win->fbinfo->cmap.len)
1213 fb_dealloc_cmap(&win->fbinfo->cmap);
1214 s3c_fb_free_memory(sfb, win);
1215 framebuffer_release(win->fbinfo);
1220 * s3c_fb_probe_win() - register an hardware window
1221 * @sfb: The base resources for the hardware
1222 * @variant: The variant information for this window.
1223 * @res: Pointer to where to place the resultant window.
1225 * Allocate and do the basic initialisation for one of the hardware's graphics
1228 static int __devinit s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1229 struct s3c_fb_win_variant *variant,
1230 struct s3c_fb_win **res)
1232 struct fb_var_screeninfo *var;
1233 struct fb_videomode *initmode;
1234 struct s3c_fb_pd_win *windata;
1235 struct s3c_fb_win *win;
1236 struct fb_info *fbinfo;
1240 dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1242 init_waitqueue_head(&sfb->vsync_info.wait);
1244 palette_size = variant->palette_sz * 4;
1246 fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1247 palette_size * sizeof(u32), sfb->dev);
1249 dev_err(sfb->dev, "failed to allocate framebuffer\n");
1253 windata = sfb->pdata->win[win_no];
1254 initmode = &windata->win_mode;
1256 WARN_ON(windata->max_bpp == 0);
1257 WARN_ON(windata->win_mode.xres == 0);
1258 WARN_ON(windata->win_mode.yres == 0);
1263 win->variant = *variant;
1264 win->fbinfo = fbinfo;
1266 win->windata = windata;
1267 win->index = win_no;
1268 win->palette_buffer = (u32 *)(win + 1);
1270 ret = s3c_fb_alloc_memory(sfb, win);
1272 dev_err(sfb->dev, "failed to allocate display memory\n");
1276 /* setup the r/b/g positions for the window's palette */
1277 if (win->variant.palette_16bpp) {
1278 /* Set RGB 5:6:5 as default */
1279 win->palette.r.offset = 11;
1280 win->palette.r.length = 5;
1281 win->palette.g.offset = 5;
1282 win->palette.g.length = 6;
1283 win->palette.b.offset = 0;
1284 win->palette.b.length = 5;
1287 /* Set 8bpp or 8bpp and 1bit alpha */
1288 win->palette.r.offset = 16;
1289 win->palette.r.length = 8;
1290 win->palette.g.offset = 8;
1291 win->palette.g.length = 8;
1292 win->palette.b.offset = 0;
1293 win->palette.b.length = 8;
1296 /* setup the initial video mode from the window */
1297 fb_videomode_to_var(&fbinfo->var, initmode);
1299 fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
1300 fbinfo->fix.accel = FB_ACCEL_NONE;
1301 fbinfo->var.activate = FB_ACTIVATE_NOW;
1302 fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
1303 fbinfo->var.bits_per_pixel = windata->default_bpp;
1304 fbinfo->fbops = &s3c_fb_ops;
1305 fbinfo->flags = FBINFO_FLAG_DEFAULT;
1306 fbinfo->pseudo_palette = &win->pseudo_palette;
1308 /* prepare to actually start the framebuffer */
1310 ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1312 dev_err(sfb->dev, "check_var failed on initial video params\n");
1316 /* create initial colour map */
1318 ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1320 fb_set_cmap(&fbinfo->cmap, fbinfo);
1322 dev_err(sfb->dev, "failed to allocate fb cmap\n");
1324 s3c_fb_set_par(fbinfo);
1326 dev_dbg(sfb->dev, "about to register framebuffer\n");
1328 /* run the check_var and set_par on our configuration. */
1330 ret = register_framebuffer(fbinfo);
1332 dev_err(sfb->dev, "failed to register framebuffer\n");
1336 dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1342 * s3c_fb_clear_win() - clear hardware window registers.
1343 * @sfb: The base resources for the hardware.
1344 * @win: The window to process.
1346 * Reset the specific window registers to a known state.
1348 static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1350 void __iomem *regs = sfb->regs;
1353 writel(0, regs + sfb->variant.wincon + (win * 4));
1354 writel(0, regs + VIDOSD_A(win, sfb->variant));
1355 writel(0, regs + VIDOSD_B(win, sfb->variant));
1356 writel(0, regs + VIDOSD_C(win, sfb->variant));
1357 reg = readl(regs + SHADOWCON);
1358 writel(reg & ~SHADOWCON_WINx_PROTECT(win), regs + SHADOWCON);
1361 static int __devinit s3c_fb_probe(struct platform_device *pdev)
1363 const struct platform_device_id *platid;
1364 struct s3c_fb_driverdata *fbdrv;
1365 struct device *dev = &pdev->dev;
1366 struct s3c_fb_platdata *pd;
1368 struct resource *res;
1372 platid = platform_get_device_id(pdev);
1373 fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1375 if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1376 dev_err(dev, "too many windows, cannot attach\n");
1380 pd = pdev->dev.platform_data;
1382 dev_err(dev, "no platform data specified\n");
1386 sfb = kzalloc(sizeof(struct s3c_fb), GFP_KERNEL);
1388 dev_err(dev, "no memory for framebuffers\n");
1392 dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1396 sfb->variant = fbdrv->variant;
1398 spin_lock_init(&sfb->slock);
1400 sfb->bus_clk = clk_get(dev, "lcd");
1401 if (IS_ERR(sfb->bus_clk)) {
1402 dev_err(dev, "failed to get bus clock\n");
1403 ret = PTR_ERR(sfb->bus_clk);
1407 clk_enable(sfb->bus_clk);
1409 if (!sfb->variant.has_clksel) {
1410 sfb->lcd_clk = clk_get(dev, "sclk_fimd");
1411 if (IS_ERR(sfb->lcd_clk)) {
1412 dev_err(dev, "failed to get lcd clock\n");
1413 ret = PTR_ERR(sfb->lcd_clk);
1417 clk_enable(sfb->lcd_clk);
1420 pm_runtime_enable(sfb->dev);
1422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1424 dev_err(dev, "failed to find registers\n");
1429 sfb->regs_res = request_mem_region(res->start, resource_size(res),
1431 if (!sfb->regs_res) {
1432 dev_err(dev, "failed to claim register region\n");
1437 sfb->regs = ioremap(res->start, resource_size(res));
1439 dev_err(dev, "failed to map registers\n");
1441 goto err_req_region;
1444 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1446 dev_err(dev, "failed to acquire irq resource\n");
1450 sfb->irq_no = res->start;
1451 ret = request_irq(sfb->irq_no, s3c_fb_irq,
1454 dev_err(dev, "irq request failed\n");
1458 dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1460 platform_set_drvdata(pdev, sfb);
1461 pm_runtime_get_sync(sfb->dev);
1463 /* setup gpio and output polarity controls */
1467 writel(pd->vidcon1, sfb->regs + VIDCON1);
1469 /* zero all windows before we do anything */
1471 for (win = 0; win < fbdrv->variant.nr_windows; win++)
1472 s3c_fb_clear_win(sfb, win);
1474 /* initialise colour key controls */
1475 for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1476 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1479 writel(0xffffff, regs + WKEYCON0);
1480 writel(0xffffff, regs + WKEYCON1);
1483 /* we have the register setup, start allocating framebuffers */
1485 for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1489 if (!pd->win[win]->win_mode.pixclock)
1490 s3c_fb_missing_pixclock(&pd->win[win]->win_mode);
1492 ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1493 &sfb->windows[win]);
1495 dev_err(dev, "failed to create window %d\n", win);
1496 for (; win >= 0; win--)
1497 s3c_fb_release_win(sfb, sfb->windows[win]);
1498 goto err_pm_runtime;
1502 platform_set_drvdata(pdev, sfb);
1503 pm_runtime_put_sync(sfb->dev);
1508 pm_runtime_put_sync(sfb->dev);
1509 free_irq(sfb->irq_no, sfb);
1515 release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
1518 pm_runtime_disable(sfb->dev);
1520 if (!sfb->variant.has_clksel) {
1521 clk_disable(sfb->lcd_clk);
1522 clk_put(sfb->lcd_clk);
1526 clk_disable(sfb->bus_clk);
1527 clk_put(sfb->bus_clk);
1535 * s3c_fb_remove() - Cleanup on module finalisation
1536 * @pdev: The platform device we are bound to.
1538 * Shutdown and then release all the resources that the driver allocated
1539 * on initialisation.
1541 static int __devexit s3c_fb_remove(struct platform_device *pdev)
1543 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1546 pm_runtime_get_sync(sfb->dev);
1548 for (win = 0; win < S3C_FB_MAX_WIN; win++)
1549 if (sfb->windows[win])
1550 s3c_fb_release_win(sfb, sfb->windows[win]);
1552 free_irq(sfb->irq_no, sfb);
1556 if (!sfb->variant.has_clksel) {
1557 clk_disable(sfb->lcd_clk);
1558 clk_put(sfb->lcd_clk);
1561 clk_disable(sfb->bus_clk);
1562 clk_put(sfb->bus_clk);
1564 release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
1566 pm_runtime_put_sync(sfb->dev);
1567 pm_runtime_disable(sfb->dev);
1573 #ifdef CONFIG_PM_SLEEP
1574 static int s3c_fb_suspend(struct device *dev)
1576 struct platform_device *pdev = to_platform_device(dev);
1577 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1578 struct s3c_fb_win *win;
1581 for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1582 win = sfb->windows[win_no];
1586 /* use the blank function to push into power-down */
1587 s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1590 if (!sfb->variant.has_clksel)
1591 clk_disable(sfb->lcd_clk);
1593 clk_disable(sfb->bus_clk);
1597 static int s3c_fb_resume(struct device *dev)
1599 struct platform_device *pdev = to_platform_device(dev);
1600 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1601 struct s3c_fb_platdata *pd = sfb->pdata;
1602 struct s3c_fb_win *win;
1605 clk_enable(sfb->bus_clk);
1607 if (!sfb->variant.has_clksel)
1608 clk_enable(sfb->lcd_clk);
1610 /* setup gpio and output polarity controls */
1612 writel(pd->vidcon1, sfb->regs + VIDCON1);
1614 /* zero all windows before we do anything */
1615 for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1616 s3c_fb_clear_win(sfb, win_no);
1618 for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1619 void __iomem *regs = sfb->regs + sfb->variant.keycon;
1620 win = sfb->windows[win_no];
1624 shadow_protect_win(win, 1);
1625 regs += (win_no * 8);
1626 writel(0xffffff, regs + WKEYCON0);
1627 writel(0xffffff, regs + WKEYCON1);
1628 shadow_protect_win(win, 0);
1631 /* restore framebuffers */
1632 for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1633 win = sfb->windows[win_no];
1637 dev_dbg(&pdev->dev, "resuming window %d\n", win_no);
1638 s3c_fb_set_par(win->fbinfo);
1645 #ifdef CONFIG_PM_RUNTIME
1646 static int s3c_fb_runtime_suspend(struct device *dev)
1648 struct platform_device *pdev = to_platform_device(dev);
1649 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1651 if (!sfb->variant.has_clksel)
1652 clk_disable(sfb->lcd_clk);
1654 clk_disable(sfb->bus_clk);
1659 static int s3c_fb_runtime_resume(struct device *dev)
1661 struct platform_device *pdev = to_platform_device(dev);
1662 struct s3c_fb *sfb = platform_get_drvdata(pdev);
1663 struct s3c_fb_platdata *pd = sfb->pdata;
1665 clk_enable(sfb->bus_clk);
1667 if (!sfb->variant.has_clksel)
1668 clk_enable(sfb->lcd_clk);
1670 /* setup gpio and output polarity controls */
1672 writel(pd->vidcon1, sfb->regs + VIDCON1);
1678 #define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1679 #define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1681 static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1684 .osd_size_off = 0x8,
1686 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1687 VALID_BPP(18) | VALID_BPP(24)),
1692 .osd_size_off = 0xc,
1695 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1696 VALID_BPP(18) | VALID_BPP(19) |
1697 VALID_BPP(24) | VALID_BPP(25) |
1703 .osd_size_off = 0xc,
1707 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1708 VALID_BPP(18) | VALID_BPP(19) |
1709 VALID_BPP(24) | VALID_BPP(25) |
1717 .valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
1718 VALID_BPP(18) | VALID_BPP(19) |
1719 VALID_BPP(24) | VALID_BPP(25) |
1727 .valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
1728 VALID_BPP(16) | VALID_BPP(18) |
1729 VALID_BPP(19) | VALID_BPP(24) |
1730 VALID_BPP(25) | VALID_BPP(28)),
1734 static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
1737 .osd_size_off = 0x8,
1739 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1740 VALID_BPP(15) | VALID_BPP(16) |
1741 VALID_BPP(18) | VALID_BPP(19) |
1742 VALID_BPP(24) | VALID_BPP(25) |
1748 .osd_size_off = 0xc,
1751 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1752 VALID_BPP(15) | VALID_BPP(16) |
1753 VALID_BPP(18) | VALID_BPP(19) |
1754 VALID_BPP(24) | VALID_BPP(25) |
1760 .osd_size_off = 0xc,
1763 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1764 VALID_BPP(15) | VALID_BPP(16) |
1765 VALID_BPP(18) | VALID_BPP(19) |
1766 VALID_BPP(24) | VALID_BPP(25) |
1773 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1774 VALID_BPP(15) | VALID_BPP(16) |
1775 VALID_BPP(18) | VALID_BPP(19) |
1776 VALID_BPP(24) | VALID_BPP(25) |
1783 .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
1784 VALID_BPP(15) | VALID_BPP(16) |
1785 VALID_BPP(18) | VALID_BPP(19) |
1786 VALID_BPP(24) | VALID_BPP(25) |
1791 static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1794 .vidtcon = VIDTCON0,
1795 .wincon = WINCON(0),
1796 .winmap = WINxMAP(0),
1800 .buf_start = VIDW_BUF_START(0),
1801 .buf_size = VIDW_BUF_SIZE(0),
1802 .buf_end = VIDW_BUF_END(0),
1815 .win[0] = &s3c_fb_data_64xx_wins[0],
1816 .win[1] = &s3c_fb_data_64xx_wins[1],
1817 .win[2] = &s3c_fb_data_64xx_wins[2],
1818 .win[3] = &s3c_fb_data_64xx_wins[3],
1819 .win[4] = &s3c_fb_data_64xx_wins[4],
1822 static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1825 .vidtcon = VIDTCON0,
1826 .wincon = WINCON(0),
1827 .winmap = WINxMAP(0),
1831 .buf_start = VIDW_BUF_START(0),
1832 .buf_size = VIDW_BUF_SIZE(0),
1833 .buf_end = VIDW_BUF_END(0),
1846 .win[0] = &s3c_fb_data_s5p_wins[0],
1847 .win[1] = &s3c_fb_data_s5p_wins[1],
1848 .win[2] = &s3c_fb_data_s5p_wins[2],
1849 .win[3] = &s3c_fb_data_s5p_wins[3],
1850 .win[4] = &s3c_fb_data_s5p_wins[4],
1853 static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1856 .vidtcon = VIDTCON0,
1857 .wincon = WINCON(0),
1858 .winmap = WINxMAP(0),
1862 .buf_start = VIDW_BUF_START(0),
1863 .buf_size = VIDW_BUF_SIZE(0),
1864 .buf_end = VIDW_BUF_END(0),
1877 .win[0] = &s3c_fb_data_s5p_wins[0],
1878 .win[1] = &s3c_fb_data_s5p_wins[1],
1879 .win[2] = &s3c_fb_data_s5p_wins[2],
1880 .win[3] = &s3c_fb_data_s5p_wins[3],
1881 .win[4] = &s3c_fb_data_s5p_wins[4],
1884 static struct s3c_fb_driverdata s3c_fb_data_exynos4 = {
1887 .vidtcon = VIDTCON0,
1888 .wincon = WINCON(0),
1889 .winmap = WINxMAP(0),
1893 .buf_start = VIDW_BUF_START(0),
1894 .buf_size = VIDW_BUF_SIZE(0),
1895 .buf_end = VIDW_BUF_END(0),
1907 .win[0] = &s3c_fb_data_s5p_wins[0],
1908 .win[1] = &s3c_fb_data_s5p_wins[1],
1909 .win[2] = &s3c_fb_data_s5p_wins[2],
1910 .win[3] = &s3c_fb_data_s5p_wins[3],
1911 .win[4] = &s3c_fb_data_s5p_wins[4],
1914 /* S3C2443/S3C2416 style hardware */
1915 static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1936 .win[0] = &(struct s3c_fb_win_variant) {
1938 .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1940 .win[1] = &(struct s3c_fb_win_variant) {
1944 .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
1945 VALID_BPP(18) | VALID_BPP(19) |
1946 VALID_BPP(24) | VALID_BPP(25) |
1951 static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1954 .vidtcon = VIDTCON0,
1955 .wincon = WINCON(0),
1956 .winmap = WINxMAP(0),
1960 .buf_start = VIDW_BUF_START(0),
1961 .buf_size = VIDW_BUF_SIZE(0),
1962 .buf_end = VIDW_BUF_END(0),
1970 .win[0] = &s3c_fb_data_s5p_wins[0],
1971 .win[1] = &s3c_fb_data_s5p_wins[1],
1972 .win[2] = &s3c_fb_data_s5p_wins[2],
1975 static struct platform_device_id s3c_fb_driver_ids[] = {
1978 .driver_data = (unsigned long)&s3c_fb_data_64xx,
1980 .name = "s5pc100-fb",
1981 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
1983 .name = "s5pv210-fb",
1984 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
1986 .name = "exynos4-fb",
1987 .driver_data = (unsigned long)&s3c_fb_data_exynos4,
1989 .name = "s3c2443-fb",
1990 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
1992 .name = "s5p64x0-fb",
1993 .driver_data = (unsigned long)&s3c_fb_data_s5p64x0,
1997 MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1999 static const struct dev_pm_ops s3cfb_pm_ops = {
2000 SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
2001 SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
2005 static struct platform_driver s3c_fb_driver = {
2006 .probe = s3c_fb_probe,
2007 .remove = __devexit_p(s3c_fb_remove),
2008 .id_table = s3c_fb_driver_ids,
2011 .owner = THIS_MODULE,
2012 .pm = &s3cfb_pm_ops,
2016 module_platform_driver(s3c_fb_driver);
2018 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2019 MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
2020 MODULE_LICENSE("GPL");
2021 MODULE_ALIAS("platform:s3c-fb");